Memory system

Abstract

To provide a memory system capable of efficiently performing queue management of commands.SOLUTION: According to an embodiment, a memory system includes a nonvolatile memory and a controller. The non-volatile memory includes a memory die. The controller is capable of communicating with a host including a submission queue, and includes a first command queue and a second command queue corresponding to a memory die. The controller fetches the first command from the first submission queue, stores the first command fetched from the first submission queue in the first command queue when the second command fetched from the first submission queue earlier than the first command is stored in the second command queue, and stores the first command fetched from the first submission queue in the second command queue when the second command is not stored in the second command queue.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to a memory system. [Background technology]

[0002] A memory system equipped with non-volatile memory achieves high performance by driving multiple memory dies in parallel. The memory system distributes commands issued by the host and stored in an SQ (submission queue) to multiple memory dies that can be driven in parallel. A host may have multiple SQs.

[0003] In such a memory system, it is necessary to efficiently distribute commands stored in multiple SQs to multiple memory dies. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2018 / 0285073 [Patent Document 2] US Patent Application Publication No. 2022 / 0188033 [Patent Document 3] US Patent Application Publication No. 2022 / 0261183 Summary of the Invention [Problem to be solved by the invention]

[0005] One embodiment of the present invention provides a memory system that can efficiently manage command queues. [Means for solving the problem]

[0006] According to an embodiment, a memory system includes a non-volatile memory and a controller. The non-volatile memory includes at least one memory die. The controller is capable of communicating with a host having at least one submission queue, each capable of storing a plurality of commands, and is electrically connected to the non-volatile memory. The controller has a first command queue and a second command queue corresponding to the at least one memory die. The controller retrieves a first command from a first submission queue of the at least one submission queue, determines whether a second command retrieved from the first submission queue before the first command is stored in the second command queue, and stores the first command retrieved from the first submission queue in the first command queue if the second command queue is stored. If the second command is not stored in the second command queue, the controller stores the first command retrieved from the first submission queue in the second command queue. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a diagram showing an example of the configuration of an information processing system including a memory system according to an embodiment and a host connected to the memory system. [Figure 2] FIG. 10 is a diagram illustrating an example of a die queue status table of the memory system according to the embodiment. [Figure 3] FIG. 10 is a diagram for explaining a first comparative example. [Figure 4] FIG. 10 is a diagram (first diagram) for explaining a second comparative example. [Figure 5] FIG. 10 is a diagram (second diagram) for explaining a second comparative example. [Figure 6] FIG. 10 is a diagram for explaining a third comparative example. [Figure 7] 3A and 3B are diagrams for explaining an overview of command queue management by a first NAND die queue and a second NAND die queue in the memory system of the embodiment. [Figure 8]4A and 4B are diagrams for explaining details of command queue management by a first NAND die queue and a second NAND die queue in the memory system of the embodiment. [Figure 9] 10A and 10B are diagrams for explaining an example of processing for searching for a command from a controller first NAND die queue in the memory system of the embodiment. [Figure 10] 10A and 10B are diagrams showing an example of a procedure in which a controller stores commands in a first NAND die queue and a second NAND die queue in the memory system of the embodiment. [Figure 11] 10 is a flowchart showing a processing flow when a controller retrieves a command from a submission queue (SQ) in the memory system of the embodiment. [Figure 12] 10 is a flowchart showing a processing flow when the controller retrieves a command from the second NAND die queue in the memory system of the embodiment. [Figure 13] 10 is a flowchart showing the flow of a process in which a controller searches for a command from a first NAND die queue in the memory system of the embodiment. [Figure 14] 1A and 1B are diagrams for explaining an example of a method for implementing a first NAND die queue and a second NAND die queue in the memory system of the embodiment. [Figure 15] FIG. 10 is a diagram for explaining an example of searching the first NAND die queue in the memory system according to the first modification of the embodiment. [Figure 16] FIG. 10 is a diagram showing an example in which a plurality of second NAND die queues are provided in a memory system according to a second modification of the embodiment. [Figure 17] FIG. 10 is a diagram for explaining queue management of commands using a plurality of second NAND die queues in a memory system according to a second modification of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described with reference to the drawings. FIG. 1 is a diagram showing an example of the configuration of an information processing system including a memory system 1 according to an embodiment and a host 2 connected to the memory system 1. As shown in FIG.

[0009] The memory system 1 is a storage device. Here, an example is shown in which the memory system 1 is realized as an SSD (solid state drive).

[0010] The host 2 is an information processing device such as a server or a personal computer. The memory system 1 and the host 2 are connected to each other via, for example, a PCI Express TM (PCIe TM The memory system 1 and the host 2 are connected by an interface conforming to the NVM Express standard. TM (NVMe TM ) and communicates in accordance with a standard-compliant protocol.

[0011] The host 2 has a main memory 50. The main memory 50 is, for example, a DRAM (dynamic random access memory). The host 2 provides SQs 51 in the main memory 50 for storing commands for the memory system 1. Here, an example is shown in which 256 SQs 51 (SQ[0-255]) are provided in the main memory 50. The host 2 uses multiple SQs 51 for each program, for example.

[0012] In the information processing system of the embodiment, the command that the host 2 issues to the memory system 1 and stores in SQ51 is an NVMe command that complies with the NVMe standard. When the host 2 stores the NVMe command in SQ51, the host 2 transmits a PCIe packet that complies with the PCIe standard to the memory system 1 to notify the issuance of the NVMe command. The host 2 can notify the memory system 1 of the issuance of multiple NVMe commands with one PCIe packet.

[0013] The memory system 1 includes a controller 10 and a nonvolatile memory 20. The controller 10 and the nonvolatile memory 20 are electrically connected by a signal line. The controller 10 is configured as, for example, a system on a chip (SoC). The functions of each part of the controller 10 can be realized by dedicated hardware, a processor that executes a program, or a combination of these.

[0014] Based on commands issued by the host 2, the controller 10 performs processes such as writing data received from the host 2 to the nonvolatile memory 20 and reading data requested by the host 2 from the nonvolatile memory 20.

[0015] When the above-mentioned PCIe packet for notifying the issuance of an NVMe command is received from the host 2, the controller 10 transmits a PCIe packet for extracting the NVMe command from SQ51 to the host 2. In response to this PCIe packet, the host 2 transmits the NVMe command in SQ51 to the memory system 1. The controller 10 can extract multiple NVMe commands from SQ51 with one PCIe packet.

[0016] The nonvolatile memory 20 is, for example, a NAND flash memory. The nonvolatile memory 20 includes a plurality of memory dies 21. Hereinafter, the nonvolatile memory 20 will also be referred to as a NAND memory 20. The memory dies 21 will also be referred to as NAND dies 21, memory chips 21, or NAND chips 21. Here, an example will be shown in which the NAND memory 20 includes 512 NAND dies 21 (NAND dies [0-511]).

[0017] The controller 10 has a host interface (I / F) unit 11, a NAND interface (I / F) unit 12, a first NAND die queue 13 (first NAND die queue [0-511]) and a second NAND die queue 14 (second NAND die queue [0-511]) in the same number as the NAND dies 21, a search engine 15, and a die queue status table 16. The first NAND die queue 13, the second NAND die queue 14, and the die queue status table 16 are provided in, for example, static RAM (SRAM) built into the controller 10.

[0018] The host interface unit 11 controls communication with the host 2. The NAND interface unit 12 controls writing of data to the NAND die 21 in the NAND memory 20 and reading of data from the NAND die 21.

[0019] The first NAND die queue 13 is a command queue that stores commands retrieved from SQ51. When the controller 10 retrieves a command from SQ51, it identifies the NAND die 21 that is the target of the command. For example, the controller 10 identifies the NAND die 21 that is the target of the command by converting the logical address of the data to be accessed, specified by the command retrieved from SQ51, into a physical address of the NAND memory 20. The controller 10 basically stores the retrieved command in the first NAND die queue 13 that corresponds to the identified NAND die 21. In other words, the controller 10 distributes commands issued by the host 2 to the memory system 1 to multiple first NAND die queues 13.

[0020] When the data to be accessed specified by a command spans multiple NAND dies 21, the controller 10 may divide the command into subcommands for each NAND die 21 and store the subcommands in the first NAND die queue 13 corresponding to the target NAND die 21 of each subcommand. Alternatively, the controller 10 may store the command in the first NAND die queue 13 corresponding to the NAND die 21 to be accessed first in response to the command, and after starting access to the target NAND die 21, store the command again in the first NAND die queue 13 corresponding to the NAND die 21 to be accessed next in response to the command.

[0021] In addition, under certain circumstances, the controller 10 stores the retrieved command in the second NAND die queue 14, not in the first NAND die queue 13. This point will be described later.

[0022] Commands retrieved from multiple different SQs 51 may be mixed in one first NAND die queue 13. The controller 10 is configured to be able to retrieve not only the first or last command but also intermediate commands from the multiple commands stored in the first NAND die queue 13.

[0023] The second NAND die queue 14 is a command queue that stores commands retrieved from the first NAND die queue 13 or SQ51. The process of moving commands from the first NAND die queue 13 to the second NAND die queue 14 will be described later. The controller 10 controls access to the NAND die 21 based on commands stored in the second NAND die queue 14, not the first NAND die queue 13. That is, the controller 10 controls data write and read operations to and from the NAND die 21 based on commands retrieved from the second NAND die queue 14.

[0024] The search engine 15 searches the first NAND queue 13 for commands that match the given search criteria.

[0025] FIG. 2 is a diagram showing an example of the die queue status table 16. As shown in FIG. The die queue status table 16 records information for managing the status of the corresponding first NAND die queue 13 and second NAND die queue 14 for each NAND die 21. Specifically, the die queue status table 16 records the SQ number being searched, a command addition presence / absence flag, and a command presence / absence flag corresponding to each SQ 51.

[0026] The SQ number being searched is information indicating the SQ 51 to be searched when the search engine 15 is searching for a command to be moved from the first NAND die queue 13 to the second NAND die queue 14.

[0027] The command addition flag indicates whether a command belonging to the SQ51 to be searched has been added to the first NAND die queue 13 to be searched during a search by the search engine 15.

[0028] The command presence / absence flag corresponding to each SQ51 indicates whether the command extracted from that SQ51 should be stored in the first NAND die queue 13. In other words, the command presence / absence flag corresponding to each SQ51 indicates whether the command of that SQ51 is stored in at least one of the first NAND die queue 13 and the second NAND die queue 14. If the command of a certain SQ51 is stored in at least one of the first NAND die queue 13 and the second NAND die queue 14, the command extracted from that SQ51 is a command to be stored in the first NAND die queue 13. If the command of a certain SQ51 is not stored in either the first NAND die queue 13 or the second NAND die queue 14, the command extracted from that SQ51 is a command to be stored in the second NAND die queue 14.

[0029] A first comparative example will now be described. Fig. 3 is a diagram for explaining a first comparative example.

[0030] The memory system of the first comparative example has one NAND die queue for each NAND die. In the first comparative example, each NAND die queue has one entry. The dotted hatched rectangle indicated by symbol a1 represents a command for NAND die [0]. The diagonally hatched rectangle indicated by symbol a2 represents a command for NAND die [1]. FIG. 3(A) shows an example in which commands are stored in SQ[0] in the following order: command 0 for NAND die [0], command 1, command 2, command 3 for NAND die [1], command 4 for NAND die [0], and command 5 for NAND die [1]. In other words, the numbers inside the rectangles representing commands indicate the order in which the commands were stored in SQ.

[0031] If each NAND die queue can only store a small number of commands, there is a greater chance that multiple NAND dies cannot be driven in parallel. This problem is known as head of line blocking.

[0032] As shown in FIG. 3B, after command 0 at the beginning of SQ[0] is retrieved and stored in the NAND die queue [0], the next command at the beginning of SQ[0] is command 1. Command 1, like command 0, is a command for NAND die [0]. NAND die queue [0] has only one entry. Therefore, command 1 is not stored in NAND die queue [0] until command 0 is removed from NAND die queue [0]. In other words, command 1 remains at the beginning of SQ[0]. Therefore, at this point, command 3 for NAND die [1], which is located after command 1 in SQ[0], is not retrieved and stored in NAND die queue [1]. As a result, NAND die [0] and NAND die [1] cannot be driven in parallel.

[0033] 4 and 5 are diagrams for explaining a second comparative example.

[0034] As shown in Figure 4A, each NAND die queue in the memory system of the second comparative example has three entries. If each NAND die queue can store a larger number of commands, the opportunities for driving multiple NAND dies in parallel increase. In other words, the head-of-line blocking problem can be avoided.

[0035] 4B, the memory system of the second comparative example can retrieve command 0, command 1, and command 2 from SQ[0] and store them in the NAND die queue [0], and can also retrieve command 3 from SQ[0] and store it in the NAND die queue [1]. As a result, NAND die [0] and NAND die [1] can be driven in parallel.

[0036] However, if the number of entries in each NAND die queue is large, the start of processing commands in other SQs may be delayed. Figure 5(A) shows an example in which SQ[0] stores Command 0, Command 1, Command 2, Command 3, Command 4, and Command 5 for NAND die[0].

[0037] 5(B) shows an example in which commands 0, 1, and 2 from SQ[0] are retrieved and stored in the NAND die queue [0], and then commands 6 and 7 for NAND die [0] are stored in SQ[1]. In this case, commands 1 and 2 from SQ[0] are already stored in the NAND die queue [0], so for example, command 6 from SQ[1] cannot be processed next to command 0 from SQ[0].

[0038] Figure 5(C) shows an example in which, after processing command 0 in SQ[0], command 6 in SQ[1] is stored in NAND die queue [0] after command 1 and command 2 in SQ[0]. Figure 5(D) also shows an example in which, after processing command 1 in SQ[0], command 2 in SQ[0] becomes the head of NAND die queue [0], while command 6 in SQ[1] is still stored in NAND die queue [0]. Figure 5(D) also shows an example in which, through round-robin arbitration, a command is retrieved from SQ[1] (retrieval of command 6) followed by a command is retrieved from SQ[0] (retrieval of command 3).

[0039] FIG. 6 is a diagram for explaining the third comparative example.

[0040] To increase the chances of parallel operation of NAND dies and to allow a command stored later in a certain SQ (such as command 6 in Figure 5) to be processed before a command stored earlier in another SQ (such as command 1 in Figure 5), a NAND die queue may be provided for each NAND die, the number of which corresponds to the number of SQs. In this case, arbitration is performed between the NAND die queues for each SQ to select the command to be processed.

[0041] 6A shows an example in which two NAND die queues, one for SQ[0] and one for SQ[1], are provided for NAND die [0]. Each NAND die queue has three entries. 6A also shows an example in which SQ[0] stores Command 0, Command 1, Command 2, Command 3, Command 4, and Command 5 for NAND die [0].

[0042] Also, Figure 6(B) shows an example in which command 0, command 1, and command 2 from SQ[0] are extracted and stored in the NAND die queue [0] for SQ[0], and then command 6 and command 7 for NAND die [0] are stored in SQ[1].

[0043] The memory system of the third comparative example has a NAND die queue for each SQ. Therefore, as shown in Figure 6(C), commands 6 and 7 of SQ[1] are stored in the NAND die queue [0] for SQ[1]. Figure 6(C) also shows an example in which command 3 of SQ[0] is stored in the NAND die queue [0] for SQ[0] after command 0 of SQ[0] is processed.

[0044] The memory system of the third comparative example has NAND die queues for the number of SQs, so that commands 6 and 7 can be stored in the NAND die queue [0] for SQ[1]. Therefore, as shown in Fig. 6(D), after processing command 0 in SQ[0], the memory system of the third comparative example can process command 6 in SQ[1] before commands 1 and 2 in SQ[0].

[0045] However, in the case of the third comparative example, a NAND die queue of the number of NAND dies multiplied by the number of SQs is required, which means that a large amount of memory is required for command queue management.

[0046] The memory system 1 of the embodiment does not provide a NAND die queue for each NAND die 21 for the number of SQs as in the third comparative example, but provides a first NAND die queue 13 and a second NAND die queue 14 for each NAND die 21. This reduces the amount of memory required for command queue management.

[0047] FIG. 7 is a diagram for explaining an outline of queue management of commands by the first NAND die queue 13 and the second NAND die queue 14 of the memory system 1 of the embodiment.

[0048] 7 shows an example in which the host 2 has nine SQ51 (SQ[0-8]). FIG. 7 also shows a state in which three commands for a certain NAND die 21 (NAND die[j]) are stored in each SQ51.

[0049] Under these circumstances, the memory system 1 of the embodiment manages the queues of commands stored in each SQ 51 using only two die queues, the first NAND die queue 13 and the second NAND die queue 14, without providing as many NAND die queues as there are SQs per NAND die 21 (nine NAND die queues in the example of FIG. 7). In the memory system 1 of the embodiment, commands stored in each SQ 51 are retrieved, for example, by arbitration using a round-robin method, and stored in the first NAND die queue 13 or the second NAND die queue 14. Then, the controller 10 controls access to the NAND die 21 based on the commands stored in the second NAND die queue 14.

[0050] 8 is a diagram for explaining details of command queue management by the first NAND die queue 13 and the second NAND die queue 14 of the memory system 1 of the embodiment. Fig. 8 shows a state in which the first command belonging to each SQ51 targeting a certain NAND die 21 (NAND die[j]) is stored in the second NAND die queue[j], and the second and subsequent commands belonging to the same SQ51 are stored in the first NAND die queue[j].

[0051] Specifically, the second NAND die queue [j] stores command 0 for each SQ51 in the following order: SQ[1], SQ[3], SQ[8], SQ[7], SQ[2], SQ[5], SQ[4], SQ[6], SQ[0]. The first NAND die queue 13 stores command 1 of SQ[3] at the beginning, followed by command 1 of SQ[1], command 2 of SQ[1], command 1 of SQ[8], command 2 of SQ[8], command 1 of SQ[7], command 2 of SQ[3], command 1 of SQ[2], command 2 of SQ[7], command 1 of SQ[5], command 1 of SQ[4], command 1 of SQ[6], command 2 of SQ[6], command 1 of SQ[0], command 2 of SQ[5], command 2 of SQ[4], command 2 of SQ[0], and command 2 of SQ[2].

[0052] When the controller 10 receives a command for a NAND die [j] from a certain SQ51 (SQ[i]) via the host interface unit 11, it refers to the state of SQ[i] in the die queue status table 16 and determines whether a command belonging to the same SQ[i] as the command is stored in either the first NAND die queue [j] or the second NAND die queue [j]. As described above, the die queue status table 16 stores, for each NAND die 21, information indicating whether a command belonging to each SQ51 is stored in at least one of the first NAND die queue [j] or the second NAND die queue [j].

[0053] If the command belonging to SQ[i] is not stored in either the first NAND die queue [j] or the second NAND die queue [j], the controller 10 stores the command obtained from SQ[i] at the end of the second NAND die queue [j]. In this case, the controller 10 records information indicating that the command belonging to SQ[i] is stored in the second NAND die queue [j] as a command presence / absence flag corresponding to SQ[i] in the die queue status table 16.

[0054] On the other hand, if the command belonging to that SQ[i] is already stored in either the first NAND die queue[j] or the second NAND die queue[j], the controller 10 stores the command obtained from SQ[i] at the end of the first NAND die queue[j].

[0055] As mentioned above, the die queue status table 16 also stores information indicating the search target SQ 51 when the search engine 15 is searching for a command to be moved from the first NAND die queue 13 to the second NAND die queue 14. When the search engine 15 is searching for the SQ[i] to which the command acquired from the host 2 belongs, the controller 10 stores the command at the end of the first NAND die queue 13. In this case, the controller 10 sets information indicating that the command belonging to the search target SQ[i] has been added to the first NAND die queue 13 in the die queue information table 16 as a command addition presence / absence flag. Details of this case will be described later.

[0056] When commands are stored in the second NAND die queue [j] of a certain NAND die 21 (NAND die [j]), the controller 10 retrieves and processes the first command. More specifically, the controller 10 controls, via the NAND interface unit 12, the writing of data to or reading of data from the NAND die [j] requested by the retrieved command.

[0057] In parallel with processing the command retrieved from the top of the second NAND die queue [j], the controller 10 uses the search engine 15 to search the first NAND die queue [j] for the next command of the SQ [i] to which the command belongs. The search engine 15 searches for commands in the order in which the commands were stored in the first NAND die queue [j] (the order in which the commands were retrieved from SQ 51). The search engine 15 sets one SQ [i] as a search key and searches one first NAND die queue [j] at a time. In the memory system 1 of this embodiment, the search engine 15 stores up to 512 search keys (SQ [i]) in each of the 512 die queue status tables 16.

[0058] 9, an example of a process in which the search engine 15 searches the first NAND die queue 13 for the next command of SQ51 to which a command extracted from the second NAND die queue 14 belongs will be described. Here, an example is shown in which, for a certain NAND die 21, the search engine 15 searches the first NAND die queue 13 for the next command of SQ[0] when the command of SQ[0] is extracted from the second NAND die queue 14. Note that the first NAND die queue 13 manages the storage location of the first command, a link pointer for tracing subsequent entries in the order in which the commands were stored in the first NAND die queue 13, and the storage location of the last command.

[0059] When searching for the next command of SQ[0] from the first NAND die queue 13, the controller 10 sets SQ[0] as the SQ number being searched in the die queue status table 16. Furthermore, when the search by the search engine 15 starts, the controller 10 clears the command addition presence / absence flag in the die queue status table 16. That is, the controller 10 sets the flag to a state in which no command addition has occurred during the search. In the search engine 15, the storage location of the last command in the first NAND die queue 13 at the start of the search is set as the search end entry.

[0060] The search engine 15 first refers to the storage location (search start entry) where the first command in the first NAND die queue 13 is stored. In the example shown in FIG. 9, the search start entry is entry 3. Since the command SQ[1] is stored in entry 3 (search miss), the search engine 15 then refers to the entry where the subsequent command is stored (entry 5). The command SQ[2] is stored in entry 5 (search miss). Thereafter, the search engine 15 similarly refers to entry 2 (the command SQ[3]) and entry 8 (the command SQ[1]). Then, the search engine 15 detects the command SQ[0] stored in entry 7 (search hit). Since the command SQ[0] is detected, the search engine 15 ends the search process. In this case, the controller 10 records information indicating that the command belonging to SQ[0] is stored in the first NAND die queue 13 as a command presence / absence flag corresponding to SQ[0] in the die queue status table 16.

[0061] If the command SQ[0] is added to the first NAND die queue 13 during command search, the controller 10 records information indicating that an addition has been made in the die queue status table 16 as a command addition presence / absence flag.

[0062] If the command of SQ[0] is not detected even after searching up to the search end entry, the controller 10 checks the command addition presence flag recorded in the die queue status table 16.

[0063] If no command has been added, the controller 10 ends the search process. In this case, the controller 10 records information indicating that the command belonging to SQ[0] is not stored in either the first NAND die queue 13 or the second NAND die queue 14 in the die queue status table 16 as a command presence / absence flag corresponding to SQ[0].

[0064] When a command is added, the controller 10 resets the storage location of the command at the end of the first NAND queue 13 at the time of search completion as a new search completion entry in the search engine 15. This causes the search engine 15 to resume the search process from the entry next to the last referenced entry.

[0065] The SQ number being searched, which is set in the DQ status table 16 at the start of the search, is updated to information (invalid value) indicating that no SQ51 command is being searched for at the end of the search, regardless of whether the command being searched for is detected or not.

[0066] If a plurality of SQ51 commands to be searched for are stored in the first NAND die queue 13, the command that is stored first in the first NAND die queue 13 among them is detected.

[0067] As described above, when a command for a certain NAND die 21 (NAND die[j]) is obtained from a certain SQ 51 (SQ[i]), and information indicating that a command belonging to that SQ[i] is being searched for is set in the die queue status table 16, the controller 10 provisionally stores the command in the first NAND die queue[j]. The reason why the command is provisionally stored in the first NAND die queue[j] is because it is unclear whether the command belonging to that SQ[i] that should be moved to the second NAND die queue[j] is already stored in the first NAND die queue[j].

[0068] If a command belonging to that SQ[i] is already stored in the first NAND die queue[j], the command is detected by the search engine 15, retrieved by the controller 10, and stored in the second NAND die queue[j]. In this case, the command temporarily stored in the first NAND die queue[j] remains stored in the first NAND die queue[j].

[0069] On the other hand, if no commands belonging to that SQ[i] are stored in the first NAND die queue [j], a re-search is performed targeting commands that have been additionally stored after the search began, and the commands provisionally stored in the first NAND die queue [j] are detected by the search engine 15, retrieved by the controller 10, and stored in the second NAND die queue [j].

[0070] In this way, the controller 10 performs queue management of commands for each NAND die 21 so that the first command belonging to each SQ[i] is stored in the second NAND die queue 14, and the second and subsequent commands are stored in the first NAND die queue 13.

[0071] As a result, the memory system 1 of the embodiment does not require a NAND die queue equal to the number of NAND dies x the number of SQs as in the third comparative example, but can perform command queue management using a NAND die queue equal to the number of NAND dies x 2 and die queue information tables equal in number to the number of NAND dies.

[0072] Furthermore, the controller 10 can simultaneously search for a command to be moved to the second NAND die queue 14 from all commands stored in the first NAND die queue 13 and process the command retrieved from the second NAND die queue 14. In other words, the search time for this command can be hidden by the command processing time. Therefore, it is believed that the search for this command will not adversely affect the performance of the memory system 1.

[0073] As described above, the amount of memory required for managing the command queue is reduced.

[0074] FIG. 10 is a diagram showing an example of a procedure in which the controller 10 stores commands in the first NAND die queue 13 and the second NAND die queue 14 in the memory system 1 of the embodiment.

[0075] The dotted hatched rectangle indicated by symbol b1 represents a command for a certain SQ51 (let's say SQ[X]). The diagonally hatched rectangle indicated by symbol b2 represents a command for another SQ51 (let's say SQ[Y]). The numbers inside the rectangles representing commands indicate the order in which the commands were issued.

[0076] Figure 10(A) shows that the first NAND die queue 13 (first NAND die queue [j]) and the second NAND die queue 14 (second NAND die queue [j]) of a certain NAND die 21 (NAND die [j]) are both empty and do not store any commands.

[0077] When the first NAND die queue[j] and the second NAND die queue[j] are in the state shown in Figure 10(A), if command 0 for NAND die[j] is retrieved from SQ[X], the controller 10 stores command 0 in the second NAND die queue[j] as shown in Figure 10(B). Command 0 is stored in the second NAND die queue[j] because the controller 10 recognizes from the die queue status table 16 that the command in SQ[X] is not stored in the second NAND die queue[j]. Because command 0 has been stored in the second NAND die queue[j], the die queue status table 16 indicates that the command in SQ[X] is stored in the second NAND die queue[j].

[0078] Next, assume that Command 1 and Command 2 are extracted from SQ[X]. At this time, Command 0 of SQ[X] is stored in the second NAND die queue [j], so the controller 10 stores Command 1 and Command 2 in the first NAND die queue [j], as shown in FIG. 10(C).

[0079] Next, assume that command 3 is extracted from SQ[Y]. When the controller 10 recognizes from the die queue status table 16 that the command in SQ[Y] is not stored in the second NAND die queue[j], it stores command 3 in the second NAND die queue[j] as shown in FIG. 10(D).

[0080] Next, assume that command 4 of SQ[X] and command 5 of SQ[Y] are extracted. Since commands SQ[X] and SQ[Y] are both stored in the second NAND die queue [j], the controller 10 stores command 4 of SQ[X] and command 5 of SQ[Y] in the first NAND die queue [j], as shown in FIG. 10(E).

[0081] Now, assume that the controller 10 retrieves the first command 0 from the second NAND die queue [j]. FIG. 10(F) shows the state after command 0 has been retrieved from the second NAND die queue [j]. Because command 0 is a command of SQ[X], the controller 10 uses the search engine 15 to search for commands of SQ[X] from the beginning of the first NAND die queue [j]. As a result, command 1 of SQ[X] is detected, and the controller 10 retrieves command 1 from the first NAND die queue [j] and stores it in the second NAND die queue [j], as shown in FIG. 10(G).

[0082] If the command SQ[X] is not detected, the controller 10 updates the die queue status table 16 to indicate that the command SQ[X] is not stored in the second NAND die queue[j].

[0083] Next, assume that the controller 10 retrieves the first command 3 from the second NAND die queue [j]. FIG. 10(H) shows the state after command 3 has been retrieved from the second NAND die queue [j]. Because command 3 is a command in SQ[Y], the controller 10 uses the search engine 15 to search for commands in SQ[Y] from the beginning of the first NAND die queue [j]. As a result, command 5 in SQ[Y] is detected, and the controller 10 retrieves command 5 from the first NAND die queue [j] and stores it in the second NAND die queue [j], as shown in FIG. 10(I).

[0084] In this way, for each NAND die 21, the controller 10 controls so that the first command of each SQ51 (SQ[i]) is stored in the second NAND die queue [j], thereby reducing the amount of memory required for command queue management.

[0085] FIG. 11 is a flowchart showing the flow of processing when the controller 10 of the memory system 1 of the embodiment extracts a command from SQ51.

[0086] When the controller 10 retrieves a command from a certain SQ 51 (SQ[i]), it determines whether or not the command of that SQ[i] is stored in the second NAND die queue 14 (S11). If the command of SQ[i] is stored (S11: YES), the controller 10 stores the retrieved command in the first NAND die queue 13 (S12).

[0087] If the command SQ[i] is not stored in the second NAND die queue 14 (S11: NO), the controller 10 next determines whether the command SQ[i] is currently being searched for in the first NAND die queue 13 (S13). If the command is currently being searched for (S13: YES), the controller 10 temporarily stores the retrieved command in the first NAND die queue 13 (S12).

[0088] If the command SQ[i] is not stored in the second NAND die queue 14 (S11: NO) and the command SQ[i] is not currently being searched for (S13: NO), the controller 10 stores the retrieved command in the second NAND die queue 14 (S14).

[0089] FIG. 12 is a flowchart showing the flow of processing in which the controller 10 of the memory system 1 of this embodiment retrieves a command from the second NAND die queue 14 and determines whether the command to be moved to the second NAND die queue 14 is stored in the first NAND die queue 13. In this processing, the controller 10 uses the search engine 15 to search the first NAND die queue 13. This processing is performed for each NAND die 21. That is, in this embodiment, the processing shown in this flowchart is performed in parallel. The maximum number of processes performed in parallel is equal to the number of NAND dies 21, which is 512 in this embodiment. FIG. 13 is a flowchart showing the flow of processing in which the search engine 15 searches the first NAND die queue 13 for the next command following SQ51 to which the command retrieved from the second NAND die queue 14 belongs.

[0090] The controller 10 selects one of the second NAND die queues 14 by arbitration using a round robin method, for example (S21). The controller 10 extracts a command from the head of the selected second NAND die queue 14 (S22).

[0091] The controller 10 first sets the first entry of the first NAND die queue 13 as a start entry in the search engine 15 (S23). Then, the controller 10 searches the first NAND die queue 13 using the search engine 15 for commands in SQ51(SQ[i]) to which the extracted command belongs (S24). At this time, the search end entry set in the search engine 15 is the last entry of the first NAND die queue 13.

[0092] The explanation will be shifted to FIG. 13. The search engine 15 sets the search start entry as the first entry to be referenced (S31). The search engine 15 references the number of the SQ51 to which the command stored in the entry to be referenced belongs (S32). The search engine 15 determines whether the number of the referenced SQ51 matches the search key (SQ number) (S33). If the SQ numbers match (S33: YES), the search engine 15 ends the process with a successful search (search hit).

[0093] If the SQ numbers do not match (S33: NO), the search engine 15 determines whether the referenced entry is a search end entry (S34). If the referenced entry is a search end entry (S34: YES), the search engine 15 ends the process with a search failure (search miss).

[0094] If the referenced entry is not a search end entry (S34: NO), the search engine 15 determines whether the number of referenced entries has reached the upper limit (S35). If the number of referenced entries has reached the upper limit (S35: YES), the search engine 15 terminates the process by suspending the search. An example of a case where an upper limit is set on the number of referenced entries will be described later.

[0095] If the number of referenced entries has not reached the upper limit (S35: NO), the search engine 15 sets the entry indicated by the Link pointer of the referenced entry as the next entry to be referenced (S36), and executes the process from step S32.

[0096] Returning to FIG. 12, the description of the processing after the controller 10 retrieves the command from the second NAND die queue 14 will be continued.

[0097] If the command SQ[i] is found (S25: YES), the controller 10 moves the found command from the first NAND die queue 13 to the second NAND die queue 14 (S26).

[0098] On the other hand, if the command for SQ[i] is not found (S25: NO), the controller 10 determines whether the search has been interrupted (S27). If the search has not been interrupted (S27: NO), the controller 10 determines whether a command belonging to the SQ[i] being searched for has been added to the first NAND queue 13 after the search by the search engine 15 started (S28).

[0099] If the search is interrupted (S27: YES) or if a command has been added (S28: YES), the controller 10 re-searches the first NAND die queue 13, including the command added during the search (S29). At this time, the search start entry set in the search engine 15 is the entry next to the entry last referenced when the previous search ended (i.e., the entry indicated by the Link pointer). Also, the search end entry set in the search engine 15 is the last entry in the first NAND die queue 13. The command SQ[i] detected in the re-search is, for example, the command SQ[i] determined to be under search in the processing of steps S13 to S12 described with reference to FIG. 11 and provisionally stored in the first NAND die queue 13. The processing by the controller 10 proceeds to step S24 (search processing by the search engine 15).

[0100] On the other hand, if no command has been added (S28: NO), the controller 10 records information indicating that the command of SQ[i] is not stored in either the first NAND die queue 13 or the second NAND die queue 14 in the die queue status table 16 (S30).

[0101] Next, an example of a method for implementing the first NAND die queue 13 and the second NAND die queue 14 will be described with reference to FIG.

[0102] The controller 10 of the memory system 1 of the embodiment manages a command table 17 in which commands extracted from SQ51 are stored. The command table 17 has a plurality of entries. Each entry stores a command (the command body), information indicating the SQ51 in which the command was stored, and a link pointer for tracing the subsequent entry. For example, the command table 17 is provided in an SRAM built into the controller 10. In this case, the link pointer is an address indicating the location in the SRAM where the subsequent entry is stored.

[0103] Each of the 512 first NAND die queues 13 can be implemented with a Head pointer indicating the position of the entry in which the first command of each first NAND die queue 13 is stored, and a Tail pointer indicating the position of the entry in which the last command is stored.

[0104] In an empty first NAND die queue 13, the Head pointer and Tail pointer do not point to a valid entry in the command table 17. That is, the Head pointer and Tail pointer are NULL pointers. When adding a new command to the first NAND die queue 13 in this state, the controller 10 first stores the new command and information (SQ number) for identifying the SQ 51 in which the command was stored in an empty entry in the command table 17. Then, the Head pointer and Tail pointer are updated to point to the position of the entry in which the new command is stored.

[0105] Furthermore, when a new command is added to the first NAND die queue 13, the controller 10 first stores the command to be added and information (SQ number) for identifying the SQ 51 in which the command was stored in an empty entry in the command table 17. Then, the controller 10 updates the Link pointer of the entry pointed to by the Tail pointer so that the Link pointer points to the position of the entry that stores the added command. Furthermore, the controller 10 updates the Tail pointer so that the Link pointer points to the position of the entry that stores the added command.

[0106] As a result, a new command is added to the last entry of the first NAND die queue 13. Note that a command can be added to the first NAND die queue 13 even while the search engine 15 is searching the first NAND die queue 13.

[0107] When retrieving a command from an intermediate entry located between the beginning and end of the first NAND die queue 13 in order to move it to the second NAND die queue 14, the controller 10 replaces the value of the link pointer of the entry storing the command immediately before the command to be retrieved with the value of the link pointer of the entry storing the command to be retrieved. Note that for this process, the search engine 15 stores the position of the entry immediately before the entry found (hit) in the search. This makes it possible to retrieve a command from an intermediate entry in the first NAND die queue 13 even if there is only one link pointer connecting the entries in the command table 17 (i.e., a unidirectional linked list).

[0108] When retrieving a command from the first entry of the first NAND die queue 13, the controller 10 replaces the value of the Head pointer with the value of the Link pointer of the entry in which the command to be retrieved is stored.When retrieving a command from the last entry of the first NAND die queue 13, the controller 10 replaces the value of the Tail pointer with a value (address) indicating the position of the entry in which the command immediately before the command to be retrieved is stored.

[0109] It should be noted that while the search engine 15 is searching the first NAND die queue 13, it is not possible to extract commands from the first NAND die queue 13 that is the search target.

[0110] When implemented as described above, the amount of data required for one first NAND die queue 13 is 2+2=4 bytes, assuming that the Head pointer and the Tail pointer each are 2 bytes (the total number of entries in the command table is 65,536 or less).

[0111] Each of the 512 second NAND die queues 14 can also be implemented with a Head pointer indicating the position of the entry in which the first command of the second NAND die queue 14 is stored, and a Tail pointer indicating the position of the entry in which the last command is stored.

[0112] When a new command is added to the second NAND die queue 14, the controller 10 updates the value of the Link pointer of the entry pointed to by the Tail pointer so that the value points to the position of the entry storing the added command. The controller 10 also updates the value of the Tail pointer so that the value points to the position of the entry storing the added command. This adds the new command to the last entry of the second NAND die queue 14.

[0113] Commands are retrieved from the second NAND die queue 14 only from the first entry. When retrieving a command from the second NAND die queue 14, the controller 10 replaces the value of the Head pointer with the value of the Link pointer of the entry in which the command to be retrieved is stored. Note that the controller 10 sets the Head pointer and Tail pointer of the second NAND die queue 14, which has become empty after retrieving the command, to NULL pointers.

[0114] When implemented as described above, the amount of data required for one second NAND die queue 14 is 2+2=4 bytes, assuming that the Head pointer and Tail pointer each are 2 bytes (the total number of entries in the command table is 65,536 or less).

[0115] The first NAND die queue 13 and the second NAND die queue 14 commonly reference entries in the command table 17. Each entry in the command table 17 is referenced by either the first NAND die queue 13 or the second NAND die queue 14, or by neither. An entry in the command table 17 is never referenced by the first NAND die queue 13 and the second NAND die queue 14 at the same time.

[0116] As described above, the die queue status table 16 records, for each NAND die 21, a command presence / absence flag corresponding to each SQ 51, the SQ number being searched, and a command addition presence / absence flag.

[0117] The amount of data in the die queue status table 16 required per NAND die 21 is, for example, 256 bits + 15 bits + 1 bit = 272 bits = 34 bytes if the command presence / absence flag corresponding to each SQ51 is 1 bit (256 bits in total if there are 256 SQ51s), the SQ number being searched is 15 bits (the maximum number of SQ51s identified by the SQ number is 32,767), and the command addition presence / absence flag is 1 bit.

[0118] Therefore, the amount of data required for the first NAND die queue 13, second NAND die queue 14, and die queue status table 16 per NAND die 21 is 4+4+34=42 bytes. Therefore, the amount of data required for queue management of commands for 512 NAND dies 21 is 42×512=21K bytes.

[0119] On the other hand, for example, in the third comparative example described with reference to Fig. 6, NAND die queues are provided for each NAND die as many as the number of SQs. Therefore, if each NAND die queue consists of four bytes, a 2-byte Head pointer and a 2-byte Tail pointer, the amount of data required for command queue management is 512 (number of NAND dies) x 256 (number of SQs) x 4 bytes = 512K bytes.

[0120] In other words, the amount of memory required for queue management by the memory system 1 of the embodiment in which only the first command of each SQ51 for each NAND die 21 is stored in the second NAND die queue 14 is less than the amount of memory required for queue management by the memory system of the comparative example.

[0121] (Variation 1) When multiple first NAND die queues 13 are searched by one search engine 15, the search engine 15 may, for example, complete a search of all entries in one first NAND die queue 13 before starting a search of another first NAND die queue 13. Alternatively, the search engine 15 may suspend a search of one first NAND die queue 13 and start a search of another first NAND die queue 13 before completing a search of all entries in that first NAND die queue 13.

[0122] The number of entries in the first NAND die queue 13 that the search engine 15 targets in one search is determined by the search performance of the search engine 15 and the access time to the NAND die 21. To avoid degrading the performance of the memory system 1, the search in the first NAND die queue 13 must be completed by the time the access to the NAND die 21 is completed and the next command is retrieved from the second NAND die queue 14. Here, the number of entries is synonymous with the number of commands.

[0123] When a search of another first NAND die queue 13 is started after the search of all entries has been completed, a first NAND die queue 13 that takes a long time to complete the search may affect the command processing of the NAND die 21 corresponding to another first NAND die queue 13 that takes a short time to complete the search. On the other hand, by setting an upper limit on the number of entries (or search time) of the first NAND die queue 13 that the search engine 15 targets in one search, it is possible to prevent the command processing of the NAND die 21 corresponding to another first NAND die queue 13 that takes a short time to complete the search from being affected.

[0124] An example of a search of the first NAND die queue 13 in Modification 1 will be described with reference to FIG. 15. FIG. 15 illustrates an example in which the NAND memory 20 includes four NAND dies 21 (NAND dies [0-3]). FIG. 15 illustrates a state in which the search engine 15 repeatedly searches the four first NAND die queues 13 in the order of first NAND die queue [0], first NAND die queue [1], first NAND die queue [2], and first NAND die queue [3]. Here, command processing for each NAND die 21 (i.e., retrieval of a command from the second NAND die queue 14) is not initiated until the search processing for the first NAND die queue 13 associated with the previous command processing is completed. In other words, a mechanism for queuing multiple search requests for one first NAND die queue 13 is not provided.

[0125] 15A shows a case where the time required to complete searching all four first NAND die queues 13 is equal to or less than the time required to process one command. In this case, command processing for the four NAND dies 21 is executed without gaps.

[0126] 15(B) shows a case where the search processing time for the first NAND die queue [3] becomes longer, and the time required to complete the search of all four first NAND die queues 13 becomes longer than the command processing time. In this case, not only is the start of command processing for the NAND die [3] delayed, but the start of command processing for the other NAND dies [0-2] is also delayed. In other words, in this case, command processing for the four NAND dies 21 cannot be executed smoothly.

[0127] FIG. 15(C) shows an example in which an upper limit is set on the number of entries (or search time) in the first NAND die queue 13 that can be searched in one search, and the search of the first NAND die queue [3] is divided into two parts. The start of command processing for the NAND die [3] is delayed until the previous search process is completed, but this does not affect the start of command processing for the other NAND dies [0-2]. In other words, the start of command processing for the other NAND dies [0-2] is not delayed. By dividing the search of one first NAND die queue 13 in this way and limiting the number of entries (or search time) to be searched, the degradation of command processing performance can be limited to the NAND die [3], preventing a degradation of command processing performance for the other NAND dies [0-2].

[0128] (Variation 2) An example has been described above in which one second NAND die queue 14 is provided for each NAND die 21. The memory system 1 according to the second modification of the embodiment has two or more second NAND die queues 14 for each NAND die 21. FIG. 16 shows an example in which one first NAND die queue 13 (first NAND die queue[j]) and three second NAND die queues 14 (second NAND die queue[j] 14-1 to 14-3) are provided for a certain NAND die 21 (NAND die[j]).

[0129] 16 shows an example in which the host 2 has nine SQs [0-8] 51. The second NAND die queue [j] 14-1 is assigned SQs [0-2] 51. The second NAND die queue [j] 14-2 is assigned SQs [3-5] 51. The second NAND die queue [j] 14-3 is assigned SQs [6-8] 51.

[0130] The controller 10 determines from which of SQ[0-8] to take out a command, for example, by arbitration using a round robin method.

[0131] Here, it is assumed that SQ[1] is determined as the target.

[0132] If the die queue status table 16 does not record information indicating that the command of SQ[1] is stored in the second NAND die queue 14-1, the controller 10 stores the retrieved command of SQ[1] in the second NAND die queue [j] 14-1.

[0133] If the die queue status table 16 records information indicating that the command of SQ[1] is stored in the second NAND die queue 14-1, the controller 10 stores the retrieved command of SQ[1] in the first NAND die queue [j].

[0134] The controller 10 selects one of the three second NAND die queues [j] 14-1 to 14-3 by arbitration using a round-robin method, for example, and extracts the command from it. The controller 10 controls the processing of the NAND die [j] according to the extracted command.

[0135] For example, when command SQ[1] is retrieved from second NAND die queue [j] 14-1, the controller 10 searches for command SQ[1] from the beginning of the first NAND die queue [j] using the search engine 15. If command SQ[1] is detected, the controller 10 stores the detected command in second NAND die queue [j] 14-1.

[0136] FIG. 17 is a diagram for explaining queue management of commands executed using three second NAND die queues 14 for one NAND die 21. In FIG.

[0137] For example, suppose that host 2 has nine SQ51s (SQ[0-8]), and second NAND die queue [j] 14-1 is assigned SQ[0-2], second NAND die queue [j] 14-2 is assigned SQ[3-5], and second NAND die queue [j] 14-3 is assigned SQ[6-8].

[0138] The controller 10 determines the second NAND die queue 14 from which to retrieve a command from among the three second NAND die queues [j] 14-1 to 14-3, for example, by arbitration using a round robin method.

[0139] For example, if the second NAND die queue [j] 14-1 is determined as the second NAND die queue 14 from which to extract a command, the controller 10 extracts command 0 of SQ [1] stored at the beginning of the second NAND die queue [j] 14-1. After extracting command 0 of SQ [1], the controller 10 searches the first NAND die queue [j] for the next command of SQ [1] and moves the detected command 1 of SQ [1] to the end of the second NAND die queue [j] 14-1.

[0140] When the second NAND die queue [j] 14-2 is determined as the second NAND die queue 14 from which to extract the command, the controller 10 extracts command 0 of SQ [3] stored at the beginning of the second NAND die queue [j] 14-2. After extracting command 0 of SQ [3], the controller 10 searches the first NAND die queue [j] for the next command of SQ [3] and moves command 1 of the detected SQ [3] to the end of the second NAND die queue [j] 14-2.

[0141] Similarly, when the second NAND die queue [j] 14-3 is determined as the second NAND die queue 14 from which to extract a command, the controller 10 extracts command 0 of SQ [8] stored at the beginning of the second NAND die queue [j] 14-3. After extracting command 0 of SQ [8], the controller 10 searches the first NAND die queue [j] for the next command of SQ [8] and moves command 1 of the detected SQ [8] to the end of the second NAND die queue [j] 14-3.

[0142] In FIG. 17, the number of SQ51s assigned to each of the second NAND die queues [j] 14-1 to 14-3 is the same, but by changing the number of assigned SQ51s between the second NAND die queues [j] 14-1 to 14-3, the frequency at which commands are executed can be changed between the three groups of SQ51s.

[0143] For example, by assigning a relatively small number of SQ51s to the second NAND die queue [j] 14-1, in which commands requiring high responsiveness are stored, it is possible to execute the commands of the second NAND die queue [j] 14-1, overtaking commands that have been previously stored in other second NAND die queues [j] 14-2 to 14-3.

[0144] Alternatively, in arbitration for selecting the second NAND die queue 14 that retrieves a command from the three second NAND die queues [j] 14-1 to 14-3, the second NAND die queues [j] 14-1 to 14-3 may be selected with different frequencies.

[0145] For example, the host 2 may want to change the execution frequency of commands stored in each SQ 51 depending on the data transfer bandwidth and command response time required by each application. The memory system 1 according to the second modification of the embodiment can meet such a request from the host 2 by providing multiple second NAND die queues 14 for one NAND die 21.

[0146] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0147] 1...memory system, 2...host, 10...controller, 11...host interface section, 12...NAND interface section, 13...first NAND die queue, 14...second NAND die queue, 15...search engine, 16...die queue status table, 17...command table, 20...non-volatile memory, 21...memory die, 50...main memory, 51...SQ.

Claims

1. a non-volatile memory including at least one memory die; a controller capable of communicating with a host having at least one submission queue, each capable of storing a plurality of commands, electrically connected to the non-volatile memory, the controller including a first command queue corresponding to the at least one memory die and a second command queue corresponding to the at least one memory die; Equipped with The controller retrieving a first command from a first submission queue of the at least one submission queue; determining whether a second command retrieved from the first submission queue prior to the first command is stored in the second command queue; If the second command is stored in the second command queue, the first command retrieved from the first submission queue is stored in the first command queue; If the second command is not stored in the second command queue, the first command retrieved from the first submission queue is stored in the second command queue. Memory system.

2. The controller further comprises: and controlling access to the at least one memory die based on the first commands stored in the second command queue rather than the first command queue.

10. The memory system of claim 1.

3. the at least one memory die is a plurality of memory dies; the at least one submission queue is a plurality of submission queues; The controller further configures, for each of the plurality of memory dies: retrieve a third command from each of the plurality of submission queues; determining whether a fourth command retrieved from each of the plurality of submission queues prior to the third command is stored in the second command queue; If the fourth command is stored in the second command queue, the third command retrieved from each of the plurality of submission queues is stored in the first command queue; If the fourth command is not stored in the second command queue, the third command retrieved from each of the plurality of submission queues is stored in the second command queue.

10. The memory system of claim 1.

4. The controller further comprises: In response to retrieving the first command from the second command queue, searching the first command queue to find a fifth command that was removed from the first submission queue after the first command; When the fifth command is detected from the first command queue, the fifth command is retrieved from the first command queue and stored in the second command queue.

10. The memory system of claim 1.

5. The controller further comprises: In response to retrieving the sixth command from the first submission queue, determining whether a search for the fifth command is in progress; and storing the sixth command in the first command queue if a search for the fifth command is in progress.

5. The memory system of claim 4.

6. The controller further comprises: managing first information indicating whether a command retrieved from the first submission queue is stored in at least one of the first command queue and the second command queue; in response to the fifth command being detected from the first command queue, setting the first information to indicate that the command retrieved from the first submission queue is stored in at least one of the first command queue and the second command queue; and in response to the fifth command not being detected from the first command queue, setting the first information to indicate that the command retrieved from the first submission queue is not stored in either the first command queue or the second command queue.

5. The memory system of claim 4.

7. The controller further comprises: and in response to storing the first command in the second command queue, setting the first information to indicate that the command retrieved from the first submission queue is stored in at least one of the first command queue and the second command queue.

7. The memory system of claim 6.

8. The controller further comprises: managing second information indicating whether a command is being retrieved from the first submission queue; and when searching the first command queue to detect the fifth command, setting the second information to indicate that the fifth command is being searched for.

5. The memory system of claim 4.

9. the at least one memory die is a plurality of memory dies; the controller has a plurality of the first command queues corresponding to the plurality of memory dies, each of the plurality of first command queues including a first number of entries; The controller further comprises: when searching for commands stored in each of the plurality of first command queues, after searching for commands from a second number of the entries for one of the plurality of first command queues, which is less than the first number, a search for commands for another of the plurality of first command queues is started.

5. The memory system of claim 4.

10. the at least one submission queue is a plurality of submission queues, the plurality of submission queues including at least the first submission queue and a second submission queue; the controller has the first command queue corresponding to the at least one memory die and a plurality of second command queues corresponding to the at least one memory die, the plurality of second command queues including at least a third command queue and a fourth command queue; The controller further comprises: removing a seventh command from the first submission queue; storing the seventh command retrieved from the first submission queue in the third command queue; retrieve an eighth command from the first submission queue; storing the eighth command retrieved from the first submission queue in the first command queue; In response to retrieving the seventh command from the third command queue, retrieve the eighth command from the first command queue and store it in the third command queue; retrieve a ninth command from the second submission queue; storing the ninth command retrieved from the second submission queue in the fourth command queue; retrieve a tenth command from the second submission queue; storing the tenth command retrieved from the second submission queue in the first command queue; In response to retrieving the ninth command from the fourth command queue, the tenth command is retrieved from the first command queue and stored in the fourth command queue. The memory system according to any one of claims 1 to 9.

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