Semiconductor device and method of manufacturing the same

Abstract

To suppress expansion of a lamination defect existing in a semiconductor layer.SOLUTION: A semiconductor device includes a first semiconductor layer of a first conductivity type having a first surface and a second surface facing the first surface in a first direction and including a recombination center, and a second semiconductor layer of a second conductivity type opposite to the first conductivity type adjacent to the second surface. A maximum value appears in the distribution of the concentration of the recombination centers along the first direction at least at one position between the first surface and the second surface and away from both the first surface and the second surface.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] It is desirable to suppress the expansion of stacking faults in semiconductor devices. For example, stacking faults expand when a current is applied to a semiconductor device. Stacking faults originate from, for example, basal plane dislocations. For example, expansion of stacking faults in the substrate of a semiconductor device that uses silicon carbide as the semiconductor material (hereinafter also referred to as a "silicon carbide semiconductor device") is known. The expansion of stacking faults leads to an increase in the forward voltage of the semiconductor device. The increase in forward voltage leads to a deterioration in the reliability of the semiconductor device.

[0003] One example of a technique for suppressing the expansion of stacking faults due to the application of current is disclosed in Patent Document 1. Patent Document 1 discloses a silicon carbide semiconductor device in which a substrate, a boundary layer, and a drift layer, all of the same conductivity type, are stacked in this order. Both the boundary layer and the drift layer are formed by epitaxial growth. The boundary layer has a lower impurity concentration than the substrate, and the drift layer has a lower impurity concentration than the boundary layer.

[0004] Patent Document 1 exemplifies a case where the substrate is a single crystal substrate and contains basal plane dislocations. According to Patent Document 1, when defects exist in the crystal of the substrate, basal plane dislocations present in the substrate move due to recombination energy, and stacking faults sandwiched between two basal plane dislocations expand.

[0005] The boundary layer is provided to prevent crystal defects in the substrate from being transmitted to the drift layer. Protons injected near the interface between the substrate and the boundary layer act as lifetime killers, reducing the hole density at the interface. This reduces the recombination of holes and electrons (hereinafter simply referred to as "recombination") and suppresses the growth of crystal defects. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2022-17550 Summary of the Invention [Problem to be solved by the invention]

[0007] However, stacking faults exist not only in the substrate but also in the epitaxial layer. Application of current to a semiconductor device also expands stacking faults present in the epitaxial layer. It is presumed that Patent Document 1 is a technology that suppresses the growth of basal plane dislocations contained in the substrate into stacking faults. It is unclear whether the expansion of stacking faults inherent in a semiconductor layer provided on a substrate is suppressed by protons injected into the boundary between the semiconductor layer and the substrate.

[0008] The present disclosure aims to suppress the expansion of stacking faults inherent in a semiconductor layer. [Means for solving the problem]

[0009] A semiconductor device according to the present disclosure includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type opposite to the first conductivity type. The first semiconductor layer has a first surface and a second surface facing the first surface in a first direction and includes recombination centers. The second semiconductor layer is adjacent to the second surface. A maximum value appears in the distribution of the concentration of the recombination centers along the first direction at at least one position between the first surface and the second surface and away from both the first surface and the second surface. [Effects of the Invention]

[0010] According to the semiconductor device according to the present disclosure, the expansion of stacking faults present in the semiconductor layer is suppressed. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a cross-sectional view schematically illustrating a semiconductor device according to a first embodiment of the present disclosure. [Figure 2]1 is a cross-sectional view schematically illustrating a semiconductor device according to a first embodiment of the present disclosure. [Figure 3] 1 is a cross-sectional view schematically illustrating a semiconductor device according to a first embodiment of the present disclosure and the distribution of the concentration of recombination centers. [Figure 4] FIG. 10 is a cross-sectional view schematically illustrating a semiconductor device according to a second embodiment of the present disclosure. [Figure 5] FIG. 10 is a cross-sectional view schematically illustrating a semiconductor device according to a third embodiment of the present disclosure. [Figure 6] FIG. 10 is a cross-sectional view schematically illustrating a semiconductor device according to a fourth embodiment of the present disclosure. [Figure 7] FIG. 10 is a cross-sectional view schematically illustrating a semiconductor device according to a fifth embodiment of the present disclosure. [Figure 8] FIG. 13 is a cross-sectional view schematically illustrating a semiconductor device according to a sixth embodiment of the present disclosure. [Figure 9] FIG. 13 is a cross-sectional view schematically illustrating a semiconductor device according to a sixth embodiment of the present disclosure. [Figure 10] FIG. 12 is a cross-sectional view schematically illustrating a semiconductor device according to a seventh embodiment of the present disclosure. [Figure 11] FIG. 12 is a cross-sectional view schematically illustrating a semiconductor device according to a seventh embodiment of the present disclosure. [Figure 12] FIG. 12 is a cross-sectional view schematically illustrating a semiconductor device according to a seventh embodiment of the present disclosure. [Figure 13] FIG. 12 is a cross-sectional view schematically illustrating a semiconductor device according to a seventh embodiment of the present disclosure. [Figure 14] FIG. 13 is a cross-sectional view schematically illustrating a semiconductor device according to an eighth embodiment of the present disclosure. [Figure 15] FIG. 13 is a cross-sectional view schematically illustrating a semiconductor device according to an eighth embodiment of the present disclosure. [Figure 16] FIG. 13 is a cross-sectional view schematically illustrating a semiconductor device according to an eighth embodiment of the present disclosure. [Figure 17] FIG. 20 is a plan view schematically showing a wafer and a die according to a ninth embodiment of the present disclosure. [Figure 18] FIG. 2 is a plan view schematically showing one of the dies. [Figure 19] FIG. 20 is a plan view schematically showing a wafer and a die according to a ninth embodiment of the present disclosure. [Figure 20] FIG. 2 is a plan view schematically showing one of the dies. [Figure 21] FIG. 13 is a cross-sectional view schematically illustrating a semiconductor device according to a ninth embodiment of the present disclosure. [Figure 22] FIG. 13 is a cross-sectional view schematically illustrating a semiconductor device according to a ninth embodiment of the present disclosure. [Figure 23] FIG. 10 is a cross-sectional view schematically showing deformation of the termination region. [Figure 24] FIG. 22 is a cross-sectional view schematically showing a first example of the tenth embodiment. [Figure 25] FIG. 22 is a cross-sectional view schematically showing a second example of the tenth embodiment. [Figure 26] 1 is a flowchart outlining a process for manufacturing various semiconductor devices according to the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0012] The embodiments will be described with reference to the accompanying drawings. The drawings are diagrammatic. The relative sizes and positions of images shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. The same reference numerals are used for similar components, and their names and functions are also similar. Therefore, repeated detailed descriptions may be omitted.

[0013] In the following description, terms indicating specific positions and directions, such as "top," "bottom," "side," "bottom," "front," or "back," may be used. These terms are used for convenience to facilitate understanding of the contents of the embodiments. Therefore, these terms indicating positions and directions may not necessarily coincide with positions and directions when actually implemented. When directions are indicated in this disclosure, a right-handed XYZ coordinate system may be used.

[0014] In the embodiments of the present disclosure, the symbols "n" and "p" both indicate the conductivity type of a semiconductor. In the present disclosure, n-type conductivity can be considered as the first conductivity type, and p-type conductivity can be considered as the second conductivity type. The p-type conductivity can be used as the first conductivity type, and the n-type conductivity can be used as the second conductivity type.

[0015] The term "defects" as used in this disclosure includes point defects, line defects, and planar defects. For example, basal plane dislocations, micropipes, stacking faults, and lattice defects can be defects. For example, lattice defects act as recombination centers and can be formed by ion implantation, as described below.

[0016] As a semiconductor material, silicon carbide has a wider band gap and higher breakdown field strength than silicon. This contributes to increasing the impurity concentration and reducing resistance, which in turn contributes to reducing losses during switching in semiconductor devices. Silicon carbide also has high thermal conductivity, which provides excellent heat dissipation, contributing to the high efficiency and low losses of semiconductor devices made from it.

[0017] In the following embodiments and modifications, silicon carbide is used as an example of a semiconductor material, which tends to exhibit significant stacking fault expansion. However, the following embodiments and modifications can also be realized using semiconductor materials other than silicon carbide.

[0018] <1. First Embodiment> <1-1. Structure of planar insulated gate field effect transistor> 1 and 2 are cross-sectional views schematically illustrating a semiconductor device 100 according to a first embodiment of the present disclosure. FIG. 2 is a cross-sectional view of the semiconductor device 100 taken along direction X at position II-II in FIG. 1. FIG. 1 is a cross-sectional view of the semiconductor device 100 taken along direction Z at position II in FIG. 2. Hereinafter, the situation viewed along direction Z will also be referred to as "plan view" for convenience.

[0019] The semiconductor device 100 includes an active region R1 and a termination region R2. Position J is the boundary between the active region R1 and the termination region R2. The active region R1 is a region in the semiconductor device 100 that functions as an insulated gate field effect transistor. The termination region R2, for example, relieves electric field concentration at the edge of the active region R1 and suppresses deterioration of the breakdown voltage of the insulated gate field effect transistor. The termination region R2 is adjacent to the active region R1 and, for example, surrounds the active region R1 in a plan view.

[0020] The semiconductor device 100 includes an electrode 10, a gate pad 24, a gate wiring 21, and a protective insulating film 23, all of which are shown in Figure 1. The gate pad 24 and the gate wiring 21 are electrically connected, for example, they are continuous. A gate voltage is applied to the gate pad 24 to control whether the semiconductor device 100 is conductive or not.

[0021] As shown in FIG. 2, the semiconductor device 100 includes a substrate 1 and semiconductor layers 2, 3a, and 3b. The substrate 1 is made of n-type, low-resistivity silicon carbide. The semiconductor layer 2 is made of n-type, high-resistivity silicon carbide, and has surfaces 2s and 2t. The surface 2s is adjacent to the substrate 1. The surface 2t faces the surface 2s in the Z direction. For example, the surface 2s is flat, while the surface 2t is uneven. For example, the semiconductor layer 2 is a so-called epitaxial layer formed by epitaxial growth on the substrate 1. After epitaxial growth, the surface 2t is uneven because semiconductor layers 3a and 3b are formed on the semiconductor layer 2.

[0022] The semiconductor device 100 includes an electrode 11. The electrode 11 is adjacent to the substrate 1 on the side opposite to the semiconductor layer 2.

[0023] <1-1-1.Active region R1> 3 is a cross-sectional view schematically illustrating the semiconductor device 100 in a portion of the active region R1. The cross-section is taken along direction X. The cross-section may also appear as viewed along direction Y. FIG. 3 also schematically illustrates the distribution Q0 of the recombination center concentration Cr along direction Z.

[0024] The semiconductor layer 3a is located in the active region R1 and is adjacent to the surface 2t. The semiconductor layer 3a is made of p-type silicon carbide. 2 and 3 illustrate a case where the semiconductor layer 3a is located in a recess in the surface 2t, forming a so-called well region.

[0025] The semiconductor layers 3a may be arranged separately as shown in the figure, or may be connected to each other.

[0026] The semiconductor device 100 includes a semiconductor layer 5a. The semiconductor layer 5a is adjacent to the semiconductor layer 3a from the side opposite to the semiconductor layer 2. The semiconductor layer 5a is away from the surface 2t. The semiconductor layer 5a is made of n-type silicon carbide.

[0027] The semiconductor layer 4a is located in the active region R1 and is adjacent to the semiconductor layer 3a on the side opposite to the semiconductor layer 2. The semiconductor layer 4a is away from the surface 2t. The semiconductor layer 4a is also adjacent to the semiconductor layer 5a. The semiconductor layer 4a is made of p-type silicon carbide. The resistivity of the semiconductor layer 4a is lower than the resistivity of the semiconductor layer 3a. The semiconductor layer 4a is also commonly referred to as a well junction region.

[0028] An electrode 12a is adjacent to the semiconductor layers 4a and 5a from the side opposite the semiconductor layer 2. An electrode 10 is adjacent to the electrode 12a from the side opposite the semiconductor layer 2. The electrode 12a and the electrode 10 are electrically connected. A material that realizes an ohmic junction between the semiconductor layers 4a and 5a and the electrode 10 is used for the electrode 12a. The semiconductor layer 4a and the electrode 12a contribute to easy exchange of electrons and holes between the semiconductor layer 3a and the electrode 10. The electrode 12a contributes to easy exchange of electrons and holes between the semiconductor layer 5a and the electrode 10.

[0029] The semiconductor device 100 includes an insulating layer 6a and a conductive layer 7a. For example, the insulating layer 6a is made of silicon oxide. For example, the conductive layer 7a is made of polycrystalline silicon (also commonly known as "polysilicon").

[0030] The insulating layer 6a is adjacent to the semiconductor layers 2, 3a, and 5a, and extends from the semiconductor layer 2 across the semiconductor layer 3a to the semiconductor layer 5a. The conductive layer 7a faces the semiconductor layer 3a via the insulating layer 6a. The conductive layer 7a is connected to the gate wiring 21 via a conductive layer 7b (described later), for example, in the termination region R2. The conductive layer 7a is electrically connected to the gate pad 24 and functions as a gate electrode. In the semiconductor device 100, the insulating layer 6a and the conductive layer 7a both extend along the direction Y, forming a so-called planar insulated gate.

[0031] The portion of the semiconductor layer 3a facing the conductive layer 7a near the conductive layer 7a is commonly referred to as the channel region. The substrate 1, the electrode 11, the semiconductor layer 2, the semiconductor layer 5a, and the electrode 10 function as the drain region, the drain electrode, the drift region, the source region, and the source electrode, respectively, of the insulated gate field effect transistor.

[0032] The conductive layer 7a is covered with an interlayer insulating film 8a from the side opposite to the semiconductor layer 2. The interlayer insulating film 8a is interposed between the conductive layer 7a and the electrode 10 to insulate them from each other. The interlayer insulating film 8a is made of, for example, silicon oxide.

[0033] The semiconductor device 100 includes a semiconductor layer 3b, which is located not only in the active region R1 but also in the termination region R2.

[0034] The semiconductor layer 3b is adjacent to the surface 2t. The semiconductor layer 3b is made of p-type silicon carbide. FIG. 2 illustrates a case where the semiconductor layer 3b is located in a recessed portion of the surface 2t, forming a so-called well region. The semiconductor layers 3a and 3b are separated by the semiconductor layer 2, for example, by a protruding portion of the surface 2t.

[0035] The semiconductor device 100 includes a semiconductor layer 5b. The semiconductor layer 5b is adjacent to the semiconductor layer 3b on the side opposite to the semiconductor layer 2 in the active region R1. The semiconductor layer 5b is away from the surface 2t. The semiconductor layer 5b is made of n-type silicon carbide. The semiconductor layer 5b is adjacent to the semiconductor layer 4a that is adjacent to the termination region R2. Here, "adjacent" refers to a situation in which no other semiconductor layer 4a is located between the semiconductor layer 4a and the termination region R2. For example, the semiconductor layers 5a, 4a, and 5b are arranged in this order along the direction Y.

[0036] An electrode 12a is adjacent to the semiconductor layer 4a and the adjacent semiconductor layers 5a and 5b on the side opposite to the semiconductor layer 2. The electrode 12a also establishes an ohmic contact between the semiconductor layer 5b and the electrode 10.

[0037] A hole 27 is opened in the interlayer insulating film 8a. The electrode 12a is exposed from the interlayer insulating film 8a at the hole 27. The electrode 10 is connected to the electrode 12a at the hole 27. The hole 27 is also commonly called a contact hole. Since the hole 27 opens in the active region R1, it can be called an active region contact hole.

[0038] <1-1-2. Termination area R2> The semiconductor device 100 includes a semiconductor layer 4b and a field insulating film 8b in the termination region R2. The semiconductor layer 4b is adjacent to the semiconductor layer 3b on the side opposite to the semiconductor layer 2. For example, the semiconductor layers 4a, 5b, and 4b are arranged in this order along the direction Y. The semiconductor layer 4b is away from the surface 2t. The semiconductor layer 4b is made of p-type silicon carbide. The resistivity of the semiconductor layer 4b is lower than the resistivity of the semiconductor layer 3b. The semiconductor layer 4b is also commonly referred to as a well contact region.

[0039] Field insulating film 8b covers semiconductor layers 2, 3b, 4b in termination region R2 and termination structure 22 (described later) from the side opposite semiconductor layer 2, except for position J and its vicinity and the region where hole 26 (described later) opens.

[0040] Except for the region where a hole 26 (described later) opens, the insulating layer 6b covers the end of the semiconductor layer 5b on the termination region R2 side, the semiconductor layer 3b not covered with the field insulating film 8b, and the field insulating film 8b from the side opposite the semiconductor layer 2. The thickness of the insulating layer 6b is designed to be equal to the thickness of the insulating layer 6a, for example. The field insulating film 8b is designed to be thicker than the insulating layer 6b, for example.

[0041] The conductive layer 7a extends from the end of the semiconductor layer 5b on the termination region R2 side to the end of the semiconductor layer 4b on the active region R1 side, and covers the insulating layer 6b from the side opposite the semiconductor layer 2. The conductive layer 7b faces the semiconductor layer 4b via the field insulating film 8b and the insulating layer 6b. The conductive layers 7a and 7b are aligned along the Y direction.

[0042] The interlayer insulating film 8a extends from the end of the semiconductor layer 5b on the termination region R2 side to the termination region R2, covering the field insulating film 8b, insulating layer 6b, and conductive layers 7a and 7b from the side opposite the semiconductor layer 2, except for the areas where holes 25 and 26 described below are opened.

[0043] A hole 26 is opened in the insulating layer 6b and the field insulating film 8b. The hole 26 penetrates the insulating layer 6b. In the hole 26, an electrode 12b is adjacent to the semiconductor layer 4b from the side opposite the semiconductor layer 2. In the hole 26, the electrode 12b is exposed from the interlayer insulating film 8a, the field insulating film 8b, and the insulating layer 6b.

[0044] Electrode 10 is adjacent to electrode 12b on the opposite side to semiconductor layer 2. Electrode 10 is connected to electrode 12b through hole 26. Electrode 12b is made of a material that provides an ohmic junction between electrode 10 and semiconductor layer 4b. Electrode 10 is connected to electrode 12b through hole 26. Semiconductor layer 4b and electrode 12b contribute to easy exchange of electrons and holes between semiconductor layer 3b and electrode 10.

[0045] Hole 26 is also commonly referred to as a contact hole. Because hole 26 opens in termination region R2, it can be called a termination region contact hole.

[0046] Electrode 12b does not establish an ohmic contact between semiconductor layer 3b and electrode 10, and does not connect semiconductor layers 3b and 4b to each other. For example, in a plan view, hole 26 is located within the region occupied by semiconductor layer 4b, and electrode 12b is not adjacent to semiconductor layer 3b.

[0047] The range in which the semiconductor layer 4b is formed along the direction Y in the cross section viewed along the direction X does not need to cover the entire semiconductor layer 3b, but may be partial.

[0048] In termination region R2, interlayer insulating film 8a has hole 25. Part of conductive layer 7b is exposed from interlayer insulating film 8a in hole 25.

[0049] Gate wiring 21 partially covers interlayer insulating film 8a in termination region R2 and is connected to conductive layer 7b through hole 25. Conductive layer 7a is electrically connected to gate pad 24 via gate wiring 21 and conductive layer 7b, and functions as a gate electrode.

[0050] The holes 25 are also commonly called contact holes. The holes 25 are involved in the connection between the gate wiring 21 and the conductive layer 7b, and therefore may be called gate contact holes.

[0051] The semiconductor device 100 includes a termination structure 22 in the termination region R2. The termination structure 22 is located on the opposite side of the semiconductor layer 3b from the semiconductor layer 3a. For example, the termination structure 22 is adjacent to the semiconductor layer 3b. For example, the termination structure 22 may be a structure commonly known as a JTE (Junction Termination Extension) that uses p-type silicon carbide with a lower impurity concentration than the semiconductor layer 3b. Alternatively, the termination structure 22 may be a structure commonly known as a FLR (Field Limiting Ring). Alternatively, the termination structure 22 may be a combination of a JTE and an FLR.

[0052] The semiconductor device 100 includes a protective insulating film 23. In the termination region R2, the protective insulating film 23 covers the electrode 10, the interlayer insulating film 8a, and at least a part of the gate wiring 21 from the side opposite the semiconductor layer 2. FIG. 2 illustrates a state in which the entire gate wiring 21 is covered with the protective insulating film 23.

[0053] <1-2. Recombination center concentration distribution> When defects exist in the substrate 1 or the semiconductor layer 2, carriers injected into the semiconductor layer 2 are trapped by the defects when a current is applied between the electrodes 10 and 11. This trapping reduces the defect energy and causes the stacking faults to expand. This tendency is particularly noticeable when silicon carbide is used as the semiconductor material.

[0054] By causing the carriers to disappear in the recombination centers before they are captured by the defects, the capture is suppressed, which in turn contributes to suppressing the expansion of stacking faults present in the semiconductor layer 2.

[0055] The semiconductor layer 2 has recombination centers. For example, recombination centers are introduced into the semiconductor layer 2 by implanting protons or helium. Such recombination centers function as lifetime killers as described in Patent Document 1.

[0056] 2 and 3, a position LK is shown where the concentration Cr reaches a maximum value Cp, which is a concentration peak, in the distribution Q0.

[0057] 3, the concentration Cr exhibits a distribution Q0 between a value Cd and a maximum value Cp. The value Cd conveniently indicates the concentration Cr in a region where fluctuations are small, and in reality, the fluctuation range may be small. For example, the value Cd is a baseline value for the concentration Cr.

[0058] Position LK is between surfaces 2s and 2t and is spaced from surface 2s. Position LK is between semiconductor layer 3a and surface 2s. Referring to Figure 2, semiconductor layer 2 is divided along direction Z into region S1 extending from position B1 to position B2 and region S2 extending from position B2 to position B3. Figure 2 illustrates a case where the bottom of the recess in surface 2t, position LK, and surface 2s are independent of direction Y.

[0059] Position B1 is the position in direction Z of the bottom of the recess on surface 2t. Position B1 can also be seen as the position in direction Z of the end of semiconductor layer 3a on the surface 2s side. Position B2 is the position in direction Z of position LK. Position B3 is the position in direction Z of surface 2s.

[0060] In Patent Document 1, protons are injected near the interface between the epitaxial layer and the substrate, so that application of a current can cause stacking faults in the epitaxial layer to extend from the substrate side of the epitaxial layer to the opposite side.

[0061] In contrast, in the semiconductor device 100, the recombination center concentration reaches a maximum at position B2, which is far from surface 2s, in the semiconductor layer 2, which is an epitaxial layer. Therefore, even if stacking faults expand in the epitaxial layer due to the application of current, the expansion range is limited to only one of regions S1 and S2. This contributes to reducing the area of ​​expanding stacking faults compared to conventional methods.

[0062] The position LK can be estimated by measuring the ion concentration distribution in the semiconductor layer 2 when protons or helium are implanted, for example, by using secondary ion mass spectrometry (SIMS). After the semiconductor device 100 is manufactured, the position LK can also be estimated by performing deep level transient spectroscopy (DLTS) measurement in the semiconductor layer 2.

[0063] The end of semiconductor layer 3a opposite semiconductor layer 2, the end of semiconductor layers 4a and 5a opposite semiconductor layer 2, and the position of surface 2t farthest from surface 2s (which can also be said to be the end of the convex portion of surface 2t) are all at the same position in direction Z, and the following description will be given assuming that this position is the reference position in direction Z.

[0064] Introducing the thickness D0 of the semiconductor layer 3a along the direction Z (which can also be considered the distance from the reference position at position B1 in the above assumption), the thickness S of the semiconductor layer 2 along the direction Z from the surface 2s to the semiconductor layer 3a, and the distance Dp from the reference position (which can also be considered the distance from the reference position at position B2), the following inequality (1) is expressed. A maximum value Cp appears in the distribution Q0 at the distance Dp that satisfies this inequality. In this case, the position LK is at the distance Dp from the reference position.

[0065]

number

[0066] If the concentration Cr is not taken into consideration, stacking faults may extend from the surface 2s to the semiconductor layer 3a in the semiconductor layer 2. Even if stacking faults extend in the semiconductor layer 2 due to the application of current, if the concentration Cr reaches a peak at the position LK, the range is limited to only one of the regions S1 and S2.

[0067] Therefore, when the distance Dp satisfies the following formula (2) (in this case, the inequality (1) is always satisfied), the range of the stacking fault expansion does not exceed half of the range in the case where no recombination centers are introduced. When the distance Dp satisfies the following formula (2), the effect of suppressing the expansion of the stacking fault is higher than when the following formula (2) is not satisfied even if the inequality (1) is satisfied.

[0068]

number

[0069] It can be said that when formula (2) is satisfied, a maximum value Cp appears in the distribution Q0 in the center in the direction Z between the semiconductor layer 3a and the surface 2s.

[0070] <2. Second Embodiment> 4 is a cross-sectional view schematically illustrating a semiconductor device 101 according to a second embodiment of the present disclosure. Like FIG. 3, FIG. 4 illustrates a cross-section of the semiconductor device 101 in a portion of the active region R1 (see FIG. 2) viewed along direction X. The cross-section may also appear as viewed along direction Y. FIG. 4 also schematically illustrates a distribution Q1 of the recombination center concentration Cr along direction Z.

[0071] The difference between the semiconductor device 101 and the semiconductor device 100 is the difference between the distribution Q1 and the distribution Q0, so a description of other components, such as the semiconductor layer, the conductive layer, and the insulating film, will be omitted.

[0072] The concentration Cr has multiple maximum values ​​Cp1 and Cp2. At distances Dp1 and Dp2 in the direction Z, the maximum values ​​Cp1 and Cp2 appear in the distribution Q1, respectively.

[0073] In Figure 4, positions LK1 and LK2 indicate the positions where local maxima Cp1 and Cp2 appear, respectively. Position LK1 is at a distance Dp1 from the reference position in direction Z. Position LK2 is at a distance Dp2 from the reference position in direction Z. As in the first embodiment, thicknesses D0 and S are introduced to show inequality (3). Local maxima Cp1 and Cp2 appear in distribution Q1 at distances Dp1 and Dp2 that satisfy this inequality.

[0074]

number

[0075] When the distances Dp1 and Dp2 satisfy the following formula (4) (in this case, inequality (3) is always satisfied), the range of stacking fault expansion does not exceed one-third of the range in which no recombination centers are introduced. When the distances Dp1 and Dp2 satisfy the following formula (4), the effect of suppressing the expansion of stacking faults is higher than when inequality (3) is satisfied but formula (4) is not satisfied.

[0076]

number

[0077] In the semiconductor layer 2, the concentration Cr may have a maximum value at three or more positions along the direction Z. For example, if there are n such positions, each at a distance Dp1, Dp2, ..., Dpn from a reference position along the direction Z, an integer r between 1 and n is introduced to satisfy the following formula (5). In this case, the positions where the concentration Cr has a maximum value are equally spaced along the direction Z. Satisfying the following formula (5) enhances the effect of suppressing the expansion of stacking faults. This is because the range of stacking fault expansion does not exceed 1 / (n+1) of the range in the case where recombination centers are not introduced.

[0078]

number

[0079] <3. Embodiment 3> 5 is a cross-sectional view schematically illustrating a semiconductor device 102 according to a third embodiment of the present disclosure. Similar to FIG. 3, FIG. 5 illustrates a cross-section of the semiconductor device 102 in a portion of the active region R1 (see FIG. 2) viewed along direction X. The cross-section may also appear as viewed along direction Y. FIG. 5 also schematically illustrates a distribution Q2 of the recombination center concentration Cr along direction Z.

[0080] The difference between the semiconductor device 102 and the semiconductor device 100 is the difference between the distribution Q2 and the distribution Q0, so a description of other components, such as the semiconductor layer, the conductive layer, and the insulating film, will be omitted.

[0081] The concentration Cr has multiple maximum values ​​Cp1, Cp2, and Cp3. At multiple distances Dp1, Dp2, and Dp3 in the direction Z, the maximum values ​​Cp1, Cp2, and Cp3 appear in the distribution Q2, respectively.

[0082] 5, positions LK1, LK2, and LK3 indicate positions where local maxima Cp1, Cp2, and Cp3 appear, respectively. Position LK1 is at a distance Dp1 from the reference position in direction Z. Position LK2 is at a distance Dp2 from the reference position in direction Z.

[0083] As in the second embodiment, maximum values ​​Cp1 and Cp2 appear in the distribution Q2 at distances Dp1 and Dp2, respectively, that satisfy inequality (3) by introducing thicknesses D0 and S. When equation (4) is satisfied as in the second embodiment, the effect of suppressing the expansion of stacking faults is higher than when equation (4) is not satisfied even if inequality (3) is satisfied.

[0084] Unlike the semiconductor device 101, the semiconductor device 102 has a maximum value Cp3 in the distribution Q2 at a distance (D0+S) from the reference position in the direction Z. It can also be said that the maximum value Cp3 appears in the distribution Q2 on the surface 2s. It can also be said that the position LK3 is at the interface between the substrate 1 and the semiconductor layer 2.

[0085] The fact that the concentration of recombination centers has a maximum value at the position LK3 contributes to suppressing the expansion of stacking faults originating from basal plane dislocations present in the substrate 1.

[0086] Position LK1 may not exist in semiconductor device 102. In this case, position LK2 is treated equivalently to position LK shown in semiconductor device 100. Alternatively, position LK2 may not exist in semiconductor device 102. In this case, position LK1 is treated equivalently to position LK shown in semiconductor device 100. As in the first embodiment, inequality (1), and preferably equation (2), is satisfied.

[0087] As in the second embodiment, when there are n positions where the concentration Cr has a maximum value, each of which is located at a distance Dp1, Dp2, ..., Dpn from the reference position along the direction Z, the following formula (6) is satisfied by introducing an integer r between 1 and n. In this case, the positions where the concentration Cr has a maximum value are equally spaced along the direction Z. It can also be said that the surface 2s is located at a distance Dpn from the reference position.

[0088] Satisfying the following formula (6) enhances the effect of suppressing the expansion of stacking faults, because the range of expansion of stacking faults does not exceed 1 / n of the range in the case where recombination centers are not introduced.

[0089]

number

[0090] <4. Embodiment 4> 6 is a cross-sectional view schematically illustrating a semiconductor device 103 according to a fourth embodiment of the present disclosure. Like FIG. 3, FIG. 6 illustrates a cross-section of the semiconductor device 103 in a portion of the active region R1 (see FIG. 2) viewed along direction X. The cross-section may also appear as viewed along direction Y. FIG. 6 also schematically illustrates a distribution Q3 of the recombination center concentration Cr along direction Z.

[0091] The difference between semiconductor device 103 and semiconductor device 101 is whether or not semiconductor layer 9 is present, and distribution Q3 is not substantially different from distribution Q1. Therefore, explanations of other components, such as the semiconductor layer, conductive layer, and insulating film, will be omitted.

[0092] The semiconductor device 103 includes a semiconductor layer 9. The semiconductor layer 9 is located between a substrate 1 and a semiconductor layer 2. The semiconductor layer 2, the semiconductor layer 9, and the substrate 1 are arranged in this order along the direction Z. The semiconductor layer 9 functions as a boundary layer as described in Patent Document 1, for example. Alternatively, the semiconductor layer 9 may also be commonly referred to as a buffer layer, for example.

[0093] The semiconductor layer 9 is made of n-type silicon carbide. The impurity concentration of the semiconductor layer 9 is higher than the impurity concentration of the semiconductor layer 2. For example, the impurity concentration of the semiconductor layer 9 is 1×10 18cm -3 Greater than or equal to 1 x 10 19 cm -3 The maximum impurity concentration of the semiconductor layer 2 is 1×10 18 cm -3 For example, the impurity concentration of the semiconductor layer 9 is less than 5×10 18 cm -3 The thickness of the semiconductor layer 9 is, for example, not less than 0.5 μm and not more than 5 μm.

[0094] For example, the semiconductor layer 9 is an epitaxial layer obtained by epitaxial growth on the substrate 1. For example, the semiconductor layers 2 and 9 are both epitaxial layers on the substrate 1, and are distinguished from each other by the impurity concentrations described above.

[0095] The semiconductor layer 9 has the above impurity concentration and thickness, for example, 500 A / cm 2 Even when a current is applied at a high current density of 1000 .mu.m or more, this contributes to suppressing the expansion of stacking faults originating from basal plane dislocations present in the substrate 1. The thickness of the semiconductor layer 9 may be as thin as 0.3 μm or as thick as 10 μm.

[0096] In addition to the effects of the semiconductor device 101, the semiconductor device 103 has the effects brought about by the semiconductor layer 9 described above.

[0097] In semiconductor device 103, as in semiconductor device 102, either position LK1 or LK2 may be absent. If position LK1 is absent, position LK2 is treated equivalently to position LK shown in semiconductor device 100. If position LK2 is absent, position LK1 is treated equivalently to position LK shown in semiconductor device 100. As in embodiment 1, inequality (1), and preferably equation (2), is satisfied.

[0098] As in the second embodiment, for example, when there are n positions where the concentration Cr has a maximum value, and each is at a distance Dp1, Dp2, ..., Dpn from the reference position along the direction Z, equation (5) is satisfied by introducing an integer r between 1 and n.

[0099] <5. Embodiment 5> 7 is a cross-sectional view schematically illustrating a semiconductor device 104 according to a fifth embodiment of the present disclosure. Similar to FIG. 3, FIG. 7 illustrates a cross-section of the semiconductor device 104 in a portion of the active region R1 (see FIG. 2) viewed along direction X. The cross-section may also appear as viewed along direction Y. FIG. 7 also schematically illustrates a distribution Q4 of the recombination center concentration Cr along direction Z.

[0100] The difference between the semiconductor device 104 and the semiconductor device 103 is whether or not there is a position LK3 where the concentration has a maximum value. Therefore, explanations of other aspects, such as the semiconductor layer, the conductive layer, and the insulating film, will be omitted.

[0101] Like the semiconductor device 103, the semiconductor device 104 also includes a semiconductor layer 9. The position LK3 is in the semiconductor layer 9. The position LK3 may be on the surface 2s or at the interface between the semiconductor layer 9 and the substrate 1.

[0102] Inequality (7) is given by introducing thickness Tb of semiconductor layer 9 along direction Z and multiple distances Dp1, Dp2, and Dp3 in direction Z at which distribution Q4 exhibits maximal values ​​Cp1, Cp2, and Cp3, respectively (see embodiment 3 and inequality (3)).

[0103]

number

[0104] Due to the presence of position LK3, the semiconductor device 104 can obtain the effects of the semiconductor layer 9 even if the thickness Tb and the impurity concentration of the semiconductor layer 9 are reduced compared to the semiconductor device 103. Compared to the semiconductor device 103, the semiconductor device 104 can obtain the same effects at a lower cost.

[0105] Compared to the semiconductor device 102, the semiconductor device 104 has the semiconductor layer 9, which increases the range of current densities at which the expansion of stacking faults originating from basal plane dislocations present in the substrate 1 can be suppressed.

[0106] When the distances Dp1 and Dp2 satisfy the formula (4), the range of the stacking fault expansion does not exceed one-third of that when no recombination centers are introduced. When the distances Dp1 and Dp2 satisfy the formula (4), the effect of suppressing the expansion of the stacking fault is higher than when the formula (7) is not satisfied, even if the formula (7) is satisfied.

[0107] The surface 2s is directly adjacent to the substrate 1 in the semiconductor devices 100, 101, and 102, and is indirectly adjacent to the substrate 1 via the semiconductor layer 9 in the semiconductor devices 103 and 104. Therefore, it can also be expressed that the semiconductor layer 2 is directly or indirectly adjacent to the substrate 1.

[0108] Alternatively, the substrate 1 can include a region having the above-mentioned impurity concentration and adjacent to the surface 2s on the semiconductor layer 2 side, and this region can be understood as the semiconductor layer 9. In this case, it can also be said that the semiconductor layer 2 is adjacent to the substrate 1, and in particular adjacent to the semiconductor layer 9 as this region.

[0109] In the semiconductor device 104, as in the semiconductor device 102, either one of the positions LK1 and LK2 may be absent. If the position LK1 is absent, the position LK2 is treated equivalently to the position LK shown in the semiconductor device 100. If the position LK2 is absent, the position LK1 is treated equivalently to the position LK shown in the semiconductor device 100. As in the first embodiment, inequality (1), preferably equation (2), is satisfied.

[0110] As in the third embodiment, when there are n positions where the concentration Cr has a maximum value, each of which is at a distance Dp1, Dp2, ..., Dpn from the reference position along the direction Z, an integer q between 1 and n is introduced to satisfy the following formula (8). Satisfying formula (8) enhances the effect of suppressing the expansion of stacking faults, because the range of stacking fault expansion does not exceed 1 / n of the range in the case where no recombination centers are introduced.

[0111]

number

[0112] <6. Embodiment 6> <6-1. Structure of trench-type insulated gate field-effect transistor> Fig. 8 is a cross-sectional view schematically illustrating a semiconductor device 200 according to a sixth embodiment of the present disclosure. Fig. 8 is a cross-sectional view of the semiconductor device 200 taken along direction X at position II-II in Fig. 1. Fig. 1 is also a cross-sectional view of the semiconductor device 200 taken along direction Z at position II in Fig. 8.

[0113] The semiconductor device 200 also includes an active region R1 and a termination region R2, similar to the semiconductor devices 100 to 104. Position J is the boundary between the active region R1 and the termination region R2.

[0114] 8, the semiconductor device 200 includes a substrate 1, semiconductor layers 2 and 3a, and an electrode 11. The materials, conductivity types, and resistivities of the substrate 1, semiconductor layer 2, and semiconductor layer 3a are the same as those in the first embodiment, and details thereof will be omitted.

[0115] <6-1-1.Active region R1> 9 is a cross-sectional view schematically illustrating a portion of the active region R1 of the semiconductor device 200. The cross-section is taken along the X direction. The cross-section may also be viewed along the Y direction. FIG. 9 also shows a schematic distribution Q5 of the recombination center concentration Cr along the Z direction.

[0116] The semiconductor layer 3a is located in the active region R1 and is adjacent to the surface 2t. Figures 8 and 9 illustrate a case where the semiconductor layer 3a is adjacent to the convex portion of the surface 2t from the side opposite to the surface 2s.

[0117] The semiconductor device 200 includes semiconductor layers 4a and 5a and electrodes 10 and 12a.

[0118] The semiconductor layer 5a is adjacent to the semiconductor layer 3a from the side opposite to the semiconductor layer 2. The semiconductor layer 5a is away from the surface 2t. The semiconductor layer 5a is made of n-type silicon carbide.

[0119] The semiconductor layer 4a is located in the active region R1 and is adjacent to the semiconductor layer 3a on the opposite side to the semiconductor layer 2. The semiconductor layer 4a is away from the surface 2t. For example, the semiconductor layers 5a, 3a, and 2 are arranged in this order along the direction Z. For example, the semiconductor layers 4a, 3a, and 2 are arranged in this order along the direction Z.

[0120] The semiconductor layer 4a is made of p-type silicon carbide. The resistivity of the semiconductor layer 4a is lower than the resistivity of the semiconductor layer 3a. The semiconductor layer 4a is also commonly called a well contact region.

[0121] An electrode 12a is adjacent to the semiconductor layers 4a and 5a from the side opposite the semiconductor layer 2. An electrode 10 is adjacent to the electrode 12a from the side opposite the semiconductor layer 2. The electrode 12a and the electrode 10 are electrically connected. A material that realizes an ohmic junction between the semiconductor layers 4a and 5a and the electrode 10 is used for the electrode 12a. The semiconductor layer 4a and the electrode 12a contribute to easy exchange of electrons and holes between the semiconductor layer 3a and the electrode 10. The electrode 12a contributes to easy exchange of electrons and holes between the semiconductor layer 5a and the electrode 10.

[0122] The semiconductor device 200 includes an insulating layer 6t and a conductive layer 7t. For example, the insulating layer 6t is made of silicon oxide. For example, the conductive layer 7t is made of polycrystalline silicon (polysilicon).

[0123] The insulating layer 6t is adjacent to the semiconductor layers 2, 3a, and 5a, and extends from the semiconductor layer 2 across the semiconductor layer 3a to the semiconductor layer 5a. The conductive layer 7t faces the semiconductor layers 2, 3a, and 5a via the insulating layer 6t.

[0124] The conductive layer 7t is connected to the gate wiring 21, for example, in the termination region R2, via a conductive layer 7b (described later). The conductive layer 7t is electrically connected to the gate pad 24 and functions as a gate electrode. In the semiconductor device 200, the insulating layer 6t and the conductive layer 7t both extend along the direction Z, and form a so-called trench-type insulated gate TG.

[0125] The portion of the semiconductor layer 3a facing the conductive layer 7t near the conductive layer 7t is commonly referred to as a channel region. As in the semiconductor device 100, the substrate 1, the electrode 11, the semiconductor layer 2, and the semiconductor layer 5a function as the drain region, the drain electrode, the drift region, and the source region, respectively, of an insulated gate field effect transistor.

[0126] The conductive layer 7t is covered with an interlayer insulating film 8a from the side opposite to the semiconductor layer 2. The interlayer insulating film 8a is interposed between the conductive layer 7t and the electrode 10 to insulate them from each other. The interlayer insulating film 8a is made of, for example, silicon oxide.

[0127] The semiconductor device 200 includes a semiconductor layer 13a. The semiconductor layer 13a is adjacent to the insulated gate TG and is located at the end of the insulated gate TG on the surface 2s side. The semiconductor layer 13a is adjacent to the surface 2t. The semiconductor layer 13a is made of p-type silicon carbide. FIG. 9 illustrates a case in which the semiconductor layer 13a is located in a recess in the surface 2t and is surrounded by the insulated gate TG and the semiconductor layer 2. The semiconductor layer 13a contributes to reducing the electric field applied to the insulated gate TG at a position where the insulating layer 6t bends between the directions Y and Z when viewed along the direction X.

[0128] The semiconductor device 200 includes a semiconductor layer 5b. The semiconductor layer 5b is adjacent to the semiconductor layer 3a on the side opposite to the semiconductor layer 2 in the active region R1. The semiconductor layer 5b is away from the surface 2t. The semiconductor layer 5b is made of n-type silicon carbide. The semiconductor layer 5b is adjacent to the semiconductor layer 4a that is adjacent to the termination region R2. Here, "adjacent" refers to a situation in which no other semiconductor layer 4a is located between the semiconductor layer 4a and the termination region R2. For example, the semiconductor layers 5a, 4a, and 5b are arranged in this order along the direction Y.

[0129] An electrode 12a is adjacent to the semiconductor layer 4a and the adjacent semiconductor layers 5a and 5b on the side opposite to the semiconductor layer 2. The electrode 12a also establishes an ohmic contact between the semiconductor layer 5b and the electrode 10.

[0130] Holes 27, which are commonly called contact holes and may be called active region contact holes, are formed in the interlayer insulating film 8a. The electrodes 12a are exposed from the interlayer insulating film 8a in the holes 27. The electrodes 10 are connected to the electrodes 12a in the holes 27.

[0131] <6-1-2. Termination area R2> The semiconductor device 200 includes an insulating layer 6b and a conductive layer 7b. The insulating layer 6b and the conductive layer 7b are provided from the active region R1 across position J to the termination region R2. Specifically, the insulating layer 6b is provided from above a portion of the semiconductor layer 5b on the side opposite to the semiconductor layer 5a to above a portion of the termination region R2 on the active region R1 side. In FIG. 8, "above" an object refers to a position farther from the object as viewed from the semiconductor layer 2.

[0132] Insulating layer 6b bends toward face 2s from active region R1 toward termination region R2 near position J. At least near position J, the distance between insulating layer 6b and face 2s in termination region R2 is shorter than the distance between insulating layer 6t and face 2s in active region R1.

[0133] Conductive layer 7b is provided on insulating layer 6b, extending from above a portion of semiconductor layer 5b on the side opposite semiconductor layer 5a to above a portion of termination region R2 on the active region R1 side. Figure 8 illustrates a case in which conductive layer 7b does not partially cover both ends of insulating layer 6b along a direction (Y direction in Figure 8) non-parallel to the direction in which the boundary between active region R1 and termination region R2 extends (X direction in Figure 8). This case can also be said to be a case in which both ends of insulating layer 6b are exposed from conductive layer 7b.

[0134] The conductive layer 7b faces the semiconductor layers 5b, 3a, and 2 in direction Y via the insulating layer 6b. Therefore, the conductive layer 7b and the insulating layer 6b near position J may function as an insulated gate TG, similar to the conductive layer 7t and the insulating layer 6t in the active region R1. In this case, the portion of the semiconductor layer 3a in the active region R1 near position J that faces the conductive layer 7b is a channel region.

[0135] The semiconductor device 200 includes semiconductor layers 4b and 13b in the termination region R2. The semiconductor layers 4b and 13b partially cover the surface 2t of the semiconductor layer 2. The semiconductor layer 13b is adjacent to the surface 2t. The semiconductor layer 13b is made of p-type silicon carbide. FIG. 2 illustrates an example in which the semiconductor layer 13b is located in a recess in the surface 2t. The semiconductor layers 13a and 13b are separated by the semiconductor layer 2, for example, by a protrusion in the surface 2t.

[0136] The semiconductor layer 4b is adjacent to the semiconductor layer 13b on the side opposite to the semiconductor layer 2. The semiconductor layer 4b is away from the surface 2t. The semiconductor layer 4b is made of p-type silicon carbide. The resistivity of the semiconductor layer 4b is lower than the resistivity of the semiconductor layer 13b. The semiconductor layer 4b is also commonly referred to as a well contact region.

[0137] 8 illustrates a case where semiconductor layer 4b does not partially cover both ends of semiconductor layer 13b along a direction (Y direction in FIG. 8) non-parallel to the direction in which the boundary between active region R1 and termination region R2 extends (X direction in FIG. 8). This case can also be said to be a case where both ends of semiconductor layer 13b are exposed from semiconductor layer 4b.

[0138] Semiconductor device 200 includes field insulating film 8b in termination region R2. Field insulating film 8b covers semiconductor layers 2, 13b, and 4b in termination region R2 and termination structure 22 (described later) from the side opposite semiconductor layer 2, except for a region where hole 26 (described later) opens.

[0139] Insulating layer 6b covers the end of semiconductor layer 5b on the termination region R2 side, semiconductor layers 13b and 4b in the region not covered with field insulating film 8b, and field insulating film 8b from the side opposite semiconductor layer 2. The thickness of insulating layer 6b is designed to be equal to the thickness of insulating layer 6t, for example. Field insulating film 8b is designed to be thicker than insulating layer 6b, for example.

[0140] Conductive layer 7b extends from the end of semiconductor layer 5b on the termination region R2 side to the end of semiconductor layer 4b on the active region R1 side, straddling semiconductor layer 13b, and covering insulating layer 6b from the side opposite semiconductor layer 2. Conductive layer 7b faces semiconductor layer 4b via insulating layer 6b or via field insulating film 8b and insulating layer 6b.

[0141] The interlayer insulating film 8a extends from the end of the semiconductor layer 5b on the termination region R2 side to the termination region R2, covering the field insulating film 8b, insulating layer 6b, and conductive layer 7b from the side opposite the semiconductor layer 2, except for the areas where holes 25 and 26 described below are opened.

[0142] A hole 26 is opened in the insulating layer 6b and the field insulating film 8b. The hole 26 penetrates the insulating layer 6b. In the hole 26, an electrode 12b is adjacent to the semiconductor layer 4b from the side opposite the semiconductor layer 2. An electrode 10 is adjacent to the electrode 12b from the side opposite the semiconductor layer 2. The electrode 12b and the electrode 10 are electrically connected. The electrode 12b is exposed from the interlayer insulating film 8a, the field insulating film 8b, and the insulating layer 6b in the hole 26.

[0143] Electrode 10 is adjacent to electrode 12b on the opposite side to semiconductor layer 2. Electrode 10 is connected to electrode 12b through hole 26. A material that realizes ohmic contact between electrode 10 and semiconductor layer 4b is used for electrode 12b. Electrode 10 is connected to electrode 12b through hole 26.

[0144] Hole 26 is also commonly referred to as a contact hole. Because hole 26 opens in termination region R2, it can be called a termination region contact hole.

[0145] Electrode 12b does not establish an ohmic junction between semiconductor layer 13b and electrode 10, and does not connect semiconductor layers 13b and 4b to each other. For example, in a plan view, hole 26 is located within the region occupied by semiconductor layer 4b, and electrode 12b is not adjacent to semiconductor layer 13b.

[0146] The range in which the semiconductor layer 4b is formed along the direction Y in the cross section viewed along the direction X does not need to cover the entire semiconductor layer 13b, but may be partial.

[0147] The semiconductor layer 13b contributes to reducing the electric field applied to the insulating layer 6b at the position where the insulating layer 6b bends between the directions Y and Z when viewed along the direction X.

[0148] In termination region R2, interlayer insulating film 8a has hole 25. Part of conductive layer 7b is exposed from interlayer insulating film 8a in hole 25.

[0149] Gate wiring 21 partially covers interlayer insulating film 8a in termination region R2 and is connected to conductive layer 7b through hole 25. Conductive layer 7a is electrically connected to gate pad 24 via gate wiring 21 and conductive layer 7b, and functions as a gate electrode.

[0150] The holes 25 are also commonly called contact holes. The holes 25 are involved in the connection between the gate wiring 21 and the conductive layer 7b, and therefore may be called gate contact holes.

[0151] Semiconductor device 200 includes termination structure 22 in termination region R2. Termination structure 22 is located on the opposite side of semiconductor layer 13b from semiconductor layer 3a. For example, termination structure 22 is adjacent to semiconductor layer 13b. For example, similar to semiconductor device 100, termination structure 22 may be a structure commonly known as a JTE, a structure commonly known as an FLR, or a structure that combines a JTE and an FLR.

[0152] Termination structure 22 is adjacent to surface 2t. Surface 2t protrudes from termination structure 22 on the side opposite to semiconductor layer 4b (direction Y in FIG. 8) toward the side opposite to surface 2s (the direction opposite to direction Z in FIG. 8). Reflecting this protrusion, field insulating film 8b, insulating layer 6b, and interlayer insulating film 8a also bend.

[0153] In termination region R2, semiconductor layers 4b and 13b, insulating layer 6b, conductive layer 7b, and termination structure 22 are disposed in a recess in surface 2t, which is illustrated in Figure 8 as outer trench TO.

[0154] The semiconductor device 200 includes a protective insulating film 23. In the termination region R2, the protective insulating film 23 covers the electrode 10, the interlayer insulating film 8a, and at least a part of the gate wiring 21 from the side opposite to the semiconductor layer 2. FIG. 8 illustrates a state in which the entire gate wiring 21 is covered with the protective insulating film 23.

[0155] <6-2. Recombination Center Concentration Distribution> In the semiconductor device 200, recombination centers are introduced in the same manner as in the semiconductor device 100. The recombination centers are included in, for example, the semiconductor layer 2. The recombination centers are introduced into the semiconductor layer 2 by, for example, implanting protons or helium.

[0156] 9 also shows a distribution Q5 of the concentration Cr of recombination centers along the direction Z. In FIGS. 8 and 9, a position LK where the concentration Cr has a maximum value Cp as a concentration peak in the distribution Q5 is shown.

[0157] 9, the concentration Cr exhibits a distribution Q5 between a value Cd and a maximum value Cp. For example, the value Cd is a baseline value for the concentration Cr.

[0158] Position LK is located between the surfaces 2s and 2t and is spaced apart from the surface 2s. Position LK is located between the end of the insulated gate TG on the surface 2s side and the surface 2s.

[0159] The semiconductor layer 2 is divided into a region S1 extending from position B1 to position B2 and a region S2 extending from position B2 to position B3, similar to the semiconductor device 100. Figure 8 illustrates an example in which the position LK and the surface 2s do not depend on the direction Y.

[0160] In the semiconductor device 200, the position B1 is, for example, the position in the direction Z of the end of the semiconductor layer 13a on the surface 2s side or the position in the direction Z of the end of the semiconductor layer 13b on the surface 2s side, whichever is closer to the surface 2s.

[0161] 8 illustrates a case where the positions of both are the same, and the position B1 is the position in the direction Z of the end of the semiconductor layer 13b on the surface 2s side. In this case, similar to the semiconductor device 100, position B1 can be said to be the position in the direction Z of the bottom of the recess on the surface 2t.

[0162] Similar to the semiconductor device 100, the position B2 is a position of the position LK in the direction Z. The position B3 is a position of the surface 2s in the direction Z.

[0163] In the semiconductor device 200, the concentration of recombination centers also has a maximum value at position B2 away from surface 2s. Therefore, even if stacking faults expand in the epitaxial layer due to the application of current, the range is limited to only one of regions S1 and S2, reducing the area of ​​the expanding stacking faults compared to conventional devices.

[0164] 9, the end of semiconductor layer 4a opposite to semiconductor layer 2 and the end of semiconductor layer 5a opposite to semiconductor layer 2 are at the same position in direction Z, and the following description will be made assuming that this position is the reference position in direction Z. For simplicity's sake, it is also assumed that the position in direction Z of the end of insulating layer 6t on the surface 2s side coincides with the position in direction Z of the end of semiconductor layer 13b on the surface 2s side.

[0165] Introducing the thickness D1 of the insulated gate TG along the Z direction (which can also be considered the distance from the reference position at position B1 in the above assumption), the thickness S of the semiconductor layer 2 along the Z direction from the surface 2s to the insulated gate TG, and the distance Dp from the reference position (which can also be considered the distance from the reference position at position B2), the following inequality (9) is expressed. A local maximum Cp appears in the distribution Q5 at the distance Dp that satisfies this inequality. In this case, the position LK is at the distance Dp from the reference position.

[0166]

number

[0167] If the concentration Cr is not taken into consideration, stacking faults may extend from the surface 2s to the insulated gate TG or the external trench TO in the semiconductor layer 2. As described above, even if stacking faults extend in the semiconductor layer 2 due to the application of current, the extent of the extension is limited to only one of the regions S1 and S2.

[0168] Therefore, when the distance Dp satisfies the following formula (10) (in this case, the inequality (9) is always satisfied), the range of stacking fault expansion does not exceed half of the range in the case where no recombination centers are introduced. When the distance Dp satisfies the following formula (10), the effect of suppressing the expansion of stacking faults is higher than when the following formula (10) is not satisfied even if the inequality (9) is satisfied.

[0169]

number

[0170] When equation (10) is satisfied, it can be said that a maximum value Cp appears in the distribution Q5 in the middle in the direction Z between the insulating gate TG or the external trench TO and the surface 2s.

[0171] In the semiconductor device 200, similarly to the semiconductor device 101 (see FIG. 4), the concentration Cr can have a maximum value at multiple positions along the direction Z. For example, when there are n such positions, each at a distance Dp1, Dp2, ..., Dpn from a reference position along the direction Z, an integer r between 1 and n is introduced, and the thickness D0 in equation (5) is replaced with the thickness D1, so that the following equation (11) is satisfied. Satisfying the following equation (11) enhances the effect of suppressing the expansion of stacking faults.

[0172]

number

[0173] In the semiconductor device 200, the concentration Cr may have a maximum value at the surface 2s, as exemplified in the semiconductor device 102 (see FIG. 5). In the semiconductor device 200, a semiconductor layer 9 serving as a boundary layer or a buffer layer may be provided, as exemplified in the semiconductor device 103 (see FIG. 6) and the semiconductor device 104 (see FIG. 7). In these cases, the formulas (6) to (8) for the semiconductor device 200 can be applied by replacing the thickness D0 with the thickness D1.

[0174] <7. Embodiment 7> In the seventh embodiment, pillar regions are introduced. The pillar regions contribute to improving depletion in the drift layer and, in turn, improving the breakdown voltage of the semiconductor device.

[0175] <7-1. Variations on planar insulated gate field effect transistors> 10 is a cross-sectional view schematically illustrating the semiconductor device 100A in a portion of the active region R1. The cross-section is taken along direction X. The cross-section may also be viewed along direction Y. FIG. 10 also schematically illustrates the distribution Q0 of the recombination center concentration Cr along direction Z.

[0176] The semiconductor device 100A is a modification of the semiconductor device 100 described with reference to Fig. 3. Specifically, the semiconductor device 100A has a configuration in which a part of the semiconductor layer 2 of the semiconductor device 100 is replaced with a semiconductor layer 14a.

[0177] The semiconductor layer 14a is disposed in contact with the end of the semiconductor layer 3a on the surface 2s side. The semiconductor layer 14a is disposed extending in the direction Z from the end toward the surface 2s. It can be said that the semiconductor layer 14a is adjacent to the semiconductor layer 3a and extends toward the surface 2s. The semiconductor layer 14a may be separated from the substrate 1 or may reach the substrate 1 by penetrating the semiconductor layer 2.

[0178] The conductivity type of semiconductor layer 14a is the same as that of semiconductor layer 3a and is opposite to that of semiconductor layer 2. For example, semiconductor layer 14a is made of p-type silicon carbide.

[0179] The semiconductor layers 14a function as pillar regions in a so-called superjunction structure. The semiconductor layers 14a arranged along the direction Y improve depletion in the semiconductor layer 2 between them, thereby contributing to an improvement in the breakdown voltage of the semiconductor device 100A.

[0180] In the semiconductor device 100A, as in the semiconductor device 100, the distribution Q0 of the concentration Cr has a maximum value Cp, which contributes to reducing the area of ​​expanding stacking faults.

[0181] As illustrated in the semiconductor device 101 (see FIG. 4), the semiconductor layer 14a can be used even when the concentration Cr has a distribution Q1 with multiple maximum values. As illustrated in the semiconductor device 102 (see FIG. 5), the semiconductor layer 14a can be used even when the concentration Cr has a maximum value at the surface 2s. As illustrated in the semiconductor device 103 (see FIG. 6) and the semiconductor device 104 (see FIG. 7), the semiconductor layer 14a can be used even when the semiconductor layer 9 is provided as a boundary layer or buffer layer. In this case, the semiconductor layer 14a does not contact the semiconductor layer 9 or contacts the semiconductor layer 9 on the side opposite to the semiconductor layer 2.

[0182] Regardless of whether the semiconductor layer 14a is introduced into any of the semiconductor devices 100, 101, 102, 103, and 104, the function of the recombination centers is maintained, and the introduction of the semiconductor layer 14a improves the breakdown voltage.

[0183] <7-2. Modifications to Trench-Type Insulated Gate Field-Effect Transistors> <7-2-1. First Modification of the Semiconductor Device 200> 11 is a cross-sectional view schematically illustrating a portion of the active region R1 of the semiconductor device 200A. The cross-section is taken along the X direction. The cross-section may also be viewed along the Y direction. FIG. 11 also shows a schematic distribution Q5 of the recombination center concentration Cr along the Z direction.

[0184] The semiconductor device 200A is a modification of the semiconductor device 200 described with reference to Fig. 9. The semiconductor device 200A has a configuration in which the semiconductor layer 13a of the semiconductor device 200 (see Fig. 9) is omitted and a semiconductor layer 14b is used.

[0185] Similar to semiconductor layer 14a (see FIG. 10) in semiconductor device 100A, semiconductor layer 14b is disposed in contact with the end of semiconductor layer 3a on the surface 2s side. For example, semiconductor layer 14b is disposed adjacent to insulated gate TG along direction X. In the cross section shown in FIG. 11, semiconductor layer 14b also appears on the surface 2s side of insulated gate TG, similar to semiconductor layer 13a.

[0186] Semiconductor layer 14b is disposed extending from the end toward face 2s along direction Z. It can be said that semiconductor layer 14b is adjacent to semiconductor layer 3a and extends toward face 2s. Semiconductor layer 14b may be separated from substrate 1 or may reach substrate 1 by penetrating semiconductor layer 2.

[0187] The conductivity type of semiconductor layer 14b is the same as that of semiconductor layers 3a and 13a, and is opposite to that of semiconductor layer 2. For example, semiconductor layer 14b is made of p-type silicon carbide. For example, the impurity concentration of semiconductor layer 14b is lower than that of semiconductor layer 13a.

[0188] The semiconductor layers 14b also function as pillar regions. The semiconductor layers 14b arranged along the direction Y improve depletion in the semiconductor layer 2 between them, thereby contributing to an improvement in the breakdown voltage of the semiconductor device 200A.

[0189] <7-2-2. Second Modification of the Semiconductor Device 200> 12 is a cross-sectional view schematically illustrating a portion of the active region R1 of the semiconductor device 200B. The cross-section is taken along the X direction. The cross-section may also be viewed along the Y direction. FIG. 12 also shows a schematic distribution Q5 of the recombination center concentration Cr along the Z direction.

[0190] The semiconductor device 200B is a modification of the semiconductor device 200 described with reference to Fig. 9. Specifically, the semiconductor device 200B has a configuration in which a semiconductor layer 14c is added to the semiconductor device 200 (see Fig. 9).

[0191] The semiconductor layer 14c is disposed in contact with the end of the semiconductor layer 3a on the surface 2s side. The semiconductor layer 14c is disposed extending in the direction Z from the end toward the surface 2s. It can be said that the semiconductor layer 14c is adjacent to the semiconductor layer 3a and extends toward the surface 2s. The semiconductor layer 14c may be separated from the substrate 1 or may reach the substrate 1 by penetrating the semiconductor layer 2.

[0192] The conductivity type of the semiconductor layer 14c is the same as that of the semiconductor layer 3a and is opposite to that of the semiconductor layer 2. For example, the semiconductor layer 14c is made of p-type silicon carbide. For example, the impurity concentration of the semiconductor layer 14c is lower than that of the semiconductor layer 13a.

[0193] The semiconductor layer 14c also functions as a pillar region. The semiconductor layers 14c arranged along the direction Y improve depletion in the semiconductor layer 2 between them, thereby contributing to an improvement in the breakdown voltage of the semiconductor device 200B.

[0194] <7-2-3. Third Modification of the Semiconductor Device 200> 13 is a cross-sectional view schematically illustrating a semiconductor device 200C in a portion of the active region R1. The cross-section is taken along direction X. The cross-section may also appear as viewed along direction Y. FIG. 13 also schematically illustrates a distribution Q5 of the recombination center concentration Cr along direction Z.

[0195] The semiconductor device 200C is a variation of the semiconductor device 200 described with reference to Fig. 9. Specifically, the semiconductor device 200C has a configuration in which a semiconductor layer 14c is added to the semiconductor device 200A (see Fig. 11). The semiconductor layers 14b and 14c arranged along the direction Y improve depletion in the semiconductor layer 2 sandwiched between them, thereby contributing to an improvement in the breakdown voltage of the semiconductor device 200C.

[0196] The function of the recombination centers is maintained even if either or both of the semiconductor layers 14b and 14c are introduced into the semiconductor device 200. In each of the semiconductor devices 200A, 200B, and 200C, the distribution Q5 of the concentration Cr has a maximum value Cp, as in the semiconductor device 200, which contributes to reducing the area of ​​expanding stacking faults.

[0197] By introducing either or both of the semiconductor layers 14b and 14c into the semiconductor device 200, the depletion of the semiconductor layer 2 is improved. In any of the semiconductor devices 200A, 200B, and 200C, the improvement in the depletion of the semiconductor layer 2 improves the device breakdown voltage.

[0198] As illustrated in the semiconductor device 101 (see FIG. 4), the concentration Cr may have multiple maximum values ​​in the distribution Q5. As illustrated in the semiconductor device 102 (see FIG. 5), the concentration Cr may have a maximum value on the surface 2s.

[0199] As illustrated in semiconductor device 103 (see FIG. 6) and semiconductor device 104 (see FIG. 7), semiconductor layer 14c may be employed even when semiconductor layer 9 is provided as a boundary layer or a buffer layer. When semiconductor layer 9 is provided, semiconductor layers 14b and 14c do not contact semiconductor layer 9 or contact semiconductor layer 9 on the side opposite to semiconductor layer 2.

[0200] <8. Embodiment 8> In the eighth embodiment, a semiconductor device other than the insulated gate field effect transistor having the above-described configuration and into which recombination centers are introduced will be exemplified.

[0201] <8-1. Built-in Schottky barrier diode> 14 is a cross-sectional view schematically illustrating a portion of the active region R1 of the semiconductor device 500. The cross-section is taken along direction X. The cross-section may also be viewed along direction Y. FIG. 14 also schematically illustrates the distribution Q0 of the recombination center concentration Cr along direction Z.

[0202] The semiconductor device 500 functions as an insulated gate field effect transistor with a built-in Schottky barrier diode. The semiconductor device 500 differs from the semiconductor device 100 (see FIG. 3) in the configuration between a pair of adjacent conductive layers 7a in a cross-sectional view (here, in a cross-section viewed along the X direction).

[0203] Specifically, in a cross-sectional view, an electrode 15b and a pair of electrodes 12a sandwiching the electrode 15b are disposed between the pair of conductive layers 7a.

[0204] The semiconductor device 500 includes a semiconductor layer 28. The semiconductor layer 28 is disposed on the surface 2s side of the electrode 15b. For example, the electrode 15b faces at least the entire semiconductor layer 28 in a plan view. A material that forms a Schottky junction with the semiconductor layer 28 is used for the electrode 15b.

[0205] Semiconductor layer 28 is adjacent to semiconductor layer 2 from the side opposite to surface 2s. Along direction Z, electrodes 10, 15b, semiconductor layer 28, 2, substrate 1, and electrode 11 are arranged in this order. Semiconductor layer 28 faces semiconductor layer 4a with semiconductor layer 3a interposed therebetween. Semiconductor layer 5a faces semiconductor layer 28 with semiconductor layers 4a, 3a interposed therebetween.

[0206] The conductivity type of semiconductor layer 28 is the same as that of semiconductor layer 2. For example, semiconductor layer 28 is made of n-type silicon carbide. The impurity concentration of semiconductor layer 28 is equal to or higher than the impurity concentration of semiconductor layer 2. Semiconductor layer 28 can also be considered to be part of semiconductor layer 2.

[0207] The substrate 1, the semiconductor layers 2, 28, and the electrode 15b are incorporated into the semiconductor device 500 and function as a Schottky barrier diode between the source and the drain.

[0208] In the semiconductor device 500, similarly to the semiconductor device 100, thicknesses D0 and S are introduced, and a maximum value Cp appears in the distribution Q0 at a distance Dp that satisfies inequality (1). For example, the distance Dp satisfies equation (2). In the semiconductor device 500, similarly to the semiconductor device 100, the area of ​​expanding stacking faults is reduced.

[0209] As illustrated in the semiconductor device 101 (see FIG. 4), the concentration Cr may have multiple maximum values ​​in the distribution Q0. As illustrated in the semiconductor device 102 (see FIG. 5), the concentration Cr may have a maximum value at the surface 2s. As illustrated in the semiconductor device 103 (see FIG. 6) and the semiconductor device 104 (see FIG. 7), a semiconductor layer 9 may be provided as a boundary layer or a buffer layer.

[0210] <8-2. Insulated Gate Bipolar Transistor> 15 is a cross-sectional view schematically illustrating a portion of the active region R1 of the semiconductor device 600. The cross-section is taken along the X direction. The cross-section may also be viewed along the Y direction. FIG. 15 also shows a schematic distribution Q0 of the recombination center concentration Cr along the Z direction.

[0211] The semiconductor device 600 functions as an insulated gate bipolar transistor. The semiconductor device 600 has a configuration in which the substrate 1 of the semiconductor device 100 (see FIG. 3) is replaced with a semiconductor layer 16. The conductivity type of the semiconductor layer 16 is opposite to that of the semiconductor layer 2. For example, the semiconductor layer 16 is made of p-type silicon carbide.

[0212] In the semiconductor device 600, the electrode 10 functions as an emitter electrode, and the electrode 11 functions as a collector electrode.

[0213] In the semiconductor device 600, similar to the semiconductor device 100, thicknesses D0 and S are introduced, and a maximum value Cp appears in the distribution Q0 at a distance Dp that satisfies inequality (1). For example, the distance Dp satisfies equation (2). In the semiconductor device 600, similar to the semiconductor device 100, the area of ​​expanding stacking faults is reduced.

[0214] As illustrated in the semiconductor device 101 (see FIG. 4), the concentration Cr may have multiple maximum values ​​in the distribution Q0. As illustrated in the semiconductor device 102 (see FIG. 5), the concentration Cr may have a maximum value on the surface 2s.

[0215] <8-3. Schottky Barrier Diode> 16 is a cross-sectional view schematically illustrating a portion of the active region R1 of the semiconductor device 700. The cross-section is taken along the X direction. The cross-section may also be viewed along the Y direction. FIG. 16 also shows a schematic distribution Q6 of the recombination center concentration Cr along the Z direction.

[0216] The semiconductor device 700 functions as a Schottky barrier diode. The semiconductor device 700 includes a substrate 1 and semiconductor layers 2 and 17. For example, the semiconductor layer 2 is formed by epitaxial growth on the substrate 1, and is a so-called epitaxial layer.

[0217] Similar to the semiconductor device 100 (see FIG. 3), the semiconductor layer 2 has surfaces 2s and 2t. Surface 2s is adjacent to the substrate 1. Surface 2t faces surface 2s in direction Z. For example, surface 2s is flat, while surface 2t is uneven. A part of the semiconductor layer 2 that becomes a convex portion can be recognized as the semiconductor layer 29. For example, the substrate 1 is made of n-type low-resistivity silicon carbide, and the semiconductor layer 2 is made of n-type silicon carbide that has a higher resistivity than the substrate 1.

[0218] The semiconductor layer 17 is adjacent to the semiconductor layer 2 from the side opposite to the surface 2s. The semiconductor layer 17 is adjacent to the surface 2t in the recessed portion of the semiconductor layer 2. When the protruding portion of the semiconductor layer 2 is recognized as the semiconductor layer 29, the semiconductor layer 29 separates the semiconductor layer 17.

[0219] The semiconductor device 700 includes electrodes 15a and 18. The electrode 15a is adjacent to the semiconductor layer 17 and the semiconductor layer 29 from the side opposite to the semiconductor layer 2. It can also be said that the electrode 15a is adjacent to the surface 2t in a region other than the region where the semiconductor layer 17 is provided.

[0220] The conductivity type of semiconductor layer 17 is opposite to that of semiconductor layers 2 and 29. For example, semiconductor layer 17 is made of p-type silicon carbide. A material that forms a Schottky junction with semiconductor layer 29 is used for electrode 15a.

[0221] Electrode 18 is adjacent to electrode 15a on the side opposite to semiconductor layer 2. Electrode 18 faces semiconductor layer 17 and semiconductor layer 29 via electrode 15a. A material that forms an ohmic junction with electrode 15a is used for electrode 18.

[0222] The semiconductor device 700 includes an electrode 19. The electrode 19 is adjacent to the substrate 1 on the side opposite to the semiconductor layer 2. Along the direction Z, the electrodes 18, 15a, the semiconductor layer 29,2, the substrate 1, and the electrode 19 are arranged in this order, or the electrodes 18, 15a, the semiconductor layer 17,2, the substrate 1, and the electrode 19 are arranged in this order. For example, the electrode 18 functions as an anode electrode, and the electrode 19 functions as a cathode electrode.

[0223] In the semiconductor device 700, similar to the semiconductor device 100, the thickness D2 of the semiconductor layer 17 along the direction Z, the thickness S of the semiconductor layer 2 along the direction Z from the surface 2s to the semiconductor layer 3a, and the distance Dp from the reference position (which can also be said to be the distance from the reference position of the position B2) are introduced to give the following inequality (12): In the semiconductor device 700, the area of ​​the expanding stacking faults is reduced in the same manner as in the semiconductor device 100.

[0224]

number

[0225] For example, in formula (10), the thickness D0 is replaced with the thickness D2, and the distance Dp satisfies formula (13). In this case, the effect of suppressing the expansion of stacking faults is enhanced.

[0226]

number

[0227] As illustrated in the semiconductor device 101 (see FIG. 4), the concentration Cr may have multiple maximum values ​​in the distribution Q6. As illustrated in the semiconductor device 102 (see FIG. 5), the concentration Cr may have a maximum value at the surface 2s. As illustrated in the semiconductor device 103 (see FIG. 6) and the semiconductor device 104 (see FIG. 7), a semiconductor layer 9 may be provided as a boundary layer or a buffer layer.

[0228] <9. Embodiment 9> In the ninth embodiment, various modes are exemplified for the range in plan view where the recombination centers are introduced.

[0229] <9-1. Introduction of recombination centers throughout the entire surface> Fig. 17 is a plan view schematically showing the wafer 30a and the die 20a, and Fig. 18 is a plan view schematically showing one die 20a.

[0230] The die 20a can be used to manufacture the semiconductor devices 100, 101, 102, 103, 104, 100A, 200, 200A, 200B, 200C, 500, 600, and 700. The wafer 30a is, for example, a so-called epitaxial wafer provided with a substrate 1 and a semiconductor layer 2. For example, in the manufacture of the semiconductor device 600, a p-type impurity is introduced into the substrate 1 to obtain the semiconductor layer 16.

[0231] The wafer 30a is cut along the dicing lines 39 to obtain the dies 20a. In this example, the dicing lines 39 are lattice-shaped in a plan view, and the dies 20a are rectangular. In a plan view, all the dies 20a are adjacent to each other without overlapping on the wafer 30a. The outer edges of the dies 20a correspond to the dicing lines 39 before the wafer 30a is cut.

[0232] 18 shows a region 31a where recombination centers are introduced. For example, recombination centers are introduced over the entire wafer 30a in a plan view. In this case, the region 31a is introduced over the entire die 20a in a plan view.

[0233] <9-2. Avoiding introduction into dicing lines> It is not necessary to introduce recombination centers into the entire semiconductor layer 2 in plan view. For example, no substantially operating semiconductor device is formed on the dicing line 39. It is not necessary to introduce recombination centers into the dicing line 39.

[0234] Fig. 19 is a plan view schematically showing the wafer 30b and the die 20b, and Fig. 20 is a plan view schematically showing one die 20b.

[0235] The die 20b can be used to manufacture the semiconductor devices 100, 101, 102, 103, 104, 100A, 200, 200A, 200B, 200C, 500, 600, and 700. The wafer 30b is, for example, a so-called epitaxial wafer provided with a substrate 1 and a semiconductor layer 2. For example, in manufacturing the semiconductor device 600, a p-type impurity is introduced into the substrate 1 to obtain the semiconductor layer 16.

[0236] The wafer 30b is cut along the dicing lines 39 to obtain the dies 20b. In this example, the dicing lines 39 are lattice-shaped in a plan view, and the dies 20b are rectangular. In a plan view, all the dies 20b are adjacent to each other without overlapping on the wafer 30b. The outer edges of the dies 20b correspond to the dicing lines 39 before the wafer 30b is cut.

[0237] 19 and 20 show a region 31b where recombination centers are to be introduced. For example, recombination centers are introduced into wafer 30b so as to avoid dicing line 39 and its vicinity in a plan view. In this case, region 32 where the introduction of recombination centers is to be avoided is the vicinity of the outer edge of die 20b that surrounds region 31b in die 20b.

[0238] The main current does not flow in the region 32, and therefore, in the region 32, it is not important to suppress the growth of crystal defects in the semiconductor layer 2. Therefore, it is not necessary to introduce recombination centers into the region 32.

[0239] Here, the "main current" refers to the current flowing between the surfaces 2s and 2t in the semiconductor layer 2. For example, in the semiconductor devices 100, 101, 102, 103, 104, 100A, 200, 200A, 200B, 200C, and 500, the "main current" refers to the so-called drain current that flows between the electrodes 10 and 11. For example, in the semiconductor device 600, the "main current" refers to the so-called collector current that flows between the electrodes 10 and 11. For example, in the semiconductor device 700, the "main current" refers to the forward current that flows through the electrodes 18 and 19.

[0240] Introduction of recombination centers into the wafer 30b, for example, while avoiding the dicing lines 39 in the wafer 30b, contributes to reducing warpage of the wafer 30b caused by the introduction of recombination centers.

[0241] For example, a method of introducing recombination centers is to implant protons or helium into the semiconductor layer 2. The implantation is performed, for example, prior to patterning of a semiconductor layer to be formed on the surface 2t side of the semiconductor layer 2. The implantation makes the wafer 30b less likely to warp than the wafer 30a, improving the accuracy of the patterning.

[0242] <9-3. Avoiding introduction into the termination region R2> <9-3-1. Planar Insulated Gate Field-Effect Transistor> Fig. 21 is a cross-sectional view schematically showing a semiconductor device 100B. The semiconductor device 100B is a variation of the semiconductor device 100 described with reference to Fig. 2. Like Fig. 2, Fig. 21 also shows a cross section appearing at position II-II in Fig. 1.

[0243] Specifically, the semiconductor device 100B differs from the semiconductor device 100 in that introduction of recombination centers is avoided in the region 32. The boundary between the region 31b where recombination centers are introduced and the region 32 where introduction of recombination centers is avoided reflects the position of the end LKB of the chain line indicating the position LK.

[0244] Considering the range in which the above-mentioned "main current" flows in termination region R2, region 31b desirably extends to include semiconductor layer 4b in a planar view. Region 31b may also extend to include semiconductor layer 3b in a planar view. Region 32 may, for example, extend to include the range in which termination structure 22 is provided in a planar view. Region 32 may also extend to the opposite side of termination structure 22 from active region R1 (toward direction Y in FIG. 21).

[0245] It can be said that the concentration of recombination centers in semiconductor layer 2 between termination structure 22 and face 2s is lower than the maximum value that the concentration takes between face 2s and face 2t.

[0246] <9-3-2. Trench-type insulated gate field-effect transistor> Fig. 22 is a cross-sectional view schematically showing a semiconductor device 200D. The semiconductor device 200D is a variation of the semiconductor device 200 described with reference to Fig. 8. Like Fig. 8, Fig. 22 also shows a cross section appearing at position II-II in Fig. 1.

[0247] Specifically, the semiconductor device 200D differs from the semiconductor device 200 in that introduction of recombination centers is avoided in the region 32. The boundary between the region 31b where recombination centers are introduced and the region 32 where introduction of recombination centers is avoided reflects the position of the end LKB of the chain line indicating the position LK.

[0248] Considering the range in which the above-mentioned "main current" flows in termination region R2, region 31b desirably extends to include semiconductor layer 4b in a planar view. Region 31b may also extend to include semiconductor layer 13b in a planar view. Region 32 may extend, for example, to include the range in which termination structure 22 is provided in a planar view. Region 32 may also extend to the opposite side of termination structure 22 from active region R1 (toward direction Y in FIG. 22).

[0249] It can be said that the concentration of recombination centers in semiconductor layer 2 between termination structure 22 and face 2s is lower than the maximum value that the concentration takes between face 2s and face 2t.

[0250] In both the semiconductor devices 100B and 200D, similarly to the third embodiment, a plurality of positions LK may exist along the direction Z. For example, the ends LKB of the plurality of positions LK may coincide in a plan view.

[0251] <10. Deformation of the terminal region R2> In view of the ninth embodiment, a semiconductor element of a different type from the semiconductor device 100B can be formed in the region 32 together with the semiconductor device 100B (see FIG. 21).

[0252] Fig. 23 is a cross-sectional view showing a cross section at a position corresponding to Fig. 21. Fig. 23 illustrates a structure in which a semiconductor element 40 is provided in region 31b. Region 31b extends to include semiconductor layer 4b in plan view. The semiconductor element 40 is, for example, a temperature sensor diode.

[0253] 23 illustrates a case where the semiconductor layer 3b also extends in the region 32. In the region 32, along the direction Z, the insulating layer 6b, the field insulating film 8b, the semiconductor layer 3b, the semiconductor layer 2, and the substrate 1 are arranged in this order.

[0254] The semiconductor element 40 has an anode region 33 and a cathode region 34. The anode region 33 and the cathode region 34 are adjacent to each other on the side of the insulating layer 6b in the region 32 opposite the semiconductor layer 2. The anode region 33 and the cathode region 34 are disposed adjacent to each other. The anode region 33 and the cathode region 34 form a so-called pn junction. For example, the anode region 33 is made of p-type doped polysilicon, and the cathode region 34 is made of n-type doped polysilicon.

[0255] Holes 37 and 38 are opened in the interlayer insulating film 8a. The anode region 33 is exposed from the interlayer insulating film 8a at the hole 37. The cathode region 34 is exposed from the interlayer insulating film 8a at the hole 38.

[0256] The electrodes 35 and 36 are adjacent to the interlayer insulating film 8a on the side opposite to the semiconductor layer 2. The electrode 35 is adjacent to the anode region 33 at a hole 37. A material that forms an ohmic junction with the anode region 33 is used for the electrode 35. The electrode 36 is adjacent to the cathode region 34 at a hole 38. A material that forms an ohmic junction with the cathode region 34 is used for the electrode 36. For example, at least a portion of the electrodes 35 and 36 is covered with the protective insulating film 23.

[0257] Similarly to the above, a semiconductor element of a type different from the semiconductor device 200D (see FIG. 22) can be formed in the region 32 together with the semiconductor device 200D.

[0258] 22 and 23, as described in the ninth embodiment, a plurality of positions LK may exist along the direction Z. For example, the ends LKB of the plurality of positions LK coincide in a plan view.

[0259] Another example of the "different type of semiconductor element" mentioned above is a current sensor (not shown). The current sensor is a control pad for detecting the current flowing in a cell region of a semiconductor device. When a current flows in the cell region of the semiconductor device, the current sensor is electrically connected to a cell in an active region of a part of the cell region so that a current that flows is one-several to several tens of thousands of times less than the current flowing in the entire cell region.

[0260] The current sense may be provided in region 31b. Recombination centers are introduced in region 31b. As described in the above embodiments and modifications, the recombination centers reduce the expansion of the stacking fault area. Providing the current sense in region 31b reduces the influence of the stacking fault area on the current sense, contributing to improving the measurement accuracy of the current sense.

[0261] The gate pad 24 may be provided in the region 31b. Providing the gate pad 24 in the region 31b reduces the influence of the area of ​​stacking faults on the gate pad 24, and contributes to improving the accuracy of controlling the semiconductor device by the gate voltage.

[0262] <11. Embodiment 10> In the tenth embodiment, a method for introducing recombination centers into a semiconductor layer 2 is exemplified. For the sake of simplicity, the semiconductor layer 2 is obtained by epitaxial growth on a substrate 1 and is adjacent to the substrate 1 (see FIGS. 2 to 5, 8 to 14, and 16). However, it is clear that the method can also be applied to a case where a semiconductor layer 9 is provided between the substrate 1 and the semiconductor layer 2 (see FIGS. 6 and 7) or a case where a semiconductor layer 16 is used instead of the substrate 1 (see FIG. 15).

[0263] 24 is a cross-sectional view schematically illustrating a first example of the tenth embodiment. In the first example, protons or helium (hereinafter, collectively referred to as "particles H") are injected into a laminated structure of a substrate 1 and a semiconductor layer 2 from the semiconductor layer 2 side (face 2t). In the first example, particles H are injected into the semiconductor layer 2 in the direction from face 2t toward face 2s.

[0264] 25 is a cross-sectional view schematically illustrating a second example of the tenth embodiment. In the second example, particles H are injected from the substrate 1 side into a laminated structure of a substrate 1 and a semiconductor layer 2. In the second example, particles H are injected into the semiconductor layer 2 in a direction from the surface 2s toward the surface 2t.

[0265] 26 is a flowchart showing an outline of the steps for manufacturing various semiconductor devices according to the present disclosure, and includes steps F1 to F7.

[0266] Step F1 is a step of preparing a semiconductor substrate. For example, a substrate 1 made of n-type silicon carbide is used as the semiconductor substrate. Step F2 is a step of obtaining a semiconductor layer 2, or semiconductor layers 2 and 9, which are epitaxial layers, by epitaxial growth on the substrate 1. When the substrate 1 is made of n-type silicon carbide, the semiconductor layers 2 and 9 are, for example, epitaxial layers made of n-type silicon carbide.

[0267] After step F2 is completed to obtain an epitaxial layer, step F3 is performed. Step F3 is a process for introducing recombination centers. In step F3, for example, either the first example (FIG. 24) or the second example (FIG. 25), or both, of the methods are employed.

[0268] Step F4 is a process of introducing impurities into the semiconductor layer 2. For example, p-type or n-type impurities are introduced into the surface 2t. The region into which the impurities are introduced is also commonly referred to as the "injection layer." Step F5 is a process of performing annealing, which is a process of activating the impurities introduced in step F4 (abbreviated as "activation annealing process" in Figure 26). By step F5, for example, semiconductor layers 3a, 3b, 4a, 4b, 5a, and 5b are obtained from the injection layer. Step F5 is performed after the process of step F3 is completed. It is desirable to introduce recombination centers prior to the injection of impurities, and therefore it is desirable to perform step F4 after the process of step F3 is completed.

[0269] Step F6 is a process for forming electrodes. These electrodes may include electrodes 10, 11, 12a, 12b, 15a, 15b, 18, 19, 35, and 36, as well as planar insulating gates and trench insulating gates. Step F7 is a process for dicing. In step F7, dicing is performed along dicing lines 39 (see FIGS. 17 and 19), for example, to obtain dies 20a and 20b (see FIGS. 18 and 20).

[0270] According to the method of the second example, defects due to implantation (hereinafter referred to as "implantation defects") are unlikely to be formed on the surface 2t and its vicinity. The semiconductor layers 3a, 3b, 4a, 4b, 5a, and 5b are obtained by introducing impurities into the surface 2t and annealing (see steps F4 and F5). Therefore, the second example, in which implantation defects are unlikely to be formed on the surface 2t and its vicinity, is advantageous over the first example in that it suppresses deterioration of the electrical characteristics of the resulting semiconductor device.

[0271] In the first and second examples, the case where there is only one position LK where the concentration of the recombination center reaches a maximum value has been illustrated. As in the third embodiment, there may be multiple positions where the concentration reaches a maximum value. For example, if the concentration reaches a maximum value at two different positions along the direction Z, particles H can be implanted using the method of the second example to introduce a recombination center so that the concentration reaches a maximum value at the position closer to the surface 2s, and particles H can be implanted using the method of the first example to introduce a recombination center so that the concentration reaches a maximum value at the position closer to the surface 2t. Using different methods for implanting particles H in this way is advantageous in terms of improving the accuracy of the position where the recombination center is formed.

[0272] 12. Deformation of concentration distribution <12-1. First deformation of concentration distribution> In the semiconductor layer 2, when the concentration Cr has a maximum value at multiple positions along the direction Z, the concentration Cr does not have a maximum value but has a minimum value between adjacent positions. The distance between the positions may be narrow, and the concentration Cr between the positions may be greater than the value Cd. This state can also be described as the concentration Cr being distributed in a multi-peaked manner, with the tails of adjacent peaks overlapping.

[0273] <12-2. Second Variation of Concentration Distribution> The distance Dp or the distances Dp1, Dp2, ... at which the concentration Cr has a maximum value may satisfy the above formula, or may deviate from the position that satisfies the formula along the direction Z, for example, by up to 1 μm.

[0274] <13. General Description of the Disclosure> A general description of the above embodiments and examples is provided below.

[0275] <13-1. General explanation of concentration distribution> Each of the semiconductor devices 100, 100A, 100B, 101, 102, 103, 104, 200, 200A, 200B, 200C, 200D, 500, 600, and 700 includes semiconductor layers 2 and 3a.

[0276] The semiconductor layer 2 has surfaces 2s and 2t. The surface 2t faces the surface 2s in the direction Z. The conductivity type of the semiconductor layer 2 is, for example, n-type.

[0277] The semiconductor layer 3a is adjacent to the surface 2t. The conductivity type of the semiconductor layer 3a is opposite to that of the semiconductor layer 2, and is, for example, p-type.

[0278] The semiconductor layer 2 includes recombination centers at a concentration Cr. The distribution Q0, Q1, ..., Q6 of the concentration Cr along the direction Z has maximum values ​​Cp, Cp1, Cp2, ... at at least one position (distance Dp, Dp1, Dp2, ...) between the surface 2s and the surface 2t and away from both the surface 2s and the surface 2t.

[0279] In accordance with the semiconductor devices 100, 100A, 500, and 600, the distribution Q0 has a maximum value Cp of the concentration Cr at a position LK at a distance Dp (see FIGS. 3, 10, 14, and 15).

[0280] In terms of the semiconductor device 101, the distribution Q1 has maximum values ​​Cp1 and Cp2 of the concentration Cr at positions LK1 and LK2 at distances Dp1 and Dp2 (see FIG. 4).

[0281] In terms of the semiconductor device 102, the distribution Q2 has maximum values ​​Cp1, Cp2, and Cp3 of the concentration Cr at positions LK1, LK2, and LK3 at distances Dp1, Dp2, and Dp3 (see FIG. 5).

[0282] In terms of the semiconductor device 103, the distribution Q3 has maximum values ​​Cp1 and Cp2 of the concentration Cr at positions LK1 and LK2 at distances Dp1 and Dp2 (see FIG. 6).

[0283] In terms of the semiconductor device 104, the distribution Q4 has maximum values ​​Cp1, Cp2, and Cp3 of the concentration Cr at positions LK1, LK2, and LK3 at distances Dp1, Dp2, and Dp3 (see FIG. 7).

[0284] In accordance with the semiconductor devices 200, 200A, 200B, and 200C, the distribution Q5 has a maximum value Cp of the concentration Cr at the position LK at the distance Dp (see FIGS. 9, 11, 12, and 13).

[0285] In terms of the semiconductor device 700, the distribution Q6 has a maximum value Cp of the concentration Cr at a position LK at a distance Dp (see FIG. 16).

[0286] In the distributions Q1, Q2, Q3, and Q4 of the concentration Cr, maximum values ​​Cp1, Cp2, . . . appear at a plurality of positions (distances Dp1, Dp2, . . . ) in the direction Z.

[0287] In accordance with the semiconductor devices 101 and 103, the distributions Q1 and Q3 have maximum values ​​Cp1 and Cp2 of the concentration Cr at positions LK1 and LK2 at distances Dp1 and Dp2, respectively (see FIGS. 4 and 6).

[0288] In accordance with the semiconductor devices 102 and 104, the distributions Q2 and Q4 have maximum values ​​Cp1, Cp2, and Cp3 of the concentration Cr at positions LK1, LK2, and LK3 at distances Dp1, Dp2, and Dp3, respectively (see FIGS. 5 and 7).

[0289] In the semiconductor layer 2, the distributions Q1, Q2, Q3, and Q4 have local maximum values ​​Cp1 and Cp2 that appear at equal intervals along the direction Z (see equations (4), (5), (6), (8), (10), (11), and (13)).

[0290] In the distribution Q2, a maximum value Cp3 also appears on the surface 2s (see Figure 5).

[0291] <13-2. General explanation of insulated gate transistors> Each of the semiconductor devices 100, 100A, 100B, 101, 102, 103, 104, 200, 200A, 200B, 200C, 200D, 500, and 600 includes a semiconductor layer 5a, a first insulating layer, and a first conductive layer.

[0292] The semiconductor layer 5a is adjacent to the semiconductor layer 3a from the side opposite to the semiconductor layer 2. The conductivity type of the semiconductor layer 5a is the same as that of the semiconductor layer 2, for example, n-type.

[0293] In accordance with the semiconductor devices 100, 101, 102, 103, 104, 100A, 100B, 500, and 600, the insulating layer 6a corresponds to the first insulating layer. In accordance with the semiconductor devices 200, 200A, 200B, 200C, and 200D, the insulating layer 6t corresponds to the first insulating layer. The insulating layer 6a and the insulating layer 6t are common in that they are adjacent to the semiconductor layers 2, 3a, and 5a and extend from the semiconductor layer 2 across the semiconductor layer 3a to reach the semiconductor layer 5a.

[0294] In accordance with the semiconductor devices 100, 101, 102, 103, 104, 100A, 100B, 500, and 600, the conductive layer 7a corresponds to the first conductive layer. In accordance with the semiconductor devices 200, 200A, 200B, 200C, and 200D, the conductive layer 7t corresponds to the first conductive layer. The conductive layer 7a and the conductive layer 7t are common in that they face the semiconductor layer 3a via the first insulating layer.

[0295] The insulating layer 6a and the conductive layer 7a form a planar type insulated gate, and the insulating layer 6t and the conductive layer 7t form a trench type insulated gate TG.

[0296] The semiconductor devices 100, 101, 102, 103, 104, 100A, 100B, 500, and 600 each have a planar insulated gate. For example, all of the maximum values ​​of the concentration Cr distributions Q0, Q1, Q2, Q3, and Q4 appear closer to the surface 2s than the insulating layer 6a (see FIGS. 2 to 7, 10, 14, and 15). For example, the maximum value Cp appears in the distribution Q0 at the center (distance Dp) in the direction Z between the semiconductor layer 3a and the surface 2s (see FIGS. 3, 10, 14, and Equation (2)).

[0297] Each of the semiconductor devices 200, 200A, 200B, 200C, and 200D has a trench-type insulated gate TG. For example, all of the maximum values ​​Cp of the distribution Q5 of the concentration Cr appear on the surface 2s side of the insulating layer 6t (see FIGS. 8, 9, 11 to 13). For example, the maximum value Cp of the distribution Q5 appears at the center (distance Dp) in the direction Z between the end of the insulating layer 6t on the surface 2s side and the surface 2s (see equation (10)).

[0298] <13-3. General explanation of the termination region> For example, termination structure 22 is provided in termination region R2. Semiconductor layer 3b is adjacent to surface 2t. The conductivity type of semiconductor layer 3b is opposite to that of semiconductor layer 2, for example, p-type. Termination structure 22 is adjacent to surface 2t and is arranged alongside semiconductor layer 3b on the side opposite to semiconductor layer 5a (see FIGS. 2, 8, and 21 to 23).

[0299] The concentration of recombination centers in semiconductor layer 2 between termination structure 22 and surface 2s is lower than the maximum value of the recombination centers. For example, position LK has end LKB in termination region R2, and termination structure 22 is located on the opposite side of end LKB from position LK in plan view (see FIGS. 21 to 23).

[0300] <13-4. General explanation of Schottky junction> The semiconductor device 500 includes an electrode 15b adjacent to both the semiconductor layers 3a and 28 (see FIG. 14). The semiconductor layer 28 can also be considered as part of the semiconductor layer 2.

[0301] The semiconductor device 700 includes an electrode 15a adjacent to both semiconductor layers 17 and 29 (see FIG. 16). The semiconductor layer 17 is adjacent to the surface 2t, similar to the semiconductor layer 3a. The conductivity type of the semiconductor layer 17 is the same as that of the semiconductor layer 3a, e.g., p-type. The semiconductor layer 29 can also be considered as part of the semiconductor layer 2.

[0302] Electrode 15a and electrode 15b are common in that they both use a material that forms a Schottky junction with part of semiconductor layer 2. Semiconductor layer 3a and semiconductor layer 17 are common in that they both have the opposite conductivity type to semiconductor layer 2.

[0303] It should be noted that the embodiments can be freely combined, and each embodiment can be modified or omitted as appropriate.

[0304] Various aspects of the present disclosure are summarized below as appendices.

[0305] (Appendix 1) a first semiconductor layer of a first conductivity type, the first semiconductor layer having a first surface and a second surface facing the first surface in a first direction, the first semiconductor layer including a recombination center; a second semiconductor layer adjacent to the second surface and having a second conductivity type opposite to the first conductivity type; Equipped with A semiconductor device, wherein a maximum value appears in the distribution of the concentration of recombination centers along the first direction at at least one position between the first surface and the second surface and away from both the first surface and the second surface.

[0306] (Appendix 2) 2. The semiconductor device of claim 1, wherein the distribution has a maximum value at a plurality of positions in the first direction.

[0307] (Appendix 3) 3. The semiconductor device according to claim 2, wherein the maximum values ​​appear in the distribution at equal intervals along the first direction in the first semiconductor layer.

[0308] (Appendix 4) 4. The semiconductor device according to claim 1, wherein the maximum value also appears in the distribution on the first surface.

[0309] (Appendix 5) a third semiconductor layer having the first conductivity type and adjacent to the second semiconductor layer from the side opposite to the first semiconductor layer; a first insulating layer adjacent to the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer, extending from the first semiconductor layer across the second semiconductor layer to reach the third semiconductor layer; a first conductive layer facing the second semiconductor layer via the first insulating layer; Further provided with 5. The semiconductor device according to claim 1, wherein all of the maximum values ​​of the distribution appear on the first surface side of the first insulating layer.

[0310] (Appendix 6) 6. The semiconductor device according to claim 5, wherein the maximum value appears in the distribution at the center in the first direction between the second semiconductor layer and the first surface.

[0311] (Appendix 7) 6. The semiconductor device according to claim 5, wherein the maximum value appears in the distribution at the center in the first direction between the end of the first insulating layer on the first surface side and the first surface.

[0312] (Appendix 8) a fourth semiconductor layer of the second conductivity type adjacent to the second surface; a termination structure adjacent to the second surface and arranged side by side with the fourth semiconductor layer on the opposite side from the third semiconductor layer; Further provided with 8. The semiconductor device according to claim 5, wherein the concentration of the recombination centers in the first semiconductor layer between the termination structure and the first surface is lower than the maximum value.

[0313] (Appendix 9) an electrode adjacent to both the second semiconductor layer and the first semiconductor layer; Further provided with 5. The semiconductor device according to claim 1, wherein the electrode is made of a material that forms a Schottky junction with the second semiconductor layer.

[0314] (Appendix 10) a fifth semiconductor layer of the first conductivity type adjacent to the first semiconductor layer in the first surface; Further provided with The impurity concentration of the fifth semiconductor layer is 1×10 18 cm -3 Greater than or equal to 1 x 10 19 cm -3 is as follows: The maximum impurity concentration of the first semiconductor layer is 1×10 18cm -3 10. The semiconductor device according to any one of claims 1 to 9, wherein the semiconductor device has a capacitance of less than 100 Ω / cm.

[0315] (Appendix 11) 11. The semiconductor device according to claim 10, wherein the maximum value appears in the distribution in the fifth semiconductor layer.

[0316] (Appendix 12) a fifth semiconductor layer of the second conductivity type adjacent to the first semiconductor layer in the first surface; 10. The semiconductor device according to any one of claims 1 to 9, further comprising:

[0317] (Appendix 13) a sixth semiconductor layer of the second conductivity type adjacent to the second semiconductor layer and extending toward the first surface; 13. The semiconductor device according to any one of claims 1 to 12, further comprising:

[0318] (Appendix 14) A method for manufacturing a semiconductor device according to any one of claims 1 to 13, comprising: A method for manufacturing a semiconductor device, comprising: injecting protons or helium into the first semiconductor layer in a direction from the first surface toward the second surface. [Explanation of symbols]

[0319] 2,3a,3b,4a,4b,5a,5b,9,14a,14b,14c,16,17,28,29 Semiconductor layer, 2s,2t plane, 6a,6t insulating layer, 7a,7t conductive layer, 15a,15b electrode, 22 termination structure, Cp,Cp1,Cp2,Cp3 maximum value, Cr Concentration, Dp,Dp1,Dp2,Dp3 distance, LK,LK1,LK2,LK3 position, Q0~Q6 distribution, X,Y,Z direction.

Claims

1. a first semiconductor layer of a first conductivity type, the first semiconductor layer having a first surface and a second surface facing the first surface in a first direction, the first semiconductor layer including a recombination center; a second semiconductor layer adjacent to the second surface and having a second conductivity type opposite to the first conductivity type; Equipped with a maximum value appears in the distribution of the concentration of recombination centers along the first direction at at least one position between the first surface and the second surface and away from both the first surface and the second surface.

2. The semiconductor device according to claim 1 , wherein the maximum value appears in the distribution at a plurality of positions in the first direction.

3. The semiconductor device according to claim 2 , wherein the maximum values ​​appear in the distribution at equal intervals along the first direction in the first semiconductor layer.

4. The semiconductor device according to claim 1 , wherein the maximum value also appears in the distribution on the first surface.

5. a third semiconductor layer having the first conductivity type and adjacent to the second semiconductor layer from the side opposite to the first semiconductor layer; a first insulating layer adjacent to the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer, extending from the first semiconductor layer across the second semiconductor layer to reach the third semiconductor layer; a first conductive layer facing the second semiconductor layer via the first insulating layer; Further provided with The semiconductor device according to claim 1 , wherein all of the maximum values ​​of the distribution appear on the first surface side of the first insulating layer.

6. The semiconductor device according to claim 5 , wherein the maximum value appears in the distribution at a center in the first direction between the second semiconductor layer and the first surface.

7. 6. The semiconductor device according to claim 5, wherein the maximum value appears in the distribution at a center in the first direction between the first surface and an end of the first insulating layer on the first surface side.

8. a fourth semiconductor layer of the second conductivity type adjacent to the second surface; a termination structure adjacent to the second surface and arranged side by side with the fourth semiconductor layer on the opposite side from the third semiconductor layer; Further provided with The semiconductor device according to claim 5 , wherein the concentration of the recombination centers in the first semiconductor layer between the termination structure and the first surface is lower than the maximum value.

9. an electrode adjacent to both the second semiconductor layer and the first semiconductor layer; Further provided with The semiconductor device according to claim 1 , wherein the electrode is made of a material that forms a Schottky junction with the second semiconductor layer.

10. a fifth semiconductor layer of the first conductivity type adjacent to the first semiconductor layer in the first surface; Further provided with The impurity concentration of the fifth semiconductor layer is 1×10 １８ cm －３ Greater than or equal to 1 x 10 １９ cm －３ is as follows: The maximum impurity concentration of the first semiconductor layer is 1×10 １８ cm －３ The semiconductor device according to claim 1 , wherein the thickness is less than 100 μm.

11. The semiconductor device according to claim 10 , wherein the maximum value appears in the distribution in the fifth semiconductor layer.

12. a fifth semiconductor layer of the second conductivity type adjacent to the first semiconductor layer in the first surface; The semiconductor device according to claim 1 , further comprising:

13. a sixth semiconductor layer of the second conductivity type adjacent to the second semiconductor layer and extending toward the first surface; The semiconductor device according to claim 1 , further comprising:

14. 10. A method for manufacturing a semiconductor device according to claim 1, comprising: A method for manufacturing a semiconductor device, comprising: injecting protons or helium into the first semiconductor layer in a direction from the first surface toward the second surface.

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