Wiring board

Abstract

To provide a technique useful for suppressing the occurrence of cracks in a wiring board on which two or more functional devices are surface-mounted.SOLUTION: In the printed circuit board 10A, one main surface has two or more mounting regions on which two or more functional devices 20 are surface-mounted, respectively, and a groove G for partitioning adjacent two or more mounting regions is provided on the main surface.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a wiring board. [Background technology]

[0002] As semiconductor chips become more highly integrated and multifunctional, the number of external connection terminals on the chips increases. These semiconductor chips are surface-mounted on wiring substrates such as motherboards as semiconductor packages, for example, ball grid arrays (BGAs).

[0003] In recent years, chiplets have been attracting attention. Chiplets are a technology in which, instead of forming a large-scale integrated circuit on a single semiconductor chip, it is formed on multiple semiconductor chips and these semiconductor chips are then mounted on a single wiring substrate, such as an interposer.

[0004] In a semiconductor package in which multiple semiconductor chips are mounted on an interposer, the semiconductor chips are arranged with very short gaps between them to shorten the length of the wiring that electrically connects them. In such a semiconductor package, stress concentrates in the parts of the interposer that correspond to the gaps between the semiconductor chips, which can cause cracks or warping in these parts.

[0005] Patent Document 1 describes providing an internal support inside a wiring board at a position corresponding to the gap between multiple mounting areas where semiconductor chips are surface-mounted. The internal support provides structural stability to the wiring board, suppressing cracks and warping of the wiring board. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Patent No. 11,784,140 Summary of the Invention [Problem to be solved by the invention]

[0007] The present inventors have found that although the method described in Patent Document 1 can suppress the occurrence of warping and cracks in the wiring board to a certain extent, there is still room for improvement, particularly with regard to the suppression of crack occurrence.

[0008] Therefore, an object of the present invention is to provide a technique that is useful for suppressing the occurrence of cracks in a wiring board on which two or more functional devices are surface-mounted. [Means for solving the problem]

[0009] According to one aspect of the present invention, there is provided a wiring substrate having, on one main surface thereof, two or more mounting areas in which two or more functional devices are surface-mounted, and in which the main surface is provided with grooves separating adjacent ones of the two or more mounting areas.

[0010] According to another aspect of the present invention, there is provided a wiring substrate according to the above aspect, which is configured to electrically connect the functional device surface-mounted in one of the two or more mounting areas with the functional device surface-mounted in another of the two or more mounting areas.

[0011] According to yet another aspect of the present invention, there is provided a wiring board according to any one of the above aspects, which is an interposer.

[0012] According to yet another aspect of the present invention, there is provided the wiring board according to any one of the above aspects, wherein the groove has no corners in a cross section perpendicular to the longitudinal direction thereof.

[0013] According to yet another aspect of the present invention, there is provided the wiring board according to any one of the above aspects, wherein the groove is provided so as to surround each of the two or more mounting regions.

[0014] According to yet another aspect of the present invention, there is provided a wiring board according to any of the above aspects, comprising two or more structures each including an insulating resin layer and a conductor pattern provided thereon, stacked on top of each other, wherein the insulating resin layer of the uppermost of the two or more structures has a recess that opens on its upper surface at the position of the groove, and a stress relaxation layer that covers the inner surface of the recess and has a thermal expansion coefficient smaller than that of the insulating resin layer.

[0015] According to yet another aspect of the present invention, there is provided a wiring substrate relating to the above-mentioned side, wherein the bottom surface of the recess is part of the upper surface of the insulating resin layer included in the second-highest one of the two or more structures.

[0016] According to yet another aspect of the present invention, there is provided a wiring board with a support, comprising: a wiring board according to any one of the above aspects; and a support that supports the wiring board.

[0017] According to yet another aspect of the present invention, there is provided an aggregate substrate including a plurality of portions to be separated into individual wiring substrates according to any of the above aspects.

[0018] According to yet another aspect of the present invention, there is provided an aggregate substrate with supports, comprising: an aggregate substrate according to the above aspect; and a support that supports the aggregate substrate.

[0019] According to yet another aspect of the present invention, there is provided a packaged device comprising a wiring substrate according to any of the above aspects, two or more functional devices surface-mounted in the two or more mounting areas, two or more first portions located between the wiring substrate and the two or more functional devices, and a sealing resin layer including a second portion that connects adjacent ones of the two or more first portions to each other and covers the side walls and bottom surface of the groove.

[0020] According to yet another aspect of the present invention, there is provided a packaged device according to the above aspect, wherein the wiring board is made up of two or more structures stacked on top of each other, each structure including an insulating resin layer and a conductor pattern provided thereon, and the insulating resin layer of the uppermost structure among the two or more structures has a recess that opens on its upper surface at the position of the groove, and a stress relaxation layer that covers the inner surface of the recess and has a thermal expansion coefficient that is smaller than that of the insulating resin layer and larger than that of the sealing resin layer.

[0021] According to yet another aspect of the present invention, there is provided a packaged device according to the above aspect, wherein the bottom surface of the recess is part of the upper surface of the insulating resin layer included in the second-highest one of the two or more structures.

[0022] According to yet another aspect of the present invention, there is provided a packaged device according to any one of the above aspects, wherein the sealing resin layer is an underfill layer whose upper surface is recessed at the position of the groove.

[0023] According to yet another aspect of the present invention, there is provided the packaged device according to any one of the above aspects, wherein the sealing resin layer is a molded resin layer in which the two or more functional devices are embedded. [Effects of the Invention]

[0024] According to the present invention, a technique useful for suppressing the occurrence of cracks in a wiring board on which two or more functional devices are surface-mounted is provided. [Brief explanation of the drawings]

[0025] [Figure 1] FIG. 1 is a top view showing a packaged device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view of the packaged device shown in FIG. 1 taken along line II-II. [Figure 3] FIG. 3 is an enlarged cross-sectional view of a portion of the packaged device shown in FIGS. [Figure 4] FIG. 4 is a cross-sectional view illustrating a step in a method for manufacturing the packaged device shown in FIGS. [Figure 5] FIG. 5 is a cross-sectional view illustrating another step in the method of manufacturing the packaged device shown in FIGS. [Figure 6] FIG. 6 is a cross-sectional view illustrating yet another step in the method for manufacturing the packaged device shown in FIGS. [Figure 7] FIG. 7 is a cross-sectional view illustrating yet another step in the method for manufacturing the packaged device shown in FIGS. [Figure 8] FIG. 8 is a cross-sectional view illustrating yet another step in the method for manufacturing the packaged device shown in FIGS. [Figure 9] FIG. 9 is a cross-sectional view illustrating yet another step in the method for manufacturing the packaged device shown in FIGS. [Figure 10] FIG. 10 is a cross-sectional view illustrating yet another step in the method of manufacturing the packaged device shown in FIGS. [Figure 11] FIG. 11 is a cross-sectional view illustrating yet another step in the method for manufacturing the packaged device shown in FIGS. [Figure 12] FIG. 12 is a cross-sectional view illustrating yet another step in the method for manufacturing the packaged device shown in FIGS. [Figure 13] FIG. 13 is a cross-sectional view illustrating yet another step in the method of manufacturing the packaged device shown in FIGS. [Figure 14] FIG. 14 is a cross-sectional view illustrating yet another step in the method of manufacturing the packaged device shown in FIGS. [Figure 15] FIG. 15 is an enlarged cross-sectional view showing a part of a packaged device according to a comparative example. [Figure 16] FIG. 16 is an enlarged cross-sectional view showing a part of a packaged device according to a first modification. [Figure 17]FIG. 17 is an enlarged cross-sectional view showing a part of a packaged device according to a second modification. [Figure 18] FIG. 18 is an enlarged cross-sectional view showing a part of a packaged device according to a third modification. [Figure 19] FIG. 19 is a top view showing a packaged device according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0026] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments described below are more specific embodiments of any of the above aspects. The following items can be incorporated into each of the above aspects, either singly or in combination.

[0027] Furthermore, the embodiments shown below are merely examples of configurations for embodying the technical idea of ​​the present invention, and the technical idea of ​​the present invention is not limited by the materials, shapes, structures, etc. of the components described below. Various modifications can be made to the technical idea of ​​the present invention within the technical scope defined by the claims.

[0028] In the drawings, elements having the same or similar functions are denoted by the same reference numerals, and redundant explanations will be omitted. Furthermore, the drawings are schematic, and the relationship between dimensions in one direction and dimensions in another direction, and the relationship between the dimensions of one member and the dimensions of another member, etc. may differ from the actual relationship.

[0029] <1> First embodiment <1.1> Packaged devices Fig. 1 is a top view showing a packaged device according to a first embodiment of the present invention. Fig. 2 is a cross-sectional view taken along line II-II of the packaged device shown in Fig. 1. Fig. 3 is a cross-sectional view showing an enlarged portion of the packaged device shown in Figs. 1 and 2. In this disclosure, the terms "upper surface" and "lower surface" refer to the two main surfaces of a plate-like member or a layer included therein, i.e., the surface perpendicular to the thickness direction and having the largest area, and the back surface thereof, and refer to the surface shown at the top and the surface shown at the bottom in the drawings, respectively.

[0030] 1 to 3 includes a wiring substrate 10A, a functional device 20, and a sealing resin layer 40. Here, the packaged device 1A includes two functional devices 20, but the number of functional devices 20 included in the packaged device 1A may be three or more.

[0031] Here, the wiring board 10A is an interposer. One main surface of the wiring board 10A has two or more mounting areas, each having two or more functional devices 20 surface-mounted thereon. Here, the wiring board 10A is configured to electrically connect the functional device 20 surface-mounted in one of the mounting areas to the functional device 20 surface-mounted in the other mounting area. As described above, here, the number of functional devices 20 included in the packaged device 1A is two, and therefore the number of mounting areas is also two. The main surface of the wiring board 10A is provided with a groove G that separates adjacent mounting areas.

[0032] The wiring board 10A includes two or more stacked structures, each of which includes an insulating resin layer 11 shown in Fig. 3 and a conductor pattern provided thereon. The wiring board 10A further includes a main conductor layer 12 located on the lower surface of the lowest structure. This main conductor layer 12 forms a plurality of pads.

[0033] Here, the number of the above structures included in wiring board 10A is 3. The number of the above structures included in wiring board 10A may be 1 or 2, or may be 4 or more.

[0034] The insulating resin layer 11 is made of, for example, a cured product of a photosensitive resin or a thermosetting resin, and may have a single-layer structure or a multi-layer structure.

[0035] Each insulating resin layer 11 has a plurality of through holes. The uppermost insulating resin layer 11 has a groove-shaped recess that opens at the position of the groove G on its upper surface.

[0036] Here, the depth D1 of the recess in the uppermost insulating resin layer 11 is equal to the thickness of this insulating resin layer 11. That is, here, the bottom surface of the recess is part of the upper surface of the insulating resin layer 11 included in the second-highest structure. The depth D1 may be smaller than the thickness of the uppermost insulating resin layer 11, or may be larger than the thickness of the uppermost insulating resin layer 11.

[0037] Also, here, the width W of the recess is larger than the distance between adjacent functional devices 20. The width W may be equal to the distance between adjacent functional devices 20, or may be smaller than the distance between adjacent functional devices 20.

[0038] Here, the width W is larger than the depth D1. The width W may be equal to the depth D1 or may be smaller than the depth D1.

[0039] The depth D1 is preferably in the range of 1 μm to 100 μm, and more preferably in the range of 1 μm to 10 μm. The width W is preferably in the range of 0.5 to less than 2 times the distance A between adjacent functional devices 20, and more preferably in the range of 0.9 to less than 1.5 times. Alternatively, the width W is preferably in the range of 50 μm to 2000 μm, and more preferably in the range of 90 μm to 1500 μm.

[0040] Here, each of the conductor patterns includes a main conductor layer 12 and a seed layer 13 or a part thereof. The main conductor layer 12 is made of a first metal material such as copper or an alloy containing copper. The seed layer 13 is made of a second metal material such as copper, a copper alloy, titanium, tungsten, or nickel. The seed layer 13 may have a single-layer structure or a multi-layer structure.

[0041] The main conductor layer 12 included in the above structures other than the top layer includes a via portion located in the through hole of the insulating resin layer 11 included in the structure, and a land portion and a wiring portion located on the upper surface of the insulating resin layer 11. The seed layer 13 included in the above structures other than the top layer includes a portion interposed between the insulating resin layer 11 included in the structure and the land portion, a portion interposed between the insulating resin layer 11 included in the structure and the wiring portion, a portion interposed between the insulating resin layer 11 and the via portion, and a portion interposed between the via portion and the main conductor layer 12 located below it.

[0042] The main conductor layer 12 included in the uppermost structure includes via portions located in through holes of the insulating resin layer 11 included in this structure, and pad portions located on the upper surface of this insulating resin layer 11. The pad portions included in the main conductor layer 12 of the uppermost layer are arranged in the mounting area. The pad portions included in the main conductor layer 12 of the uppermost layer form a plurality of pad groups corresponding to the plurality of mounting areas.

[0043] The seed layer 13 included in the uppermost structure includes a portion interposed between the insulating resin layer 11 included in the structure and the pad portion, a portion interposed between this insulating resin layer 11 and the via portion, a portion interposed between the via portion and the main conductor layer 12 located below it, and a portion covering the inner surface of a recess provided in this insulating resin layer 11. Here, the portion of the seed layer 13 that covers the inner surface of the recess provided in the insulating resin layer 11 is a stress relaxation layer 15.

[0044] The seed layer 13 may not include a portion that covers the inner surface of a recess provided in the insulating resin layer 11. In this case, the stress relaxation layer 15 may be provided separately from the seed layer 13. The stress relaxation layer 15 may have a multi-layer structure. In this case, the stress relaxation layer 15 may be provided separately from the seed layer 13, or a part of the seed layer 13 may be used as one of the layers included in the stress relaxation layer 15.

[0045] The stress relaxation layer 15 has a thickness that is smaller than the depth D1 of the recess in the uppermost insulating resin layer 11 and smaller than half the width W of the recess. The stress relaxation layer 15 has a surface that conforms to the inner surface of the recess in the uppermost insulating resin layer 11 so as to form a groove G that separates adjacent mounting areas. The thickness of the stress relaxation layer 15 is preferably 10 nm or more, more preferably 100 nm or more, and even more preferably 200 nm or more. In one example, the thickness of the stress relaxation layer 15 is 300 nm or less, and in another example, 400 nm or less.

[0046] The stress relaxation layer 15 has a thermal expansion coefficient that is smaller than that of the insulating resin layer 11 and larger than that of the sealing resin layer 40. According to one example, the thermal expansion coefficient of the sealing resin layer 40 is 5×10 -6 / ℃ or more 10×10 -6 / °C or less, and the thermal expansion coefficient of the insulating resin layer 11 is 40×10 -6 / ℃ or more 100×10 -6 / °C or less. In this case, the material of the stress relaxation layer 15 is, for example, copper (17×10 -6 / ℃), titanium (8×10 -6 / ℃), nickel (13×10 -6 / ℃), or gold (14×10 -6 / °C), or an alloy containing two or more of them can be used. The number in parentheses following each material indicates the thermal expansion coefficient of that material. Other metal materials may also be used for the stress relaxation layer 15. Materials other than metal materials may also be used for the stress relaxation layer 15.

[0047] The functional devices 20 are respectively bonded to the mounting areas of the wiring substrate 10A via bonding conductors 30. Here, the functional devices 20 are bonded to the wiring substrate 10A by flip-chip bonding. The material of the bonding conductors 30 is, for example, one or more of copper, a copper-containing alloy, tin, and a tin-containing alloy. According to one example, the bonding conductors 30 are solder bumps.

[0048] Each of the functional devices 20 is a device that operates when supplied with at least one of power and an electrical signal, a device that outputs at least one of power and an electrical signal in response to an external stimulus, or a device that operates when supplied with at least one of power and an electrical signal and outputs at least one of power and an electrical signal in response to an external stimulus. The functional device 20 is in the form of a chip, such as a semiconductor chip or a chip in which circuits and elements are formed on a substrate made of a material other than a semiconductor, such as a glass substrate. The functional device 20 may include, for example, one or more of a large-scale integrated circuit (LSI), a memory, an imaging element, a light-emitting element, and a microelectromechanical system (MEMS). The MEMS may include, for example, one or more of a pressure sensor, an acceleration sensor, a gyro sensor, a tilt sensor, a microphone, and an acoustic sensor. According to one example, the functional device 20 is a semiconductor chip including an LSI.

[0049] The functional devices 20 are spaced apart from one another by a small gap, with the distance between adjacent functional devices 20 preferably being in the range of 1 μm to 5000 μm, and more preferably being in the range of 1 μm to 1000 μm.

[0050] The distance D2 from a plane including the lower surface of the functional device 20 to the bottom surface of the recess provided in the top insulating resin layer 11 is preferably in the range of 1 μm to 2000 μm, and more preferably in the range of 1 μm to 1000 μm.

[0051] The sealing resin layer 40 includes first portions located between the wiring substrate 10A and the functional device 20, and second portions that connect adjacent first portions to each other and cover the side walls and bottom surface of the groove G.

[0052] Here, the sealing resin layer 40 is an underfill layer. Also, here, the upper surface of the sealing resin layer 40 is recessed in a groove shape at the position of the groove G.

[0053] The thickness of the second portion of the sealing resin layer 40 is preferably 1 μm or more, more preferably 5 μm or more, and even more preferably 10 μm or more. The upper surface of the second portion may be located below the opening of the groove G, at the same height as the opening of the groove G, or higher than the opening of the groove G. When the upper surface of the second portion is located higher than the opening of the groove G, the upper surface of the second portion may be located below the lower surface of the functional device 20, at the same height as the lower surface of the functional device 20, or higher than the lower surface of the functional device 20. When the upper surface of the second portion is located higher than the lower surface of the functional device 20, the upper surface of the second portion may be located below the upper surface of the functional device 20, at the same height as the upper surface of the functional device 20, or higher than the upper surface of the functional device 20.

[0054] The sealing resin layer 40 securely fixes the functional device 20 to the wiring substrate 10A and prevents the bonding portion from being exposed to the external environment. This improves connection reliability. For example, an epoxy resin can be used as the sealing resin layer 40.

[0055] <1.2> Manufacturing method of packaged device The above-described packaged device 1A can be manufactured, for example, by the following method.

[0056] 4-14 are cross-sectional views illustrating a method for manufacturing the packaged device shown in FIGS. 1-3.

[0057] First, a structure shown in Fig. 4 is prepared. The structure shown in Fig. 4 includes a support 61, and a release layer 62 and a protective layer 63 provided in this order thereon.

[0058] The support 61 is a base material for forming the insulating resin layer 11, the conductor pattern, etc. For example, a glass substrate, a silicon substrate, a ceramic substrate, a metal substrate, or an organic substrate can be used as the support 61. When the release layer 62 exhibits a release action upon receiving light energy, it is preferable to use a glass substrate with excellent light transmittance as the support 61.

[0059] The release layer 62 is a layer that facilitates peeling of the wiring substrate 10A or the assembly substrate from the support 61 in the final process. The release layer 62 can be made of, for example, a material that causes chemical peeling, which causes the layer to lose its adhesive strength and peel off when exposed to external energy such as heat or light, or a material that causes mechanical peeling, which causes the layer to physically peel off when external force is applied. The material of the release layer 62 can be selected from, for example, resin and metal.

[0060] The protective layer 63 is a layer for preventing adhesion between the release layer 62 and the insulating resin layer 11. If the protective layer 63 is conductive, it can also be used as a power supply layer when the lowermost main conductor layer 12 is formed by electrolytic plating. The material of the protective layer 63 can be, for example, a metal.

[0061] 5, a resist pattern 71 is formed on the protective layer 63. The resist pattern 71 is formed so as to have a plurality of through holes at the positions of the pad portions formed by the lowermost main conductor layer 12. Then, the main conductor layer 12 is formed in the regions of the upper surface of the protective layer 63 that are exposed at the positions of the through holes of the resist pattern 71.

[0062] This main conductor layer 12 forms a plurality of pads for joining the wiring board 10A to another wiring board such as a motherboard. The main conductor layer 12 can be formed by, for example, a plating method such as electrolytic plating, a sputtering method, a vapor deposition method, or a coating or printing method using a metal paste. The main conductor layer 12 is preferably made of copper or a copper alloy.

[0063] Next, the resist pattern 71 is removed. Subsequently, as shown in FIG. 6, an insulating resin layer 11 having through-holes at the positions of the pad portions of the main conductor layer 12 is formed on the protective layer 63 and the main conductor layer 12. The insulating resin layer 11 can be obtained, for example, by forming a photosensitive resin layer and then subjecting this photosensitive resin layer to pattern exposure and development. Alternatively, the insulating resin layer 11 can also be obtained by forming a cured resin layer made of a thermosetting resin or the like and then subjecting this cured resin layer to drilling processes such as laser processing and dry etching.

[0064] 7, a seed layer 13 is formed. The seed layer 13 is formed so as to cover the upper surface of the insulating resin layer 11, the side walls of the through holes provided in the insulating resin layer 11, and the exposed areas of the upper surface of the main conductor layer 12. Here, the upper surface of the seed layer 13 is conformal to the upper surface of the composite including the insulating resin layer 11 and the main conductor layer 12.

[0065] The seed layer 13 is a layer used as a power supply layer when the main conductor layer 12 is formed by electroplating in the next step. The seed layer 13 may be made of any conductive material. Examples of materials that can be used for the seed layer 13 include copper, copper alloys, titanium, tungsten, and nickel. The seed layer 13 may have a single-layer structure or a multi-layer structure. The seed layer 13 may be formed by, for example, a plating method such as electroless plating, a sputtering method, a vapor deposition method, or a coating or printing method using a metal paste. If the main conductor layer 12 is formed in the next step without using electroplating, the seed layer 13 can be omitted.

[0066] Next, as shown in FIG. 8 , a resist pattern 72 is formed on the seed layer 13. The resist pattern 72 is formed so that it has a plurality of through holes at the positions of the plurality of land portions formed by the second-lowest main conductor layer 12, and a plurality of grooves at the positions of the plurality of wiring portions formed by the second-lowest main conductor layer 12. Some of the through holes in the resist pattern 72 are positioned directly above the through holes in the insulating resin layer 11. Each of the grooves in the resist pattern 72 has a bottom surface formed by a portion of the upper surface of the insulating resin layer 11, and is formed so that one end is continuous with a certain through hole and the other end is continuous with another through hole. Next, a main conductor layer 12 is formed on the upper surface of the seed layer 13 in the region exposed by the through holes and grooves in the resist pattern 72. This main conductor layer 12 can be formed by the method described above for the lowermost main conductor layer 12.

[0067] Next, the resist pattern 72 is removed. Subsequently, the exposed portion of the seed layer 13 is removed, as shown in Fig. 9. The exposed portion of the seed layer 13 can be removed by an etching method such as a wet etching method or a dry etching method.

[0068] After forming the first layer structure including the insulating resin layer 11 and the main conductor layer 12 thereon in the above manner, the first process described with reference to Figures 6 to 9 is carried out again to form the second layer structure. Then, the second process described below is carried out to form the topmost insulating resin layer 11 and the seed layer 13 thereon. This results in the structure shown in Figure 10.

[0069] 6 and 7 except for the following point: In other words, the insulating resin layer 11 is formed so as to have through holes at the positions of the lands formed by the main conductor layer 12 located directly below it, and also to have recesses corresponding to the grooves G. The seed layer 13 is formed so as to cover the upper surface of the insulating resin layer 11, the side walls of the through holes formed in the insulating resin layer 11, and the exposed areas of the upper surface of the main conductor layer 12, and also to cover the inner surfaces of the recesses formed in the insulating resin layer 11.

[0070] 11, a resist pattern 73 is formed on the seed layer 13. The resist pattern 73 has through holes at the positions of the pad portions formed by the uppermost main conductor layer 12, and is formed so as to cover the seed layer 13 at other positions. Subsequently, a main conductor layer 12 is formed on the upper surface of the seed layer 13 in the areas exposed by the through holes in the resist pattern 73. This main conductor layer 12 can be formed by the method described above for the lowermost main conductor layer 12.

[0071] Next, the resist pattern 73 is removed. Subsequently, as shown in Fig. 12, a resist pattern 74 is formed on the seed layer 13. The resist pattern 74 is formed to cover the portion of the seed layer 13 that covers the inner surface of the groove-shaped recess in the uppermost main conductor layer 12, and to expose other portions of the seed layer 13. The resist pattern 74 may also be formed to cover the portions of the seed layer 13 on both sides of the groove-shaped recess in the uppermost main conductor layer 12.

[0072] Next, the exposed portion of seed layer 13 is removed, and then resist pattern 74 is removed to obtain the wiring substrate with support shown in Fig. 13. Of seed layer 13, the portion covering the inner surface of the recess provided in uppermost insulating resin layer 11 is stress relaxation layer 15. The exposed portion of seed layer 13 can be removed by the method described with reference to Fig. 9.

[0073] Here, a wiring substrate with supports is manufactured, but an aggregate substrate with supports can also be manufactured by the same method as above. When an aggregate substrate with supports is manufactured, at some stage, the aggregate substrate is singulated into wiring substrates 10A, or the aggregate substrate with supports is singulated into wiring substrates with supports. This singulation may be performed before or after the functional device 20 is mounted.

[0074] Next, as shown in FIG. 14 , functional devices 20 are mounted on the wiring substrate 10A. Subsequently, a sealant is injected between them. For example, the sealant is injected between each functional device 20 and the wiring substrate 10A, starting from the position farthest from the groove G. When the sealant is injected in this manner, the sealant injected between one of the adjacent functional devices 20 and the wiring substrate 10A and the sealant injected between the other of the adjacent functional devices 20 and the wiring substrate 10A spread between the functional devices 20 and the wiring substrate 10A, and some of them flow into the groove G. As a result, the sealant layer formed by the sealant spreading between one of the adjacent functional devices 20 and the wiring substrate 10A and the sealant layer formed by the sealant spreading between the other of the adjacent functional devices 20 and the wiring substrate 10A merge at the position of the groove G to form a single sealant layer. This sealant layer is cured to obtain the sealing resin layer 40. In this manner, a packaged device with a support body is obtained, which includes the packaged device 1A and the support body 61 that supports the packaged device 1A.

[0075] Thereafter, the support 61 is removed from the packaged device 1A. This removal is performed, for example, by the chemical peeling or mechanical peeling described above. Next, the protective layer 63 remaining on the lower surface of the wiring substrate 10A is removed. The protective layer 63 can be removed, for example, by an etching method such as a wet etching method or a dry etching method.

[0076] In this manner, the packaged device 1A described with reference to FIGS. 1 to 3 is obtained.

[0077] <1.3> Effects The packaged device 1A described above is less susceptible to cracks occurring in the wiring substrate 10A, as will be explained below.

[0078] Fig. 15 is an enlarged cross-sectional view of a portion of a packaged device according to a comparative example. The packaged device 1X shown in Fig. 15 is similar to the packaged device 1A described with reference to Figs. 1 to 3, except for the following points.

[0079] That is, the packaged device 1X includes a wiring board 10X instead of the wiring board 10A. The wiring board 10X is similar to the wiring board 10A except that the uppermost insulating resin layer 11 does not have a recess, and therefore does not have a groove G on its upper surface that separates adjacent mounting areas, and the wiring board 10X does not include a stress relief layer 15. Furthermore, in the packaged device 1X, the sealing resin layer 40 interposed between one functional device 20 and the wiring board 10X and the sealing resin layer 40 interposed between the other functional device 20 and the wiring board 10X are spaced apart from each other.

[0080] In the packaged device 1X, the insulating resin layer 11 has a large thermal expansion coefficient, while the functional device 20 has a small thermal expansion coefficient. Generally, the thermal expansion coefficient of the sealing resin layer 40 is between the thermal expansion coefficients of the insulating resin layer 11 and the functional device 20, but the difference between the thermal expansion coefficients of the insulating resin layer 11 and the sealing resin layer 40 is larger than the difference between the thermal expansion coefficients of the sealing resin layer 40 and the functional device 20.

[0081] Furthermore, in the packaged device 1X, the multilayer wiring structure consisting of a plurality of conductor patterns is bonded to the functional device 20, which has a small thermal expansion coefficient, via the bonding conductor 30. Therefore, in the portion of the uppermost insulating resin layer 11 located directly below the functional device 20, particularly in the vicinity of the bonding conductor 30, the expansion or contraction in the in-plane direction due to temperature changes is restricted by the multilayer wiring structure. On the other hand, in the portion of the uppermost insulating resin layer 11 corresponding to the gaps between the functional devices 20 and their vicinity, the expansion or contraction in the in-plane direction due to temperature changes is not restricted as much as in the portion located directly below the functional device 20.

[0082] Thus, in the packaged device 1X, the portions of the uppermost insulating resin layer 11 corresponding to and adjacent to the gaps between the functional devices 20 are susceptible to in-plane expansion or contraction due to temperature changes, and these portions are sandwiched between portions that are less susceptible to in-plane expansion or contraction due to temperature changes. The difference between the thermal expansion coefficient of the insulating resin layer 11 and the thermal expansion coefficient of the sealing resin layer 40 is greater than the difference between the thermal expansion coefficient of the sealing resin layer 40 and the thermal expansion coefficient of the functional device 20. Furthermore, since the sealing resin layer 40 interposed between one functional device 20 and the wiring board 10X and the sealing resin layer 40 interposed between the other functional device 20 and the wiring board 10X are spaced apart from each other, the insulating resin layer 11 is exposed at the gaps between the adjacent functional devices 20 without being covered by the sealing resin layer 40, and this may cause significant deformation.

[0083] Therefore, in the packaged device 1X, under high or low temperature conditions, stress is concentrated in the region of the uppermost insulating resin layer 11 near the gap between adjacent functional devices 20. Therefore, the packaged device 1X is prone to cracks CK in this region.

[0084] In contrast, the packaged device 1A has a groove G on its top surface that separates adjacent mounting areas from each other. In the packaged device 1A, the sealing resin layer 40 includes first portions located between the wiring substrate 10A and the functional device 20, and second portions that connect the adjacent first portions to each other and cover the side walls and bottom surfaces of the groove G.

[0085] The groove G increases the distance D2 from the plane including the lower surfaces of the functional devices 20 to the bottom surface of the recess provided in the uppermost insulating resin layer 11, i.e., the distance from the plane including the lower surfaces of the functional devices 20 to the upper surface of the insulating resin layer 11 located directly below the gap between the functional devices 20. Increasing the distance D2 increases the effect of the sealing resin layer 40 in alleviating the above-mentioned stress. Therefore, the packaged device 1A is less likely to develop cracks in the wiring substrate 10A.

[0086] Furthermore, wiring board 10A includes stress relaxation layer 15 that covers the inner surface of a recess provided in uppermost insulating resin layer 11. The thermal expansion coefficient of stress relaxation layer 15 is between the thermal expansion coefficient of insulating resin layer 11 and the thermal expansion coefficient of sealing resin layer 40. Therefore, packaged device 1A is less susceptible to cracking than a similar packaged device that does not include stress relaxation layer 15.

[0087] Thus, the structure described above for packaged device 1A makes it possible to achieve high reliability.

[0088] <1.4> Variations Many variations on the structures and manufacturing methods described above are possible.

[0089] <1.4.1> First modified example 16 is an enlarged cross-sectional view of a portion of a packaged device according to a first modification. Packaged device 1B shown in FIG. 16 is similar to packaged device 1A except that it includes wiring board 10B instead of wiring board 10A. Wiring board 10B is similar to wiring board 10A except that it does not include stress relaxation layer 15.

[0090] Although packaged device 1B does not include stress relaxation layer 15, it does include grooves G, which makes it less susceptible to cracks in wiring board 10B, although not as susceptible as packaged device 1A. Furthermore, because wiring board 10B does not include stress relaxation layer 15, it can be manufactured without forming and removing resist pattern 74 shown in FIG.

[0091] <1.4.2> Second modified example 17 is an enlarged cross-sectional view of a portion of a packaged device according to a second modification. Packaged device 1C shown in FIG. 17 is similar to packaged device 1A, except that it includes wiring board 10C instead of wiring board 10A. Wiring board 10C is similar to wiring board 10A, except that the cross sections of the recesses in uppermost insulating resin layer 11 are squared rather than rectangular, and therefore the cross sections of grooves G perpendicular to their length direction are squared rather than rectangular, and in this case, these cross sections are approximately semicircular.

[0092] If the cross section of the groove G has corners, stress may be concentrated at the corners. Packaged device 1C, which employs a structure in which the cross section of the groove G does not have corners, is less susceptible to cracking than packaged device 1A.

[0093] The cross section of the groove G, which does not have corners in a cross section perpendicular to the longitudinal direction, does not have to be substantially semicircular. For example, the cross section may be substantially semi-elliptical, substantially semi-oval, substantially rectangular with rounded corners, or substantially trapezoidal with rounded corners.

[0094] The cross-sectional shape of the groove G can be changed, for example, by changing the cross-sectional shape of the recess provided in the insulating resin layer 11. When the insulating resin layer 11 is formed using a photosensitive resin, the cross-sectional shape of the recess can be tapered by adjusting the exposure amount, or can be made to have no corners by generating a footing. When the recess is formed using a laser, the cross-sectional shape of the recess can be changed by changing the intensity of the laser beam or the processing time.

[0095] <1.4.3> Third modified example Fig. 18 is an enlarged cross-sectional view of a portion of a packaged device according to Modification 3. Packaged device 1D shown in Fig. 18 is similar to packaged device 1A except that it includes wiring board 10B instead of wiring board 10A, and the sealing resin layer 40 is replaced by a molded resin layer in which multiple functional devices 20 are integrally embedded, instead of an underfill layer.

[0096] Like packaged device 1B, packaged device 1D employing such a structure is also less susceptible to cracks in wiring substrate 10B. Furthermore, since wiring substrate 10B does not include stress relaxation layer 15, it can be manufactured without forming and removing resist pattern 74 shown in FIG.

[0097] <1.4.3> Other variations The above-described configurations can be combined with each other. For example, in the packaged devices 1A and 1C, the encapsulating resin layer 40 may be the molded resin layer described above for the packaged device 1D instead of the underfill layer. In the packaged device 1C, the stress relief layer 15 may be omitted. In the packaged device 1C in which the stress relief layer 15 is omitted, the encapsulating resin layer 40 may be the molded resin layer described above for the packaged device 1D instead of the underfill layer.

[0098] The modifications described above regarding the packaged device and the wiring substrate may be applied to other structures such as a wiring substrate with a support, an aggregate substrate, and an aggregate substrate with a support, etc. Furthermore, the wiring substrate may be a wiring substrate other than an interposer.

[0099] Various modifications are possible in the manufacturing method of structures such as packaged devices and wiring boards. For example, the order of forming the layers included in the wiring board may be reversed. In this case, before mounting the functional device 20 on the wiring board with a support, the wiring board with a support may be mounted on another wiring board and the support 61 and the like may be removed, and then the functional device 20 may be mounted on the former wiring board. When the order of forming the layers included in the wiring board is reversed, a wiring board with a support that does not have the groove G and / or stress relaxation layer 15 may be first manufactured, and then this wiring board with a support may be mounted on another wiring board and the support 61 and the like may be removed, and then the groove G and / or stress relaxation layer 15 may be formed.

[0100] <2> Second embodiment FIG. 19 is a top view showing a packaged device according to a second embodiment of the present invention.

[0101] 19 is similar to packaged device 1A, except that it includes wiring board 10E instead of wiring board 10A. Wiring board 10E is similar to wiring board 10A, except that instead of providing grooves G only between adjacent mounting areas, grooves G are provided so as to surround each of the mounting areas, and in order to form grooves G, recesses in uppermost insulating resin layer 11 are provided so as to surround each of the portions corresponding to the mounting areas.

[0102] As described above, in the packaged device 1X, stress is concentrated in the region of the uppermost insulating resin layer 11 near the gap between adjacent functional devices 20. In the packaged device 1A, stress may also be concentrated in regions of the peripheral region of the mounting area other than the region near the gap between adjacent functional devices 20, although not as much as in this region. By employing the above-described structure for the packaged device 1E, cracks can be made less likely to occur in these regions, and therefore even higher reliability can be achieved compared to the packaged device 1A.

[0103] The packaged device 1E and the wiring board 10E can be modified in the same manner as in the first embodiment, for example.

[0104] The structure described above for the packaged device 1E and the wiring board 10E may be employed in other structures such as a wiring board with a support, an aggregate substrate, an aggregate substrate with a support, etc. These structures can also be modified in the same manner as in the first embodiment, for example. [Explanation of symbols]

[0105] 1A...packaged device, 1B...packaged device, 1C...packaged device, 1D...packaged device, 1E...packaged device, 1X...packaged device, 10A...wiring board, 10B...wiring board, 10C...wiring board, 10E...wiring board, 10X...wiring board, 11...insulating resin layer, 12...main conductor layer, 13...seed layer, 15...stress relaxation layer, 20...functional device, 30...bonding conductor, 40...encapsulating resin layer, 61...support, 62...peeling layer, 63...protective layer, 71...resist pattern, 72...resist pattern, 73...resist pattern, 74...resist pattern, CK...crack, D1...depth, D2...distance, G...groove, W...width.

Claims

1. A wiring board having, on one main surface thereof, two or more mounting areas in which two or more functional devices are surface-mounted, and on said main surface, grooves are provided to separate adjacent ones of said two or more mounting areas.

2. 2. The wiring board according to claim 1, configured to electrically connect the functional device surface-mounted in one of the two or more mounting areas with the functional device surface-mounted in another of the two or more mounting areas.

3. 2. The wiring board according to claim 1, which is an interposer.

4. 2. The wiring board according to claim 1, wherein the groove has a cross section perpendicular to its length direction that has no corners.

5. The wiring board according to claim 1 , wherein the groove is provided so as to surround each of the two or more mounting areas.

6. Two or more structures each including an insulating resin layer and a conductor pattern provided thereon, stacked on one another, wherein the insulating resin layer included in the uppermost structure of the two or more structures has a recessed portion that opens on its upper surface at the position of the groove; a stress relaxation layer that covers the inner surface of the recess and has a thermal expansion coefficient smaller than that of the insulating resin layer; The wiring board according to claim 1 , comprising:

7. The wiring board according to claim 6 , wherein the bottom surface of the recess is a part of the upper surface of the insulating resin layer included in the second-highest one of the two or more structures.

8. A wiring board with a support, comprising: the wiring board according to claim 1; and a support that supports the wiring board.

9. An aggregate substrate including a plurality of portions to be separated into the wiring substrates according to any one of claims 1 to 7.

10. A support-attached aggregate substrate comprising: the aggregate substrate according to claim 9; and a support that supports the aggregate substrate.

11. A wiring board according to any one of claims 1 to 5; the two or more functional devices surface-mounted on the two or more mounting areas, respectively; a sealing resin layer including two or more first portions located between the wiring substrate and the two or more functional devices, and a second portion connecting adjacent ones of the two or more first portions to each other and covering the sidewalls and bottom surface of the groove; A packaged device comprising:

12. The wiring board is Two or more structures each including an insulating resin layer and a conductor pattern provided thereon, stacked on one another, wherein the insulating resin layer included in the uppermost structure of the two or more structures has a recessed portion that opens on its upper surface at the position of the groove; a stress relaxation layer that covers the inner surface of the recess and has a thermal expansion coefficient that is smaller than that of the insulating resin layer and larger than that of the sealing resin layer; The packaged device of claim 11 , comprising:

13. The packaged device according to claim 12 , wherein the bottom surface of the recess is a part of the upper surface of the insulating resin layer included in the second-highest one of the two or more structures.

14. The packaged device according to claim 11 , wherein the encapsulating resin layer is an underfill layer whose upper surface is recessed at the position of the groove.

15. The packaged device according to claim 11 , wherein the sealing resin layer is a molded resin layer in which the two or more functional devices are embedded.

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