Systems and methods for fabrication of superconducting integrated circuits

Abstract

To provide a system and method for fabricating integrated circuits for superconducting applications.SOLUTION: A method of depositing a protective cap over a trilayer Josephson junction includes depositing a trilayer comprising a Nb / AlOx / Nb trilayer over a wafer, over a surface of a dielectric layer, or over a surface of a metal layer, patterning the trilayer by a lithographic process, pre-cleaning an exposed surface (e.g., a top surface) of the patterned trilayer, and depositing a protective cap over the trilayer. The cap comprises silicon nitride and serves to protect the tri-layer (specifically, the aluminum oxide layer) from degradation in subsequent processing.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present systems and methods relate to the fabrication of integrated circuits for superconducting applications. [Background technology]

[0002] Methods for quantum computing There are several general approaches to the design and operation of quantum computers. One such approach is the "circuit" or "gate" model of quantum computing, in which qubits are acted upon by a sequence of logic gates that are a compiled representation of an algorithm. Much research has focused on developing qubits with sufficient coherence to form the building blocks of circuit-model quantum computers.

[0003] Another approach to quantum computing involves using the natural physical evolution of a system of coupled quantum elements as a computing system. This approach may not utilize quantum gates or circuits. Instead, the computing system starts from a known initial Hamiltonian with easily accessible ground states and can be controllably guided to a final Hamiltonian whose ground states represent the solution to the problem. This approach typically does not require long qubit coherence times and can be more robust than circuit models. Examples of this type of approach include adiabatic quantum computing and quantum annealing.

[0004] quantum processor Quantum computing can be performed using a quantum processor, such as a superconducting quantum processor. A superconducting quantum processor can, for example, comprise a superconducting integrated circuit that includes many qubits, such as two or more superconducting qubits, and associated local bias elements. Further details of exemplary superconducting quantum processor systems and methods that can be fabricated according to the present system and method are described in U.S. Patent No. 7,135,701, U.S. Patent No. 7,418,283, U.S. Patent No. 7,533,068, U.S. Patent No. 7,619,437, U.S. Patent No. 7,639,035, U.S. Patent No. 7,898,282, U.S. Patent No. 8,008,942, U.S. Patent No. 8,190,548, U.S. Patent No. 8,195,596, U.S. Patent No. 8,283,943, and U.S. Patent Application Publication No. 2011-0022820, each of which is incorporated herein by reference in its entirety.

[0005] Superconducting qubit A superconducting qubit is a type of superconducting quantum device that can be included in a superconducting integrated circuit. Superconducting qubits can be divided into several categories depending on the physical properties used to encode information. For example, superconducting qubits can be classified as charge, flux, and phase devices. Charge devices store and manipulate information about the charge state of the device. Flux devices store and manipulate information about a variable related to the magnetic flux passing through some part of the device. Phase devices store and manipulate information about a variable related to the superconducting phase difference between two regions of the phase device. Recently, hybrid devices have been developed that use two or more of the charge, flux, and phase degrees of freedom.

[0006] Superconducting integrated circuits can include single flux quantum (SFQ) devices. The integration of SFQ devices with superconducting qubits is discussed, for example, in U.S. Patent Nos. 7,876,248, 8,035,540, 8,098,179, and U.S. Patent Application Publication No. 2011-0065586, each of which is incorporated by reference in its entirety.

[0007] Superconducting Processor A computer processor may take the form of a superconducting processor, which may not be a quantum processor in the traditional sense. For example, some embodiments of a superconducting processor may not focus on quantum effects such as quantum tunneling, superposition, and entanglement, but rather may operate by emphasizing different principles, such as those that govern the operation of classical computer processors. However, there may still be certain advantages to implementing such a “classical” superconducting processor. Due to the natural physical properties of classical superconducting processors, classical superconducting processors may be capable of higher switching speeds and shorter computation times than non-superconducting processors, and therefore, it may be more practical to solve certain problems with classical superconducting processors. The present systems and methods are particularly well suited for use in the fabrication of both superconducting quantum processors and classical superconducting processors.

[0008] Integrated circuit fabrication Traditionally, the fabrication of superconducting integrated circuits has not been performed in state-of-the-art semiconductor fabrication facilities. This may be due to the fact that some of the materials used in superconducting integrated circuits may contaminate semiconductor facilities. For example, gold may be used as resistors in superconducting circuits, but gold may contaminate the fabrication tools used to produce CMOS wafers in semiconductor facilities. As a result, superconducting integrated circuits containing gold are not typically processed in tools that process CMOS wafers.

[0009] Superconductor fabrication has typically been performed in a research environment where standard industry practices can be optimized for superconducting circuit production. Superconducting integrated circuits are often fabricated with tools traditionally used to fabricate semiconductor chips or integrated circuits. Due to issues unique to superconducting circuits, not all semiconductor processes and techniques can be transferred to superconductor chip manufacturing. Converting semiconductor processes and techniques for use in superconductor chip and circuit fabrication often requires modifications and fine-tuning. Such modifications and adjustments are usually not obvious and can require significant experimentation. The semiconductor industry faces problems and issues not necessarily related to the superconducting industry. Similarly, problems and issues related to the superconducting industry often have little or no relevance to standard semiconductor fabrication.

[0010] Any impurities in the superconducting chip can introduce noise that can impair or degrade the functionality of individual elements, such as superconducting qubits, and the superconducting chip as a whole. Because noise is a serious concern for the operation of quantum computers, steps should be taken to reduce the dielectric noise as much as possible.

[0011] The technical field of integrated circuit fabrication typically involves multiple processes that can be sequenced and / or combined to produce a desired effect. Exemplary systems and methods for superconducting integrated circuit fabrication that can be combined in whole or in part with at least some embodiments of the present systems and methods are described in U.S. Patent Application Publication No. 2011-0089405, which is incorporated herein by reference in its entirety.

[0012] etching Etching removes layers, such as substrates, dielectric layers, oxide layers, electrically insulating layers, and / or metal layers, according to a desired pattern delineated by photoresist or other masking techniques. Two exemplary etching techniques are chemical wet etching and chemical dry etching.

[0013] Chemical wet etching, or "wet etching," is typically accomplished by immersing the wafer in a corrosive bath, such as an acid bath. The etchant is typically contained in a temperature-controlled polypropylene bath. The bath is typically equipped with a ring-type plenum exhaust or a grooved exhaust at the rear of the etching station. A vertical laminar flow hood is typically used to supply uniformly filtered, particulate-free air to the upper surface of the etching bath.

[0014] Chemical dry etching, or "dry etching," is commonly used due to its ability to provide better control over the etching process and reduce contamination levels. Dry etching effectively etches the desired layer through the use of gases, either by chemical reaction, such as using chemically reactive gases, or through physical bombardment, such as plasma etching using argon atoms.

[0015] Plasma etching systems have been developed that can effectively etch silicon, silicon oxide, silicon nitride, aluminum, tantalum, tantalum compounds, chromium, tungsten, gold, and many other materials. Two types of plasma etch reactor systems are commonly used: barrel reactors and parallel-plate reactors. Both reactor types operate on the same principles and differ primarily in their construction. A typical reactor consists of a vacuum reactor chamber, usually made of aluminum, glass, or quartz. A radio frequency or microwave energy source (collectively referred to as an RF energy source) is used to activate a fluorine- or chlorine-based gas, which acts as an etchant. A wafer is placed in the chamber, which is then pumped out, and a reagent gas is introduced. The RF energy ionizes the gas, forming an etching plasma, which reacts with the wafer to form volatile products, which are then pumped away.

[0016] Physical etching processes use physical bombardment. For example, argon gas atoms can be used to physically bombard the layer to be etched, and a vacuum pumping system is used to remove the spalled material. Sputter etching is a physical technique involving ion bombardment and energy transfer. The wafer to be etched is attached to the negative pole or "target" of a glow discharge circuit. Argon positive ions bombard the wafer surface, resulting in spallation of surface atoms. Power is provided by an RF energy source. Ion beam etching and milling are physical etching processes that use a low-energy ion beam to remove material. The ion beam is extracted from an ionized gas (e.g., argon or argon / oxygen) or plasma created by an electrical discharge.

[0017] Reactive ion etching (RIE) is a combination of chemical and physical etching. During RIE, the wafer is placed in a chamber containing an airborne atmosphere of low-pressure chemical reactive gases (e.g., CF4, CCl4, CHF3, and many others). An electrical discharge creates an ion plasma with energies of several hundred electron volts. The ions strike the wafer surface perpendicularly, where they react to form volatile species that are removed by a low-pressure in-line vacuum system. Summary of the Invention [Means for solving the problem]

[0018] The method for forming a tri-layer Josephson junction can be summarized as including depositing a superconducting tri-layer including a base electrode layer, an insulating layer, and a counter-electrode layer, depositing a photoresist mask pattern over the superconducting tri-layer, and etching the pattern into the superconducting tri-layer to form at least one Josephson junction, wherein etching the pattern into the superconducting tri-layer to form at least one Josephson junction includes removing at least two portions of the counter-electrode layer to expose at least two portions of the base electrode layer and removing at least two portions of the insulating layer. Removing the at least two portions of the counter-electrode layer can include removing the at least two portions of the counter-electrode layer using a combination of SF6, BCl3, and Cl2, and removing the at least two portions of the insulating layer can include removing the at least two portions of the insulating layer using a combination of SF6, BCl3, and Cl2.

[0019] A method of forming a superconducting tri-layer can be summarized as including depositing a first layer of niobium, depositing an aluminum oxide layer over at least a portion of the first layer of niobium via atomic layer deposition, and depositing a second layer of niobium over at least a portion of the aluminum oxide layer. The method can further include depositing an aluminum layer over at least a portion of the first layer of niobium and depositing an aluminum oxide layer over at least a portion of the aluminum layer.

[0020] A method of forming a superconducting tri-layer in a chamber can be summarized as including the steps of depositing a base layer of niobium in the chamber, depositing an aluminum oxide layer in the chamber over at least a portion of the niobium base layer, filling the chamber with an inert gas to thermalize the niobium base layer and the aluminum oxide layer, pumping the inert gas out of the chamber, and depositing a top layer of niobium in the chamber over at least a portion of the aluminum oxide layer. The step of filling the chamber with an inert gas can include filling the chamber with argon.

[0021] A method for depositing a protective cap over a Josephson junction can be summarized as including depositing a superconducting tri-layer including an aluminum oxide layer, patterning the superconducting tri-layer to expose at least a portion of the aluminum oxide layer, pre-cleaning the exposed portions of the aluminum oxide layer, and depositing a protective cap over the tri-layer. Pre-cleaning the exposed portions of the aluminum oxide layer can include pre-cleaning the exposed portions of the aluminum oxide layer with ions. Pre-cleaning the exposed portions of the aluminum oxide layer can include pre-cleaning the exposed portions of the aluminum oxide layer via a mild anisotropic low-pressure etch.

[0022] A method for depositing a hybrid dielectric can be summarized as including depositing a first dielectric layer comprising a first dielectric material, depositing a second dielectric layer over at least a portion of the first dielectric layer, the second dielectric layer comprising the second dielectric material, and depositing a third dielectric layer over at least a portion of the second dielectric layer, the third dielectric layer comprising a third dielectric material. Depositing the third dielectric material may include depositing a material of the same type as the first dielectric material. Depositing the first dielectric material may include depositing a non-oxide dielectric, and depositing the second dielectric material may include depositing an oxide dielectric.

[0023] The superconducting integrated circuit can be summarized as including a first superconducting metal layer, a hybrid dielectric layer overlying the first superconducting metal layer, the hybrid dielectric layer comprising a first layer of silicon nitride directly overlying the first superconducting metal layer, a layer of silicon oxide directly overlying the first layer of silicon nitride, and a second layer of silicon nitride directly overlying the silicon oxide layer, and a second superconducting metal layer overlying the hybrid dielectric layer, the second superconducting metal layer directly overlying the second layer of silicon nitride of the hybrid dielectric layer.

[0024] A method for fabricating a superconducting integrated circuit can be summarized as including the steps of depositing a first dielectric layer, depositing a negative photoresist mask over the first dielectric layer, tracing a negative pattern of a desired circuit pattern such that the desired circuit pattern corresponds to areas of the first dielectric layer not directly covered by the negative photoresist mask, etching the desired circuit pattern in the first dielectric layer to create open features in the first dielectric layer, depositing a first superconducting metal layer over the first dielectric layer to at least partially fill the open features in the first dielectric layer, planarizing the first superconducting metal layer, depositing a second dielectric layer to create a desired inner-layer dielectric thickness, the inner-layer dielectric thickness being controlled by a deposition process, and depositing the second superconducting metal layer over the second dielectric layer. The step of depositing the first superconducting metal layer can include depositing the first superconducting metal layer via electroplating.

[0025] A method of fabricating a superconducting integrated circuit includes the steps of patterning a first superconducting metal layer, depositing a first dielectric layer over the first superconducting metal layer, depositing a first negative photoresist mask over the first dielectric layer, the first negative photoresist mask providing a negative of the location of at least one via such that the location of the at least one via corresponds to an area of ​​the first dielectric layer not directly covered by the first negative photoresist mask, and creating at least one hole corresponding to the at least one via. etching the first dielectric layer to form at least one hole exposing a portion of the first superconducting metal layer; depositing a second superconducting metal layer over the first dielectric layer to at least partially fill the at least one hole and provide at least a first portion of a first via; planarizing the second superconducting metal layer; depositing a second dielectric layer; and depositing a desired circuit pattern over the second dielectric layer such that the desired circuit pattern corresponds to an area of ​​the second dielectric layer not directly covered by the second negative photoresist mask. depositing a second negative photoresist mask tracing a negative of the circuit pattern of the first via; etching the desired circuit pattern in the second dielectric layer to create open features in the second dielectric layer; and depositing a third negative photoresist mask over the second dielectric layer, the third negative photoresist mask providing a negative of the location of at least one via such that the location of the at least one via corresponds to an area of ​​the second dielectric layer not directly covered by the third negative photoresist mask. a location of the at least one via within the open feature of the second dielectric layer; etching the second dielectric layer to create at least one hole corresponding to the at least one via, the at least one hole exposing a portion of a first portion of the first via; and depositing a third superconducting metal layer over the second dielectric layer to at least partially fill the at least one hole in the second dielectric layer and to provide a second portion of the first via and to at least partially fill the open feature of the second dielectric layer.and planarizing the third superconducting metal layer. At least one of the steps of depositing the second superconducting metal layer and depositing the third superconducting metal layer may include electroplating. At least one of the steps of planarizing the second superconducting metal layer and planarizing the third superconducting metal layer may include chemical mechanical planarization.

[0026] A substrate for use in a superconducting integrated circuit can be summarized as including a base layer comprising silicon and a top layer comprising aluminum oxide. The base layer can include at least one of undoped silicon, doped silicon, sapphire, and quartz. The base layer can be thicker than the top layer.

[0027] A method for depositing a superconducting metal layer in an integrated circuit can be summarized as including depositing a first portion of the superconducting metal layer, stopping deposition of the first portion of the superconducting metal layer to prevent excessive heating, cooling the superconducting metal layer, and depositing a second portion of the superconducting metal layer over the first portion of the superconducting metal layer. The method can further include stopping deposition of the second portion of the superconducting metal layer to prevent excessive heating, cooling the superconducting metal layer, and depositing a third portion of the superconducting metal layer over the second portion of the superconducting metal layer.

[0028] A method for aligning multiple layers in a multi-layer superconducting integrated circuit can be summarized as comprising the steps of patterning a first superconducting metal layer to include at least one alignment mark, depositing a first dielectric layer over the first superconducting metal layer, patterning the first dielectric layer to expose the at least one alignment mark, depositing a second superconducting metal layer over the first dielectric layer such that an imprint of the at least one alignment mark is formed on the exposed surface of the second superconducting metal layer, and aligning a photoresist mask to the imprint of the at least one alignment mark on the second superconducting metal layer. The method may further comprise depositing a photoresist mask over the second superconducting metal layer.

[0029] A method of fabricating a superconducting integrated circuit may be summarized as including the steps of depositing a first superconducting metal layer, depositing a superconducting protection capping layer over the first superconducting metal layer, patterning both the first superconducting metal layer and the superconducting protection capping layer over the first superconducting metal layer, depositing a dielectric layer over the patterned superconducting protection capping layer, etching a hole through the dielectric layer to expose a portion of at least one of the superconducting protection capping layer or the first superconducting metal layer, and depositing a second superconducting metal layer over the dielectric layer such that at least a portion of the second superconducting metal layer at least partially fills the hole through the dielectric layer and forms a superconducting electrical connection with at least one of the superconducting protection capping layer or the first superconducting metal layer. Depositing a superconducting protective capping layer over the first superconducting metal layer may include depositing a titanium nitride layer over the first superconducting metal layer.

[0030] The superconducting integrated circuit can be summarized as including: a first patterned superconducting metal layer; a superconducting protection capping layer disposed over the first patterned superconducting metal layer, the superconducting protection capping layer being patterned to match the pattern of the first patterned superconducting metal layer; a dielectric layer disposed over the superconducting protection capping layer; a second patterned superconducting metal layer disposed over the dielectric layer; and a superconducting via extending through the dielectric layer and superconductively electrically coupling a portion of the second patterned superconducting metal layer to at least one of a portion of the superconducting protection capping layer or a portion of the first superconducting metal layer. The superconducting protection capping layer can include titanium nitride.

[0031] A method for fabricating a Josephson junction pentalayer can be summarized as including the steps of depositing a first superconducting metal layer, depositing a first insulating barrier over the first superconducting metal layer, the first insulating barrier having a first thickness, depositing a second superconducting metal layer over the first insulating barrier, depositing a second insulating barrier over the second superconducting metal layer, the second insulating barrier having a second thickness different from the first insulating barrier first thickness, and depositing a third superconducting metal layer over the second insulating barrier. The second insulating barrier over the second superconducting metal layer, the second insulating barrier having a second thickness different from the first insulating barrier first thickness, may include depositing a second insulating barrier over the second superconducting metal layer, the second insulating barrier having a second thickness greater than the first insulating barrier first thickness.

[0032] A superconducting integrated circuit can be summarized as including a Josephson junction pentalayer including a first superconducting metal layer, a first insulating barrier having a first thickness and disposed over the first superconducting metal layer, a second superconducting metal layer disposed over the first insulating barrier, a second insulating barrier having a second thickness and disposed over the second superconducting metal layer, and a third superconducting metal layer disposed over the second insulating barrier, a dielectric layer disposed over the Josephson junction pentalayer, a superconducting wiring layer disposed over the dielectric layer, and at least one superconducting via superconductively electrically coupling at least a portion of the superconducting wiring layer to at least a portion of the Josephson junction pentalayer. A second thickness of the second insulating barrier can be greater than the first thickness of the first insulating barrier. At least a first portion of the Josephson junction pentad can be patterned to form a first Josephson junction including a first portion of the third superconducting metal layer, a first portion of the second insulating barrier, a first portion of the second superconducting metal layer, a first portion of the first insulating barrier, and a first portion of the first superconducting metal layer, wherein the at least one superconducting via can superconductively electrically couple the first portion of the second superconducting wiring layer to the first portion of the third superconducting metal layer. At least a second portion of the Josephson junction pentad can be patterned to form a second Josephson junction including a second portion of the second superconducting metal layer, a second portion of the first insulating barrier, and a second portion of the first superconducting metal layer, wherein the at least one superconducting via can superconductively electrically couple the second portion of the second superconducting wiring layer to the second portion of the second superconducting metal layer. At least a first portion of the Josephson junction five-layer can be patterned to form a first Josephson junction including a first portion of the second superconducting metal layer, a first portion of the first insulating barrier, and a first portion of the first superconducting metal layer, and the at least one superconducting via can superconductively electrically couple the first portion of the second superconducting wiring layer to the first portion of the second superconducting metal layer.

[0033] In the drawings, identical reference numbers identify similar elements or acts. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes and angles of various elements are not drawn to scale, and some of these elements are arbitrarily enlarged and positioned to facilitate reading of the drawings. Furthermore, the particular shapes of the elements as depicted are not intended to convey any information regarding the actual shape of the particular elements, but have been selected merely for ease of recognition in the drawings. [Brief explanation of the drawings]

[0034] [Figure 1A] 1 is a partial cross-sectional elevation view of a portion of a superconducting integrated circuit including three unpatterned layers according to one embodiment shown. [Figure 1B] 1B is a partial cross-sectional elevation view of a portion of the superconducting integrated circuit of FIG. 1A after further processing operations, including a patterned tri-layer and counter electrode, according to one illustrated embodiment. [Figure 1C] 1C is a partial cross-sectional elevation view of a portion of the superconducting integrated circuit of FIG. 1B after further processing operations, including individual Josephson junctions, according to one illustrated embodiment. [Figure 2] FIG. 1 is a flow diagram illustrating a method for fabricating a Josephson junction from a niobium / aluminum oxide / niobium tri-layer, according to one illustrated embodiment. [Figure 3] FIG. 1 is a flow diagram illustrating a method of fabricating a niobium / aluminum oxide / niobium tri-layer, according to one illustrated embodiment. [Figure 4] FIG. 1 is a flow diagram illustrating a method of forming a niobium / aluminum oxide / niobium tri-layer, according to one illustrated embodiment. [Figure 5] 1 is a partial cross-sectional elevation view of a portion of a superconducting integrated circuit including a Josephson junction covered with a protective cap, according to one embodiment shown. [Figure 6] FIG. 1 is a flow diagram illustrating a method for depositing a protective cap over a tri-layer Josephson junction, according to one illustrated embodiment. [Figure 7] 1 is a partial cross-sectional elevation view of a portion of a superconducting integrated circuit including a hybrid dielectric layer according to one embodiment shown. [Figure 8] FIG. 1 is a flow diagram illustrating a method for depositing a hybrid dielectric, according to one illustrated embodiment. [Figure 9A] 1 is a partial cross-sectional elevation view of a portion of a superconducting integrated circuit during a masking stage of a subtractive patterning process, according to one illustrated embodiment. [Figure 9B] 9B is a partial cross-sectional elevation view of the portion of the superconducting integrated circuit of FIG. 9A after an etching stage of a subtractive patterning process, according to one embodiment shown. [Figure 9C] 9C is a partial cross-sectional elevation view of the portion of the superconducting integrated circuit of FIG. 9B after a dielectric deposition stage of a subtractive patterning process, according to one illustrated embodiment. [Figure 9D] 9D is a partial cross-sectional elevation view of the portion of the superconducting integrated circuit of FIG. 9C after a dielectric planarization stage of a subtractive patterning process, according to one embodiment shown. [Figure 9E] 9D after depositing a second superconducting metal layer, according to one embodiment shown. FIG. [Figure 10A] 1 is a partial cross-sectional elevation view of a portion of a superconducting integrated circuit during a masking stage of an additive patterning process, according to one illustrated embodiment. [Figure 10B] 10B is a partial cross-sectional elevation view of the portion of the superconducting integrated circuit of FIG. 10A after an etching stage of an additive patterning process, according to one embodiment shown. [Figure 10C] 10C is a partial cross-sectional elevation view of the portion of the superconducting integrated circuit of FIG. 10B after a metal deposition stage of an additive patterning process, according to one embodiment shown. [Figure 10D] 10D is a partial cross-sectional elevation view of the portion of the superconducting integrated circuit of FIG. 10C after a metal planarization stage of an additive patterning process, according to one embodiment shown. [Figure 10E] FIG. 10E is a partial cross-sectional elevation view of the portion of the superconducting integrated circuit of FIG. 10D after depositing a dielectric layer, according to one embodiment shown. [Figure 10F] FIG. 10F is a partial cross-sectional elevation view of the portion of the superconducting integrated circuit of FIG. 10E after depositing an etch stop layer, according to one embodiment shown. [Figure 10G] FIG. 10F is a partial cross-sectional elevation view of a portion of the superconducting integrated circuit of FIG. 10F after deposition of a dielectric layer, according to one embodiment shown. [Figure 10H] 10G after depositing a negative photoresist mask over the dielectric layer, according to one embodiment shown. FIG. [Figure 10I] 10H is a partial cross-sectional elevation view of the portion of the superconducting integrated circuit of FIG. 10H after an etching stage of an additive patterning process, according to one embodiment shown. [Figure 10J] 10I is a partial cross-sectional elevation view of the portion of the superconducting integrated circuit of FIG. 10I after a metal deposition stage of an additive patterning process, according to one embodiment shown. [Figure 10K] FIG. 10J is a partial cross-sectional elevation view of the portion of the superconducting integrated circuit of FIG. 10J after a metal planarization stage of an additive patterning process, according to one embodiment shown. [Figure 11] FIG. 1 is a flow diagram illustrating a method for using additive patterning techniques in a superconducting integrated circuit fabrication process to achieve improved ILD thickness control, according to one illustrated embodiment. [Figure 12A] 1 is a partial cross-sectional elevation view of a portion of a superconducting integrated circuit during a via masking stage of a superconducting dual damascene process, according to one illustrated embodiment. [Figure 12B] 12B is a partial cross-sectional elevation view of the portion of the superconducting integrated circuit of FIG. 12A after the dielectric etch, metal deposition, and metal planarization / polishing stages of an additive patterning process, according to one embodiment shown. [Figure 12C] 12C is a partial cross-sectional elevation view of the portion of the superconducting integrated circuit of FIG. 12B during an interconnect masking stage of a dual damascene process after depositing an etch stop layer and a dielectric layer, according to one illustrated embodiment. [Figure 12D]12D is a partial cross-sectional elevation view of the portion of the superconducting integrated circuit of FIG. 12C after a wiring etching stage of an additive patterning process, according to one embodiment shown. [Figure 12E] 12D during a via masking stage of a dual damascene process, according to one embodiment shown. FIG. [Figure 12F] 12F is a partial cross-sectional elevation view of the portion of the superconducting integrated circuit of FIG. 12E after a via etching stage of a dual damascene process, according to one embodiment shown. [Figure 12G] 12F is a partial cross-sectional elevation view of a portion of the superconducting integrated circuit of FIG. 12F after completing superconducting metal deposition and planarization, according to one embodiment shown. [Figure 13] FIG. 1 is a flow diagram illustrating a method for implementing a superconducting dual damascene process, according to one illustrated embodiment. [Figure 14] 1 is a partial cross-sectional elevation view of a portion of a substrate for use in a superconducting integrated circuit, according to one embodiment shown. [Figure 15] FIG. 1 is a flow diagram illustrating a method for performing a multi-stage metal deposition, according to one illustrated embodiment. [Figure 16] 1 is a partial cross-sectional elevation view of a portion of an integrated circuit showing imprinting of alignment marks in a superconducting metal layer, according to one illustrated embodiment. [Figure 17] FIG. 1 is a flow diagram illustrating a method for aligning multiple layers of a multi-layer superconducting integrated circuit without using open frame and matching techniques, according to one illustrated embodiment. [Figure 18] 1 is a cross-sectional view of a portion of an exemplary superconducting integrated circuit showing a superconducting via having non-vertical sidewalls, according to one embodiment shown. [Figure 19] 1 illustrates a method for forming a superconducting via in accordance with the present systems and methods. [Figure 20] 1 is a cross-sectional view of a portion of a superconducting integrated circuit including a superconducting protective capping layer over a superconducting metal layer in accordance with the present systems and methods. [Figure 21A]1 is a cross-sectional view of a portion of a superconducting integrated circuit including five layers of Josephson junctions in accordance with the present systems and methods. [Figure 21B] 1 is a cross-sectional view of a portion of an exemplary superconducting integrated circuit in accordance with the present systems and methods. [Figure 22] A method for forming a five-layer Josephson junction according to the present systems and methods is presented. DETAILED DESCRIPTION OF THE INVENTION

[0035] In the following description, certain specific details are set forth to provide a thorough understanding of various disclosed embodiments. However, those skilled in the art will recognize that the embodiments can be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other examples, well-known structures associated with superconducting circuits or structures, quantum computer circuits or structures, and / or cryogenic cooling systems, such as dilution refrigerators, are not shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0036] Unless the context requires otherwise, throughout this specification and the claims that follow, the word "comprise" and variations thereof, such as "comprises" and "comprising," are to be construed in their open-ended, inclusive sense, i.e., "including, but not limited to."

[0037] Throughout this specification, a reference to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Moreover, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0038] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. It should also be noted that the term "or" is generally used in its sense to include "and / or" unless the context clearly dictates otherwise.

[0039] As used in this specification and the appended claims, the terms "carried by," "carried on," or variations thereof, and similarly, the terms "over" and "above," mean that a structure is, at least in some instances, directly or indirectly supported by another structure, e.g., directly on a surface thereof, spaced above or below a surface thereof by one or more intervening layers or structures, or located within it.

[0040] The headings and abstracts of the disclosure provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

[0041] Unless the particular context requires otherwise, throughout this specification the terms "deposit," "deposited," "deposition," and the like are used generally to encompass any method of material deposition, including, but not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced PVD, plasma-enhanced CVD, and atomic layer deposition (ALD).

[0042] Various embodiments described herein provide systems and methods for fabricating superconducting integrated circuits. As previously explained, in the art, superconducting integrated circuits are typically fabricated using many of the same tools and techniques traditionally used in the semiconductor fabrication industry, yet superconducting integrated circuits tend to be fabricated in research environments outside of state-of-the-art semiconductor fabrication facilities. Due to issues unique to superconducting circuits, semiconductor processes and techniques generally need to be modified for use in superconductor chip and circuit fabrication. Such modifications are typically not obvious and may require some experimentation.

[0043] Josephson junctions are a common element in superconducting integrated circuits. Physically, a Josephson junction is a small interruption in an otherwise continuous superconducting current path, typically realized by a thin insulating barrier sandwiched between two superconducting electrodes. In superconducting integrated circuits, Josephson junctions are typically fabricated as a stack, comprising a superconducting base electrode covered by a thin insulating layer, which is covered by a superconducting counter electrode. Thus, Josephson junctions are typically formed as three-layer or "tri-layer" structures. The tri-layer can be completely deposited over the entire wafer (i.e., in the same way that metal wiring and dielectric layers are deposited) and then patterned to define individual Josephson junctions.

[0044] FIG. 1A shows a cross-sectional view of a portion of a superconducting integrated circuit 100a including an unpatterned tri-layer 110. The tri-layer 110 is supported on a substrate 130 and comprises a superconducting base electrode 111, formed, for example, of niobium (Nb), an insulating barrier 112, formed, for example, of aluminum oxide (AlOx), and a superconducting counter electrode 113, formed, for example, of niobium (Nb). The substrate 130 may comprise silicon, sapphire, quartz, silicon oxide, or any similar suitable material. In some embodiments, the top surface of the niobium base electrode 111 may be covered with a thin layer of aluminum (not shown), upon which an aluminum oxide layer 112 is grown (thus, the "tri-layer" may actually comprise four layers: the niobium base electrode, the aluminum layer, an aluminum oxide layer grown on the aluminum layer, and the niobium counter electrode). The tri-layer 110 may be patterned, for example, by lithographic photoresist masking and plasma etching processes, to form individual Josephson junctions. In some applications, the counter electrode 113 can be patterned to define individual junctions, and the base electrode 111 can be used as an interconnect layer to provide electrical connection between the junctions. During patterning of the counter electrode 113, the aluminum oxide layer 112 can be used as an etch stop, and the niobium counter electrode 113 can be etched using a chemistry that does not etch through the aluminum oxide layer 112.

[0045] FIG. 1B shows a cross-sectional view of a portion of superconducting integrated circuit 100b, including patterned tri-layer 110. FIG. 1B depicts superconducting integrated circuit 100a from FIG. 1A after counter electrode 113 has been etched to define individual Josephson junctions 121 and 122, using aluminum oxide layer 112 as an etch stop. A dielectric layer 140 (which may include, for example, silicon oxide) has also been deposited over tri-layer 110. Using aluminum oxide layer 112 as an etch stop, regions of aluminum oxide layer 112 outside of individual Josephson junctions 121 and 122 can be left in place (i.e., not etched). However, Applicant recognizes that in applications where sensitivity to noise in the superconducting wiring of Josephson junctions 121 and 122 and / or base electrode 111 is particularly high (e.g., applications using superconducting qubits, such as superconducting quantum processors), the interface between niobium base electrode 111 and aluminum oxide layer 112 and / or the interface between aluminum oxide layer 112 and dielectric layer 140 can introduce unwanted and unnecessary noise into the system. The present systems and methods avoid such noise by removing regions of aluminum oxide layer 112 outside of individual Josephson junctions 121 and 122, thereby reducing the total number of material interfaces in the integrated circuit structure.

[0046] 1C illustrates a cross-sectional view of a portion of a superconducting integrated circuit 100c including a patterned tri-layer 110 and after excess aluminum oxide 112 has been removed from the patterned tri-layer 110, in accordance with the present systems and methods. FIG. 1C depicts the superconducting integrated circuit 100a from FIG. 1A after the counter electrode 113 has been etched to define the individual Josephson junctions 121 and 122 without using the aluminum oxide layer 112 as an etch stop. Thus, the integrated circuit 100c differs from the integrated circuit 100b in that in the integrated circuit 100c, regions of the aluminum oxide layer 112 outside the individual Josephson junctions 121 and 122 have been etched out. The regions of the aluminum oxide layer 112 outside the individual Josephson junctions 121 and 122 can be etched out during the patterning and etching of the niobium counter electrode 113, for example, by using a chemical etch that does not use the aluminum oxide layer 112 as an etch stop. Niobium can be etched using SF, while aluminum can be etched using a combination of BCl, Cl, and N. According to the present systems and methods, the niobium counter electrode 113 can be etched using a combination of SF, BCl, Cl, and / or N because such chemical etching can also remove regions of the aluminum oxide layer 112 outside the individual Josephson junctions 121 and 122. Removal of the aluminum oxide during etching of the individual Josephson junctions can reduce the number of material interfaces in a superconducting integrated circuit, thereby reducing noise that could otherwise adversely affect circuit performance. According to the present systems and methods, the regions of the aluminum oxide layer 112 outside the individual Josephson junctions 121 and 122 can also be removed in a separate process act or operation after the Josephson junctions 121 and 122 are defined by using a separate etch specifically designed for aluminum oxide removal.

[0047] Moreover, according to the present systems and methods, any superconductor fabrication process involving etching of niobium (even if the process does not pattern Josephson junctions and / or remove aluminum oxide layers) can benefit from a modified niobium etch chemistry using a combination of SF, BCl, Cl, and / or N because such results in a smoother, flatter niobium surface profile, specifically, smoother, flatter niobium sidewalls, compared to etching with SF alone.

[0048] The process of removing excess aluminum oxide during Josephson junction fabrication (i.e., proceeding from FIG. 1A to FIG. 1C ) is summarized in FIG. 2 . FIG. 2 illustrates a method 200 for fabricating a Josephson junction from a niobium / aluminum oxide / niobium tri-layer in accordance with the present systems and methods. Method 200 includes three acts 201-203, although one skilled in the art will understand that in alternative embodiments, certain acts may be omitted and / or additional acts may be added. One skilled in the art will understand that the order of the acts shown is for illustrative purposes only and may be altered in alternative embodiments. In 201, a Nb-AlOx-Nb tri-layer is deposited, for example, using techniques previously described. In 202, a photoresist mask pattern is deposited over or on top of the tri-layer. The photoresist mask layer may cover some portions of the tri-layer and leave other portions of the tri-layer uncovered. Those portions of the trilayer that are not covered are etched away during the etching process (see act 203), while those portions of the trilayer that are covered remain after the etching process. At 203, a pattern defined by a photoresist mask is etched into the trilayer to form at least one Josephson junction. Where a Josephson junction is to be formed, a portion of aluminum oxide is sandwiched between two portions of niobium metal (i.e., the patterned counter electrode that covers the base electrode). Where a Josephson junction is not to be formed, the niobium counter electrode layer of the trilayer is etched away (i.e., stripped), and at least a portion of the aluminum oxide underlying the stripped counter electrode is also etched away, such that excess aluminum oxide that is not part of the at least one Josephson junction is removed.

[0049] In processes using niobium etching, the photoresist mask typically needs to be removed after the niobium etch is complete. The chemical etchant used to etch niobium cannot intentionally etch the photoresist mask, or the process would fail to pattern the niobium. However, the photoresist mask still typically needs to be removed once the niobium etch is complete, for example, to allow for via connections to be made to subsequent niobium layers added to the circuit (e.g., additional niobium layers are supported on the etched niobium layer). In the art, photoresist masks (and associated polymers that may form due to the interaction of the photoresist mask with the niobium itself) are typically stripped via an O2 plasma etch / bombardment process. However, O2 plasma alone may not be sufficient to remove some of the polymer resulting from the adhesion of the photoresist mask to the niobium metal. According to the present system and method, a modified photoresist stripping process can use a combination of CF4 and O2 plasma to reliably remove photoresist mask residue (e.g., polymers formed due to the interaction of the photoresist mask with the niobium metal) from the surface of the niobium metal.

[0050] In the fabrication of an Nb-AlOx-Nb trilayer, a first layer of niobium is deposited, followed by a thin layer of aluminum deposited over the first niobium layer. The aluminum is then exposed to O2 gas to grow an aluminum oxide layer on top of the aluminum. It is typically desirable to produce a highly specific and uniform aluminum oxide thickness at this stage. The thickness of the AlOx layer ultimately affects the critical current of any Josephson junctions in the resulting superconducting integrated circuit and is therefore a critical fabrication parameter. In this process, the thickness of the AlOx layer is determined by several parameters, including the duration of O2 gas exposure, O2 gas concentration, temperature, and pressure. Therefore, the O2 exposure time is calculated to produce the desired AlOx thickness, taking into account the O2 concentration, pressure, and temperature. After the calculated O2 exposure time has elapsed, a second layer of niobium is deposited over the aluminum oxide layer to complete the Nb-AlOx-Nb trilayer. While this process for fabricating Nb-AlOx-Nb tri-layers is well established, it ultimately offers limited control over the thickness of the resulting AlOx layer. The AlOx thickness is determined indirectly through calculations involving many inputs, each of which has some uncertainty that affects the resulting thickness of the AlOx layer. For example, any variations in pressure, temperature, O2 concentration, O2 exposure time, etc., affect the thickness of the resulting AlOx layer. Accordingly, there remains a need in the art for a method for fabricating Nb-AlOx-Nb tri-layers that achieves improved AlOx thickness control.

[0051] According to the present system and method, improved AlOx thickness control in the fabrication of an Nb-AlOx-Nb tri-layer can be achieved by directly depositing an aluminum oxide layer via atomic layer deposition. Figure 3 illustrates a method 300 for fabricating a niobium / aluminum oxide / niobium tri-layer according to the present system and method. Method 300 includes three acts 301-303, although one skilled in the art will understand that alternative embodiments can omit certain acts and / or add additional acts. One skilled in the art will understand that the order of the acts shown is for illustrative purposes only and can be altered in alternative embodiments. In 301, a first layer of niobium is deposited via a standard deposition process, such as chemical vapor deposition, physical vapor deposition, or the like. The niobium can be deposited over a substrate or over any other layer of the integrated circuit (e.g., over a dielectric layer or over another metal layer). The top surface of the niobium is preferably smooth and substantially uniform. If the desired smoothness cannot be achieved during the deposition process alone, the top surface of the niobium can be planarized and / or polished via a chemical mechanical planarization process (e.g., CMP). In 302, an aluminum oxide layer is deposited over the smooth top surface of the first niobium layer via atomic layer deposition. Atomic layer deposition allows for active structuring of the aluminum oxide layer and can allow for improved control of the thickness of the aluminum oxide layer compared to O2 exposure processes known in the art and described above. In some embodiments, adhesion of the aluminum oxide layer to the niobium layer can be increased by first depositing a thin aluminum layer (e.g., via CVD, PVD, or ALD) over the smooth top surface of the niobium layer, and then depositing an aluminum oxide layer over the thin aluminum layer via atomic layer deposition (such thin aluminum layer can be planarized or polished to improve smoothness, if necessary). In 303, a second layer of niobium is deposited over the aluminum oxide layer via a standard deposition process (e.g., CVD or PVD).Deposition of a second niobium layer completes the Nb-AlOx-Nb trilayer, which can be used to form one or more Josephson junctions in a superconducting integrated circuit.

[0052] Trilayer deposition (specifically, the aluminum oxide deposition / growth process) is particularly sensitive to temperature. The presence of non-uniform temperatures (e.g., temperature gradients) across the wafer can result in non-uniform aluminum oxide thickness across the wafer. Such non-uniform temperatures can similarly occur during the heating and / or cooling processes. For example, the wafer can be heated during the aluminum oxide deposition process and cooled before the subsequent niobium deposition process. During this cooling, the aluminum oxide layer can continue to form and grow. Therefore, it is desirable to ensure substantially uniform wafer cooling between the aluminum oxide deposition / growth and subsequent niobium deposition of the trilayer fabrication process. According to the present systems and methods, uniformity during such cooling can be enhanced by filling the deposition chamber with an inert gas (e.g., argon) to provide a thermalizing medium with a substantially uniform pressure across the wafer. In some embodiments, the trilayer can be simultaneously deposited on multiple wafers in the same chamber, and filling the chamber with an inert cooling gas (e.g., argon) can improve temperature uniformity across the multiple wafers.

[0053] FIG. 4 illustrates a method 400 for forming a niobium / aluminum oxide / niobium tri-layer according to the present systems and methods. Method 400 includes four acts 401-404, although one skilled in the art would understand that alternative embodiments may omit certain acts and / or add additional acts. One skilled in the art would understand that the order of the depicted acts is shown for illustrative purposes only and may be altered in alternative embodiments. At 401, a niobium base layer is deposited over the wafer. The niobium can be deposited via any known deposition technique, including CVD, PVD, ALD, and the like. Deposition can occur in a sealed chamber. At 402, an aluminum oxide layer is deposited over the niobium base layer. In some embodiments, "depositing the aluminum oxide layer" may include depositing a thin layer of aluminum directly on the niobium base layer and then growing the aluminum oxide layer on the thin aluminum layer (e.g., by exposing the aluminum layer to oxygen gas). In 403, the chamber is filled with a substantially uniform pressure of an inert gas (e.g., argon, etc.). The inert gas provides a medium through which thermal energy can dissipate, ensuring that the wafer (specifically, the aluminum oxide layer located on the surface of the wafer) has a substantially uniform temperature as the aluminum oxide layer cools. In 404, the inert gas is pumped out of the chamber, and a top layer of niobium is deposited over the aluminum oxide layer. The uniform cooling process of act 403 can improve the uniformity of the aluminum oxide thickness across the wafer.

[0054] Josephson junctions can be formed with Nb-AlOx-Nb trilayers by patterning the counter electrode, as described in Figures 1A-1C. U.S. Patent Application Publication No. 2011-0089405 (incorporated herein by reference in its entirety) further describes protecting the formed Josephson junction from subsequent processing operations by depositing a cap (e.g., formed of silicon nitride SiN) over the top of the Josephson junction counter electrode. Figure 5 shows a cross-sectional view of a portion of a superconducting integrated circuit 500 including a Josephson junction 510 covered with a protective cap 520. As described in U.S. Patent Application Publication No. 2011-0089405, the cap 520 can be formed of, for example, silicon nitride, hydrogenated amorphous silicon, an organic polymer dielectric material, or a similar dielectric material. The Josephson junction 510 includes a base electrode 511 (formed of a superconducting metal such as niobium), an insulating barrier 512 (formed, for example, of aluminum oxide), and a counter electrode 513 (formed of a superconducting metal such as niobium). A challenge in depositing the cap 520 of a superconducting integrated circuit 500 is that the cap material does not adhere well to the aluminum oxide layer 512. This challenge can be overcome by etching away the excess aluminum oxide, as previously described and shown in FIG. 1C (compare FIG. 1B). However, in circuits where removing the excess aluminum oxide is impractical, adhesion between the cap 520 and the aluminum oxide layer 512 can be improved by pre-cleaning the top surface of the aluminum oxide layer 512, particularly to remove moisture and any other particles that may contaminate the exposed surface of the aluminum oxide layer 512. This pre-cleaning can include, for example, ion bombardment of the exposed surface of the aluminum oxide layer 512 and / or using a mild anisotropic low-pressure etch.

[0055] FIG. 6 illustrates a method 600 for depositing a protective cap over a tri-layer Josephson junction according to the present systems and methods. Method 600 includes four acts 601-604, although one skilled in the art would understand that alternative embodiments can omit certain acts and / or add additional acts. One skilled in the art would understand that the order of the acts shown is shown for illustrative purposes only and can be changed in alternative embodiments. At 601, a tri-layer is deposited (e.g., over the wafer, over the surface of a dielectric layer, or over the surface of a metal layer, etc.) as previously described. The tri-layer may include, for example, a Nb / AlOx / Nb tri-layer. At 602, the tri-layer is patterned, for example, by a lithography process, as previously described. At 603, the exposed surface (e.g., top surface) of the patterned tri-layer is pre-cleaned according to the present systems and methods. The exposed surfaces of the trilayer may include both a superconducting metal surface (i.e., a niobium counter electrode surface) and an insulating barrier surface (i.e., an aluminum oxide surface). As previously described, this pre-cleaning may include, for example, ion bombarding the exposed surfaces of the aluminum oxide layer and / or using a mild anisotropic low-pressure etch. At 604, a protective cap is deposited over the trilayer. The cap may include, for example, silicon nitride and may help protect the trilayer (specifically, the aluminum oxide layer) from degradation during subsequent processing. The pre-cleaning at 603 may improve adhesion between the cap and the aluminum oxide layer.

[0056] The cap 520 described above comprises a layer of material (e.g., SiN) covering the Josephson junctions (510) to protect them (particularly the aluminum oxide layer 512) from subsequent processing operations. Similar "capping" techniques can be used in accordance with the present systems and methods to reduce noise in superconducting integrated circuits by protecting the wiring layers from oxides that may be present in the dielectric layer (e.g., silicon dioxide) and / or to prevent oxidation of the wiring layers during deposition of the oxide dielectric layer (e.g., silicon dioxide). For example, a hybrid dielectric can be used to effectively sandwich a metal wiring layer between non-oxide caps (e.g., SiN) both above and below the dielectric layer.

[0057] 7 illustrates a cross-sectional view of a portion of a superconducting integrated circuit 700 including hybrid dielectric layers 710 and 720 in accordance with the present systems and methods. The superconducting integrated circuit 700 includes metal wiring layers 730 and 740, each of which includes patterned conductors formed of a superconducting material such as niobium or aluminum. The hybrid dielectric layer 710 itself consists of three layers: a base layer 711 of a non-oxide dielectric material (e.g., SiN), a silicon oxide layer 712, and a top layer 713 of a non-oxide dielectric material (e.g., SiN). The hybrid dielectric layer 720 similarly consists of three layers: a base layer 721 of a non-oxide dielectric material (e.g., SiN), a silicon oxide layer 722, and a top layer 723 of a non-oxide dielectric material (e.g., SiN). The non-oxide dielectric layer 711 protects the metal wiring layer 730 from the silicon oxide layer 712. Similarly, non-oxide dielectric layers 713 and 721 protect metal wiring layer 740 from silicon oxide layers 712 and 722, respectively. Thus, hybrid dielectric layers 710 and 720 may isolate metal wiring layers 730 and 740, respectively, from oxides present in silicon oxide layers 712 and 722, and thus aid in reducing noise in superconducting integrated circuit 700. Similarly, hybrid dielectric layers 710 and 720 also aid in preventing oxidation of metal wiring layers 730 and 740, respectively, during the deposition of silicon oxide layers 712 and 722. Those skilled in the art will appreciate that the circuit details of integrated circuit 700 are merely exemplary and that similar hybrid dielectric processes can be used in superconducting integrated circuits that include Josephson junctions (e.g., tri-layer) and / or via connections between metal wiring layers.

[0058] FIG. 8 illustrates a method 800 for depositing a hybrid dielectric in accordance with the present systems and methods. Method 800 includes three acts 801-803, although one skilled in the art would understand that alternative embodiments may omit certain acts and / or add additional acts. One skilled in the art would understand that the order of the depicted acts is shown for illustrative purposes only and may be varied in alternative embodiments. At 801, a first layer including a first dielectric material is deposited. The first dielectric material may include a non-oxide dielectric, such as silicon nitride, and the first layer may be deposited by any deposition process, including CVD, PVD, and / or ALD. The first layer may be deposited, for example, on top of or over a metal layer of an integrated circuit. At 802, a second layer including a second dielectric material may be deposited on top of or over the first layer. The second dielectric material may include an oxide dielectric, such as silicon oxide, and the second layer may be deposited by any deposition process, including CVD, PVD, and / or ALD. In 803, a third layer including the first dielectric material may be deposited on top of or over the second layer. In some embodiments, the third layer may include a third dielectric material that is a non-oxide dielectric. In some embodiments, at least one layer may be polished or planarized after deposition before another layer is deposited thereon. For example, a first layer may be polished or planarized before a second layer is deposited thereon. In some embodiments, a metal layer (e.g., a superconducting metal layer) may be deposited over the third layer. If the integrated circuit includes additional metal layers, each metal layer may be separated from the upper and / or lower metal layers by a respective hybrid dielectric formed by method 800.

[0059] In the semiconductor industry, processes known as "additive patterning" or "damascene" processing have been developed to process materials that cannot be directly patterned by standard photoresist masking and plasma etching techniques. For example, semiconductor integrated circuits that use copper interconnects (as opposed to, e.g., aluminum interconnects) are typically fabricated by this additive patterning approach because copper is incompatible with standard photoresist masking and plasma etching techniques. Copper may be preferred over aluminum in some semiconductor applications because it is a better conductor than aluminum, which means that copper circuits can use less energy and include smaller components.

[0060] In additive patterning, an underlying dielectric layer is patterned with open features (e.g., trenches), and then a thick layer of conductor is deposited over the dielectric so that it completely fills the open features of the pattern. Chemical-mechanical planarization / polishing (CMP) is then used to remove the excess conductor down to the level of the top of the underlying dielectric. As a result, patterned conductors are created by filling the pattern in the dielectric, as opposed to traditional approaches that etch the pattern directly into the conductor itself. In other words, "additive patterning" is the process of adding conductors to an existing pattern. Conversely, standard photoresist masking and plasma etching techniques provide "subtractive patterning," which removes (i.e., etches out) portions of the conductor to create the pattern.

[0061] As explained above, additive patterning is used in the semiconductor industry to pattern materials (e.g., copper) that are incompatible with standard photoresist masking and plasma etching techniques. The present system and method allows for techniques that are motivated by reasons entirely different from those in the semiconductor industry, but that are similar in some respects, to be used in the fabrication of superconducting integrated circuits.

[0062] In multilayer integrated circuits (semiconductor or superconducting), successive layers of conductive wiring are typically separated from one another by an interlayer dielectric ("ILD"). The ILD provides structural support for the entire circuit while electrically insulating adjacent conductive layers. The thickness of the ILD determines the distance between two adjacent conductive layers of the circuit, and this distance, among other things, affects the inductive and capacitive coupling between adjacent conductive layers. In semiconductor integrated circuits, inductive and capacitive coupling between adjacent conductive layers is typically not a critical design feature. Conversely, in superconducting integrated circuits, inductive and / or capacitive coupling between conductive layers can be an important feature of the circuit design. Superconducting integrated circuits are often designed to propagate signals in the form of magnetic flux quanta (e.g., via single flux quantum logic) and often use intentional inductive coupling to convey these magnetic signals. These intentional inductive couplings may exist between adjacent conductive layers of the circuit, and the strength of those couplings therefore depends on the corresponding ILD thickness. Circuits that manipulate magnetic signals are also particularly sensitive to unintentional inductive coupling between wiring and circuit elements, often referred to as "crosstalk." Avoiding and / or minimizing unwanted crosstalk is a critical aspect of superconducting integrated circuit design. Insufficient control over the overall thickness of the ILD can cause crosstalk between wiring layers that degrades or completely suppresses circuit performance. For at least these reasons, some implementations of superconducting integrated circuits could benefit significantly from improved ILD thickness control.

[0063] According to the present systems and methods, improved ILD thickness control can be achieved in the fabrication of superconducting integrated circuits by using additive patterning or damascene fabrication processes. To clarify the unique features of the superconducting additive patterning process, a typical standard subtractive patterning process will first be described.

[0064] 9A is a cross-sectional view of a portion of an exemplary superconducting integrated circuit 900a during the masking stage of a subtractive patterning process. The integrated circuit 900a includes a substrate 930 (e.g., formed of silicon, silicon oxide, sapphire, or a similar material), a superconducting metal layer 920 (e.g., formed of niobium), and a photoresist mask 910. In the subtractive patterning process, the mask 910 overlies the metal layer 920, effectively tracing a desired circuit pattern in the metal layer 920. In other words, the desired circuit pattern corresponds to the areas of the metal layer 920 that are covered by the photoresist mask 910. Those areas of the metal layer 920 that are not directly covered by the mask 910 are etched away and do not form part of the circuit, while those areas of the metal layer 920 that are directly covered by the mask 910 remain after etching and become part of the circuit pattern.

[0065] FIG. 9B is a cross-sectional view of a portion of an exemplary superconducting integrated circuit 900b. FIG. 9B depicts the superconducting integrated circuit 900a from FIG. 9A after the etching stage of a subtractive patterning process. The superconducting integrated circuit 900b includes a substrate 930 and a superconducting metal layer 920, but the photoresist mask 910 from FIG. 9A has been stripped away. Compared to the superconducting integrated circuit 900a from FIG. 9A, only those areas of the metal layer 920 that were directly covered by the photoresist mask 910 remain in the superconducting integrated circuit 900b of FIG. 9B. The metal layer 920 has been subtractively patterned, for example, by using plasma etching, to remove the areas of the metal layer 920 that were not covered by the photoresist mask. As discussed in more detail below, the superconducting metal layer 920 and the photoresist mask 910 are typically etched / removed via different processes.

[0066] FIG. 9C is a cross-sectional view of a portion of an exemplary superconducting integrated circuit 900c. FIG. 9C depicts the superconducting integrated circuit 900b from FIG. 9B after the dielectric deposition stage of a subtractive patterning process. While the superconducting integrated circuit 900c includes a substrate 930 and a patterned superconducting metal layer 920, the superconducting integrated circuit 900c also includes a dielectric layer 940 deposited (e.g., by chemical vapor deposition, atomic layer deposition, or another known technique) over the top of the patterned metal layer 920 and the substrate 930. The dielectric layer 940 serves to protect the metal layer 920 from the external environment and to insulate the metal layer 920 from subsequent metal layers that may be added to the integrated circuit 900c. The pattern of the metal layer 920 typically creates features and non-uniformities (e.g., 950) in the surface of the dielectric layer 940, which must be smoothed out before additional layers can be deposited.

[0067] Figure 9D is a cross-sectional view of a portion of an example superconducting integrated circuit 900d. Figure 9D depicts superconducting integrated circuit 900c from Figure 9C after the dielectric planarization stage of the subtractive patterning process. Superconducting integrated circuit 900d includes substrate 930, patterned superconducting metal layer 920, and dielectric layer 940. In comparison to superconducting integrated circuit 900c from Figure 9C, dielectric layer 940 of integrated circuit 900d has been planarized to remove any unwanted non-uniformities (e.g., 950 from Figure 9C) resulting from the pattern of the underlying metal layer 920. This dielectric planarization can be completed, for example, by a CMP process.

[0068] FIG. 9E is a cross-sectional view of a portion of an exemplary superconducting integrated circuit 900e. FIG. 9E depicts the superconducting integrated circuit 900d from FIG. 9D after depositing a second superconducting metal layer 960. The superconducting integrated circuit 900e further includes a substrate 930, a patterned first superconducting metal layer 920, and a dielectric layer 940. The second metal layer 960 is separated from the first metal layer 920 by the dielectric 940, and the distance between the second metal layer 960 and the first metal layer 920 is directly related to the thickness of the dielectric layer 940. The dielectric layer 940 is an inner-layer dielectric, and its ILD thickness is shown in FIG. 9E. The top surface of the dielectric layer 940 is planarized to remove unwanted features (e.g., 950 from FIG. 9C), and therefore the ILD thickness of layer 940 is determined by this planarization in a subtractive patterning process.

[0069] The subtractive patterning process shown in Figures 9A-9E is commonly used in both the semiconductor and superconductor fabrication industries. However, an aspect of this process that is particularly disadvantageous in the fabrication of superconducting (as opposed to semiconductor) integrated circuits is that the thickness of each ILD is defined by a planarization process such as CMP. Planarizing a dielectric layer to a specific layer thickness is a difficult process to control, at least in part because there is no reference point that indicates when the desired thickness is reached. According to the present systems and methods, additive patterning processes can be used to enhance ILD thickness control in the fabrication of integrated circuits, a benefit that has particular utility in the fabrication of superconducting integrated circuits. Additive patterning processes enable enhanced ILD thickness control because, in additive patterning processes, the ILD thickness is substantially determined by the dielectric deposition operation (e.g., via chemical vapor deposition, physical vapor deposition, atomic layer deposition, or similar processes) as opposed to the planarization / polishing operation. According to the present systems and methods, the dielectric deposition process provides better ILD thickness control than the dielectric planarization process.

[0070] 10A is a cross-sectional view of a portion of an exemplary superconducting integrated circuit 1000a during a masking stage of an additive patterning process in accordance with the present systems and methods. The integrated circuit 1000a includes a substrate 1030 (e.g., formed of silicon, silicon oxide, sapphire, or a similar material), a dielectric layer 1040 (e.g., formed of silicon oxide), a negative photoresist mask 1010, and an etch stop layer 1070 (which may include, e.g., silicon nitride). In the additive patterning process, the mask 1010 overlies the dielectric layer 1040, effectively tracing the negative or inverse of a desired circuit pattern in the dielectric layer 1040. In other words, the desired circuit pattern corresponds to the areas of the dielectric layer 1040 that are not covered by the photoresist mask 1010. Those areas of the dielectric layer 1040 that are not directly covered by the mask 1010 are etched away to form open features (e.g., trenches), while those areas of the dielectric layer 1040 that are directly covered by the mask 1010 remain after etching.

[0071] FIG. 10B is a cross-sectional view of a portion of an exemplary superconducting integrated circuit 1000b in accordance with the present systems and methods. FIG. 10B depicts the superconducting integrated circuit 1000a from FIG. 10A after the etching stage of the additive patterning process. The superconducting integrated circuit 1000b includes a substrate 1030, a dielectric layer 1040, and an etch-stop layer 1070, while the negative photoresist mask 1010 from FIG. 10A has been stripped away. In comparison to the superconducting integrated circuit 1000a from FIG. 10A, the dielectric layer 1040 of the superconducting integrated circuit 1000b in FIG. 10B has been etched to create open features (e.g., trenches) 1080 that trace the desired circuit pattern into the dielectric layer 1040. Those areas of the dielectric layer 1040 that were directly covered by the photoresist mask 1010 remain unetched. Etching into the dielectric layer 1040 can be controlled, for example, by an etch stop layer 1070, which provides an interface between the dielectric layer 1040 and the substrate 1030 through which the etch will not pass. Some embodiments may not include an etch stop layer 1070 and / or may use the substrate 1030 as the etch stop.

[0072] FIG. 10C is a cross-sectional view of a portion of an exemplary superconducting integrated circuit 1000c in accordance with the present systems and methods. FIG. 10C depicts the superconducting integrated circuit 1000b from FIG. 10B after the metal deposition stage of the additive patterning process. In addition to the features from FIG. 10B, the superconducting integrated circuit 1000c also includes a superconducting metal layer 1020 deposited (e.g., by electroplating) over the top of the patterned dielectric layer 1040. The superconducting metal layer 1020 may comprise, for example, niobium or another material capable of superconducting during operation. The deposition of the metal layer 1020 fills the open features (e.g., 1080 from FIG. 10B) of the dielectric layer 1040 with the superconducting metal. Thus, the pattern of the dielectric layer 1040 serves as a mold for patterning the metal layer 1020.

[0073] FIG. 10D is a cross-sectional view of a portion of an example superconducting integrated circuit 1000d in accordance with the present systems and methods. FIG. 10D depicts the superconducting integrated circuit 1000c from FIG. 10C after the metal planarization stage of the additive patterning process. In comparison to the superconducting integrated circuit 1000c from FIG. 10C, the metal layer 1020 of the integrated circuit 1000d has been planarized / polished (e.g., by CMP or a similar process) to remove excess metal down to the level of the top of the dielectric layer 1040. After this planarization operation, all that remains of the metal layer 1020 are those portions of the metal layer 1020 that fill open features (e.g., 1080 from FIG. 10B) in the dielectric layer 1040. Thus, the metal layer 1020 has been patterned by adding the metal layer 1020 to the mold of the dielectric layer 1040 and polishing away any excess metal. The planarization / polishing of the metal layer 1020 can be configured to stop upon reaching the interface between the metal layer 1020 and the dielectric layer 1040. Those skilled in the art will appreciate that the planarization / polishing of the metal layer 1020 may require a special slurry that is different / modified from the slurry used to planarize / polish the dielectric layer.

[0074] FIG. 10E is a cross-sectional view of a portion of an exemplary superconducting integrated circuit 1000e in accordance with the present systems and methods. FIG. 10E depicts the superconducting integrated circuit 1000d from FIG. 10D after deposition of a dielectric layer 1060. The dielectric layer 1060 covers the metal layer 1020 and can be deposited by CVD, PVD, ALD, or any other known method of dielectric deposition. The combination of the dielectric layer 1040 and the dielectric layer 1060 together form an inner-layer dielectric (“ILD”), the thickness of which is substantially determined by the deposition of the dielectric layer 1060. As previously explained, greater thickness control can be achieved through the deposition process compared to the planarization process; therefore, the thickness of the ILD formed by the dielectric layers 1040 and 1060 can be controlled with greater precision than the thickness of the ILD formed by the dielectric layer 940 from FIG. 9E. In some embodiments, the top surface of the dielectric layer 1060 can be polished / planarized sufficiently to provide a smooth surface without substantially affecting the thickness of the dielectric layer 1060.

[0075] FIG. 10F is a cross-sectional view of a portion of an example superconducting integrated circuit 1000f in accordance with the present systems and methods. FIG. 10F depicts the superconducting integrated circuit 1000e from FIG. 10E after deposition of an etch-stop layer 1071. The etch-stop layer 1071 covers the dielectric layer 1060 and may be formed of, for example, silicon nitride, deposited by CVD, PVD, ALD, or any other known method of dielectric deposition. The etch-stop layer 1071 ensures that patterning (i.e., etching) of an additional dielectric layer deposited above the etch-stop layer 1071 does not penetrate through to the dielectric layer 1060. Those skilled in the art will understand that the definition of ILD thickness may or may not include the thickness of one of more etch-stop layers.

[0076] FIG. 10G is a cross-sectional view of a portion of an exemplary superconducting integrated circuit 1000g in accordance with the present systems and methods. FIG. 10G depicts superconducting integrated circuit 1000f from FIG. 10F after depositing dielectric layer 1043. Dielectric layer 1043 may include, for example, silicon oxide, deposited via CVD, PVD, ALD, or the like. Dielectric layer 1043 is deposited over etch stop layer 1071.

[0077] FIG. 10H is a cross-sectional view of a portion of an exemplary superconducting integrated circuit 1000h in accordance with the present systems and methods. FIG. 10H depicts superconducting integrated circuit 1000g from FIG. 10G after depositing a negative photoresist mask 1011 over dielectric layer 1043. In an additive patterning process, mask 1011 overlies dielectric layer 1043, effectively tracing the negative or inverse of the desired circuit pattern in dielectric layer 1043. In other words, the desired circuit pattern corresponds to areas of dielectric layer 1043 that are not covered by negative photoresist mask 1011. Those areas of dielectric layer 1043 that are not directly covered by mask 1011 are etched away, forming open features (e.g., trenches), while those areas of dielectric layer 1043 that are directly covered by mask 1011 remain after etching.

[0078] FIG. 10I is a cross-sectional view of a portion of an exemplary superconducting integrated circuit 1000i in accordance with the present systems and methods. FIG. 10I depicts superconducting integrated circuit 1000h from FIG. 10H after the etching stage of the additive patterning process. In superconducting integrated circuit 1000i, negative photoresist mask 1011 from FIG. 10H has been stripped. In comparison to superconducting integrated circuit 1000h from FIG. 10H, dielectric layer 1043 of superconducting integrated circuit 1000i of FIG. 10I has been etched to create open features (e.g., trenches) 1081 that trace the desired circuit pattern into dielectric layer 1043. Those areas of dielectric layer 1043 that were directly covered by photoresist mask 1011 remain unetched. Etching into dielectric layer 1043 can be controlled by etch stop layer 1071, which provides an interface between dielectric layer 1043 and dielectric layer 1042 and through which etching does not pass.

[0079] FIG. 10J is a cross-sectional view of a portion of an example superconducting integrated circuit 1000j in accordance with the present systems and methods. FIG. 10J depicts the superconducting integrated circuit 1000i from FIG. 10I after the metal deposition stage of the additive patterning process. In addition to the features from FIG. 10I, the superconducting integrated circuit 1000j also includes a superconducting metal layer 1021 deposited (e.g., by electroplating) over the top of the patterned dielectric layer 1043. The superconducting metal layer 1021 may include, for example, niobium or another material capable of superconducting during operation. The deposition of the metal layer 1021 fills the open features (e.g., 1081 from FIG. 10I) of the dielectric layer 1043 with the superconducting metal. Thus, the pattern of the dielectric layer 1043 serves as a mold for patterning the metal layer 1021.

[0080] FIG. 10K is a cross-sectional view of a portion of an exemplary superconducting integrated circuit 1000k in accordance with the present systems and methods. FIG. 10K depicts the superconducting integrated circuit 1000j from FIG. 10J after the metal planarization stage of the additive patterning process. In comparison to the superconducting integrated circuit 1000j from FIG. 10J, the metal layer 1021 of the integrated circuit 1000k has been planarized / polished (e.g., by CMP or a similar process) to remove excess metal down to the level of the top of the dielectric layer 1043. After this planarization operation, all that remains of the metal layer 1021 are those portions of the metal layer 1021 that fill open features (e.g., 1081 from FIG. 10I) in the dielectric layer 1043. Thus, the metal layer 1021 has been patterned by adding the metal layer 1021 to the mold of the dielectric layer 1043 and polishing away any excess metal. The planarization / polishing of the metal layer 1021 can be configured to stop when the interface between the metal layer 1021 and the dielectric layer 1043 is reached.

[0081] As previously described, additive patterning processes can improve ILD thickness control in superconducting integrated circuits. Once the ILD thickness is defined, subsequent processing acts can use additive or subtractive patterning techniques, as dictated by the requirements of the circuit being fabricated. For example, Figures 10G-10K depict a second superconducting metal layer being patterned by additive patterning techniques, which can be advantageous in some circuits (e.g., circuits including at least a third metal layer, and consequently a second ILD, overlying the second metal layer 1021). However, in alternative embodiments (e.g., circuits in which the second metal layer 1021 is the top metal layer and no ILD is defined above the second metal layer 1021), the deposition and patterning of the second metal layer 1021 can use subtractive patterning techniques, if preferred, without adversely affecting the ILD thickness control of the circuit.

[0082] The acts, actions, or processes described in Figures 10A-10K can be repeated for additional dielectric and wiring layers above layers 1043 and 1021 (with additional via connections, if desired) to provide as many layers as needed in any particular integrated circuit design. The acts, actions, or processes described in Figures 10A-10K are summarized in Figure 11.

[0083] FIG. 11 illustrates a method 1100 of using additive patterning techniques in a superconducting integrated circuit fabrication process to achieve improved ILD thickness control in accordance with the present systems and methods. Method 1100 includes six operations or acts 1101-1106, although one skilled in the art would understand that alternative embodiments may omit certain acts and / or add additional acts. One skilled in the art would understand that the order of the acts shown is for illustrative purposes only and may be altered in alternative embodiments. At 1101, a negative photoresist mask is deposited over a first dielectric layer. As explained in the context of FIG. 10A, the negative photoresist mask traces the inverse of a desired circuit pattern. The desired circuit pattern corresponds to areas of the first dielectric layer not covered by the photoresist mask. At 1102, the pattern provided by the negative photoresist mask is etched into the first dielectric layer to create open features (e.g., trenches). In some embodiments, the first dielectric layer can overlie an etch stop layer, so that the etch in 1102 does not pass through it. At 1103, a superconducting metal layer is deposited on or over the patterned dielectric layer to fill the open features of the first dielectric layer. The superconducting metal layer can include, for example, niobium, which, as described above, can be deposited by electroplating or by standard niobium deposition techniques, depending on the requirements and characteristics of the particular circuit being fabricated. To fill the open features of the first dielectric layer, an excess of superconducting metal can be deposited so that the first dielectric layer is completely coated with superconducting metal. At 1104, the superconducting metal layer is planarized (e.g., by a CMP process) to the height of the first dielectric layer, so that only the portions of the superconducting metal layer that fill the open features of the first dielectric layer remain. At 1105, a second dielectric layer is deposited to produce the desired ILD thickness. A second dielectric layer is deposited on top of or over the superconducting metal layer (and consequently over the first dielectric layer) to a height at least approximately corresponding to the desired inner layer dielectric thickness.The second dielectric layer can be deposited, for example, by CVD, PVD, ALD, or a similar process. The second dielectric layer can be planarized, if necessary, to provide a smooth surface. In 1106, a second superconducting metal layer is deposited on top of or over the second dielectric layer such that the second superconducting metal layer is separated from the first superconducting metal layer by at least an ILD thickness. In some embodiments, the second superconducting metal layer can be deposited directly on top of or over the second dielectric layer (and can be patterned, for example, by standard subtractive patterning techniques (e.g., Figures 9A-9E)). In other embodiments, an etch stop layer may first be deposited directly on top of the second dielectric layer, a third dielectric layer may be deposited on top of or over the etch stop layer, the third dielectric layer may be patterned with a negative mask to create open features, and then a second superconducting metal layer may be deposited on top of or over the third dielectric layer (still on top of or over the second dielectric layer) to fill the open features in the third dielectric layer.

[0084] 10A-10K depict a superconducting additive patterning process, in which electroplating can be used to deposit the superconducting metal (e.g., niobium) layer, and the thickness of the ILD separating the two metal layers is substantially controlled by a dielectric deposition process (e.g., CVD, PVD, ALD, or the like), as opposed to being completely controlled by a planarization / polishing process. FIGS. 10A-10K and 11 depict a superconducting damascene process. However, those skilled in the art will appreciate that the process depicted in FIGS. 10A-10K (and FIG. 11) is simplified in that it does not provide any via connections between separate metal layers. According to the present system and method, the additive process can also be used to fabricate superconducting integrated circuits with via connections between metal layers. For example, a superconducting dual damascene process can be used to fill both via holes and open features in a dielectric layer with superconducting metal. According to the present system and method, the superconducting dual damascene process can include separate via masking / etching and interconnect masking / etching operations. In some embodiments, the open vias and wiring features can be filled with the superconducting metal simultaneously. In some embodiments, the vias can be masked, etched, and filled in multiple stages.

[0085] Superconducting integrated circuits that use multiple superconducting layers often require superconducting interconnects between the layers. These interconnects are known as "vias." Hinode et al., Physica C 426-432 (2005) 1533-1540, discuss some of the challenges inherent in superconducting vias. For example, niobium is a superconducting metal commonly used as a conductor in superconducting integrated circuits, but niobium does not naturally fill via holes very well. This results in poor contact between wiring layers in superconducting integrated circuits that use niobium. Specifically, niobium incompletely fills holes with a depth-to-width aspect ratio greater than about 0.7:1, or 70%. Those skilled in the art will recognize that it is the inherent chemical and / or physical properties of niobium that prevent it from properly filling high-aspect-ratio holes.

[0086] Circuit size is a common design consideration in both semiconductor and superconductor integrated circuits, and the goal is often to fit denser and more sophisticated circuits within limited spatial dimensions. High aspect ratio vias are desirable because they enable the development of more densely packed circuits. According to the state of the art, the inability to produce high aspect ratio superconducting vias currently limits the density and miniaturization of superconducting integrated circuits that use niobium. According to the present system and method, high aspect ratio (i.e., greater than about 0.7:1) niobium vias can be fabricated by using "superconducting additive patterning," "superconducting damascene," and / or "superconducting dual damascene" processes.

[0087] Various embodiments described herein provide systems and methods for superconducting dual damascene processing. The superconducting dual damascene process uses additive patterning and can be similar to the superconducting damascene process depicted in FIGS. 10A-10K and 11 , with the additional feature of providing superconducting via connections between separate superconducting wiring layers. The via connections can be patterned and formed within the patterned dielectric, for example, before open features in the dielectric are filled with superconducting metal. Thus, for each metal wiring layer of a multilayer integrated circuit, the superconducting dual damascene process can include a wiring masking / etching operation to create wiring features, followed by a separate via masking / etching operation to etch vias within the wiring features.

[0088] FIG. 12A is a cross-sectional view of a portion of an exemplary superconducting integrated circuit 1200a during a via masking stage of a superconducting dual damascene process in accordance with the present systems and methods. The integrated circuit 1200a includes a Nb-AlOx-Nb tri-layer 1210 supported on or by a substrate 1230, and a dielectric layer 1241. The integrated circuit 1200a is depicted at an intermediate stage of the fabrication process after the tri-layer 1210 has already been patterned (e.g., via photoresist masking and plasma etching techniques) to define Josephson junctions 1221 and wiring components 1222. At the via masking stage depicted in FIG. 12A, the integrated circuit 1200a further includes a negative-tone photoresist mask layer 1251 overlying the dielectric layer 1241. The mask 1251 effectively traces the negative, or inverse, of the desired location for a via connection to the tri-layer 1210. In other words, the desired via location corresponds to the area of ​​the dielectric layer 1241 not covered by the photoresist mask 1251. Those areas of dielectric layer 1241 that are not directly covered by mask 1251 are etched away to form open holes that expose trilayer 1210, while those areas of dielectric layer 1241 that are directly covered by mask 1251 remain after etching.

[0089] Figure 12B is a cross-sectional view of a portion of an example superconducting integrated circuit 1200b in accordance with the present systems and methods. Figure 12B depicts superconducting integrated circuit 1200a from Figure 12A after the dielectric etch, metal deposition, and metal planarization / polishing stages of an additive patterning process, similar to the acts or actions described in Figures 10B-10D. Photoresist mask 1251 and those areas of dielectric layer 1241 not directly covered by photoresist mask 1251 have been etched out (i.e., in a manner similar to that described in proceeding from Figure 10A to Figure 10B). The resulting holes in dielectric layer 1241 are filled with superconducting metal (i.e., in a manner similar to that described in proceeding from Figure 10B to Figure 10C), creating first portions of vias 1261 and 1262 that provide superconducting connections to Josephson junctions 1221 and 1222, respectively. The first portions of superconducting vias 1261 and 1262 can be filled with niobium using, for example, a niobium electroplating process and can have an aspect ratio of about 0.7:1, less than 0.7:1, or greater than 0.7:1 (as enabled by the electroplating filling process). Excess niobium deposited above the top surface of dielectric layer 1241 is removed via a CMP process (i.e., in a manner similar to that described in proceeding from FIGS. 10C to 10D). As described in FIGS. 12C-12G, FIG. 12B shows only the first portions of each of superconducting vias 1261 and 1262. Additional processing operations or acts can be used to add to the structure of vias 1261 and 1262.

[0090] Figure 12C is a cross-sectional view of a portion of an exemplary superconducting integrated circuit 1200c in accordance with the present systems and methods. Figure 12C depicts circuit 1200b from Figure 12B during the interconnect masking stage of a dual damascene process after deposition of etch stop layers 1271, 1272 and dielectric layers 1242, 1243. Etch stop layer 1271 is deposited on or over dielectric layer 1241, e.g., via a CVD, PVD, or ALD process, and may comprise, e.g., SiN. Dielectric layer 1242 is deposited on or over etch stop layer 1271, e.g., via a CVD, PVD, or ALD process, and may comprise, e.g., SiO2. Deposition of dielectric layer 1242 can be used to control the thickness of the resulting ILD that separates trilayer 1210 from the next overlying metal layer (not yet shown—see metal layer 1290 in Figure 12G). According to the present systems and methods, additive patterning techniques provide improved ILD thickness control because the thickness of the dielectric layer can be more precisely controlled through a deposition process compared to a planarization / polishing process. Etch stop layer 1272 is deposited on or over dielectric layer 1242, e.g., via a CVD, PVD, or ALD process, and may comprise, e.g., SiN. Dielectric layer 1243 is deposited on or over etch stop layer 1272, e.g., via a CVD, PVD, or ALD process, and may comprise, e.g., SiO. In the interconnect masking stage depicted in FIG. 12C , integrated circuit 1200 c further includes a negative photoresist mask layer 1252 overlying dielectric layer 1243. In this additive patterning process, mask 1252 effectively traces the negative, or inverse, of the desired circuit pattern in dielectric layer 1243. In other words, the desired circuit pattern corresponds to areas of dielectric layer 1243 that are not covered by negative photoresist mask 1252. Those areas of dielectric layer 1243 that are not directly covered by mask 1252 are etched away to form open features (e.g., trenches), while those areas of dielectric layer 1243 that are directly covered by mask 1252 remain after etching.Mask 1252 defines the circuit pattern for a metal wiring layer (not shown, see metal layer 1290 in FIG. 12G) located above tri-layer 1210.

[0091] FIG. 12D is a cross-sectional view of a portion of an exemplary superconducting integrated circuit 1200d in accordance with the present systems and methods. FIG. 12D depicts superconducting integrated circuit 1200c from FIG. 12C after the wiring etching stage of the additive patterning process. Photoresist mask 1252 from FIG. 12C has been stripped, and dielectric layer 1243 has been etched to create open features (e.g., trenches) 1281 and 1282 that trace the desired circuit pattern into dielectric layer 1243. Those areas of dielectric layer 1243 that were directly covered by photoresist mask 1252 remain unetched. The etch into dielectric layer 1243 can be controlled, for example, by etch stop layer 1272, which provides an interface between dielectric layer 1243 and dielectric layer 1242 through which the etch will not pass, thereby ensuring that the ILD thickness described in FIG. 12C remains unaffected by this etch.

[0092] Figure 12E is a cross-sectional view of a portion of an exemplary superconducting integrated circuit 1200e in accordance with the present systems and methods. Figure 12E depicts superconducting integrated circuit 1200d from Figure 12D during a via masking stage of a dual damascene process. Integrated circuit 1200e includes a negative photoresist mask 1253 that overlies patterned dielectric layer 1243 and effectively traces the negative or inverse of the locations for the second portions of via connections 1261 and 1262, respectively, so that vias 1261 and 1262 extend down to dielectric layer 1243. Etching for the second portions of vias (e.g., vias 1261 and 1262) can use a chemical etch (i.e., a "slurry") that etches through etch stop layers 1272 and 1271 and dielectric layer 1242 all at once. Alternatively, etching of the second portions of the vias (e.g., vias 1261 and 1262) can be completed in multiple stages, with a first stage using a chemical etch that etches through etch stop layer 1272, a second stage using a chemical etch that etches through dielectric layer 1242, and a third stage using a chemical etch that etches through etch stop layer 1271. Whether the etching is performed in a single operation or multiple operations or acts, the etching can be designed to stop when the existing metal in the first portions of each of vias 1261 and 1262 is exposed. The locations of vias 1261 and 1262 correspond to the areas of etch stop layer 1272 (above dielectric layer 1242 and etch stop layer 1271) within respective open features 1281 and 1282 in dielectric layer 1243 that are not covered by photoresist mask 1253.Those areas of etch stop layer 1272 (as well as dielectric layer 1242 and etch stop layer 1271) not directly covered by mask 1253 are etched away, forming open holes that expose the metal of vias 1261 and the first portions of 1262, while those areas of etch stop layer 1272 (as well as dielectric layer 1242 and etch stop layer 1271) directly covered by mask 1253 remain after etching. Thus, the superconducting dual damascene process uses additive patterning to define the open features in the dielectric layer (in a manner similar to the superconducting damascene process described in Figures 10A-10K) and further provides for masking and etching of via connections within the open features in the dielectric layer. The vias can be filled in multiple stages, with the second stage providing a superconducting extension to the first stage.

[0093] Figure 12F is a cross-sectional view of a portion of an example superconducting integrated circuit 1200f in accordance with the present systems and methods. Figure 12F depicts superconducting integrated circuit 1200e from Figure 12E after the via etching stage of the dual damascene process. Etch stop layer 1272, dielectric layer 1242, and etch stop layer 1271 have all been etched (all at once or sequentially as described above) to expose the existing metal in the first portions of vias 1261 and 1262, respectively, and to provide connections between open features 1281 and 1282 in dielectric layer 1243 and the first portions of vias 1261 and 1262, respectively. Photoresist mask 1253 from Figure 12E has been stripped. Those areas of dielectric layer 1243 and etch stop layer 1272 (as well as dielectric layer 1242 and etch stop layer 1271) that were directly covered by photoresist mask 1253 remain unetched. Thus, in a superconducting dual damascene process, the second portions of vias 1261 and 1262 can be etched into open features 1281 and 1282 in dielectric layer 1243. This allows for subsequent simultaneous filling of both the second portions of vias 1261 and 1262 and open features 1281 and 1282 in dielectric layer 1243 with superconducting metal.

[0094] Figure 12G is a cross-sectional view of a portion of an exemplary superconducting integrated circuit 1200g in accordance with the present systems and methods. Figure 12G depicts superconducting integrated circuit 1200f from Figure 12F after completing superconducting metal deposition and planarization operations or acts. Superconducting metal (e.g., niobium) is deposited on or over dielectric layer 1243 to fill respective portions of superconducting vias 1261 and 1262 and also fill open features (1281 and 1282 from Figure 12F) in dielectric layer 1243 to create wiring features 1291 and 1292. As previously described, the superconducting metal (e.g., niobium) can be deposited by an electroplating process that allows for sufficient filling of the second portions of vias 1261 and 1262 (and / or the entire vias 1261 and 1262, i.e., the combined length of the first and second portions of via 1261 and the combined length of the first and second portions of via 1262) can have any aspect ratio, including an aspect ratio greater than about 0.7:1. To completely fill open features 1281 and 1282 from FIG. 12F, excess metal can be deposited above the top surface of dielectric layer 1243. This excess metal can be removed to the level of dielectric layer 1243 via a planarization / polishing process (e.g., CMP as described in proceeding from FIGS. 10J to 10K). Thus, the metal deposition and planarization operations or acts fill open features 1281 and 1282 from FIG. 12F in dielectric layer 1243 and also fill second portions of vias 1261 and 1262 to define patterned metal wiring layer 1290 that provides a complete via connection between wiring layer 1290 and tri-layer 1210.

[0095] 12A-12G can be repeated for additional dielectric and wiring layers above layers 1243 and 1290 (with additional via connections, if desired) to provide as many layers as needed in any particular integrated circuit design. The acts, acts, or steps described in FIGS. 12A-12G are summarized in FIG.

[0096] FIG. 13 is a flow diagram of a method 1300 for implementing a superconducting dual damascene process in accordance with the present systems and methods. Method 1300 includes ten acts 1301-1310, although one skilled in the art would understand that alternative embodiments may omit certain acts and / or add additional acts. One skilled in the art would understand that the order of the acts shown is for illustrative purposes only and may be altered in alternative embodiments. In 1301, a negative photoresist mask is deposited on or over a first dielectric layer, the negative photoresist mask providing locations for superconducting vias. The first dielectric layer may overlie a superconducting metal layer, such as a Nb-AlOx-Nb trilayer, as depicted in FIG. 12A. In 1302, via locations are etched into the first dielectric layer to create open holes. The open holes may expose the superconducting metal of the superconducting metal layer directly beneath the first dielectric layer. At 1303, a superconducting metal layer is deposited on or over the first dielectric layer to fill the open hole and thereby provide a first portion of the superconducting via. As previously described, the superconducting metal may include niobium and may be deposited, for example, by an electroplating process. The superconducting metal layer is then planarized (e.g., by CMP) until the top surface of the first dielectric layer is exposed. At 1304, a second dielectric layer is deposited. The deposition of the second dielectric layer is preceded by the deposition of at least one etch stop layer. In some embodiments, the deposition of the second dielectric layer at 1304 may include, in order, depositing a first etch stop layer, an inner layer dielectric, a second etch stop layer, and a second dielectric layer. As previously described, the thickness of the inner layer dielectric is determined by this deposition process and therefore can be more precisely controlled than subtractive patterning processes in which the ILD thickness is controlled by a planarization process. At 1305, a first negative photoresist pattern providing a circuit pattern is deposited on or over the second dielectric layer, and at 1306, the circuit pattern is etched into the second dielectric layer to create open features (e.g., trenches).If deposition of at least one etch stop layer occurs prior to deposition of the second dielectric layer in 1304 (as described), etching in 1306 can be configured to stop at the at least one etch stop layer. The first negative photoresist pattern can then be stripped. In 1307, a second negative photoresist mask is deposited on or over the second dielectric layer, providing locations for superconducting vias within the open features of the second dielectric layer. For example, the superconducting vias from acts 1301-1303 can extend upward to connect to the circuit pattern (1305) defined by the open features of the second dielectric layer. Thus, in 1307, locations for connecting the vias from acts 1301-1303 to the circuit pattern (1305) of the second dielectric layer are defined within the open features of the second dielectric layer. In 1308, the second dielectric layer is etched at least within the open feature extending downward through the second dielectric layer to create an open hole and expose the top of a first (filled) portion of the superconducting via (from act 1303). The second negative photoresist mask can then be stripped. In 1309, a superconducting metal layer is deposited over the second dielectric layer to fill the open hole and provide the second portion of the via, as well as to fill the open feature and provide the circuit pattern of the second dielectric layer. As previously described, the superconducting metal can include niobium and can be deposited by an electroplating process that facilitates filling the open hole and allows for the creation of vias with any aspect ratio (e.g., an aspect ratio greater than about 0.7:1). Act 1309 simultaneously forms wiring elements in the second dielectric layer and completes via connections from the wiring elements in the second dielectric layer (e.g., to a wiring layer located directly below the first dielectric layer). At 1310, the superconducting metal layer is planarized or polished (eg, by a CMP process) to remove any excess metal and expose the top surface of the second dielectric layer.If additional layers need to be created in the integrated circuit, a third dielectric layer can be deposited and then acts 1301-1310 can be repeated on top of or across the third dielectric layer.

[0097] The superconducting damascene and / or dual damascene processes depicted in Figures 10A-10K, 11, 12A-12G, and 13 can be used to fabricate complete superconducting integrated circuits without ever requiring etching of the superconducting metal itself. Such may be advantageous for circuits using niobium as the superconducting metal, because techniques for etching niobium are less developed in the art than techniques for etching other materials, such as aluminum (due to the extensive use of aluminum in the semiconductor industry). Moreover, etching niobium can result in the formation of niobium oxides and / or other compounds that can adversely affect circuit operation and performance. Thus, the superconducting damascene and / or dual damascene approaches described herein have the added benefit of reducing (and in some cases eliminating) the formation of unwanted niobium oxides.

[0098] The superconducting damascene and dual damascene processes described above implement certain process modifications that, taken together, can provide specific benefits for superconducting integrated circuit fabrication compared to standard photoresist masking and plasma etching (i.e., standard subtractive patterning). However, according to the present systems and methods, some of the processes described above can be individually incorporated into otherwise standard photoresist masking and plasma etching processes to realize certain benefits. For example, via fill and via critical current control can be achieved by using electroplating to deposit niobium even in subtractive patterning processes. Such a process may involve few variations from the processes outlined in FIGS. 9A-9E, except that an electroplating process is used for the niobium deposition step, as opposed to a more typical CVD, PVD, or ALD process. As described above, niobium deposition via an electroplating process can provide better filling of via connections (compared to niobium deposition via CVD, PVD, or ALD-type processes) and enable reliable fabrication of vias with high aspect ratios (e.g., greater than about 0.7:1).

[0099] Another example of an individual aspect of the superconducting damascene and / or dual damascene processes described above that can be integrated into an otherwise standard subtractive patterning process is defining the ILD thickness by dielectric deposition as opposed to dielectric planarization. According to the present systems and methods, an otherwise typical subtractive patterning process (e.g., as shown in Figures 9A-9E) can be modified so that the ILD thickness is determined by a dielectric deposition process as opposed to a dielectric planarization process. Such a modification can include, for example, extending the dielectric planarization depicted in proceeding from Figure 9C to Figure 9D by planarizing the dielectric layer 940 all the way to the top of the metal layer 920. Additional dielectric deposition can then be used to increase the height of the dielectric layer 940 (e.g., to the height depicted in Figure 9E) until the desired ILD thickness is reached. As previously described, dielectric deposition can provide better thickness control than dielectric planarization. In some embodiments, planarizing the dielectric layer 940 all the way to the top of the metal layer 920 can involve CMP, and a highly selective slurry ("HSS") can be used as opposed to a standard slurry.

[0100] Throughout this specification, reference is often made to substrates formed of, for example, silicon, silicon oxide, sapphire, or similar materials (such as quartz). The semiconductor industry often uses doped silicon as the substrate or carrier in integrated circuits because doping can facilitate the fabrication process. However, in superconducting integrated circuits, such dopants can be a source of unwanted noise and / or can increase the heat capacity of the silicon substrate, which is particularly undesirable in superconducting circuits where an important function of the substrate is to assist in cooling a conductive metal to superconductivity. Therefore, it may be preferable to use pure, undoped silicon as the substrate or carrier in superconducting integrated circuits.

[0101] While many different materials can be used as substrates in superconducting integrated circuits, silicon with a silicon oxide top layer is commonly used. The silicon oxide top layer is often added, at least in part, because silicon alone is transparent, which can make standard lithography processes difficult to perform. However, in particularly noise-sensitive superconducting circuits (e.g., superconducting qubit circuits such as superconducting quantum processors), this silicon-silicon oxide interface can be an undesirable noise source. According to the present systems and methods, in some applications, it may be advantageous to fabricate superconducting integrated circuits on a substrate comprising silicon with an alternative material, such as aluminum oxide, as a top layer, instead of silicon with a silicon oxide top layer.

[0102] 14 is a cross-sectional view of a portion of a substrate 1400 for use in a superconducting integrated circuit in accordance with the present systems and methods. The substrate 1400 comprises two layers: a base layer 1410 of silicon (e.g., standard doped silicon as described above or undoped pure silicon) and a top layer 1420 of aluminum oxide. In some embodiments, the base layer 1410 may comprise sapphire, quartz, or any alternative material suitable as a substrate. The aluminum oxide layer 1420 is non-transparent (e.g., translucent, semi-transparent, or opaque), thus facilitating use of the substrate 1400 in conjunction with standard lithographic processing techniques. Moreover, the silicon-aluminum oxide interface can provide improved noise characteristics (i.e., behave as a less noisy source) compared to the silicon-silicon oxide interface commonly used in substrates. An additional benefit of the aluminum oxide top layer 1420 is that aluminum oxide can act as a better etch stop compared to silicon oxide, thus allowing for more precise etching and patterning of materials (e.g., superconducting metals such as niobium) deposited over the aluminum oxide top layer 1420.

[0103] As previously explained, if the junction is heated above approximately 200°C, the quality of the trilayer Josephson junction may be degraded (specifically, the quality of the insulating barrier, e.g., AlOx, may be degraded). This means that once a Josephson junction trilayer is deposited in a superconducting integrated circuit, it may be advantageous to perform all subsequent processing operations or acts at a lower temperature (i.e., <200°C) to maintain Josephson junction quality. In the semiconductor industry, dielectrics are typically deposited at high temperatures (e.g., above 400°C) to improve purity and smoothness. However, in superconducting integrated circuits using Josephson junctions, depositing a dielectric layer over the Josephson junction at such high temperatures may adversely affect the Josephson junction itself. Accordingly, it may be advantageous to use a low-temperature dielectric deposition process in circuits including Josephson junction trilayers. One example of a low-temperature dielectric process is the low-temperature tetraethyl orthosilicate (“TEOS”) dielectric deposition process. In the art, TEOS is often used as a precursor to silicon oxide, but at certain temperatures (e.g., 650-850°C), it can adversely affect Josephson junction quality. According to the present system and method, the TEOS dielectric deposition process (e.g., a CVD TEOS process or a plasma-enhanced CVD TEOS process) can be performed at a significantly lower temperature (e.g., around 200°C) when applied across a triple-layer Josephson junction to maintain Josephson junction quality.

[0104] Many of the embodiments described herein are directed to applications in superconducting quantum computing. Those skilled in the art will understand that the requirements for manipulating quantum information (e.g., noise tolerance levels) may be more stringent than those for manipulating non-quantum information. Thus, while the various embodiments described herein are particularly well-suited for use in fabricating superconducting quantum processors, these teachings may also be applicable to any application incorporating superconducting integrated circuits, including applications with less stringent performance criteria. For example, the various teachings provided herein may be applicable to single flux quantum (SFQ) circuits as well as any circuit using Josephson junctions. In some instances, application of the present systems and methods in non-quantum computing applications may allow for the relaxation of certain constraints. SFQ applications may be less sensitive to noise than quantum computing applications, and thus low-temperature dielectric processes may be more readily applied to SFQ circuits to maintain Josephson junction quality without significant concern for the resulting increase in dielectric defects.

[0105] In addition to low temperature dielectric deposition processes, metal deposition processes that occur after the Josephson junction (e.g., on or above the Josephson junction trilayer) can also result in heating of the junction to a point where the insulating barrier deteriorates. According to the present systems and methods, unwanted heating of the Josephson junction trilayer by subsequent metal deposition processes can be avoided by performing the metal deposition processes in multiple stages and allowing the system to cool between stages.

[0106] FIG. 15 illustrates a method 1500 for performing a multi-stage metal deposition in accordance with the present systems and methods. Method 1500 includes five operations or acts 1501-1505, although one skilled in the art would understand that alternative embodiments may omit certain acts and / or add additional acts. One skilled in the art would understand that the order of the depicted acts is shown for illustrative purposes only and may be varied in alternative embodiments. At 1501, a first stage of a metal deposition process is initiated to deposit a first portion of a metal layer on an integrated circuit. The metal to be deposited may be a superconducting metal such as niobium or aluminum, and the metal deposition process may use any deposition technique, such as CVD, PVD, or ALD. The metal deposition process may result in heating of the integrated circuit. At 1502, the first stage of the metal deposition process is stopped to prevent the integrated circuit from heating to a point where existing components sensitive to high temperatures (e.g., Josephson junction trilayers) may be damaged. The temperature of the integrated circuit (or the temperature of the chamber in which deposition occurs) can be monitored during the first stage of metal deposition, and the metal deposition process can be stopped when the monitored temperature appears to approach or exceed a predetermined threshold. Alternatively, a target deposition time can be predetermined based on previous data and / or calculations, and the first stage of the metal deposition process can be stopped once the predefined target deposition time has elapsed. At 1503, the integrated circuit is cooled. Because the metal deposition process has been stopped, the circuit can be passively cooled over time, and act 1503 simply involves waiting until the circuit has cooled. In some embodiments, the circuit can be actively cooled by filling the deposition chamber with an inert gas such as argon. Generally, higher gas pressures provide better thermalization, although of course, the pressure is limited by factors such as chamber strength and cooling time. At 1504, an additional stage of the metal deposition process is initiated to deposit additional portions of the metal layer on top of or over the previous portions of the metal layer (i.e., to resume deposition of the metal layer).Additional stages of metal deposition can continue until the desired total metal layer thickness (i.e., the thickness of the first portion of the metal layer plus the thickness of the additional portion of the metal layer) is deposited or until the threshold temperature / time is again reached. In 1505a, the desired total metal layer thickness is reached, completing the multi-stage metal layer deposition process. In 1505b, the temperature of the circuit reaches the threshold temperature before the desired total metal layer thickness is reached, so acts 1502-1505 are repeated until the desired total metal layer thickness is reached.

[0107] Various embodiments described herein provide systems and methods for the fabrication of multilayer superconducting integrated circuits. Such circuits are typically fabricated layer by layer (one layer at a time, including via connections between layers), and therefore it is important to ensure that features on each layer are properly aligned with features on the layer or layers above and / or below it. For example, a feature on a second layer that is to be connected to a feature on a first layer by a via connection (if the second layer is above the first layer) typically needs to be properly aligned above the feature on the first layer. Throughout the semiconductor fabrication industry, a process known as "open frame masking and etching" is often used to provide this alignment. Open frame masking and etching techniques involve marking a substrate with a "zero mark" or "alignment mark" before depositing a conductive or insulating layer. The zero mark then needs to be "seen" before each subsequent layer is deposited over the substrate. This means that after the conductive layer is deposited, the area of ​​the conductive layer overlying the zero mark on the substrate must be etched away to expose the zero mark so that the patterning of the conductive layer can be properly aligned. Thin dielectric layers (e.g., SiO2) are typically transparent enough to allow the zero mark to be visible without etching.

[0108] Thus, in the superconducting version of the open frame masking and etching alignment technique, a superconducting metal layer is deposited, and a first photoresist mask layer is deposited on or over the superconducting metal layer, completely covering the surface of the superconducting metal layer except for the open area near the zero mark. An etch is then applied, etching out the exposed area of ​​the superconducting metal layer to reveal the zero mark of the substrate. Any remaining photoresist is then stripped, and a second photoresist mask layer is then deposited on or over the superconducting metal layer, where the second photoresist mask layer provides a circuit pattern for the superconducting metal layer aligned with the exposed zero mark of the substrate. This process is repeated for each subsequent superconducting metal layer in the integrated circuit stack. As noted above, the open frame masking and etching process is commonly used in the semiconductor industry. Unfortunately, when the same technique is applied using a superconducting metal such as niobium, it has been found that exposing the same superconducting (e.g., niobium) metal layer to two photoresist masking and etching operations (i.e., a first operation to expose the zero mark, and then a second operation to apply a circuit pattern aligned with the zero mark) results in the formation of undesirable residues (e.g., photoresist residues and / or metal residues, such as Nb defects) on the surface of the superconducting metal layer that can adversely affect the performance of the integrated circuit. Thus, there is a need in the art for alternative methods of aligning multiple layers of superconducting integrated circuits that reduce the number of masking and etching operations per superconducting metal layer.

[0109] According to the present system and method, layers of a multilayer superconducting integrated circuit can be properly aligned during fabrication by etching respective alignment marks into each dielectric layer. This approach eliminates the need for zero marking on the substrate. Instead, a first superconducting metal layer can be patterned to include circuit traces and alignment marks. A dielectric layer can be deposited on or over the first superconducting metal layer. The dielectric layer (e.g., SiO2) can be sufficiently transparent so that the alignment marks of the first superconducting metal layer can be discerned through the dielectric layer. The dielectric layer can then be patterned and etched to provide holes that expose specific portions of the first superconducting metal layer, and these holes will ultimately correspond to superconducting via connections to the first superconducting metal. Such patterning and etching of dielectric layers is standard. However, according to the present system and method, the pattern of the dielectric layer can also include alignment marks that overlie the alignment marks of the first superconducting metal layer. The alignment mark is etched into the dielectric layer and can easily cover the alignment mark of the first superconducting metal layer because the dielectric layer is sufficiently transparent. A second superconducting metal layer is then deposited on top of or over the dielectric layer. The deposition of the second superconducting metal layer fills (or at least partially fills) the patterned holes in the dielectric layer, providing a superconducting via connection to the first superconducting metal layer. The deposition of the second superconducting metal layer also at least partially fills the alignment mark etched into the dielectric layer. The alignment mark can be designed (e.g., in size and / or shape) such that the alignment mark is visible on the top surface of the second superconducting metal layer due to the fact that the alignment mark is filled by the deposition of the second superconducting metal layer. For example, if the alignment mark is sufficiently large, the imprint of the alignment mark may be visible on the top surface of the second superconducting metal layer because the metal "fills in" to fill the mark. Thus, the alignment marks of the first superconducting metal layer are reproduced in the overlying dielectric layer so as to leave an imprint in the second superconducting metal layer.A photoresist mask that provides a pattern for the second superconducting metal layer can then be deposited and aligned to the imprints of the alignment marks. This process can then be repeated for any number of additional layers.

[0110] 16 is a cross-sectional view of a portion of an exemplary superconducting integrated circuit 1600 showing imprints 1680 of alignment marks in a superconducting metal layer 1622. The circuit 1600 includes a substrate 1630 upon which a first superconducting metal layer 1621 has been deposited. Layer 1621 has been patterned (e.g., by masking and etching) to define wiring features 1631, 1632 and alignment marks 1650. A dielectric layer 1640 has been deposited over the patterned metal layer 1621. The dielectric layer 1640 has also been patterned (e.g., by masking and etching) to expose the alignment marks 1650 and wiring features 1631, 1632 in the metal layer 1621. Metal layer 1622 is deposited over dielectric layer 1640, filling the open features in dielectric layer 1640 to create superconducting vias 1661, 1662 and an imprint 1680 on the top surface of metal layer 1622 overlying alignment mark 1650. Imprint 1680 may result from the size and / or shape of alignment mark 1650. In various embodiments, depending on the nature of alignment mark 1650, imprint 1680 may include at least one recess, at least one protrusion, multiple recesses, multiple protrusions, and / or a combination of at least one recess and at least one protrusion. Imprint 1680 may be discernible during subsequent lithographic processing of metal layer 1622, thereby serving as a reference point for aligning the deposition of a photoresist mask layer on top of metal layer 1622. If an additional metal layer (not shown) is to be deposited on top of or over metal layer 1622 (e.g., after deposition of an additional dielectric layer), then inscription 1680 can be patterned into a new alignment mark in metal layer 1622 (or inscription 1680 can be etched out and a new alignment mark patterned elsewhere in metal layer 1622). This process of patterning alignment marks into a dielectric layer to leave inscriptions in an overlying metal layer allows multiple layers to be aligned in a stack without the additional metal patterning operations or acts associated with open-frame masking and etching alignment techniques.In this way, potentially undesirable photoresist and / or metal residues can be avoided or reduced. In some embodiments, the alignment mark 1650 can be designed to provide a unique indicia 1680 that can be easily distinguished from other surface features inherent in the fabrication process. For example, the alignment mark can be significantly (e.g., multiple times) larger than the features of the circuit pattern itself and / or embody one or more unique shapes. The process described in the context of FIG. 16 is summarized in FIG. 17.

[0111] FIG. 17 illustrates a method 1700 for aligning multiple layers of a multi-layer superconducting integrated circuit without using open frame and matching techniques, in accordance with the present systems and methods. Method 1700 includes five operations or acts 1701-1705, although those skilled in the art will understand that alternative embodiments may omit certain acts and / or add additional acts. Those skilled in the art will understand that the order of the acts shown is for illustrative purposes only and may be altered in alternative embodiments. In 1701, a first superconducting metal layer is patterned to include at least one alignment mark. As previously described, the alignment mark may be large or otherwise specifically designed to leave a recognizable mark in an overlying metal layer so that the mark can be identified during subsequent lithography steps. In 1702, a first dielectric layer is deposited on or over the first superconducting metal layer. In 1703, the first dielectric layer is patterned (e.g., masked and etched) to define open holes at the locations of the vias and to expose at least one alignment mark. The first dielectric layer can be at least partially transparent, and the at least one alignment mark can be discernible through the first dielectric layer. In 1704, a second superconducting metal layer is deposited on or over the first dielectric layer to at least partially fill the open holes and provide via connections. The second superconducting metal layer also covers the at least one alignment mark, thereby leaving corresponding imprints on the opposite (i.e., exposed) surface of the second superconducting metal layer. In 1705, a photoresist mask is aligned to the imprints of the alignment mark on the second superconducting metal layer (e.g., on the exposed surface of the second superconducting metal layer). A photoresist mask can then be deposited on or over the second superconducting metal layer, and acts 1701-1705 can be repeated if additional superconducting metal layers are desired.The alignment marks of the subsequent layer may cover the alignment marks of the first superconducting metal layer, or the alignment marks of the subsequent metal layer may be positioned so as not to cover the alignment marks of the first superconducting metal layer.

[0112] The alignment issues discussed above can, in some instances, be avoided if an additive patterning process (such as a damascene or dual damascene process) is used.

[0113] U.S. Patent Application Publication No. 2011-0089405 describes the use of platinum as a resistor material in superconducting integrated circuits. According to this system and method, platinum can be deposited via a sputtering process, using a thin layer of an intermediate material, such as titanium, to improve adhesion between the platinum and the surface on which it is being deposited. That is, if platinum is to be used as a resistor deposited on or over a dielectric material, such as SiO2, a thin "adhesion layer" (e.g., formed of titanium) can first be deposited on the dielectric surface (e.g., via a sputtering process), and then platinum can be deposited directly on the adhesion layer. The titanium-platinum (TiPt) stack can then be patterned and etched via a lithography process, using, for example, the etchant chemistry of Cl2 and SF6.

[0114] As previously explained, some superconducting metals, including niobium, do not naturally fill via holes well. This results in poor contact between wiring layers of superconducting integrated circuits that use vias. According to the present system and method, via filling can be improved by modifying the etching profile of the via hole. Typically, via holes are etched to form substantially smooth, substantially vertical sidewalls (see, e.g., vias 1261 and 1262 in Figures 12E-12G and vias 1661 and 1662 in Figure 16). According to the present system and method, forming via holes with uneven and / or non-vertical sidewalls can improve via filling upon subsequent deposition of a superconducting metal, such as niobium. Thus, via holes with uneven and / or non-vertical sidewalls can improve electrical connections between wiring layers of multilayer superconducting integrated circuits and / or enable the fabrication of vias with high aspect ratios (e.g., aspect ratios greater than about 0.7:1). One example of a via with non-vertical sidewalls is a tapered via. Techniques for fabricating tapered vias are commonly known in the semiconductor industry, and in accordance with the present systems and methods, many of the same techniques (e.g., etchant chemistries, etc.) can be used in fabricating superconducting vias to improve superconducting electrical connections between layers of superconducting integrated circuits.

[0115] FIG. 18 is a cross-sectional view of a portion of an exemplary superconducting integrated circuit 1800 showing a superconducting via 1860 having non-vertical sidewalls 1861 and 1862 in accordance with the present systems and methods. As shown in FIG. 18, sidewalls 1861 and 1862 are tapered such that the via 1860 is wider at the top and narrower at the bottom. Tapered superconducting via 1860 provides a superconducting electrical connection between superconducting wiring layer 1852 and superconducting wiring layer 1851. As shown, superconducting wiring layer 1851 provides the top / counter electrode of a Josephson junction. Tapered superconducting via 1860 can be etched according to known techniques for etching tapered vias in the semiconductor industry; however, in accordance with the present systems and methods, the superconducting metal (e.g., niobium) of superconducting wiring layer 1851 can be used as an etch stop when etching tapered via 1860 (as opposed to materials more commonly used as etch stops in the semiconductor industry). Once the tapered profile of via 1860 has been etched into dielectric layer 1840, superconducting metal (e.g., niobium) 1852 can be deposited over dielectric layer 1840 to fill via 1860. The tapered profile of sidewalls 1861 and 1862 can facilitate improved filling of via 1860 with superconducting metal 1852, as compared to, for example, a via profile having vertical sidewalls. Thus, an improved superconducting electrical connection can be established between superconducting metal layer 1852 and superconducting metal layer 1851, where superconducting metal layer 1851 (e.g., niobium) functions both as an etch stop during etching of tapered via 1860 and as a superconducting wiring layer for circuit 1800.

[0116] In some cases, incomplete filling of superconducting vias can be the result of over-etching the via hole and undercutting the underlying superconducting metal. Such over-etching can create grooves in the metal (e.g., niobium) beneath the sidewalls of the via, resulting in a weak physical connection between the superconducting metal on the via sidewalls and the underlying superconducting metal beneath the via once the via is filled with the superconducting metal (e.g., niobium). A weak physical connection typically results in poor electrical connection. According to the present systems and methods, over-etching of the underlying superconducting metal can be reduced by depositing a protective cap layer over the underlying superconducting metal. For example, the superconducting metal layer can be capped with a thin layer of protective material (such as titanium nitride or silicon nitride). Then, when the via is etched on top of the capped superconducting metal layer, the protective cap layer can prevent over-etching into the superconducting metal layer, ultimately providing a better electrical connection between the superconducting metal on the via sidewalls and the underlying superconducting metal layer. The protective cap layer can be a superconducting material. Titanium nitride is particularly well suited for providing a capping layer on niobium wiring layers because it can be superconducting below about 4.2 K, it does not oxidize as much as niobium, and it etches well with niobium etch chemistries but acts as an excellent etch stop for SiO2 etch chemistries (i.e., during via etching). In some applications, it is advantageous to ensure that a protective capping layer formed of a superconducting material does not introduce superconducting shorts between elements of a patterned superconducting metal layer (e.g., between superconducting paths or traces in a superconducting wiring layer). Such shorts can be avoided, for example, by depositing a protective capping layer over the superconducting metal layer before patterning the superconducting metal layer, such that the capping layer is also patterned during the patterning process.

[0117] FIG. 19 illustrates a method 1900 for forming a superconducting via according to the present systems and methods. Method 1900 includes six operations or acts 1901-1906, although one skilled in the art would understand that alternative embodiments may omit certain acts and / or add additional acts. One skilled in the art would understand that the order of the depicted acts is shown for illustrative purposes only and may be varied in alternative embodiments. In 1901, a first superconducting metal layer is deposited. The first superconducting metal layer may include a superconducting metal such as niobium or aluminum and may be deposited over a substrate or dielectric layer, or over an insulating barrier such as an aluminum oxide layer. The first superconducting metal layer may be, for example, a superconducting wiring layer or a superconducting counter electrode layer of a Josephson junction. In 1902, a superconducting protection capping layer is deposited over the first superconducting metal layer. The superconducting protection capping layer may include, for example, titanium nitride, titanium niobium nitride, or any other suitable material. In 1903, the first superconducting metal layer is patterned (e.g., via a photoresist masking and etching process as previously described). Patterning the first superconducting metal layer necessarily includes patterning the superconducting protection capping layer with the same pattern so that portions of the first superconducting metal layer remaining after the patterning process (e.g., the wiring pattern of the superconducting metal layer and / or the definition of the Josephson junction counter electrode of the superconducting metal layer) retain the superconducting protection capping layer covering it. In 1904, a dielectric layer is deposited over the patterned superconducting protection capping layer and the first superconducting metal layer. The dielectric layer may include, for example, a silicon oxide or hybrid dielectric layer, as previously described. In 1905, holes are etched through the dielectric layer to expose at least a portion of the superconducting protection capping layer and the first superconducting metal layer. The etching process can be stopped when the superconducting protection capping layer is exposed, the etching process can continue at least partially into the superconducting protection capping layer, or the etching process can be stopped when the first superconducting metal layer is exposed.In either case, the superconducting protective capping layer can help maintain the shape of the hole during the etching process and prevent over-etching into the first superconducting metal layer. At 1906, a second superconducting metal layer is deposited over the dielectric layer. The second superconducting metal layer can at least partially fill the hole through the dielectric layer and form a superconducting electrical connection (i.e., a superconducting via) with at least one of the superconducting protective capping layer and the first superconducting metal layer.

[0118] 20 is a cross-sectional view of a portion of a superconducting integrated circuit 2000 including a superconducting protection capping layer 2051 overlying a superconducting metal layer 2021 in accordance with the present systems and methods. The superconducting integrated circuit 2000 further includes a superconducting metal layer 2022 separated from the superconducting metal layer 2021 by a dielectric layer 2031. Each of the superconducting metal layers 2021 and 2022 may include, for example, niobium. The superconducting metal layer 2021 is superconductively coupled to the superconducting metal layer 2022 through a superconducting via 2061. In FIG. 19, the via 2061 is shown partially etched into the superconducting protection capping layer 2051 without exposing the superconducting metal layer 2021. As described above, superconducting protection capping layer 2051 can prevent over-etching into superconducting metal layer 2021 during the formation of superconducting via 2061, thereby improving the superconducting electrical connection between superconducting metal layer 2021 and superconducting metal layer 2022. Superconducting protection capping layer 2051 can include, for example, titanium nitride, titanium niobium nitride, or any suitable material, as described above.

[0119] As previously explained, the behavior of a Josephson junction is affected by a property called its critical current. The critical current of a Josephson junction is the maximum amount of current (for a given external magnetic field, usually reported at zero external magnetic field) that can flow through the junction without the junction switching into a voltage state. The critical current of a Josephson junction depends on a number of factors, including the area of ​​the junction and the thickness of the insulating barrier. For a given thickness of the insulating barrier, the larger the area of ​​the junction, the higher its critical current. Similarly, for a given area of ​​the junction, the thicker the insulating barrier, the lower its critical current. In superconducting integrated circuits using trilayer Josephson junctions, junctions with different critical currents are typically achieved by depositing a single trilayer with a uniform barrier thickness and patterning the trilayer to form junctions of different areas. For example, if a circuit requires a first Josephson junction having a first critical current and a second Josephson junction having a second critical current, where the second critical current is greater than the first critical current, the second Josephson junction can be designed and positioned to have a larger area than the first Josephson junction. This approach is suitable for relatively small circuits and / or circuits using Josephson junctions with similar critical currents, but can be problematic for large, complex circuits and / or circuits using Josephson junctions across a wide range of critical currents. For example, in a circuit utilizing a single tri-layer to form a first set of Josephson junctions having a first critical current and a second set of Josephson junctions having a second critical current, where the second critical current is much greater than the first critical current, the area of ​​each junction in the second set of junctions must be much larger than the area of ​​each junction in the first set of junctions. The large area of ​​the second set of Josephson junctions may undesirably increase the overall footprint (i.e., area) of the integrated circuit itself, may introduce complications in connecting the circuit to electrical input / output systems and / or insulating the circuit from ambient magnetic fields, and may ultimately render the integrated circuit too large for its intended application.In some applications, it may be possible to overcome these problems by depositing a separate trilayer within an integrated circuit, where the second trilayer uses a different dielectric barrier thickness than the first trilayer. However, depositing a second trilayer significantly increases the number of layers in the integrated circuit stack and, accordingly, the number of processing steps required in fabricating the stack. This can increase the likelihood of defects and generally reduce the likelihood of producing a fully functional circuit. Also, achieving a uniform dielectric barrier thickness for the second trilayer can be very challenging because the second trilayer must necessarily be deposited at a higher level in the circuit stack, where the surface on which the second trilayer is deposited may be less smooth or planar than the substrate (i.e., the first and second trilayers cannot both be deposited on the substrate).

[0120] The thickness of the insulating barrier of a Josephson junction is determined by the "critical current density" or "J" of the Josephson junction. c This affects a parameter known as the J c is essentially a measure of the critical current per unit area of ​​the Josephson junction, and typically a thicker insulating barrier results in a lower J c Typically, a thinner insulating barrier produces a higher J c produces.

[0121] According to the present system and method, Josephson junctions with different critical currents can be realized in a single superconducting integrated circuit by replacing a Josephson trilayer with a Josephson "pentalayer" junction having two insulating barriers of different thicknesses. A Josephson "pentalayer" junction has five layers: a first layer of superconducting material (e.g., niobium) that serves as a first base electrode; c a first insulating barrier (e.g., aluminum oxide, including aluminum oxide grown on aluminum, as previously described), a second layer of superconducting material (e.g., niobium) that serves as both the first counter electrode and the second base electrode, and a first J c A second J that is different from cThe second insulating barrier may comprise a second insulating barrier (e.g., aluminum oxide, including aluminum oxide grown on aluminum) having a second J c is the first J c It may be advantageous for the second insulating barrier to be thicker than the first insulating barrier so that the temperature is lower.

[0122] 21A is a cross-sectional view of a portion of a superconducting integrated circuit 2100a including a Josephson junction pentad 2110 in accordance with the present systems and methods. The pentad 2110 includes a first base electrode 2111 formed of niobium, a first insulating barrier 2112 formed of aluminum oxide (as previously described, an aluminum layer can be disposed between the first base electrode 2111 and the first insulating barrier 2112 for the growth of the first insulating barrier 2112), a first counter-electrode 2113 formed of niobium that can also function as a second base electrode, a second insulating barrier 2114 formed of aluminum oxide (as previously described, an aluminum layer can be disposed between the first counter-electrode 2113 and the second insulating barrier 2114 for the growth of the second insulating barrier 2114), and a second counter-electrode 2115 formed of niobium. 21A, the first insulating barrier 2112 is substantially thinner than the second insulating barrier 2114. As a result, the first insulating barrier 2112 has a substantially higher J than the second insulating barrier 2114. c According to the present systems and methods, the five-layer 2110 can be patterned to form Josephson junctions whose critical current is determined by the insulating barrier 2112 or the insulating barrier 2114. Thus, the five-layer 2110 provides multiple J-junctions in defining Josephson junction circuit elements while using fewer layers and fewer processing steps than a complete second trilayer. c Moreover, the five layers 2110 minimize the number of layers between the second insulating barrier 2114 and the substrate, so that the second insulating barrier 2114 may be flatter and more uniform in thickness than if it were deposited higher in the circuit stack.

[0123] As explained above, the first insulating barrier 2112 has a substantially higher J than the second insulating barrier 2114. c According to the present system and method, for most applications, the Josephson junction five-layer has a J c The higher barrier is J c Place it under the lower barrier (or J c The lower barrier is J c It is advantageous to place the first insulating barrier 2112 above the higher barrier in a penta-stack because, like in a tri-stack, current flows "vertically" through the layers of the penta-stack. In an individual Josephson junction that includes both a first insulating barrier 2112 and a second insulating barrier 2114, the two insulating barriers are effectively in series with each other, and the critical current of the junction is the sum of the two J c The lower J c Due to the nature of the photoresist masking and etching techniques used to pattern Josephson junctions, it is easy to remove the top insulating barrier (i.e., second insulating barrier 2114) from a five-layer stack while leaving the bottom insulating barrier (i.e., first insulating barrier 2112) in place to define the Josephson junction, but it is much more difficult to remove the bottom insulating barrier while leaving the top insulating barrier in place. Thus, a Josephson junction patterned in a five-layer stack 2110 will generally have: i) both the first insulating barrier 2112 and the second insulating barrier 2114 (so that the critical current of the junction is c is determined by the lower insulating barrier (i.e., by the second insulating barrier 2114), or ii) only the first insulating barrier 2112 (so that the critical current of the junction is determined by the insulating barrier 2112). If only the first insulating barrier 2112 is present, the critical current of the Josephson junction is determined by the J c However, if both the first insulating barrier 2112 and the second insulating barrier 2114 are present, the critical current of the Josephson junction is determined by the product of the two J c The lower Jc (In this case, the critical current is determined by the second insulating barrier 2114.) Therefore, to enable the formation of Josephson junctions with two different critical currents, the J c is the J of the bottom insulating barrier (i.e., the first insulating barrier 2112). c The lower the insulating barrier (i.e., the first insulating barrier 2112), the lower the c The lower J c , only junctions with a critical current defined by the bottom insulating barrier (ie, the first insulating barrier 2112) can actually be formed.

[0124] 21B is a cross-sectional view of a portion of an example superconducting integrated circuit 2100b in accordance with the present systems and methods. FIG. 21B depicts the superconducting integrated circuit 2100a from FIG. 21A after two Josephson junctions 2121 and 2122 have been defined using five layers 2110. Junction 2121 includes patterned portions of both the first insulating barrier 2112 and the second insulating barrier 2114, while junction 2122 includes only the patterned portion of the first insulating barrier 2112. Thus, the critical current of junction 2122 is equal to the J of the first insulating barrier 2112. c The critical current of the junction 2121 is determined by the J c and the second insulating barrier 2114 J c The lower J c The second insulating barrier 2114 is thicker than the first insulating barrier 2112, and therefore the second insulating barrier 2114 has a lower J than the first insulating barrier 2112. c Therefore, the critical current of the junction 2121 is J of the second insulating barrier 2114. c However, the J of the second insulating barrier 2114 is c is the J of the first insulating barrier 2112 c If it is higher, the critical current of the junction 2121 is higher than the J cNote that despite the presence of the second insulating barrier 2114, both junction 2121 and junction 2122 will have the same critical current (for the same junction area).

[0125] One example of a superconducting integrated circuit in which it is desirable to include Josephson junctions with substantially different critical currents is a superconducting quantum processor with local on-chip memory and / or control circuitry. In such a circuit, the superconducting qubits may use Josephson junctions with a first critical current (or a first range of critical currents), and the on-chip memory / control circuitry may use Josephson junctions with a second critical current (or a second range of critical currents) that is substantially different from the first critical current (or first range of critical currents). Single flux quantum (SFQ), quantum flux parametron (QFP), or other superconducting logic circuits (including, but not limited to, those schemes described in U.S. Pat. Nos. 8,098,179, 7,876,248, 8,035,540, 7,843,209, 8,018,244, and U.S. Patent Application Publication No. 2011-0065586, each of which is incorporated by reference in its entirety) may be used. By using five Josephson junction layers, memory / control circuits can be integrated into quantum processor architectures without requiring large area Josephson junctions, which can reduce the area of ​​the processor, for example, allowing for minimization of qubit size (qubit size is advantageously minimized in quantum processors to reduce noise coupling into the qubit circuitry).

[0126] FIG. 22 illustrates a method 2200 for forming a Josephson junction pentalayer according to the present systems and methods. Method 2200 includes five operations or acts 2201-2205, although one skilled in the art would understand that alternative embodiments may omit certain acts and / or add additional acts. One skilled in the art would understand that the order of the depicted acts is shown for illustrative purposes only and may be altered in alternative embodiments. In 2201, a first superconducting metal layer is deposited. The first superconducting metal layer may comprise, for example, niobium and may be deposited on a dielectric layer or substrate. In 2202, a first insulating barrier is deposited over the first superconducting metal layer. The first insulating barrier may comprise, for example, aluminum oxide, and depositing the first insulating barrier over the first superconducting metal layer may include depositing an aluminum layer on top of the first superconducting metal layer and growing an aluminum oxide layer on the aluminum layer. The first insulating barrier has a first critical current density (J c1 ) at 2203, a second superconducting metal layer is deposited over the first insulating barrier. The second superconducting metal layer may comprise, for example, niobium. At 2204, a second insulating barrier is deposited over the second superconducting metal layer. The second insulating barrier may comprise, for example, aluminum oxide, and depositing the second insulating barrier over the second superconducting metal layer may include depositing an aluminum layer on top of the second superconducting metal layer and growing an aluminum oxide layer on the aluminum layer. The second insulating barrier may provide a second critical current density (J c2 ) is deposited over the second insulating barrier. At 2205, a third superconducting metal layer is deposited over the second insulating barrier. The third superconducting metal layer may include, for example, niobium. According to the present systems and methods, the second thickness of the second insulating barrier may be substantially different from the first thickness of the first insulating barrier (resulting in a difference in the J c1 J c2 As explained previously, the critical current density J of the second insulating barrier is c2is the critical current density J of the first insulating barrier c1 It may be advantageous to ensure that the second thickness of the second insulating barrier is substantially greater than the first thickness of the first insulating barrier, so that the critical current is substantially lower than the first thickness of the first insulating barrier. In accordance with the present systems and methods, the pentalayer formed by method 2200 can then be patterned to form Josephson junctions having substantially different critical currents without requiring the Josephson junctions to have substantially different areas.

[0127] Certain aspects of the present systems and methods can be realized at room temperature, and certain aspects can be realized at superconducting temperatures. Thus, throughout this specification and the appended claims, the term "superconducting," when used to describe a physical structure such as a "superconducting metal," is used to indicate a material capable of behaving as a superconductor at appropriate temperatures. A superconducting material does not necessarily have to operate as a superconductor at all times in all embodiments of the present systems and methods.

[0128] The above description of the illustrated embodiments, including those described in the Abstract, is not intended to be exhaustive or to limit the embodiments to the exact form disclosed. Specific embodiments and examples are described herein for illustrative purposes, but various equivalent modifications can be made by those skilled in the art without departing from the spirit and scope of the present disclosure. The teachings provided herein of the various embodiments may be applied to other superconducting circuits and structures, and not necessarily to the exemplary superconducting circuits and structures generally described above.

[0129] The teachings of U.S. Provisional Patent Application No. 61 / 608,379, filed August 3, 2012, and U.S. Provisional Patent Application No. 61 / 714,642, filed October 16, 2012, are incorporated herein by reference in their entireties.

[0130] The various embodiments described above can be combined to provide further embodiments. To the extent not inconsistent with the specific teachings and definitions herein, all U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, and foreign patent applications assigned to D-Wave Systems Inc. that are mentioned in this specification and / or listed in application data sheets are incorporated herein by reference in their entirety. Aspects of the embodiments can be modified as necessary to use the systems, circuits, and concepts of the various patents, applications, and publications to provide further embodiments.

[0131] These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments, along with the full range of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the present disclosure.

Claims

1. 1. A method for forming a trilayer Josephson junction, comprising: depositing a superconducting trilayer including a base electrode layer, an insulating layer, and a counter electrode layer; depositing a photoresist mask pattern over the superconducting trilayer; etching a pattern in the superconducting trilayer to form at least one Josephson junction, the pattern including removing at least two portions of the counter electrode layer to expose at least two portions of the base electrode layer and removing at least two portions of the insulating layer; A method comprising:

2. The step of removing at least two portions of the counter electrode layer comprises: ６ , BCl ３ and Cl ２ and removing at least two portions of the counter electrode layer using a combination of SF ６ , BCl ３ and Cl ２ 2. The method of claim 1, comprising removing at least two portions of the insulating layer using a combination of:

3. 1. A method of forming a superconducting trilayer, comprising: depositing a first layer of niobium; depositing an aluminum oxide layer over at least a portion of the niobium first layer via atomic layer deposition; depositing a second layer of niobium over at least a portion of the aluminum oxide layer; A method comprising:

4. depositing an aluminum layer over at least a portion of the first layer of niobium; depositing the aluminum oxide layer over at least a portion of the aluminum layer; The method of claim 3 further comprising:

5. 1. A method of forming a superconducting tri-layer in a chamber, comprising: depositing a base layer of niobium in the chamber; depositing an aluminum oxide layer in the chamber over at least a portion of the niobium-based layer; filling the chamber with an inert gas to thermalize the niobium base layer and the aluminum oxide layer; pumping the inert gas out of the chamber; depositing a top layer of niobium over at least a portion of the aluminum oxide layer in the chamber; A method comprising:

6. The method of claim 5 , wherein filling the chamber with an inert gas comprises filling the chamber with argon.

7. 1. A method of depositing a protective cap over a Josephson junction, comprising the steps of: depositing a superconducting trilayer including an aluminum oxide layer; patterning the superconducting tri-layer to expose at least a portion of the aluminum oxide layer; pre-cleaning the exposed portion of the aluminum oxide layer; depositing the protective cap over the three layers; A method comprising:

8. The method of claim 7 , wherein pre-cleaning the exposed portion of the aluminum oxide layer comprises pre-cleaning the exposed portion of the aluminum oxide layer with ions.

9. 8. The method of claim 7, wherein pre-cleaning the exposed portions of the aluminum oxide layer comprises pre-cleaning the exposed portions of the aluminum oxide layer via a mild anisotropic low pressure etch.

10. 1. A method for depositing a hybrid dielectric, comprising: depositing a first dielectric layer comprising a first dielectric material; depositing a second dielectric layer over at least a portion of the first dielectric layer, the second dielectric layer comprising a second dielectric material; depositing a third dielectric layer over at least a portion of the second dielectric layer, the third dielectric layer comprising a third dielectric material; A method comprising:

11. The method of claim 10 , wherein depositing a third dielectric material comprises depositing a material of the same type as the first dielectric material.

12. The method of claim 10 , wherein depositing a first dielectric material comprises depositing a non-oxide dielectric.

13. The method of claim 11 , wherein depositing a second dielectric material comprises depositing an oxide dielectric.

14. a first superconducting metal layer; a hybrid dielectric layer overlying the first superconducting metal layer, the hybrid dielectric layer comprising: a first layer of silicon nitride directly overlying the first superconducting metal layer; a layer of silicon oxide directly overlying the first layer of silicon nitride; and a second layer of silicon nitride directly overlying the layer of silicon oxide; a second superconducting metal layer overlying the hybrid dielectric layer, the second superconducting metal layer directly overlying the second layer of silicon nitride of the hybrid dielectric layer; 1. A superconducting integrated circuit comprising:

15. 1. A method of fabricating a superconducting integrated circuit, comprising: depositing a first dielectric layer; depositing a negative photoresist mask over the first dielectric layer, the negative photoresist mask tracing a negative pattern of the desired circuit pattern such that the desired circuit pattern corresponds to areas of the first dielectric layer not directly covered by the negative photoresist mask; etching the desired circuit pattern into the first dielectric layer to create open features in the first dielectric layer; depositing a first superconducting metal layer over the first dielectric layer to at least partially fill the open features in the first dielectric layer; planarizing the first superconducting metal layer; depositing a second dielectric layer to produce a desired inner-layer dielectric thickness, the inner-layer dielectric thickness being controlled by the deposition process; depositing a second superconducting metal layer over the second dielectric layer; A method comprising:

16. 16. The method of claim 15, wherein depositing a first superconducting metal layer comprises depositing the first superconducting metal layer via electroplating.

17. 1. A method of fabricating a superconducting integrated circuit, comprising: patterning the first superconducting metal layer; depositing a first dielectric layer over the first superconducting metal layer; depositing a first negative photoresist mask over the first dielectric layer, the first negative photoresist mask providing a negative of the location of the at least one via such that the location of the at least one via corresponds to an area of ​​the first dielectric layer not directly covered by the first negative photoresist mask; etching the first dielectric layer to create at least one hole corresponding to the at least one via, the at least one hole exposing a portion of the first superconducting metal layer; depositing a second superconducting metal layer over the first dielectric layer to at least partially fill the at least one hole and provide at least a first portion of a first via; planarizing the second superconducting metal layer; depositing a second dielectric layer; depositing a second negative photoresist mask over the second dielectric layer, the second negative photoresist mask tracing a negative of the desired circuit pattern such that the desired circuit pattern corresponds to areas of the second dielectric layer not directly covered by the second negative photoresist mask; etching the desired circuit pattern into the second dielectric layer to create open features in the second dielectric layer; depositing a third negative photoresist mask over the second dielectric layer, the third negative photoresist mask providing a negative of the location of the at least one via such that the location of the at least one via corresponds to an area of ​​the second dielectric layer not directly covered by the third negative photoresist mask, the location of the at least one via being within an open feature of the second dielectric layer; etching the second dielectric layer to create at least one hole corresponding to the at least one via, the at least one hole exposing a portion of the first portion of the first via; depositing a third superconducting metal layer over the second dielectric layer to at least partially fill the at least one hole in the second dielectric layer and to provide a second portion of the first via and to at least partially fill the open feature in the second dielectric layer; planarizing the third superconducting metal layer; A method comprising:

18. 20. The method of claim 17, wherein at least one of depositing the second superconducting metal layer and depositing the third superconducting metal layer comprises electroplating.

19. 20. The method of claim 18, wherein at least one of planarizing the second superconducting metal layer and planarizing the third superconducting metal layer comprises chemical mechanical planarization.

20. 1. A substrate for use in a superconducting integrated circuit, comprising: a base layer comprising silicon; a top layer comprising aluminum oxide; a substrate.

21. 21. The substrate of claim 20, wherein the base layer comprises at least one of undoped silicon, doped silicon, sapphire, and quartz.

22. The substrate of claim 20 , wherein the base layer is thicker than the top layer.

23. 1. A method for depositing a superconducting metal layer in an integrated circuit, comprising: depositing a first portion of the superconducting metal layer; stopping the deposition of the first portion of the superconducting metal layer to prevent excessive heating; cooling the superconducting metal layer; depositing a second portion of the superconducting metal layer over the first portion of the superconducting metal layer; A method comprising:

24. stopping the deposition of the second portion of the superconducting metal layer to prevent excessive heating; cooling the superconducting metal layer; depositing a third portion of the superconducting metal layer over the second portion of the superconducting metal layer; 24. The method of claim 23, further comprising:

25. 1. A method for aligning multiple layers in a multi-layer superconducting integrated circuit, comprising: patterning the first superconducting metal layer to include at least one alignment mark; depositing a first dielectric layer over the first superconducting metal layer; patterning the first dielectric layer to expose the at least one alignment mark; depositing a second superconducting metal layer over the first dielectric layer such that an imprint of the at least one alignment mark is formed on an exposed surface of the second superconducting metal layer; aligning a photoresist mask to the inscription of the at least one alignment mark on the second superconducting metal layer; A method comprising:

26. depositing the photoresist mask over the second superconducting metal layer.

26. The method of claim 25, further comprising:

27. 1. A method of fabricating a superconducting integrated circuit, comprising: depositing a first superconducting metal layer; depositing a superconducting protective capping layer over the first superconducting metal layer; patterning both the first superconducting metal layer and the superconducting protective capping layer covering the first superconducting metal layer; depositing a dielectric layer over the patterned superconducting protective capping layer; etching a hole through the dielectric layer to expose a portion of at least one of the superconducting protective capping layer or the first superconducting metallic layer; depositing a second superconducting metal layer over the dielectric layer such that at least a portion of the second superconducting metal layer at least partially fills the hole through the dielectric layer and forms a superconducting electrical connection with at least one of the superconducting protective capping layer or the first superconducting metal layer; A method comprising:

28. 30. The method of claim 27, wherein depositing a superconducting protective capping layer over the first superconducting metal layer comprises depositing a titanium nitride layer over the first superconducting metal layer.

29. a first patterned superconducting metal layer; a superconducting protection capping layer disposed over the first patterned superconducting metal layer, the superconducting protection capping layer being patterned to match the pattern of the first patterned superconducting metal layer; a dielectric layer disposed over the superconducting protective capping layer; a second patterned superconducting metal layer disposed over the dielectric layer; a superconducting via extending through the dielectric layer and superconductively electrically coupling a portion of the second patterned superconducting metal layer with at least one of a portion of the superconducting protection capping layer or a portion of the first superconducting metal layer; 1. A superconducting integrated circuit comprising:

30. 30. The superconducting integrated circuit of claim 29, wherein the superconducting protective capping layer comprises titanium nitride.

31. 1. A method of fabricating a Josephson junction pentalayer, comprising the steps of: depositing a first superconducting metal layer; depositing a first insulating barrier over the first superconducting metal layer, the first insulating barrier having a first thickness; depositing a second superconducting metal layer over the first insulating barrier; depositing a second insulating barrier over the second superconducting metal layer, the second insulating barrier having a second thickness different from the first thickness of the first insulating barrier; depositing a third superconducting metal layer over the second insulating barrier; A method comprising:

32. 32. The method of claim 31 , comprising: depositing a second insulating barrier over the second superconducting metal layer, the second insulating barrier having a second thickness different from the first thickness of the first insulating barrier; depositing a second insulating barrier over the second superconducting metal layer, the second insulating barrier having a second thickness greater than the first thickness of the first insulating barrier.

33. 1. A superconducting integrated circuit, comprising: A five-layer Josephson junction, a first superconducting metal layer; a first insulating barrier having a first thickness disposed over the first superconducting metal layer; a second superconducting metal layer disposed over the first insulating barrier; a second insulating barrier having a second thickness disposed over the second superconducting metal layer; and a third superconducting metal layer disposed over the second insulating barrier; a Josephson junction five-layer structure including: a dielectric layer disposed over the five Josephson junction layers; a superconducting wiring layer disposed over the dielectric layer; at least one superconducting via that superconductively and electrically couples at least a portion of the superconducting wiring layer with at least a portion of the Josephson junction five-layer; 1. A superconducting integrated circuit comprising:

34. 34. The superconducting integrated circuit of claim 33, wherein the second thickness of the second insulating barrier is greater than the first thickness of the first insulating barrier.

35. At least a first portion of the Josephson junction pentalayer is a first portion of the third superconducting metal layer; a first portion of the second insulating barrier; a first portion of the second superconducting metal layer; a first portion of the first insulating barrier; a first portion of the first superconducting metal layer; wherein at least one superconducting via is capable of superconductively electrically coupling a first portion of the second superconducting wiring layer to the first portion of the third superconducting metal layer.

34. The superconducting integrated circuit of claim 33, patterned to form:

36. At least a second portion of the Josephson junction pentalayer is a second portion of the second superconducting metal layer; and a second portion of the first insulating barrier; a second portion of the first superconducting metal layer; and wherein at least one superconducting via is capable of superconductively electrically coupling a second portion of the second superconducting wiring layer to the second portion of the second superconducting metal layer.

36. The superconducting integrated circuit of claim 35, patterned to form

37. At least a first portion of the Josephson junction pentalayer is a first portion of the second superconducting metal layer; a first portion of the first insulating barrier; a first portion of the first superconducting metal layer; 34. The superconducting integrated circuit of claim 33, wherein at least one superconducting via is patterned to form a first Josephson junction capable of superconductively electrically coupling a first portion of the second superconducting wiring layer with the first portion of the second superconducting metal layer.

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