Micro LED and method of manufacturing the same

Abstract

Conventional LED fabrication techniques have not been satisfactory in producing high quality micro-LEDs.SOLUTION: A method of fabricating a micro-LED, comprising forming an n-doped connection layer of a III-nitride material over a porous region of the III-nitride material, forming an electrically insulating mask layer over the n-doped connection layer, removing a portion of the mask to expose an exposed region of the n-doped connection layer, and forming a LED structure over the exposed region of the n-doped connection layer; Wherein the step of forming the LED structure comprises forming an n-doped portion, a p-doped portion, and a light emitting region disposed between the n-doped portion and the p-doped portion on the exposed region of the n-doped connection layer, wherein the light emitting region comprises one or more III-nitride light emitting layers, and wherein the or each light emitting layer comprises a nanostructure layer comprising fragmented or discontinuous quantum wells.SELECTED DRAWING: Figure 11-13

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices and methods for manufacturing semiconductor devices, and in particular to micro LEDs and improved methods for manufacturing micro LEDs. [Background technology]

[0002] Standard light-emitting diodes (LEDs) used for emitting light are usually larger than 200 μm x 200 μm. Micro-LEDs are highly dense arrays of micro-scale LEDs with lateral dimensions of less than 100 μm x 100 μm. Micro-LEDs can therefore be defined as LED structures with lateral dimensions (length and width) smaller than 100 μm x 100 μm, down to tens of nanometers and even smaller.

[0003] Previous attempts have been made to fabricate micro-LEDs using known techniques, such as conventional LED epitaxy and laser lift-off, electrostatic carry, and elastomer stamping for transfer. However, there are several challenges in applying this technology to devices as small as micro-LEDs.

[0004] These issues include: -It is difficult to produce all three primary colors (RGB) on the same micro LED chip using conventional LED epitaxy. -Green and red micro LEDs have low efficiency. Dry etching is always required to define the LED mesas at a micro-scale. As LED sizes decrease, plasma damage to the sidewalls of the LED structure affects the device's luminous efficiency and lifetime. -Laser lift-off has low yield and high cost. -Low yields in transfer due to pre-existing distortion / warpage issues.

[0005] Due to these issues, conventional LED manufacturing techniques are not satisfactory for producing high-quality micro-LEDs. Summary of the Invention

[0006] The present application relates to an improved method for manufacturing micro LEDs and to micro LEDs produced using this method. The invention is defined in the independent claims, to which reference is now made. Preferred or advantageous features of the invention are set out in the dependent claims.

[0007] The micro LEDs are preferably made from III-V semiconductor materials, and particularly preferably from III-nitride semiconductor materials.

[0008] "III-V" semiconductors include binary, ternary, and quaternary alloys of group III elements such as Ga, Al, and In, and group V elements such as N, P, As, and Sb, and are important in many applications, including optoelectronics.

[0009] Of particular importance is the class of semiconductor materials known as "III-nitride" materials, which include gallium nitride (GaN), indium nitride (InN), aluminum nitride (AlN), and their ternary and quaternary alloys. III-nitride materials have not only enjoyed commercial success in solid-state lighting and power electronics, but also have particular advantages in quantum light sources and light-matter interactions.

[0010] Although a variety of group III nitride materials are of commercial interest, gallium nitride (GaN) is widely recognized as one of the most important new semiconductor materials and is of particular importance in many application areas.

[0011] The introduction of pores into bulk GaN is known to have a significant effect on the material's properties, such as the refractive index, and therefore, by varying the porosity of GaN, its optical properties may be tuned, making porous GaN of great interest for optoelectronic applications.

[0012] Although the invention is described with reference to GaN, it also applies advantageously to alternative III-nitride materials.

[0013] Prior publications relating to the porosification of III-V semiconductor materials include International Patent Application No. PCT / GB2017 / 052895 (published as WO 2019 / 063957) and PCT / GB2019 / 050213 (published as WO 2019 / 145728).

[0014] The inventors have found that the present invention can be used to advantage to provide micro LEDs and arrays of micro LEDs.

[0015] (Micro LED manufacturing method) According to a first aspect of the present invention, there is provided a method for manufacturing a micro LED, the method comprising the steps of: forming an n-doped contact layer of III-nitride material over the porous region of III-nitride material; forming an electrically insulating mask layer on the n-doped connection layer; removing a portion of the mask to expose an exposed area of ​​the n-doped connection layer; forming an LED structure on the exposed area of ​​the n-doped connection layer; Includes:

[0016] Forming an electrically insulating (dielectric) mask layer and then removing portions of the mask to expose exposed regions of the n-doped contact layer creates a template or "footprint" upon which the LED structure of the micro LED can be formed. The size and shape of the exposed regions are controlled by controlling the size and shape of the portions removed from the mask. Subsequent layers of semiconductor material can then be deposited onto the exposed regions to form the LED structure. Controlling the size and shape of the exposed regions allows for control of the lateral size (length and width) and shape of the subsequently formed LED structure. This size control is particularly advantageous for growing micro LED structures with very small lateral dimensions.

[0017] Prior art techniques involve growing a large-scale LED structure and then cutting the structure into microscale platforms or "mesas" of desired lateral size and separating them into micro-LEDs by etching trenches. In micro-LEDs fabricated using such prior art techniques, etching damage to the sidewalls of the LED structure has a significant effect on the extremely small pixels formed by the micro-LEDs. This can adversely affect the reliability and brightness of the micro-LEDs.

[0018] The method of the present invention advantageously forms the LED structure of a micro LED in a predefined exposed area having the proper size and shape to form the micro LED. In the present invention, the exposed area controls the footprint of the LED structure, so the LED structure can be advantageously formed to the proper size from the beginning. Therefore, the LED structure of the present invention does not need to be etched to reduce its lateral size. Therefore, the resulting micro LED avoids the dry etching damage that occurs in prior art methods.

[0019] Due to the avoidance of dry etching damage to the active layer of the micro-LED, micro-LEDs fabricated using this method have the advantages of being highly reliable and bright, significantly superior to micro-LEDs prepared using conventional techniques.

[0020] Another advantage of the present invention is that even for extremely small micro LED structures, only a few microns in size, an electrical n-contact can be easily made to the n-doped portion of the LED structure by simply removing an additional portion of the electrically insulating mask layer to expose a second exposed area on the n-doped connection layer and depositing a conductive contact on this second exposed area.

[0021] The step of forming the LED structure includes growing the LED structure according to conventional methods in the art. That is, the LED structure can be grown using known semiconductor deposition techniques and can have various conventional LED epitaxial layers. While a typical LED structure is described herein as an example, those skilled in the art will recognize that various LED structures (including various combinations of layer thicknesses, materials, and doping levels) are known in the art and can be used in the present invention. However, in the present invention, the LED structure is formed, grown, or deposited only on one or more exposed regions of the n-doped connection layer.

[0022] The step of forming the LED structure preferably includes depositing on the exposed area of ​​the n-doped connection layer: an n-doped portion; a p-doped portion; a light emitting region disposed between the n-doped portion and the p-doped portion; This includes forming a

[0023] A method for fabricating a micro LED includes, as a first step, electrochemically porosifying a layer of III-nitride material to form a porous region of III-nitride material. This is achieved using a wafer-scale porosification process, as described in International Patent Applications PCT / GB2017 / 052895 (published as WO 2019 / 063957) and PCT / GB2019 / 050213 (published as WO 2019 / 145728). This step should be performed before forming an n-doped connection layer of III-nitride material on the porous region, so that the connection layer is not electrochemically porosified.

[0024] The method preferably includes the step of forming a porous region of III-nitride material by electrochemical porosification through a non-porous layer of III-nitride material, such that the non-porous layer of III-nitride material forms a non-porous intermediate layer, which can advantageously provide a smooth surface for the growth of a connecting layer, such that the intermediate layer is disposed between the porous region and the n-doped III-nitride connecting layer.

[0025] The porous region is formed by porosifying one or more layers or regions of III-nitride material on a substrate. The substrate can be silicon, sapphire, SiC, or β-Ga2O3. The crystal orientation of the substrate can be polar, semipolar, or nonpolar. The thickness of the substrate typically ranges from 100 μm to 1500 μm.

[0026] The porous region can be a porous layer, whereby the method includes forming an n-doped connecting layer of III-nitride material on the porous layer of III-nitride material. Preferably, the porous region is a continuously porous porous layer, for example formed from a continuous layer of porous III-nitride material.

[0027] The porous region can include multiple porous layers and, optionally, multiple non-porous layers. In a preferred embodiment of the present invention, the porous region is a stack of alternating porous and non-porous layers, with a top surface of the stack defining the top of the porous region and a bottom surface of the stack defining the bottom of the porous region. An n-doped connection layer of III-nitride material is formed over the porous region comprising the stack of porous layers of III-nitride material.

[0028] Alternatively, the porous region is a layer of III-nitride material that includes one or more porous regions, for example, one or more porous regions within a non-porous layer of III-nitride material.

[0029] In a preferred embodiment, the porous region or layer has a lateral dimension (width or length) comparable to the substrate on which the porous layer or region is grown. Conventional substrate wafer sizes can vary in size, for example, 1 cm. 2 , or 2 inches, 4 inches, 6 inches, 8 inches, 12 inches, or 16 inches in diameter. However, it is also possible to form small porous regions that do not extend across the entire substrate by patterning one or more layers and / or depositing regions of different charge carrier concentrations within the same layer. Thus, the lateral dimensions of the porous layer or region may vary from about one-tenth of a pixel (e.g., 0.1 μm) to the lateral dimensions of the substrate itself.

[0030] On the substrate, one or a stack of layers of n-doped III-nitride semiconductor material is grown. The III-nitride layers contain one or several combinations of the elements Al, Ga, and In (ternary layers, quaternary layers). The thickness of the III-nitride stack is preferably between 10 and 4000 nm. The III-nitride layers are preferably between 1×10 17 cm -3 ~5×10 20 cm -3 The doping concentration is

[0031] Preferably, an intermediate layer of undoped III-nitride material is deposited on the doped material before porosifying the doped material. The thickness of the intermediate layer is preferably 1 nm to 3000 nm, preferably 5 nm to 2000 nm.

[0032] In a preferred embodiment, the doped region is composed of a stack of alternating layers of highly doped and lightly doped zones. The stack can be composed of pairs of highly / lowly doped zones, preferably containing 5 to 50 pairs of layers. The thickness of each highly doped layer varies between 10 nm and 200 nm, and the thickness of each lightly doped layer varies between 5 and 180 nm.

[0033] As is known in the art, electrochemical porosification removes material from n-type doped regions of III-nitride materials, creating empty pores in the semiconductor material.

[0034] In a preferred embodiment, the n-doped connection layer of III-nitride material is formed on a stack of multiple porous layers of III-nitride material, so that the porous region is not a single porous layer of III-nitride material, but rather a stack of multiple layers of III-nitride material, at least some of which are porous.

[0035] The stack of porous layers is preferably a stack of alternating porous and non-porous layers. Preferably, the stack includes 5 to 50 pairs of porous and non-porous layers stacked one on top of the other. The porous layers preferably have a thickness of 10 nm to 200 nm, and the non-porous layers preferably have a thickness of 5 nm to 180 nm.

[0036] The porous region or each porous layer within the porous region is porous to a porosity of 1% to 99%. Preferably, the porous region or each porous layer within the stack is porous to a porosity of 10% to 90%.

[0037] In a particularly preferred embodiment, the porous layer stack comprises a porous Distributed Bragg Reflector (DBR), whereby the method includes forming an n-doped connecting layer of III-nitride material on a porous DBR of III-nitride material. The porous DBR is formed from a stack of alternating porous / non-porous layers, with different porosities between adjacent layers, resulting in refractive index differences between adjacent layers.

[0038] By controlling the thickness of the stack of alternating porous and non-porous layers of III-nitride materials and the porosity of the porous layers, the optical properties of the DBR can be controlled to reflect specific wavelengths of light.

[0039] In a first preferred embodiment, the DBR is configured to reflect light at the emission wavelength of the LED structure, meaning that light emitted from the LED structure in the direction of the DBR is reflected back, thereby increasing the amount of light emitted from the micro LED in the intended direction, which advantageously increases the brightness of the micro LED.

[0040] In a second preferred embodiment, the DBR can be configured to transmit light at the emission wavelength of the LED structure while blocking the transmission of other wavelengths of light. The micro LED can be configured such that the direction of light emission of the device is through the DBR, so that the DBR acts as an optical filter through which light emitted by the LED structure must pass to exit the device. Thus, the DBR can advantageously prevent the transmission of undesired wavelengths from the LED device.

[0041] DBRs can be advantageously configured to provide greater than 90% reflection or transmission for light of a desired wavelength. By varying the layer structure and thickness of the DBR, the reflectance or transmission characteristics of the DBR can be tailored for different wavelengths. For example, the reflectance / transmission of a DBR can be tailored to provide greater than 90% reflection / transmission for blue light up to 450 nm, or green light (520-540 nm), or red light (615-640 nm).

[0042] An n-doped connecting layer of III-nitride material is grown over this region, preferably by deposition onto a non-porous intermediate layer.

[0043] The n-doped connection layer of III-nitride material preferably has a thickness of 200 nm to 2000 nm. The n-doped connection layer of III-nitride material preferably has a dopant concentration of at least 1×10 18 cm -3 has an n-type charge carrier concentration of

[0044] The mask layer is preferably formed by depositing a dielectric material layer on the n-doped connection layer of III-nitride material. The mask layer is preferably deposited on the entire surface of the n-doped connection layer of III-nitride material, so that the connection layer is completely covered with the dielectric material. The mask layer may be formed of SiO2, SiN, SiON, AlO x , or any other suitable dielectric material.

[0045] The thickness of the mask layer is 5 nm to 1000 nm, preferably 200 nm to 800 nm, and particularly preferably 400 nm to 600 nm.

[0046] Deposition of the mask layer can be performed by conventional deposition methods such as plasma-enhanced chemical vapor deposition (PECVD), sputtering, atomic layer deposition (ALD), evaporation, or in-situ metalorganic chemical vapor deposition (MOCVD).

[0047] Standard lithographic techniques can be used to remove portions of the mask layer to form one or more openings in the non-conductive mask layer that expose areas of the n-doped contact layer underneath. Removing portions of the mask layer can include wet etching or dry etching, such as inductively coupled plasma (ICP) dry etching (RIE).

[0048] The lateral size (length and width of the opening through the mask layer) and shape of the exposed region(s) controls the lateral size and shape of the LED structure grown in the exposed region.

[0049] The exposed region or regions of the connecting layer can be formed in any desired shape, controlled by patterning and lithographically removing portions of the mask layer, for example, the exposed region can be circular, square, rectangular, hexagonal, or triangular in shape.

[0050] The size of the exposed region should be the size of the micro LED. For example, the width and / or length of the exposed region (or diameter if the exposed region is circular) is 0.05 μm to 100 μm, preferably 0.05 μm to 30 μm, and particularly preferably less than 10 μm, for example 0.1 μm to 10 μm or 0.5 μm to 10 μm. In preferred embodiments, the length, width, or diameter of the exposed region is less than 50 μm, or 40 μm, or 30 μm, or 20 μm, or less than 10 μm. Particularly preferably, the exposed region has a width or diameter less than 10 μm, so that LED structures grown within the exposed region form micro LED pixels with a size less than 10 μm.

[0051] Once the exposed areas of the n-doped contact layer are formed in the dielectric mask layer, an LED structure can be grown in the exposed areas to contact the n-doped contact layer.

[0052] The lateral dimensions of the LED structure, including the n-doped portion, the light-emitting region, and the p-doped portion, are preferably the same as those of the exposed region, since the LED structure is grown in the exposed region and inherits the lateral size of the exposed region, which means that micro LEDs can be grown to a suitable size without requiring an etching step to reduce the lateral dimensions of the LED structure.

[0053] Taking advantage of the present invention, a variety of LED structures can be grown within the exposed region. All such LED structures typically include an n-doped portion, a light-emitting region, and a p-doped portion, and optionally include additional layers of semiconductor material typical in LED epitaxy. Exemplary LED structures suitable for use with the present invention are described below.

[0054] In a preferred embodiment, the n-doped portion of the LED structure is grown on the exposed areas of the connection layer in direct contact with the n-doped connection layer.

[0055] The n-doped portion may comprise a first n-doped layer of a III-nitride material, preferably having a thickness of 0.2 μm to 3 μm and a density of at least 1×1019 cm -3 has an n-type doping concentration of

[0056] The n-doped portion includes a second n-doped layer of III-nitride material on the first n-doped layer. The second n-doped layer includes an indium-containing III-nitride layer, a stack of thin III-nitride layers with or without indium, or a bulk III-nitride layer or a stack of III-nitride layers with varying atomic percentages of indium within the layer or stack. For example, the n-doped region can be an n-GaN layer or an n-InGaN layer, or a stack of alternating n-GaN / n-InGaN layers, or a stack of alternating n-InGaN / n-InGaN layers with different amounts of indium in each layer.

[0057] The indium atomic percentage of the second n-doped layer ranges between 0.5 and 25%. The total thickness of the second n-doped layer ranges between 2 nm and 200 nm. If the second n-doped layer comprises a stack of layers, the thickness of each individual layer in the stack preferably ranges between 1 and 40 nm.

[0058] The second n-doped layer of III-nitride material is 1×10 17 cm -3 ~5×10 20 cm -3 has an n-type doping concentration of

[0059] The n-type portion of the LED structure is grown in the exposed area, and then the light emitting region of the LED is grown on top of the n-type portion.

[0060] The light emitting region includes one or more III-nitride light emitting layers, preferably indium gallium nitride (InGaN) light emitting layers, and the or each light emitting layer preferably includes a quantum well or a nanostructured layer including quantum structures such as quantum dots, fractional or discontinuous quantum wells.

[0061] The or each light-emitting layer preferably comprises a III-nitride material having an atomic indium content of 10-40%. The indium content of the light-emitting layer is selected at different levels depending on the desired emission wavelength. In preferred embodiments, the indium content of the light-emitting layer is 12-18%, preferably greater than 13%, or 20-30%, preferably greater than 22%, or 30-40%, preferably greater than 33%.

[0062] One or more light-emitting layers have the composition In x Ga 1-x N, where 0.10≦x≦0.40, preferably 0.12≦x≦0.18, or 0.20≦x≦0.30, or 0.30≦x≦0.40.

[0063] In a preferred embodiment, the light emitting region comprises one or more InGaN quantum wells, preferably 1 to 7 quantum wells, with the thickness of each quantum well varying between 1.5 and 8 nm.

[0064] The quantum wells may or may not be covered with a thin (0.5-3 nm) III-nitride layer.

[0065] III-nitride barrier layers contain one or several combinations of the elements Al, Ga, In (ternary or quaternary layers).

[0066] The quantum wells and barriers of the light-emitting region are preferably grown within a temperature range of 600 to 800°C.

[0067] The LED structure includes a cap layer of III-nitride material between the quantum well and the p-doped portion, preferably the cap layer is undoped and has a thickness of 5 nm to 30 nm.

[0068] The p-doped portion is grown above the light emitting region and includes a p-doped group III nitride layer and a p-doped aluminum gallium nitride layer disposed between the p-doped group III nitride layer and the light emitting region. The p-doped aluminum gallium nitride layer is an electron blocking layer (EBL) located between the cap layer and the p-type layer. This electron blocking layer contains 5 to 25 at % aluminum and is preferably 10 to 100 nm thick.

[0069] The p-doped group III nitride layer is preferably 5×10 18 cm -3 ~8×10 20 cm -3 The p-doped III-nitride layer contains In and Ga and is 20-200 nm thick, preferably 50-100 nm thick. The doping concentration varies within this layer, with a spike in doping level in the last 10-30 nm of the layer. To activate the Mg acceptors, the structure is annealed in an MOCVD reactor or annealing oven. The annealing temperature ranges from 700-850°C in an N2 or N2 / O2 ambient.

[0070] Because both the EBL and the p-doped layer are p-type doped, these layers can be referred to as p-doped regions.

[0071] After forming the n-doped portion and the light-emitting region and p-doped portion, the method includes depositing one or more passivation layers over the LED structure and the electrically insulating mask layer. The passivation layers are formed from a dielectric material and cover the surface and sidewalls of the LED structure as well as the mask layer. The first passivation layer deposited is, for example, Al2O3 (10-100 nm thick layer) (deposited by atomic layer deposition), followed by deposition of SiO2, SiN, or SiON (50-300 nm thick layer) by sputtering or plasma-enhanced chemical vapor deposition. The Al2O3 is deposited at 50-150°C, and the SiO2, SiN, and SiON are deposited at 250-350°C. The sputtering process can be performed at room temperature.

[0072] The method further includes removing a first portion of the passivation layer, forming an electrical connection to the p-doped portion, removing a second portion of the passivation region and a second portion of the mask to expose a second exposed region of the n-doped connection layer, and forming an electrical contact to the second exposed region of the n-doped connection layer. The portions of the passivation layer and the dielectric mask layer may be removed by a wet etch, a dry etch, or a combination of both. The wet etch buffered oxide etch may use diluted hydrofluoric acid, phosphoric acid, or a mixture thereof.

[0073] These steps are performed sequentially. For example, the method includes removing a first portion of the passivation layer and forming an electrical contact with the p-doped portion. In a preferred embodiment, a transparent conductive layer can be used to form a p-contact with the p-doped layer of the LED structure, and at least a portion of the transparent conductive layer is covered with a metal contact. The metal contact can be a combination of nickel, titanium, platinum, and gold. The transparent conductive layer can be 20 to 250 nm thick.

[0074] The method includes removing a second portion of the mask, and optionally removing a second portion of the passivation layer to expose a second exposed region of the n-doped connecting layer, and further includes forming an electrical contact on the second exposed region of the n-doped connecting layer by depositing a metal contact on the second exposed region of the n-doped connecting layer. The metal contact can be, for example, a combination of titanium, platinum, and gold.

[0075] (Preferred embodiment) In a preferred embodiment, the method for fabricating a micro LED comprises the following steps:

[0076] Step 1: GaN layers with different charge carrier densities are alternately deposited on a substrate, and then a distributed Bragg reflector (DBR) is formed on the substrate using a porosification technique, as described in International Patent Application No. PCT / GB2017 / 052895.

[0077] Step 2 Grow an n-(Al,In)GaN layer (eg, highly doped n-type (Al,In)GaN such as n-GaN, n-AlGaN, or n-InGaN) on top of the porosified DBR.

[0078] Step 3: Deposit a layer of dielectric material, such as SiO2, on the top surface of the n-GaN.

[0079] Step 4: The dielectric material is patterned by lithography, nanoimprinting, or other suitable techniques, and then portions of the dielectric layer are removed by wet chemical etching or dry etching processes. Removing the portions of the dielectric layer exposes portions of the n-GaN underneath. The area from which the dielectric is removed is the shape and size of the micro LED, e.g., 100 μm x 100 μm or smaller.

[0080] Step 5: A quantum well (QW) active light-emitting region (which may include multiple quantum wells) is deposited on the exposed portion of the n-(Al,In)GaN. The quantum wells can be InGaN, AlGaN, InN, InAlN, or AlInGaN, and the quantum barriers surrounding the quantum well layers can be GaN, AlN, AlGaN, AlInGaN, or InAlN. The structure and function of the quantum wells are defined in International Patent Application No. PCT / GB2019 / 050213. The lateral dimensions of the QWs are the same as the exposed portion of the n-(Al,In)GaN. This means that the QW region is the desired size for micro-LEDs.

[0081] Step 6: A p-(Al,In)GaN layer (highly doped p-type (Al,In)GaN) is deposited on top of the quantum well region. The lateral dimensions of the p-GaN layer are the same as those of the QWs, and also the exposed n-GaN. Thus, the p-GaN and QWs form a stack with the desired lateral dimensions for a micro-LED.

[0082] Step 7: Deposit a second layer of dielectric material, such as SiO2, on top of the first layer of dielectric, covering the edges or sidewalls of the QWs and the p-(Al,In)GaN layer. This second layer of dielectric material is a passivation layer.

[0083] Step 8 Form an electrical p-contact on the p-(Al,In)GaN, making electrical contact with the p-(Al,In)GaN layer.

[0084] Step 9 Remove a portion of the dielectric layer by wet chemical etching or dry etching process to expose a portion of the n-(Al,In)GaN layer.

[0085] Step 10 Deposit an electrical n-contact on the exposed portion of the n-(Al,In)GaN, the n-contact making electrical contact with the n-(Al,In)GaN.

[0086] Step 11 The second layer of SiO2 is passivated by known techniques. A plasma etch is used for chip singulation and transfer.

[0087] This method prevents the active QW and p-(Al,In)GaN layers of the micro-LED from any dry etching damage, and the n-contact can be fabricated very easily.

[0088] The avoidance of dry etching damage to the active layers of the micro-LEDs provides significant advantages over micro-LEDs prepared using conventional techniques, where etching damage to the sidewalls of the p-GaN and QW layers has a significant effect on the small pixels formed by the micro-LEDs, which is detrimental to the reliability and brightness of the micro-LEDs.

[0089] Micro LEDs fabricated using this method are free from plasma etching damage to the sidewalls of the LED stack, offering advantages in reliability and brightness.

[0090] Layers of the semiconductor structure can be made porous, if desired, by electrochemical etching, as described in International Patent Applications PCT / GB2017 / 052895 (published as WO 2019 / 063957) and PCT / GB2019 / 050213 (published as WO 2019 / 145728).

[0091] The above-described method relates to the construction of a p-side light-emitting LED.

[0092] Fabricating n-side light-emitting microLEDs can be done in a similar way by incorporating a "flip-chip" step to bond the microLED to a silicon CMOS backplane.

[0093] SiO2 is one example of a suitable dielectric for masking and passivation, although other dielectrics may be used instead.

[0094] The semiconductor material layers can be deposited by epitaxial growth, such as by molecular beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD) (also known as metalorganic vapor phase epitaxy (MOVPE)), hydride vapor phase epitaxy (HVPE), ammonothermal processes, or other conventional methods suitable for growing III-nitride materials.

[0095] (Micro LED array manufacturing) According to a second aspect of the present invention, there is provided a method for manufacturing an array of micro LEDs, the method comprising: forming an n-doped contact layer of III-nitride material over the porous region of III-nitride material; forming an electrically insulating mask layer on the n-doped III-nitride layer; removing portions of the mask to expose an array of exposed areas of the n-doped contact layer; forming an LED structure on each exposed region of the n-doped connection layer; Includes:

[0096] A method for manufacturing an array of micro LEDs preferably includes the method of the first aspect, which comprises forming a plurality of exposed areas in an n-doped connection layer and forming a plurality of LED structures in these exposed areas. By removing portions of the mask layer to expose the array of exposed areas, the layout of the micro LED array is designed to provide a desired size and density of pixels formed by the micro LEDs.

[0097] An array of micro LEDs is advantageously formed on a single substrate, and multiple LED structures can be formed simultaneously using a deposition step that simultaneously deposits a layer of semiconductor material on each exposed area of ​​the connection layer.

[0098] Using this method, an array of micro LEDs can be formed without requiring an etching step to cut the LED structure to the desired lateral dimensions for the individual pixels, thus avoiding any etching damage to the sidewalls of the LED structure.

[0099] The method of the second aspect advantageously includes all of the features described above in relation to the first aspect of the invention.

[0100] (Micro LED) Another aspect of the present invention relates to a micro LED fabricated by the above-described method.

[0101] According to a third aspect of the present invention, there is provided a micro LED, comprising: an n-doped contact layer of III-nitride material over the porous region of III-nitride material; an electrically insulating mask layer on the n-doped group III nitride layer; an LED structure; At least a portion of the LED structure extends through a gap in the electrically insulating mask layer and contacts the n-doped contact layer.

[0102] The micro LED is preferably a micro LED manufactured using the method described above in relation to the first aspect of the invention.

[0103] The porous region can be a single porous layer, whereby the method includes forming an n-doped interconnect layer of III-nitride material on the porous layer of III-nitride material. In some embodiments, the porous region includes multiple porous layers, and optionally multiple non-porous layers. In a preferred embodiment of the invention, the porous region is a stack of alternating porous and non-porous layers, with a top surface of the stack defining the top of the porous region and a bottom surface of the stack defining the bottom of the porous region. The n-doped interconnect layer of III-nitride material is formed on the porous region including the stack of porous layers of III-nitride material.

[0104] In a preferred embodiment, the n-doped connection layer of III-nitride material is disposed on a stack of multiple porous layers of III-nitride material, so that the porous region is not a single porous layer of III-nitride material, but rather a stack of multiple layers of III-nitride material, at least some of which are porous.

[0105] The porous layer stack is preferably a stack of alternating porous and non-porous layers. Preferably, the stack includes 5 to 50 pairs of alternating porous and non-porous layers. The porous layers preferably have a thickness of 10 nm to 200 nm, and the non-porous layers preferably have a thickness of 5 nm to 180 nm.

[0106] Preferably, the porous region or each porous layer in the stack has a porosity of between 10% and 90%.

[0107] The micro LED preferably includes a non-porous intermediate layer of III-nitride material porous region between the porous region and the n-doped III-nitride interconnect layer. Preferably, the porous region is formed by electrochemical porosification through the non-porous layer of III-nitride material, using the methods of PCT / GB2017 / 052895 (published as WO 2019 / 063957) and PCT / GB2019 / 050213 (published as WO 2019 / 145728). Thus, the non-porous layer of III-nitride material typically forms a non-porous intermediate layer that remains on top of the porous region. The non-porous intermediate layer advantageously provides a smooth surface for growing the interconnect layer during fabrication.

[0108] In a particularly preferred embodiment, the porous layer stack includes a porous distributed Bragg reflector (DBR), where an n-doped connecting layer of III-nitride material is disposed on top of a porous DBR of III-nitride material. The porous DBR is formed from a stack of alternating porous / non-porous layers, with adjacent layers having different porosities, thereby creating refractive index differences between the adjacent layers.

[0109] The micro LED has an intermediate layer made of a non-porous III-nitride material between the porous region and the connection layer, and the thickness of the intermediate layer is preferably 1 nm to 3000 nm, and more preferably 5 nm to 2000 nm.

[0110] The n-doped connection layer of III-nitride material preferably has a thickness of 200 nm to 2000 nm. The n-doped connection layer of III-nitride material preferably has a dopant concentration of at least 1×10 18 cm -3 has an n-type charge carrier concentration of

[0111] The mask layer preferably extends over the entire surface of the n-doped contact layer of III-nitride material, so that the contact layer is completely covered with a dielectric material, except for the LED structure. The mask layer may be SiO2, SiN, SiON, AlO x , or other suitable dielectric material.

[0112] The thickness of the mask layer is 5 nm to 1000 nm, preferably 200 nm to 800 nm, and particularly preferably 400 nm to 600 nm.

[0113] The LED structure can have any desired shape because the footprint of the LED structure can be controlled during fabrication by patterning and lithographically removing portions of the mask layer. For example, the footprint (in plan view) of the LED structure can be circular, square, rectangular, hexagonal, or triangular.

[0114] The LED structure has lateral dimensions that classify it as a "micro LED." For example, the width and / or length of the LED structure (or diameter if the LED is circular) can be 0.05 μm to 100 μm, preferably 0.05 μm to 30 μm, and particularly preferably less than 10 μm, for example 0.1 μm to 10 μm or 0.5 μm to 10 μm. In preferred embodiments, the length, width, or diameter of the LED structure is less than 50 μm, or 40 μm, or 30 μm, or 20 μm, or less than 10 μm. Particularly preferably, the LED structure can have a width or diameter less than 10 μm, so that the LED structure forms a micro LED pixel with a size less than 10 μm.

[0115] The LED structure is an n-doped portion; a p-doped portion; a light emitting region disposed between the n-doped portion and the p-doped portion; Equipped with.

[0116] Preferably, at least a portion of the LED structure extends through the electrically insulating dielectric mask layer so that the LED structure is in electrical contact with the n-doped contact layer.

[0117] As described above with respect to the first aspect of the invention, the LED structure can take a variety of different forms, with layers of different thicknesses, compositions, and charge carrier concentrations.

[0118] The features of the micro LEDs described above with respect to the first aspect of the present invention apply equally to the micro LEDs of the third aspect.

[0119] The micro LED includes a porous DBR.

[0120] The microLED includes an active layer that is a quantum well or quantum layer (e.g., a porous quantum well that includes multiple 3D quantum structures), where the quantum well is InGaN, AlGaN, InN, InAlN, or AlInGaN, and the quantum barriers surrounding the quantum well layer are GaN, AlN, AlGaN, AlInGaN, or InAlN.

[0121] Micro LEDs have lateral dimensions (length and width) smaller than 100 μm x 100 μm, and can be tens of nanometers or even smaller. The "height" of an LED in this context is the dimension in the intended direction of light emission.

[0122] The micro LED preferably includes an active layer (which may be a quantum well) and a p-GaN layer, the sidewalls of which are preferably covered with a dielectric material such as SiO2.

[0123] The micro-LED preferably includes a first layer of dielectric material and a second "passivation" layer of dielectric material on top of the first layer, the passivation layer of dielectric material preferably extending over the sidewalls of the active layer and the p-GaN layer.

[0124] (Micro LED array) According to a fourth aspect of the present invention, there is provided a micro LED array formed on a substrate and comprising a plurality of micro LEDs according to the third aspect of the present invention.

[0125] The array of micro LEDs comprises: an n-doped contact layer of III-nitride material over the porous region of III-nitride material; an electrically insulating mask layer on the n-doped group III nitride layer; a plurality of LED structures; at least a portion of each LED structure extends through a gap in the electrically insulating mask layer and contacts the n-doped contact layer.

[0126] An array of micro LEDs is an ordered series or arrangement of micro LEDs, for example, an ordered number of rows and columns, each containing multiple micro LEDs.

[0127] The array of micro LEDs is an array of micro LEDs manufactured using the method of the second aspect of the present invention.

[0128] All of the features described above in relation to any of the first, second, third or fourth aspects of the invention are equally applicable to the other aspects of the invention. [Brief explanation of the drawings]

[0129] Specific embodiments of the present invention will now be described with reference to the drawings.

[0130] FIG. 1 shows a porous template suitable for a micro LED or an array of micro LEDs according to the present invention. 2-18 illustrate steps for fabricating two arrays of micro LEDs according to a preferred embodiment of the present invention; 19-25 illustrate a method for fabricating a micro LED according to a preferred embodiment of the present invention.

[0131] FIG. 1 shows a porous template suitable for micro-LEDs according to the present invention.

[0132] The porous template comprises a porous region of III-nitride material on a substrate with a non-porous layer of III-nitride material disposed on a top surface of the porous region, and optionally, there can be an additional layer of III-nitride material between the substrate and the porous region.

[0133] As detailed above, the porous region is provided by epitaxially growing an n-doped region of III-nitride material followed by an undoped layer of III-nitride material and rendering the n-doped region porous using a porosification process, which is described in International Patent Applications PCT / GB2017 / 052895 (published as WO 2019 / 063957) and PCT / GB2019 / 050213 (published as WO 2019 / 145728).

[0134] The porous region may include one or more layers of one or more III-nitride materials and may have a range of thicknesses, in preferred embodiments the porous region includes, for example, GaN and / or InGaN.

[0135] In a preferred embodiment, a micro LED according to the present invention may comprise the following layers and is fabricated using the step-by-step process described below:

[0136] The following description of the LED structure of a micro LED relates to a top-emitting architecture, described from bottom to top, although the present invention is also applicable to a bottom-emitting architecture.

[0137] (Fig. 2 Substrate and III-nitride layer for porosity) A suitable substrate is used as the starting surface for epitaxial growth. The substrate can be silicon, sapphire, SiC, β-Ga2O3, GaN, glass, or metal. The crystal orientation of the substrate can be polar, semipolar, or nonpolar. The substrate size is 1 cm 2 The substrate may range in size from 2 inches, 4 inches, 6 inches, 8 inches, 12 inches, 16 inches, and larger in diameter. The thickness of the substrate may be greater than 1 μm, for example, from 1 μm to 15,000 μm. Preferably, the substrate is a semiconductor wafer. An advantage of the present invention is that it allows for the simultaneous fabrication of an array of micro LEDs on a full-sized semiconductor wafer. While the illustrated example shows two micro LEDs formed on a shared template, it is also possible to fabricate multiple arrays of micro LEDs on the same wafer using the same method.

[0138] On the substrate, a layer or stack of layers of III-nitride materials is epitaxially grown, the III-nitride layers including one or some combination of the elements Al, Ga, and In (binary, ternary, or quaternary layers).

[0139] The thickness T of the III-nitride stack is preferably at least 10 nm, or at least 50 nm, or at least 100 nm, for example 10 to 10000 nm, preferably 4000 nm.

[0140] The III-nitride layer is 1×10 17 cm -3 ~5×10 20 cm -3 The III-nitride layer may also include an undoped layer (not shown) of III-nitride material over the doped region.

[0141] The doped region terminates at the exposed upper surface of the III-nitride layer, in which case the surface of this layer is porosified during electrochemical etching.

[0142] Preferably, the doped region of III-nitride material is covered with an undoped intermediate layer (or "cap layer") of III-nitride material so that the doped region is below the surface of the semiconductor structure. The doped region has a starting depth (d) below the surface of, for example, 1 to 2000 nm.

[0143] In the examples shown in Figures 2 to 19, the porous III-nitride layer is formed by a stack of III-nitride layers consisting of alternating highly doped and undoped layers. Preferably, 5 to 50 pairs of alternating doped and undoped layers form the stack, with the highly doped layer being approximately 1 x 10 20 cm -3 and the undoped layer has a charge carrier concentration of about 1 × 10 17 cm -3 The highly doped layer preferably has a thickness of 10 nm to 200 nm, and the undoped layer preferably has a thickness of 5 to 180 nm.

[0144] (Figure 3 Porosity enhancement of porous layer) After the III-nitride layer stack is deposited on the substrate, it is rendered porous using a wafer-scale porosification process, as described in International Patent Applications PCT / GB2017 / 052895 (published as WO 2019 / 063957) and PCT / GB2019 / 050213 (published as WO 2019 / 145728). During this process, the doped layers of the III-nitride stack become porous, while the undoped regions of the III-nitride material remain non-porous. The porosity of the porous layer is controlled by an electrochemical etching process and is preferably between 10% and 90%.

[0145] Thus, after the porosification step, the structure has a non-porous intermediate layer overlying a stack of alternating porous and non-porous layers. The stack of alternating porous and non-porous layers constitutes a DBR as described above. Because the top layer of the stack is non-porous, this layer is not porosified but remains at the top of the stack as a non-porous intermediate layer.

[0146] (Fig. 4 Connection layer) After porosification, a contact layer 1 is grown on the wafer, as shown in Figure 3. The contact layer is an n-doped III-nitride layer (preferably GaN) with a thickness of 200-2000 nm (layer 1 in Figure 3) and an n-type charge carrier concentration of at least 1 x 10 18 cm -3 Higher.

[0147] The connection layer 1 is made of a III-nitride material and contains one or several combinations of the elements Al, Ga, and In (binary, ternary, or quaternary layer). The connection layer is doped with a suitable n-type dopant material, such as Si, Ge, C, or O.

[0148] (Fig. 5 Mask layer) An electrically insulating mask layer 2 is then deposited on the wafer surface, covering the connection layer 1. The purpose of the mask layer 2 is to mask and protect certain areas of the wafer in the next step and to allow selective area epitaxy on top of this template.

[0149] This mask layer 2 is made of SiO2, SiN, SiON, AlO x or other suitable layer. The thickness of this layer is between 5 and 1000 nm, preferably about 500 nm.

[0150] Methods used to deposit this layer include PECVD, sputtering, ALD, evaporation, or in-situ MOCVD techniques.

[0151] (Fig. 6 Exposed area of ​​connection layer) Standard lithographic techniques are used to create openings in the non-conductive mask layer 2. The openings can be created using either wet or dry etching methods.

[0152] In a particularly preferred example, inductively coupled plasma dry etching (ICP-RIE) is used to remove SiO2 from two areas, thereby creating two exposed regions on the surface of the connection layer 1 that are no longer covered by the mask layer 2.

[0153] The shape of the exposed area can be circular, square, rectangular, hexagonal, triangular, etc. The width or diameter of the opening is preferably less than 100 μm, so that the LED structure formed on the exposed area can be classified as a micro LED. The width of the exposed area is preferably 0.05 μm to 30 μm, and particularly preferably 10 μm or less.

[0154] These exposed areas will eventually become the microLED pixels.

[0155] (Figures 7 and 8 N-doped region) After forming the exposed areas of the connection layer 1, an n-doped layer 3 of III-nitride material is deposited on these exposed areas.

[0156] In the particular example shown, a 400 nm thick n-doped GaN layer (layer 3) is grown by MOCVD, only in the exposed areas on the surface of n-doped connection layer 1. Si is used as the dopant for n-doped layer 3, with a doping concentration of at least 1×10 19 cm -3 Higher.

[0157] After the growth of the n-doped layer 3, a bulk III-nitride layer 4 containing indium is grown, or a stack of thin III-nitride layers with or without indium, or a bulk III-nitride layer or stack of III-nitride layers with varying atomic percentages of indium therein. The atomic percentage of indium varies from 0.5% to 25%. The total thickness varies from 2 nm to 200 nm. If a stack is used, the thickness of the individual layers in the stack varies from 1 to 40 nm. Layer 4 has a thickness of 1×10 17 cm -3 ~5×10 20 cm -3 has an n-doping concentration of

[0158] (Fig. 9 Light-emitting area) After the n-type layer 4 is grown, the light emitting region 5 is grown.

[0159] The light emitting region 5 includes at least one light emitting layer. Each light emitting layer is a quantum well (QW), preferably an InGaN quantum well (QW). Preferably, the light emitting region includes 1 to 7 quantum wells. Adjacent quantum wells are separated by barrier layers of a III-nitride material having a different composition than the quantum wells.

[0160] The light emitting layer(s), referred to throughout this specification as a "quantum well," can take a variety of forms, for example, the light emitting layer can be a continuous layer of InGaN, or it can be a continuous layer, a piecemeal layer, a discontinuous layer, a layer containing gaps, or a nanostructure, where the quantum well effectively contains multiple 3D nanostructures that behave as quantum dots.

[0161] The quantum wells and barriers are grown at temperatures ranging from 600°C to 800°C.

[0162] Each quantum well preferably consists of an InGaN layer having an atomic indium percentage of 10-40%. In particular examples, the atomic indium content is 12-18%, preferably greater than 13%, or 20-30%, preferably greater than 22%, or 30-40%, preferably greater than 33%.

[0163] The thickness of each quantum well layer is 1.5 to 8 nm, preferably 1.5 to 6 nm or 1.5 to 4 nm.

[0164] The quantum wells may or may not be covered by a thin (0.5-3 nm) III-nitride QW capping layer, which contains one or a combination of the elements Al, Ga, and In (ternary, quaternary layers).

[0165] The QW capping layer (if present) is a layer added immediately after QW growth and can be AlN, AlGaN with Al% between 0.01% and 99.9%, GaN, InGaN with In% between 0.01% and 30%.

[0166] The III-nitride QW barriers separating the light-emitting layers (quantum wells) contain one or several combinations of the elements Al, Ga, In (ternary layers, quaternary layers).

[0167] As the QW capping layer(s) and the QW barrier form part of the light emitting region 5, these layers are not indicated by individual reference numbers in the drawings.

[0168] (Figure 10 Cap layer and EBL) After the growth of the quantum wells, an undoped cap layer 6 is grown. The undoped cap layer 4 can be referred to as the light emitting region cap layer because it is formed after growth of the complete light emitting region, e.g., after growth of the stack of QWs, QW cap layer, and QW barrier layer.

[0169] The cap layer (light emitting region cap layer) 6 is a standard layer that is very well known in III-nitride LED growth schemes.

[0170] The thickness of the cap layer is 5 to 30 nm, preferably 5 to 25 nm or 5 to 20 nm.

[0171] (Electron Blocking Layer (EBL)) After the cap layer 6, an aluminum-containing electron-blocking III-nitride layer 7 (EBL) is grown. The thickness of the EBL is 10 to 100 nm. The Al content is, for example, 5 to 25%, but a higher Al content is also possible.

[0172] The EBL is doped with a suitable p-type doping material. The doping concentration is 5×10 18 cm -3 ~8×10 20 cm -3 It can be said that:

[0173] (Fig. 11 p-doped layer) A p-doped layer 8 is grown above an electron blocking layer (EBL) 7 .

[0174] The p-type region is preferably doped with Mg, and the p-type doping concentration of the p-type layer is preferably 5×10 18 cm -3 ~8×10 20 cm -3 is.

[0175] The p-doped group III nitride layer includes In and Ga.

[0176] The doping layer is preferably 20-200 nm thick, and especially preferably 50-100 nm thick. The doping concentration varies within the p-type layer, but may have a spike in doping level in the last 10-30 nm of the p-type layer near the LED surface to allow for better p-contact.

[0177] To activate the Mg acceptors in the p-doped layer, the structure can be annealed in an MOCVD reactor or in an annealing oven at temperatures ranging from 700 to 850°C in an N2 or N2 / O2 atmosphere.

[0178] Because both the EBL and the p-doped layer are p-type doped, these layers can be referred to as p-doped regions.

[0179] (Fig. 12 Passivation layer) The next step is to deposit a passivation layer 9 or a combination of passivation layers. The starting passivation layer is Al2O3 (10-100 nm) (deposited by atomic layer deposition), followed by SiO2, SiN, or SiON (50-300 nm) deposited by sputtering or plasma-enhanced chemical vapor deposition.

[0180] Al2O3 is deposited at 50-150 C, and SiO2, SiN, and SiON are deposited at 250-350 C. The sputtering process can be carried out at room temperature.

[0181] In a particularly preferred example, the passivation layer 9 consists of a 30 nm thick Al2O3 layer and a 200 nm thick SiO2 layer.

[0182] (Fig. 13 Opening in the passivation layer) The next step is to create openings in the dielectric layer to expose the p-GaN and n-GaN. This can be done by wet etching, dry etching, or a combination of both. A wet buffered oxide etch can use diluted hydrofluoric acid, phosphoric acid, or a mixture of these.

[0183] In the topology shown in the drawing, two separate lithographic steps are used to form ohmic contacts to the p-doped and n-doped layers.

[0184] FIG. 13 shows creating an opening in the passivation layer 9 to expose a region of the p-type layer 8 .

[0185] (Figure 14 Transparent conductive layer) The exposed areas of the p-type layer 8 are then covered with a transparent conductive layer 10. The transparent conductive layer can be made of Ni / Au, indium tin oxide, indium zinc oxide, graphene, Pd, Rh, silver, ZnO, etc., or a combination of these materials.

[0186] The transparent conductive layer typically has a thickness of 10 to 250 nm.

[0187] Transparent conductive layers are well known in the art and may be of any suitable material and thickness.

[0188] An annealing step may be required to make the p-contact ohmic.

[0189] (Fig. 15 Second exposed area) The next step is to create openings to expose second exposed areas of the n-doped connection layer 1, which can allow electrical contact to be made to the connection layer 1. This is done by removing parts of the passivation layer 9 and the mask layer 2. This can be done by wet etching, dry etching, or a combination of both.

[0190] (Fig. 16 n-contact) A metal n-contact 11 is deposited on the second exposed region of the n-doped connection layer 1. This metal contact may be a combination of titanium, platinum, and gold.

[0191] (Fig. 17 p contact) In a final step, only a portion of the ITO is covered with a metal p-contact 12. This is used in topologies where light is extracted from the p-side, as shown in FIG.

[0192] The metal contact may be a combination of nickel, titanium, platinum, and gold.

[0193] (Micro LED example) Following the steps described above, a particularly preferred example of a micro LED according to the present invention can be fabricated. Layer details of an exemplary micro LED structure are as follows:

[0194] Substrate: A 4-inch diameter planar sapphire substrate with an undoped GaN buffer layer less than 1 μm thick.

[0195] Porous stack: A stack consisting of 15 pairs of alternating layers of undoped GaN layers (45 nm thick) and Si-doped n+ GaN layers (62.5 nm thick), with a density of 1 × 10 19 cm -3 It has a higher charge carrier concentration and is electrochemically rendered porous, with the n-doped layers being porous and the undoped layers (including the top layer of the stack) being non-porous.

[0196] Connection layer 1 (grown on top of the non-porous / porous template): n-doped GaN layer, 500 nm thick, doped with Si to a charge carrier concentration of 5 × 10 18 cm -3 Greater than.

[0197] Mask layer 2: 500 nm thick SiO2 layer deposited by PECVD.

[0198] Exposed area: SiO2 was removed from the designated area using inductively coupled plasma-irradiated etching (ICP-RIE), exposing a circular exposed area with a diameter of 10 μm.

[0199] n-doped layer 3: a 400 nm thick n-doped GaN (Si dopant) layer grown by MOCVD with a doping concentration of at least 1×10 19 cm -3 Higher.

[0200] n-type layer 4: a stack of layers with less than 5% atomic indium content, with a total stack thickness of 120 nm and a median doping concentration of 1 × 10 18 cm -3 is.

[0201] Light-emitting region 5: Five InGaN quantum wells (indium content 17.5 at%), PL emission wavelength 440 to 465 nm, with GaN as barrier layers and no cap layer.

[0202] Capping layer 6: GaN, 20 nm thick.

[0203] EBL7: AlGaN containing 15% Al, 60 nm thick.

[0204] P-type doped layer 8: a p-type GaN layer, 50 nm thick, doped with Mg to a p-type charge carrier concentration of 1×10 19 cm -3 A larger layer and subsequent p++ GaN layer, 6 nm thick, doped with Mg to a p-type charge carrier concentration of 1×10 20 cm -3Larger layers.

[0205] Passivation layer 9: a 30 nm thick Al2O3 layer and a 200 nm thick SiO2 layer.

[0206] Transparent conductive layer 10: ITO with a thickness of 150 nm.

[0207] Metal contact 11 to n-doped layer: 50 nm Ti, 100 nm Pt, and 500 nm Au.

[0208] Metal contact 12 to p-type layer: 2 nm Ni, 50 nm Ti, 100 nm Pt, and 500 nm Au.

[0209] The micro LEDs illustrated in Figures 2 through 17 have an emission wavelength between 440 and 465 nm and are designed to emit light from the p-side of the device (the top of the micro LED as shown). The stack of porous / non-porous layers forms a DBR that exhibits greater than 90% reflectivity / transmittance at approximately 450 nm, so that the DBR acts as a reflective mirror beneath the micro LED, increasing the brightness of the emitted light. The emission wavelength in the emission region and the wavelength reflected by the DBR can be tailored as desired to obtain LEDs of other colors.

[0210] (Fig. 19 Bottom Side Topology) FIG. 19 shows an alternative micro LED topology where light is extracted from the bottom side (substrate side).

[0211] A stack of porous / non-porous layers can be used to form a DBR with a reflectivity greater than 90% in the wavelength range of, for example, 440-465 nm.

[0212] In an exemplary embodiment, the QWs are selected to have an emission wavelength of 520-540 nm, and the fabrication steps described in connection with Figures 2 through 17 are also used for this embodiment, except that the n-type underlayer 3 and light-emitting region 5 are appropriately tailored to the desired output wavelength.

[0213] This bottom-side emission topology offers the following advantages: -Pure green light is transmitted from the device through the DBR, and other wavelengths below 520nm are blocked and reflected by the DBR design. There is no damage to the pixel sidewalls during manufacturing, so there is no degradation in micro-pixel performance.

[0214] (Preferred embodiment) 19 to 25 illustrate a method for manufacturing a micro LED according to a preferred embodiment of the present invention.

[0215] Figure 19. A DBR is formed on a substrate using a porosification technique, and a layer of n-GaN is deposited on top of the porosification DBR. The porosification technique is described in Cambridge Enterprises' pending patent application PCT / GB2017 / 052895.

[0216] FIG. 20. Deposit a layer of SiO2 (or another dielectric material) on the top surface of the n-GaN.

[0217] FIG. 21 The SiO2 is patterned by lithography and portions of the SiO2 with lateral dimensions of 50 μm×50 μm are removed by wet chemical etching or dry etching processes.

[0218] Figure 22. On the exposed n-GaN, a quantum well made from one of InGaN, AlGaN, InN, InAlN, or AlInGaN is deposited, surrounded by quantum barriers of GaN, AlN, AlGaN, AlInGaN, or InAlN. A layer of p-GaN is deposited on top of the QW.

[0219] Figure 23. A second layer of SiO2 is deposited on top of the first layer of SiO2 so that the SiO2 covers the edges of the QWs and the p-GaN layer. An electrical p-contact is formed on top of the p-GaN to make electrical contact with the p-GaN layer. This second SiO2 layer is a passivation layer.

[0220] FIG. 24. A portion of the SiO2 is removed using a wet chemical or dry etching process to expose a portion of the n-GaN layer. An electrical n-contact is deposited on the exposed portion to make electrical contact with the n-GaN.

[0221] Figure 25. The second layer of SiO2 is passivated by known techniques. A plasma etch is used for chip singulation and transfer.

Claims

1. A method for manufacturing a micro LED, comprising: forming an n-doped contact layer of Group III-nitride material over the porous region of Group III-nitride material; forming an electrically insulating mask layer over the n-doped connection layer; removing a portion of the mask to expose an exposed area of ​​the n-doped connection layer; forming an LED structure on the exposed region of the n-doped connection layer; A method comprising:

2. The step of forming the LED structure comprises: an n-doped portion; a p-doped portion; a light emitting region disposed between the n-doped portion and the p-doped portion; The method of claim 1 , comprising forming:

3. 3. The method of claim 1, comprising the first step of electrochemically porosifying a region of Group III-nitride material to form the porous region of Group III-nitride material.

4. 4. The method of claim 1, 2, or 3, wherein forming the porous region of III-nitride material comprises forming through a non-porous layer of III-nitride material by electrochemical porosification, thereby forming the non-porous intermediate layer of III-nitride material between the porous region and the n-doped III-nitride connecting layer.

5. The method according to claim 4, wherein the thickness of the non-porous intermediate layer is between 1 nm and 3000 nm, preferably between 5 nm and 2000 nm.

6. 10. The method of any of the preceding claims, wherein the n-doped connecting layer of III-nitride material is formed on a stack of multiple porous layers of III-nitride material.

7. 7. The method of claim 6, wherein the stack of porous layers includes a porous distributed Bragg reflector (DBR), such that the method includes forming an n-doped connecting layer of III-nitride material on top of the porous DBR of III-nitride material.

8. 8. The method of claim 6 or 7, wherein the stack of porous layers is a stack of alternating porous and non-porous layers, preferably the stack comprises 5 to 50 pairs of porous and non-porous layers.

9. The method of claim 8, wherein the porous layer has a thickness of 10 nm to 200 nm and the non-porous layer has a thickness of 5 nm to 180 nm.

10. 10. A method according to any preceding claim, wherein the or each porous region is porous to a porosity of between 10% and 90%.

11. The n-doped connection layer of III-nitride material has a thickness of 200 nm to 2000 nm and a charge carrier concentration of 1×10 １８ cm －３ A method according to any of the larger preceding claims.

12. The mask layer is made of SiO ２ , SiN, SiON, AlO ｘ 10. The method of any of the preceding claims, formed from one of:

13. 10. The method according to any of the preceding claims, wherein the thickness of the mask layer is between 5 nm and 1000 nm, preferably between 200 nm and 800 nm, particularly preferably between 400 nm and 600 nm.

14. 10. The method of any preceding claim, wherein the mask layer is deposited by PECVD, sputtering, ALD, evaporation, or in-situ MOCVD.

15. 10. The method according to any of the preceding claims, wherein the step of removing parts of the mask layer comprises wet etching or dry etching, for example inductively coupled plasma-reactive etching (ICP-RIE).

16. 10. The method of any of the preceding claims, wherein the exposed areas of the connecting layer are circular, square, rectangular, hexagonal, or triangular in shape.

17. 10. The method according to any of the preceding claims, wherein the width of the exposed areas is between 0.05 μm and 100 μm, preferably between 0.05 μm and 30 μm, particularly preferably less than 10 μm, for example between 0.1 μm and 10 μm or between 0.5 μm and 10 μm.

18. removing a second portion of the mask after forming the n-doped portion, the light emitting region, and the p-doped portion to expose a second exposed region of the n-doped connection layer; forming an electrical contact on the second exposed region of the n-doped connection layer; 10. A method according to any preceding claim, comprising:

19. 1. A method for manufacturing an array of micro LEDs, comprising: forming an n-doped contact layer of Group III-nitride material over the porous region of Group III-nitride material; forming an electrically insulating mask layer over the n-doped Group III-nitride layer; removing portions of the mask to expose an array of exposed areas of the n-doped connection layer; forming an LED structure on each exposed region of the n-doped connection layer; A method comprising:

20. A micro LED, an n-doped contact layer of Group III-nitride material over the porous region of Group III-nitride material; an electrically insulating mask layer on the n-doped Group III-nitride layer; an LED structure; wherein at least a portion of the LED structure extends through a gap in the electrically insulating mask layer and contacts the n-doped contact layer.

21. The LED structure comprises: an n-doped portion; a p-doped portion; a light emitting region disposed between the n-doped portion and the p-doped portion; 21. The micro-LED of claim 20, comprising:

22. 22. The micro-LED of claim 20 or 21, comprising a non-porous intermediate layer of a III-nitride material disposed between the porous region and the connecting layer.

23. 23. A microLED according to claim 21 or 22, wherein the n-doped portion comprises an n-doped III-nitride layer, preferably the n-doped portion comprises n-GaN, or n-InGaN, or a stack of alternating n-GaN / n-InGaN layers, or a stack of alternating n-InGaN / n-InGaN layers containing different indium concentrations.

24. 24. The microLED of any of claims 21 to 23, wherein the light emitting region comprises one or more III-nitride light emitting layers, and the or each light emitting layer comprises a quantum well or a nanostructured layer comprising a quantum structure such as a quantum dot, fractional or discontinuous quantum well.

25. 25. A microLED according to claim 24, wherein the or each light-emitting layer comprises a Group III-nitride material having an atomic indium content of 10-40%, or 12-18%, preferably greater than 13%, or 20-30%, preferably greater than 22%, or 30-40%, preferably greater than 33%.

26. The one or more light-emitting layers have a composition In ｘ Ga １－ｘ 26. A micro LED according to claim 24 or 25, having a N with 0.10≦x≦0.40, preferably 0.20≦x≦0.40 or 0.22≦x≦0.40, particularly preferably 0.30≦x≦0.

40.

27. A microLED according to any of claims 21 to 26, wherein the light emitting region comprises one or more InGaN quantum wells, preferably 1 to 7 quantum wells.

28. 28. The micro LED of any of claims 21 to 27, wherein the LED includes a cap layer of a III-nitride material between the quantum well and the p-doped portion, preferably the cap layer being undoped and having a thickness of 5 nm to 30 nm.

29. 29. The micro LED of claim 21, wherein the p-doped portion comprises a p-doped III-nitride layer and a p-doped aluminum gallium nitride layer disposed between the p-doped III-nitride layer and the light emitting region.

30. 30. The micro LED of claim 29, wherein the p-doped aluminum nitride layer is an electron blocking layer (EBL) between the cap layer and the p-type layer, the electron blocking layer containing 5-25 at % aluminum, and preferably the thickness of the electron blocking layer is 10 nm to 100 nm.

31. 31. A micro LED array comprising a plurality of micro LEDs according to any one of claims 21 to 30 formed on a substrate.

32. 1. An array of micro LEDs, an n-doped contact layer of Group III-nitride material over the porous region of Group III-nitride material; an electrically insulating mask layer on the n-doped Group III-nitride layer; a plurality of gaps in the electrically insulating mask layer; a plurality of LED structures; wherein at least a portion of each LED structure extends through a gap in an electrically insulating mask layer and is in contact with the n-doped contact layer.

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