Control of pulsing frequency and duty cycle of parameters of an RF signal

Abstract

To provide a system and a method for controlling a pulse frequency and a duty cycle at which a high frequency signal is pulsed.SOLUTION: The method includes generating a first radio frequency (RF) signal and pulsing a parameter of a 1RF signal between a first parameter level and a second parameter level at a pulsing frequency during cycles of a digital pulsed signal. The method further includes generating a 2RF signal and pulsing a parameter of the 1RF signal during the cycle at a pulsing frequency that is greater than a pulsing frequency of the parameter of the 2RF signal. During the cycle, a start time of the pulsing the parameter of the 1RF signal is synchronized with a start time of the pulsing the parameter of the 2RF signal, and an end time of the pulsing the parameter of the 1RF signal is synchronized with an end time of the pulsing the parameter of the 2RF signal.SELECTED DRAWING: Figure 2D

Description

[Technical Field]

[0001] The present embodiments relate to systems and methods for controlling the pulsing frequency and duty cycle at which a radio frequency (RF) signal is pulsed. [Background technology]

[0002] The background art provided herein is intended to provide a general background to the present disclosure, and the work of the inventors named herein, to the extent described in this background art, along with aspects of the description that would not normally be considered prior art at the time of filing, are not admitted expressly or impliedly as prior art to the present disclosure.

[0003] In a plasma tool, a radio frequency (RF) generator is connected to an impedance matching network. The impedance matching network is connected to a chuck of a plasma chamber. A semiconductor wafer is placed in the plasma chamber. A process gas is supplied to the plasma chamber, and a RF signal is supplied from the RF generator through the impedance matching network to the plasma chamber, generating a plasma in the plasma chamber.

[0004] Plasmas are used to process semiconductor wafers, however there are limitations to the types of processes that can be performed on the semiconductor wafers.

[0005] It is in this context that the embodiments described in this disclosure arise. Summary of the Invention

[0006]

[0006] Embodiments of the present disclosure provide systems, apparatus, methods, and computer programs for controlling the pulsing frequency and duty cycle at which a radio frequency (RF) signal is pulsed. It should be understood that the present embodiments can be embodied in various forms, such as a process, an apparatus, a system, a device, or a method recorded on a computer-readable medium. Some embodiments are described below.

[0007] In one embodiment, simultaneous multi-frequency and multi-duty cycle RF pulsing is described. The RF pulsing can be synchronous or asynchronous. This allows for multiple combinations of pulsing an RF component (such as a transformer-coupled plasma (TCP) coil or bias electrode) within the pulse cycle of another component (such as the bias electrode of a TCP coil). For example, the power of the RF signal supplied to the TCP coil is pulsed at a frequency of 500 Hertz (Hz) and a 50% duty cycle, and the power of the RF signal supplied to the bias electrode is pulsed at a frequency of 100 Hz and a 20% duty cycle. Different pulsing frequencies and duty cycles provide greater flexibility for achieving different processing applications. For example, different processing applications can be achieved by lowering the pulsing frequency of the RF signal power to the bias electrode compared to the pulsing frequency of the RF signal power supplied to the TCP coil, or by applying a different duty cycle to the RF signal power to the bias electrode than the pulsing frequency of the RF signal power supplied to the TCP coil.

[0008] In one embodiment, the bias RF generator, which supplies an RF signal to the bias electrode, and the TCP RF generator, which supplies an RF signal to the TCP coil, can operate independently at their respective pulsing frequencies and duty cycles and can supply their respective RF signals upon receiving a synchronization trigger signal. The bias RF generator and the TCP RF generator can start pulsing at the same time, but can operate at different pulsing frequencies and duty cycles and end pulsing at the same time. The duty cycle and pulsing frequency can be configured within the process recipe. One complete bias pulse cycle of the RF signal generated by the bias RF generator occurs over one or more complete TCP pulse cycles of the RF signal generated by the TCP RF generator. A bias pulse cycle begins at the beginning of one or more TCP pulse cycles and ends at the end of one or more TCP pulse cycles.

[0009] In one embodiment, one complete TCP pulse cycle of the RF signal generated by the TCP RF generator occurs over one or more complete bias pulse cycles of the RF signal generated by the bias RF generator, with the TCP pulse cycle starting at the beginning of one or more bias pulse cycles and ending at the end of one or more bias pulse cycles.

[0010] In one embodiment, four RF components (e.g., two TCP RF generators and two bias RF generators) have multiple pulsed frequencies. The power applied to a first of the four RF components is pulsed at a first pulsed frequency. Similarly, the power applied to a second of the four RF components is pulsed at a second pulsed frequency, the power applied to a third of the four RF components is pulsed at a third pulsed frequency, and the power applied to a fourth of the four RF components is pulsed at a fourth pulsed frequency. The second pulsed frequency is a first integer multiple of the first pulsed frequency. Similarly, the third pulsed frequency is a second integer multiple of the second pulsed frequency, and the fourth pulsed frequency is a third integer multiple of the first pulsed frequency. As an example, the first, second, and third integer multiples are equal. As another example, either the second integer multiple or the third integer multiple, or both the second integer multiple and the third integer multiple, are different (e.g., larger or smaller) than the first integer multiple. The bias pulse cycle of power of the two bias RF generators and the TCP pulse cycle of power of the two TCP RF generators start and end at the same time.

[0011] In one embodiment, a method for pulsing is described. The method includes generating a first RF signal and pulsing a parameter of the first RF signal between a first parameter level and a second parameter level at a pulse frequency during a cycle of a digital pulse signal. The method further includes generating a second RF signal and pulsing the parameter of the second RF signal during the cycle at a pulse frequency higher than the pulse frequency of the parameter of the first RF signal. During the cycle, a start time of pulsing the parameter of the first RF signal is synchronized with a start time of pulsing the parameter of the second RF signal, and an end time of pulsing the parameter of the first RF signal is synchronized with an end time of pulsing the parameter of the second RF signal.

[0012] In one embodiment, a controller is described. The controller includes a processor configured to control a first RF generator to generate a first RF signal. The first RF generator is configured to pulse a parameter of the first RF signal between a first parameter level and a second parameter level at a pulse frequency during a cycle of a digital pulse signal. The processor is configured to control a second RF generator to generate a second RF signal. The second RF generator is configured to pulse a parameter of the second RF signal during the cycle at a pulse frequency higher than the pulse frequency of the parameter of the first RF signal. A start time at which the parameter of the first RF signal is pulsed is synchronized with a start time at which the parameter of the second RF signal is pulsed, and an end time at which the parameter of the first RF signal is pulsed is synchronized with an end time at which the parameter of the second RF signal is pulsed. The controller includes a memory device coupled to the processor for storing the first and second parameter levels of the first RF signal.

[0013] In one embodiment, a plasma system for pulsing is described. The plasma system includes a first RF generator configured to generate a first RF signal. The first RF generator is configured to pulse a parameter of the first RF signal between a first parameter level and a second parameter level at a pulse frequency during a cycle of a digital pulse signal. The plasma system includes a second RF generator configured to generate a second RF signal. The second RF generator is configured to pulse a parameter of the second RF signal at a pulse frequency higher than the pulse frequency of the parameter of the first RF signal during the cycle. During the cycle, a start time at which the parameter of the first RF signal is pulsed is synchronized with a start time at which the parameter of the second RF signal is pulsed, and an end time at which the parameter of the first RF signal is pulsed is synchronized with an end time at which the parameter of the second RF signal is pulsed.

[0014] Some advantages of the systems and methods described herein include applying different pulse frequencies or different duty cycles of RF signal parameters to a plasma chamber. For example, the pulse frequency of a bias RF signal parameter supplied to a substrate support of the plasma chamber via a matcher is different from the pulse frequency of a source RF signal parameter supplied to an RF coil of the plasma chamber via a matcher. When different pulse frequencies are applied to the plasma chamber, different processes can be performed on a substrate disposed on the substrate support compared to when the same pulse frequencies of the source RF signal and bias RF signal parameters are applied. As another example, the duty cycle of the bias RF signal parameter is different from the duty cycle of the source RF signal parameter. When different duty cycles are applied to the plasma chamber, different processes can be performed on a substrate disposed on the substrate support compared to when the same duty cycles of the source RF signal and bias RF signal parameters are applied.

[0015] Other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0016] The embodiments can be best understood by referring to the following description taken in conjunction with the accompanying drawings.

[0017] [Figure 1A] FIG. 1 illustrates one embodiment of a plasma system to illustrate control of the duty cycle of a source radio frequency (RF) signal generated by a transformer coupled plasma (TCP) coil and a bias RF generator connected to a substrate support.

[0018] [Figure 1B] FIG. 1 shows an embodiment of a plasma system to illustrate an RF generator connected to a TCP coil through a matcher.

[0019] [Figure 2A] FIG. 10 illustrates one embodiment of a graph for illustrating a process recipe signal.

[0020] [Figure 2B] 2 illustrates an embodiment of a graph for illustrating parameters of an RF signal versus time t.

[0021] [Figure 2C] FIG. 10 illustrates one embodiment of a graph for illustrating a digital pulse signal generated by a source RF generator or transmitted by a processor to a source RF generator.

[0022] [Figure 2D] FIG. 2 illustrates an embodiment of a graph for illustrating parameters of an RF signal versus time t.

[0023] [Figure 2E] FIG. 10 illustrates one embodiment of a graph for illustrating a digital pulse signal generated by a source RF generator or transmitted by a processor to a source RF generator.

[0024] [Figure 2F] 2 illustrates an embodiment of a graph for illustrating parameters of an RF signal versus time t.

[0025] [Figure 2G] FIG. 10 illustrates one embodiment of a graph for illustrating synchronization signals.

[0026] [Figure 3] FIG. 1 illustrates an embodiment of a graph for illustrating parameters of multiple RF signals.

[0027] [Figure 4] FIG. 1 illustrates an embodiment of a graph for illustrating parameters of multiple RF signals.

[0028] [Figure 5] FIG. 1 illustrates an embodiment of a graph for illustrating parameters of multiple RF signals.

[0029] [Figure 6] FIG. 1 illustrates an embodiment of a graph for illustrating parameters of multiple RF signals.

[0030] [Figure 7] FIG. 1 illustrates an embodiment of a system having a source RF generator and a bias RF generator.

[0031] [Figure 8A] 2B shows an embodiment of the graph of FIG. 2A for illustrating the process recipe signals of FIG. 2A.

[0032] [Figure 8B] FIG. 2C shows an embodiment of the graph of FIG. 2B for illustrating parameters of the RF signal generated by the bias RF generator.

[0033] [Figure 8C]FIG. 2D shows an embodiment of the graph of FIG. 2C for illustrating the digital pulse signal of FIG. 2C.

[0034] [Figure 8D] 2D for illustrating parameters of the RF signal of FIG. 2D.

[0035] [Figure 9] FIG. 2 illustrates one embodiment of a display screen of a host computer.

[0036] [Figure 10A] FIG. 1 illustrates an embodiment of a plasma system to illustrate a multi-state RF generator.

[0037] [Figure 10B] FIG. 1 illustrates an embodiment of a plasma system to illustrate a continuous wave (CW) RF generator. DETAILED DESCRIPTION OF THE INVENTION

[0038] The following embodiments describe systems and methods for controlling the pulsing frequency and duty cycle of pulsing a radio frequency (RF) signal. It will be apparent that the embodiments may be practiced without some or all of these specific details. Furthermore, detailed descriptions of well-known processing operations have been omitted to avoid unnecessarily obscuring the embodiments.

[0039] 1A illustrates one embodiment of a plasma system 100 for illustrating control of duty cycle and pulsing frequency. The duty cycle and pulsing frequency are parameters of an RF signal generated by a source RF generator connected to multiple transformer-coupled plasma (TCP) coils and a bias RF generator connected to a substrate support. The plasma system 100 includes a source RF generator 102, another source RF generator 104, a bias RF generator 106, a matcher 108, another matcher 110, yet another matcher 112, a host computer 114, and a plasma chamber 116.

[0040] Examples of RF generators used herein include an RF generator having an operating frequency of 400 kilohertz (kHz), an RF generator having an operating frequency of 2 megahertz (MHz), an RF generator having an operating frequency of 27 MHz, and an RF generator having an operating frequency of 60 MHz. Examples of matchers used herein include an impedance matching circuit having a network of circuit elements (inductors, resistors, capacitors, etc.). Illustratively, a matcher includes one or more series circuits and one or more shunt circuits. Each series circuit includes one or more inductors and one or more capacitors connected in series with each other. Similarly, each shunt circuit includes one or more inductors and one or more capacitors connected in series with each other, with one of the one or more inductors and one or more capacitors connected to ground potential. Each of the one or more shunt circuits is connected to a corresponding circuit in the one or more series circuits. The terms matcher, impedance matching circuit, and impedance matching network are used interchangeably herein.

[0041] Examples of computers used herein include desktop computers, laptop computers, tablets, and smartphones. Examples of plasma chambers 116 include inductively coupled plasma (ICP) chambers, sometimes referred to herein as TCP chambers.

[0042] The host computer 114 includes a processor 118 and a memory device 120. The processor 118 is connected to the memory device 120. As used herein, a processor is an application specific integrated circuit (ASIC), a programmable logic device (PLD), a central processing unit (CPU), a microprocessor, or a microcontroller. Examples of a memory device include a random access memory (RAM) and a read-only memory (ROM). For example, the memory device may be a flash memory, a hard disk, or a storage device. A memory device is an example of a computer-readable medium.

[0043] The plasma chamber 116 includes a substrate support 122, a TCP coil 124, a TCP coil 126, and a dielectric window 128. The TCP coil 126 is an example of an inner TCP coil, and the TCP coil 124 is an example of an outer TCP coil. The TCP coil 124 has a diameter larger than that of the TCP coil 126. One end of each of the TCP coils 124 and 126 is connected to a ground connection or ground potential. The terms TCP coil and RF coil are used interchangeably herein. An example of the substrate support 122 includes a chuck such as an electrostatic chuck (ESC). For example, the chuck includes a metal base and a dielectric layer on the metal base. A substrate S (such as a semiconductor wafer) is placed on the upper surface of the substrate support 122 to be processed in the plasma chamber 116.

[0044] The substrate support 122 includes a lower electrode, which is fabricated from a metal such as aluminum or an aluminum alloy. The lower electrode is embedded within a dielectric layer of the chuck. The lower electrode is sometimes referred to herein as a bias electrode.

[0045] The processor 118 is connected to the source RF generator 102 via a cable system 130, which has an output 132 connected to an input 136 of a matcher 108 via an RF cable 134. The output 138 of the matcher 108 is connected to one end of the TCP coil 126 via an RF transmission line 140. The other end of the TCP coil 126 is connected to a ground connection. Similarly, the processor 118 is connected to the source RF generator 104 via a cable system 142, which has an output 144 connected to an input 148 of a matcher 110 via an RF cable 146. The output 150 of the matcher 110 is connected to one end of the TCP coil 124 via an RF transmission line 152. The other end of the TCP coil 124 is connected to a ground connection. The processor 118 is also connected via a cable system 154 to a bias RF generator 106, which has an output 156 connected via an RF cable 158 to an input 160 of a matcher 112. An output 162 of the matcher 112 is connected via an RF transmission line 164 to the lower electrode of the substrate support 122.

[0046] An example of a cable system used herein includes one or more cables for transferring data between the processor 118 and an RF generator, the RF generator being connected to the processor 118 via one or more cables. Data transfer can be serial, parallel, or via Universal Serial Bus (USB) protocol. An example of an RF transmission line includes an RF rod and an RF sheath. The RF sheath surrounds the RF rod, and an insulating material is disposed between the RF rod and the RF sheath.

[0047] The processor 118 generates a process recipe signal 169 (e.g., a digital pulse signal) and transmits the process recipe signal 169 to the bias RF generator 106 via the cable system 154. The process recipe signal 169 provides the duty cycle and pulsing frequency parameters of the RF signal 172 generated by the bias RF generator 106. Additionally, the processor 118 generates a synchronization signal 168 (e.g., a clock signal) and transmits the synchronization signal 168 to the bias RF generator 106 via the cable system 154. The synchronization signal 168 is sometimes referred to herein as a synchronization trigger signal.

[0048] After receiving the process recipe signal 169, upon receiving the synchronization signal 168, the bias RF generator 106 generates an RF signal 172 having parameters including the duty cycle and pulse frequency of the process recipe signal 169 and provides the RF signal 172 at the output 156 of the bias RF generator 106. The RF signal 172 is provided to an input 160 of a matcher 112 via an RF cable 158. The matcher 112 receives the RF signal 172 and modulates the impedance of the RF signal 172 by matching the impedance of a load connected to the output 162 of the matcher 112 with the impedance of a source connected to the input 160 of the matcher 112 to output a modulated RF signal 174. Examples of a load connected to the output 162 include an RF transmission line 164 and the plasma chamber 116. Examples of a source connected to the input 160 include the RF cable 158 and the bias RF generator 106. The modulated RF signal 174 is transmitted from the output 162 via the RF transmission line 164 to the lower electrode of the substrate support 122.

[0049] As an example, the parameter level of modulated RF signal 174 is within a predetermined range of the parameter level of RF signal 172 based on which modulated RF signal 174 is generated. Illustratively, modulated RF signal 174 transitions from the first parameter level to the second parameter level during the same time period that RF signal 172 transitions from the third parameter level to the fourth parameter level. Similarly, modulated RF signal 174 transitions from the second parameter level to the first parameter level during the same time period that RF signal 172 transitions from the fourth parameter level to the third parameter level. The third parameter level is within a predetermined range of the first parameter level, and the fourth parameter level is within a predetermined range of the second parameter level. Illustratively, the third parameter level is equal to the first parameter level, and the fourth parameter level is equal to the second parameter level. As another illustrative example, the third parameter level is 1 to 2 percent greater or less than the first parameter level, and the fourth parameter level is 1 to 2 percent greater or less than the second parameter level.

[0050] Examples of parameter levels used herein include power levels and voltage levels. Power and voltage are examples of parameters. A parameter level of an RF signal includes one or more values ​​of the RF signal (such as peak-to-peak amplitude and zero-to-peak amplitude), and one or more values ​​of a parameter level are different from one or more values ​​of another parameter level of the RF signal. Illustratively, one or more parameter values ​​of a first parameter level are exclusive from one or more parameter values ​​of a second parameter level. As a further illustrative example, when a first parameter level is greater than a second parameter level, the minimum value of one or more parameter values ​​of the first parameter level is greater than the maximum value of one or more parameter values ​​of the second parameter level. Conversely, when a first parameter level is lower or smaller than a second parameter level, the maximum value of one or more parameter values ​​of the first parameter level is less than the minimum value of one or more parameter values ​​of the second parameter level.

[0051] The processor 118 generates a process recipe signal 176 and transmits the process recipe signal 176 to the source RF generator 104 via the cable system 142. Additionally, the processor 118 transmits a synchronization signal 168 to the source RF generator 104 via the cable system 142. The process recipe signal 176 provides a duty cycle and pulsing frequency for the RF signal 178 generated by the source RF generator 104. Upon receiving the process recipe signal 176 and the synchronization signal 168, the source RF generator 104 generates an RF signal 178 having the duty cycle and pulsing frequency of the process recipe signal 176 and provides the RF signal 178 at the output 144 of the source RF generator 104. The RF signal 178 is provided to the input 148 of the matcher 110 via the RF cable 146. The matching circuit 110 receives the RF signal 178, modulates the impedance of the RF signal 178 by matching the impedance of a load connected to the output 150 of the matching circuit 110 with the impedance of a source connected to the input 148 of the matching circuit 110, and outputs a modulated RF signal 180. Examples of a load connected to the output 150 include the RF transmission line 152 and the plasma chamber 116. Examples of a source connected to the input 148 include the RF cable 146 and the source RF generator 104. The modulated RF signal 180 is transmitted from the output 150 via the RF transmission line 152 to the TCP coil 124.

[0052] The processor 118 generates a process recipe signal 182 and transmits the process recipe signal 182 to the source RF generator 102 via the cable system 130. The process recipe signal 182 provides the pulsing frequency and duty cycle parameters of the RF signal 184 generated by the source RF generator 102. The processor 118 also transmits a synchronization signal 168 to the source RF generator 102 via the cable system 130.

[0053] Upon receiving the process recipe signal 182 and the synchronization signal 168, the source RF generator 102 generates an RF signal 184 having the duty cycle and pulsing frequency of the process recipe signal 182 and provides the RF signal 184 at the output 132 of the source RF generator 102. The RF signal 184 is provided to the input 136 of the matcher 108 via an RF cable 134. The matcher 108 receives the RF signal 184 and modulates the impedance of the RF signal 184 by matching the impedance of a load connected to the output 138 of the matcher 108 with the impedance of a source connected to the input 136 of the matcher 108 to output a modulated RF signal 186. Examples of a load connected to the output 138 include an RF transmission line 140 and the plasma chamber 116. Examples of a source connected to the input 136 include the RF cable 134 and the source RF generator 102. The modulated RF signal 186 is transmitted from the output 138 to the TCP coil 126 via the RF transmission line 140.

[0054] Additionally, one or more process gases (such as an oxygen-containing gas and a fluorine-containing gas) are supplied to the gap between the dielectric window 128 and the substrate support 122. When the one or more process gases and the modulated RF signals 174, 180, and 186 are supplied to the plasma chamber 116, a plasma is ignited or sustained within the plasma chamber 116, and the plasma is used to process the substrate S. Examples of processing the substrate S include depositing one or more materials on the substrate S, etching the substrate S, cleaning the substrate S, sputtering the substrate S, or a combination thereof.

[0055] In one embodiment, bias RF generator 106 is a master RF generator, and RF generators 102 and 104 are slave RF generators. For example, synchronization signal 168 is generated by a processor (e.g., a digital signal processor (DSP)) of bias RF generator 106 and transmitted to source RF generator 102 via a first cable system and to source RF generator 104 via a second cable system. Processor 118 is connected to source RF generator 102 via the first cable system and to source RF generator 104 via the second cable system.

[0056] In one embodiment, the TCP coil 124 is disposed in the same horizontal plane as the TCP coil 126. In one embodiment, the TCP coil 124 is disposed in a different horizontal plane, such as a horizontal plane at a higher or lower horizontal level compared to the horizontal level of the horizontal plane on which the TCP coil 126 is disposed.

[0057] In one embodiment, the TCP coils used herein have a different number of turns than those shown in Figure 1A. For example, TCP coil 124 or 126 has 4 turns, 6 turns, or 8 turns.

[0058] In one embodiment, synchronization signal 168 is generated by a clock source (eg, a clock oscillator) located within host computer 114 .

[0059] In one embodiment, instead of being positioned above the dielectric window 128 , the TCP coil 124 or 126 is positioned on the side of the plasma chamber 116 .

[0060] In one embodiment, in addition to the bias RF generator 106, one or two additional bias RF generators are connected to the substrate support 122 via matchers 112. For example, the bias RF generator 106 having an operating frequency of 2 MHz, an additional RF generator having an operating frequency of 27 MHz, and another additional RF generator having an operating frequency of 60 MHz are connected to the substrate support 122 via matchers 112. The one or two additional bias RF generators are also connected to the processor 118 via a corresponding one or two cable systems.

[0061] 1B illustrates one embodiment of a plasma system 101 to illustrate RF generators 102 and 104 connected to a TCP coil 124 via a matcher 103. The plasma system 101 includes RF generators 102, 104, and 106, a matcher 103, a matcher 112, and a plasma chamber 105. The plasma system 101 is similar to the plasma system 100 (FIG. 1A) except that the plasma system 101 does not include matchers 108 and 110 and the TCP coil 126 (FIG. 1A). The plasma chamber 105 has a similar structure and function to the plasma chamber 116 (FIG. 1A) except that the plasma chamber 105 does not include the TCP coil 126.

[0062] An output 132 of the source RF generator 102 is connected to an input 107 of the matcher 103 via an RF cable 134, and an output 144 of the source RF generator 104 is connected to an input 109 of the matcher 103 via an RF cable 146. The input 107 is connected to an output 111 of the matcher 103 via a first branch circuit, and the input 109 is connected to the output 111 via a second branch circuit. By way of example, each branch circuit comprises a group of circuit elements, such as one or more series circuits and one or more shunt circuits. The output 111 is connected to the TCP coil 124 via an RF transmission line 152.

[0063] RF signal 184 generated by source RF generator 102 is received at input 107 of matcher 103, and RF signal 178 generated by source RF generator 104 is received at input 109 of matcher 103. RF signal 184 is routed through a first branch of matcher 103, which modulates the impedance of RF signal 184 to output a first modulated RF signal. Similarly, RF signal 178 is routed through a second branch of matcher 103, which modulates the impedance of RF signal 178 to output a second modulated RF signal. The first and second modulated signals are combined (summed or added) at output 111 of matcher 103 to provide modulated RF signal 113 at output 111. Modulated RF signal 113 is routed to TCP coil 124 via RF transmission line 152.

[0064] When one or more process gases are supplied to the gap between the substrate support 122 and the dielectric window 128, a modulated RF signal 113 is supplied to the TCP coil 124, and a modulated RF signal 174 is supplied to the substrate support 122, a plasma is ignited or sustained in the plasma chamber 105. The plasma in the plasma chamber 105 is used to process a substrate S in the plasma chamber 105.

[0065] 2A shows one embodiment of a graph 200 for illustrating the process recipe signal 169 (e.g., a digital pulse signal) (FIG. 1A) generated by or transmitted to the bias RF generator 102 by the processor 118. The graph 200 plots the process recipe signal 169 versus time t. The logic level (e.g., 1 or 0) of the process recipe signal 169 is plotted on the y-axis of the graph 200, and time t is plotted on the x-axis of the graph 200.

[0066] As shown in FIG. 2A, time t ranges from time t0 to time t20. For example, time t includes time t0, time t1, time t2, time t3, time t4, time t5, time t6, time t7, time t8, time t9, time t10, time t11, time t12, time t13, time t14, time t15, time t16, time t17, time t18, time t19, and time t20. The time interval between any two consecutive times is the same. For example, the time interval between times t0 and t2 is equal to the time interval between times t2 and t4 and the time interval between times t4 and t6. As another example, the time interval between times t0 and t1 is equal to the time interval between times t1 and t2 and the time interval between times t2 and t3.

[0067] During cycle 1 of synchronization signal 168, process recipe signal 169 transitions from logic level 0 to logic level 1 at time t0 and remains at logic level 1 from time t0 to time t4. Also during cycle 1 of synchronization signal 168, process recipe signal 169 transitions from logic level 1 to logic level 0 at time t4 and remains at logic level 0 from time t4 to time t8.

[0068] The process recipe signal 169 alternates between logic levels 1 and 0 during cycle 2 of the synchronization signal 168. For example, during cycle 2 of the synchronization signal 168, the process recipe signal 169 transitions from logic level 0 to logic level 1 at time t8 and maintains logic level 1 from time t8 to time t12. Also, during cycle 2 of the synchronization signal 168, the process recipe signal 169 transitions from logic level 1 to logic level 0 at time t12 and maintains logic level 0 from time t12 to time t16.

[0069] Cycle 2 of synchronization signal 168 is consecutive to cycle 1 of synchronization signal 168. For example, there are no other cycles between cycles 1 and 2 of synchronization signal 168.

[0070] The process recipe signal 169 has states S1 and S0. For example, the process recipe signal 169 has state S1 when it has a logic level 1 and has state S0 when it has a logic level 0. Illustratively, during cycle 1 of the synchronization signal 168, the process recipe signal 169 has state S1 during the time period between times t0 and t4 and has state S0 during the time period between times t4 and t8. During cycle 1 of the synchronization signal 168, the process recipe signal 169 transitions from state S0 to state S1 at time t0 and transitions from state S1 to state S0 at time t4. Similarly, states S1 and S0 of the process recipe signal 169 repeat during cycle 2 of the synchronization signal 168.

[0071] FIG. 2B shows one embodiment of a graph 204 for illustrating a parameter 206 of RF signal 172 (FIG. 1A) versus time t. Graph 204 plots parameter 206 on the y-axis and time t on the x-axis. During cycle 1 of synchronization signal 168, parameter 206 transitions or pulses from parameter level zero to parameter levels PRa and PR-a at time t0, remains at parameter levels PRa and PR-a for the period between times t0 and t4, transitions from parameter levels PRa and PR-a to parameter level zero at time t4, and remains at parameter level zero for the period between times t4 and t8 (where a is an integer greater than zero). Note that the terms “pulsing” and “transitioning” are used interchangeably herein. Also, the terms “pulsing” and “transitioning” are used interchangeably herein. Parameter level PRa is greater than parameter level zero, which is greater than parameter level PR-a. For example, parameter level PRa is a positive parameter level, and parameter level PR-a is a negative parameter level.

[0072] Parameter levels PRa, PR-a, and zero repeat during cycle 2 of synchronization signal 168. For example, during cycle 2 of synchronization signal 168, parameter 206 transitions from parameter level zero to parameter levels PRa and PR-a at time t8, remains at parameter levels PRa and PR-a during the time period between times t8 and t12, transitions from parameter levels PRa and PR-a to parameter level zero at time t12, and remains at parameter level zero during the time period between times t12 and t16. Parameter levels PRa and PR-a represent state S1 of RF signal 172, and parameter level zero represents state S0 of RF signal 172.

[0073] Thus, parameter 206 of RF signal 172 transitions between parameter levels PRa and zero at a pulsed frequency during cycles 1 and 2 of synchronization signal 168. For example, to generate a pulsed frequency of RF signal 172, two pulses of parameter 206 of RF signal 172 are generated during cycles 1 and 2 of synchronization signal 168, or one pulse of parameter 206 of RF signal 172 is generated during each cycle of synchronization signal 168. As another example, parameter 206 has a pulsed frequency in an integer multiple of 100 hertz, ranging from 100 hertz to 1000 hertz. Illustratively, parameter 206 has a pulsed frequency of 100 hertz, or 200 hertz, and so on, up to 1000 hertz.

[0074] Parameter 206 has a 50% duty cycle. For example, parameter 206 has parameter levels PRa and PR-a during the period between times t0 and t4 during cycle 1 of synchronization signal 168, and has a parameter level zero during the period between times t4 and t8 during cycle 1 of synchronization signal 168. The period between times t0 and t4 is half, or 50%, of the period between times t0 and t8. Similarly, parameter 206 has parameter levels PRa and PR-a during the period between times t8 and t12 during cycle 2 of synchronization signal 168, and has a parameter level zero during the period between times t12 and t16 during cycle 2 of synchronization signal 168. The period between times t8 and t12 is half, or 50%, of the period between times t8 and t16.

[0075] In one embodiment, instead of transitioning to parameter level zero, the parameters described herein transition to parameter levels greater than zero. For example, parameter 206 transitions from parameter levels PRa and PR-a to parameter levels PRx and PR-x, where x is an integer less than a and greater than zero. As another example, x is an integer greater than a.

[0076] In one embodiment, instead of the pulsed parameter 206 transitioning from two parameter levels PRa or PR-a to parameter level zero and vice versa, the parameter is generated as a continuous wave (CW) RF signal. For example, in response to receiving the synchronization signal 168, the bias RF generator 106 generates the continuous wave RF signal. Illustratively, the continuous wave RF signal does not have multiple parameter levels. Rather, the continuous wave RF signal has a single parameter level, which is equal to or greater than zero. As a further illustrative example, the parameter value of the single parameter level of the continuous wave RF signal is within a predetermined range, such as within ±5% of the mean or median of the parameter value. The mean or median of the parameter value is an example of a statistical value.

[0077] In one embodiment, during cycle 1 of synchronization signal 168, bias RF generator 106 is on for different periods of time than shown in FIG. 2B and off for different periods of time than shown in FIG. 2B. For example, during cycle 1 of synchronization signal 168, bias RF generator 106 has a duty cycle (DC) ranging from 10% to 90%. Illustratively, RF signal 172 has parameter levels PRa and PR-a during the period between times t0 and t5 and has parameter level zero during the period between times t5 and t8. Parameter 206 transitions from parameter level zero to parameter levels PRa and PR-a at time t0 and from parameter levels PRa and PR-a to parameter level zero at time t5. RF signal 172 repeatedly transitions from parameter levels PRa and PR-a to zero and from parameter level zero to parameter levels PRa and PR-a during cycle 2 of synchronization signal 168 in the same manner that RF signal 172 transitions from parameter levels PRa and PR-a to zero and vice versa during cycle 1 of synchronization signal 168.

[0078] In one embodiment, instead of a parameter level of zero for a parameter of the RF signal, a parameter level that is substantially zero is implemented. The substantially zero parameter level includes a positive parameter level and a negative parameter level. The positive parameter level is greater than the parameter level zero by a predetermined amount, such as within 5% of the parameter level zero. The negative parameter level is less than the parameter level zero by a predetermined amount.

[0079] In one embodiment, a bias pulse cycle of parameters 206 begins at time t0 and ends at time t8. Another bias pulse cycle of parameters 206 begins at time t8 and ends at time t16.

[0080] 2C shows one embodiment of a graph 208 for illustrating a digital pulse signal 210 generated by or transmitted by processor 118 to source RF generator 102 (FIG. 1A). Digital pulse signal 210 is an example of process recipe signal 182 (FIG. 1A).

[0081] Graph 208 plots digital pulse signal 210 versus time t. The logic level (e.g., 1 or 0) of digital pulse signal 210 is plotted on the y-axis of graph 208, and time t is plotted on the x-axis of graph 208. During cycle 1 of synchronization signal 168, digital pulse signal 210 transitions from logic level 0 to logic level 1 at time t0 and maintains logic level 1 from time t0 to time t2. Also during cycle 1 of synchronization signal 168, digital pulse signal 210 transitions from logic level 1 to logic level 0 at time t2 and maintains logic level 0 from time t2 to time t4. Also during cycle 1 of synchronization signal 168, digital pulse signal 210 transitions from logic level 0 to logic level 1 at time t4 and maintains logic level 1 from time t4 to time t6. Also during cycle 1 of synchronization signal 168, digital pulse signal 210 transitions from logic level 1 to logic level 0 at time t6 and remains at logic level 0 from time t6 to time t8.

[0082] Digital pulse signal 210 alternates between logic levels 1 and 0 during cycle 2 of synchronization signal 168. For example, during cycle 2 of synchronization signal 168, digital pulse signal 210 transitions from logic level 0 to logic level 1 at time t8 and maintains logic level 1 from time t8 to time t10. Also during cycle 2 of synchronization signal 168, digital pulse signal 210 transitions from logic level 1 to logic level 0 at time t10 and maintains logic level 0 from time t10 to time t12. Also during cycle 2 of synchronization signal 168, digital pulse signal 210 transitions from logic level 0 to logic level 1 at time t12 and maintains logic level 1 from time t12 to time t14. Also during cycle 2 of synchronization signal 168, digital pulse signal 210 transitions from logic level 1 to logic level 0 at time t14 and maintains logic level 0 from time t14 to time t16.

[0083] Digital pulse signal 210 has states S1 and S0. For example, digital pulse signal 210 has state S1 when it has logic level 1 and state S0 when it has logic level 0. Illustratively, during cycle 1 of synchronization signal 168, digital pulse signal 210 has state S1 during the period between times t0 and t2, state S0 during the period between times t2 and t4, state S1 during the period between times t4 and t6, and state S0 during the period between times t6 and t8. During cycle 1 of synchronization signal 168, digital pulse signal 210 transitions from state S0 to state S1 at time t0, from state S1 to state S0 at time t2, from state S0 to state S1 at time t4, and from state S1 to state S0 at time t6. Similarly, states S1 and S0 of digital pulse signal 210 repeat during cycle 2 of synchronization signal 168.

[0084] 2D shows one embodiment of a graph 212 for illustrating a parameter 214 of RF signal 184 (FIG. 1A) versus time t. Graph 212 plots parameter 214 on the y-axis and time t on the x-axis. During cycle 1 of synchronization signal 168, parameter 214 transitions from parameter level zero to parameter levels PRb and PR-b at time t, remains at parameter levels PRb and PR-b for the time period between times t and t, transitions from parameter levels PRb and PR-b to parameter level zero at time t, and remains at parameter level zero for the time period between times t and t, where b is an integer greater than zero. For example, integer b can be greater than or less than integer a and greater than zero. Also, during cycle 1 of synchronization signal 168, parameter 214 transitions from parameter level zero to parameter levels PRb and PR-b at time t4, remains at parameter levels PRb and PR-b during the period between times t4 and t6, transitions from parameter levels PRb and PR-b to parameter level zero at time t6, and remains at parameter level zero during the period between times t6 and t8.

[0085] Parameter levels PRb, PR-b, and zero repeat during cycle 2 of synchronization signal 168. For example, during cycle 2 of synchronization signal 168, parameter 214 transitions from parameter level zero to parameter levels PRb and PR-b at time t8, remains at parameter levels PRb and PR-b during the time period between times t8 and t10, transitions from parameter levels PRb and PR-b to parameter level zero at time t10, and remains at parameter level zero during the time period between times t10 and t12. Also during cycle 2 of synchronization signal 168, parameter 214 transitions from parameter level zero to parameter levels PRb and PR-b at time t12, remains at parameter levels PRb and PR-b during the time period between times t12 and t14, transitions from parameter levels PRb and PR-b to parameter level zero at time t14, and remains at parameter level zero during the time period between times t14 and t16. The parameter levels PRb and PR-b represent the state S1 of the RF signal 184, and the parameter level zero represents the state S0 of the RF signal 184.

[0086] In this manner, the parameter of RF signal 184 transitions between parameter levels PRb and zero at a pulsed frequency during cycles 1 and 2 of synchronization signal 168. For example, to generate a pulsed frequency of RF signal 184, four pulses of the parameter of RF signal 184 are generated during cycles 1 and 2 of synchronization signal 168, or two pulses of the parameter of RF signal 184 are generated during each cycle of synchronization signal 168.

[0087] Note that the pulsing frequency of the parameter of RF signal 184 is greater than the pulsing frequency of the parameter of pulsed signal 172. For example, during each cycle of synchronization signal 168 during which one pulse of the parameter of RF signal 172 is generated, two pulses of the parameter of RF signal 184 are generated. As another example, the pulsing frequency of the parameter of RF signal 184 is an integer multiple (two, three, or four) of the pulsing frequency of the parameter of RF signal 172. Illustratively, if the pulsing frequency of the parameter of RF signal 184 is 1, the pulsing frequency of the parameter of RF signal 184 is 2, 5, or 8. As another example, if the pulsing frequency of the parameter of RF signal 172 is 2, the pulsing frequency of the parameter of RF signal 184 is 6 or 10. As another example, parameter 214 has a pulsing frequency that is an integer multiple of the pulsing frequency of parameter 206 ( FIG. 2B ). By way of example, if the pulsing frequency of parameter 206 is 100 hertz, the pulsing frequency of parameter 214 ranges from 200 hertz to 10,000 hertz. By way of further example, if the pulsing frequency of parameter 206 is 100 hertz, the pulsing frequency of parameter 214 may be 200 hertz, or 300 hertz, or 400 hertz, and so on, up to 10,000 hertz.

[0088] It is further noted that time t0 is the pulse start time of the parameter of the RF signal (such as RF signal 172 or 184 or 178) during cycle 1 of synchronization signal 168, and time t8 is the pulse end time of the parameter of the RF signal during cycle 1 of synchronization signal 168. Similarly, time t8 is the pulse start time of the parameter of the RF signal during cycle 2 of pulse recipe signal 169, and time t16 is the pulse end time of the parameter of the RF signal during cycle 2.

[0089] If the parameters of RF signals 172 and 184 transition simultaneously (e.g., at time t0) during cycle 1 of synchronization signal 168, the parameters are synchronously pulsed at start time t0, and the start times t0 of the transitions of the parameters of RF signals 172 and 184 are synchronized with one another. Similarly, if the parameters of RF signals 172 and 184 transition simultaneously (e.g., at time t8) during cycle 1 of synchronization signal 168, the parameters are synchronously pulsed at end time t8, and the end times t8 of the transitions of the parameters of RF signals 172 and 184 are synchronized with one another.

[0090] Also, if the parameters of RF signals 172 and 184 transition simultaneously (e.g., at time t8) during cycle 2 of pulsed recipe signal 169, the parameters are pulsed synchronously at start time t8, and the start times t8 of the transitions of the parameters of RF signals 172 and 184 are synchronized with one another. Similarly, if the parameters of RF signals 172 and 184 transition simultaneously (e.g., at time t16) during cycle 2 of pulsed recipe signal 169, the parameters are pulsed synchronously at end time t16, and the end times t16 of the transitions of the parameters of RF signals 172 and 184 are synchronized with one another.

[0091] Parameter 214 has a 50% duty cycle. For example, parameter 214 has parameter levels PRb and PR-b during the period between times t0 and t2 during cycle 1 of synchronization signal 168, and has a parameter level zero during the period between times t2 and t4 during cycle 1 of synchronization signal 168. The period between times t0 and t2 is half, or 50%, of the period between times t1 and t4. Similarly, parameter 214 has parameter levels PRb and PR-b during the period between times t8 and t10 during cycle 2 of synchronization signal 168, and has a parameter level zero during the period between times t10 and t12 during cycle 2 of synchronization signal 168. The period between times t8 and t10 is half, or 50%, of the period between times t8 and t12.

[0092] In one embodiment, parameter 214 has a duty cycle that is different from the duty cycle of parameter 206. For example, parameter 214 has a duty cycle in the range of 10% to 90%, and parameter 206 has a duty cycle in the range of 10% to 90%. Illustratively, parameter 214 has a 60% duty cycle, and parameter 206 has a 50% duty cycle. As another illustrative example, during cycle 1 of synchronization signal 168, parameter 214 has a 20% duty cycle by pulsing from parameter level zero to parameter levels PRb and PR-b at time t0, remaining at parameter levels PRb and PR-b from time t0 to time t1, transitioning from parameter levels PRb and PR-b to parameter level zero at time t1, and remaining at parameter level zero from time t1 to time t4. Parameter 214 also has a 20% duty cycle by pulsing from parameter level zero to parameter levels PRb and PR-b at time t4, remaining at parameter levels PRb and PR-b from time t4 to time t5, transitioning from parameter levels PRb and PR-b to parameter level zero at time t5, and remaining at parameter level zero from time t5 to time t8.

[0093] In one embodiment, instead of transitioning to parameter level zero, the parameters described herein transition to parameter levels greater than zero. For example, parameter 214 transitions from parameter levels PRb and PR-b to parameter levels PRy and PR-y, where y is an integer less than b and greater than zero. As another example, y is an integer greater than b.

[0094] In one embodiment, parameter 214 is pulsed at a frequency that is an integer multiple (2x) of the pulsing frequency of parameter 206 (FIG. 2B) that is greater than the integer multiple (2x) shown in FIG. 2D . For example, the frequency of occurrence of parameter levels PRb and PR-b is greater than that shown in FIG. 2D . Illustratively, during cycle 1 of synchronization signal 168, parameter 214 transitions from parameter level zero to parameter levels PRb and PR-b at time t0, remains at parameter levels PRb and PR-b for the time period between times t0 and t1, transitions from parameter levels PRb and PR-b to parameter level zero at time t1, and remains at parameter level zero for the time period between times t1 and t2. Also during cycle 1 of synchronization signal 168, parameter 214 transitions from parameter level zero to parameter levels PRb and PR-b at time t2, remains at parameter levels PRb and PR-b during the time period between times t2 and t3, transitions from parameter levels PRb and PR-b to parameter level zero at time t3, and remains at parameter level zero during the time period between times t3 and t4. Also during cycle 1 of synchronization signal 168, parameter 214 transitions from parameter level zero to parameter levels PRb and PR-b at time t4, remains at parameter levels PRb and PR-b during the time period between times t4 and t5, transitions from parameter levels PRb and PR-b to parameter level zero at time t5, and remains at parameter level zero during the time period between times t5 and t6. During cycle 1 of synchronization signal 168, parameter 214 transitions from parameter level zero to parameter levels PRb and PR-b at time t6, remains at parameter levels PRb and PR-b for the period between times t6 and t7, transitions from parameter levels PRb and PR-b to parameter level zero at time t7, and remains at parameter level zero for the period between times t7 and t8, resulting in a pulsing frequency of four pulses of the parameter of RF signal 184. Parameter levels PRb, PR-b, and zero repeat during cycle 2 of synchronization signal 168 at a greater pulsing frequency.Also in this example, digital pulse signal 210 is replaced by a digital pulse signal having the same frequency as the larger pulsing frequency of parameter 214 .

[0095] In one embodiment, instead of pulsed parameters 214 transitioning from two parameter levels PRb or PR-b to parameter level zero and vice versa, parameters of a continuous wave RF signal are generated. For example, in response to receiving synchronization signal 168, source RF generator 102 generates a continuous wave RF signal. In this embodiment, digital pulsed signal 210 is not generated by processor 118.

[0096] In one embodiment, parameters 214 are parameters of RF signal 172, and parameters 206 (FIG. 2B) are parameters of RF signal 184. Also in this embodiment, pulse recipe signal 169 is sent to source RF generator 102 to generate RF signal 184 having parameters 206, and digital pulse signal 210 is sent to bias RF generator 106 to generate RF signal 172 having parameters 214.

[0097] In one embodiment, the first TCP pulse cycle of parameters 214 begins at time t0 and ends at time t4. The second TCP pulse cycle of parameters 214 begins at time t4 and ends at time t8. The third TCP pulse cycle of parameters 214 begins at time t8 and ends at time t12. The fourth TCP pulse cycle of parameters 214 begins at time t12 and ends at time t16.

[0098] 2E shows one embodiment of a graph 216 for illustrating a digital pulse signal 218 generated by or transmitted by processor 118 to source RF generator 104 (FIG. 1A). Digital pulse signal 210 is an example of process recipe signal 176 (FIG. 1A).

[0099] Graph 216 plots digital pulse signal 218 versus time t. The logic level (e.g., 1 or 0) of digital pulse signal 218 is plotted on the y-axis of graph 216, and time t is plotted on the x-axis of graph 216. Digital pulse signal 218 is counter-synchronous or asynchronous with digital pulse signal 210 (FIG. 2C). For example, during cycle 1 of synchronization signal 168, digital pulse signal 218 transitions from logic level 1 to logic level 0 at time t0 and maintains logic level 0 from time t0 to time t2. Also during cycle 1 of synchronization signal 168, digital pulse signal 218 transitions from logic level 0 to logic level 1 at time t2 and maintains logic level 1 from time t2 to time t4. During cycle 1 of synchronization signal 168, digital pulse signal 218 transitions from logic level 1 to logic level 0 at time t4 and maintains logic level 0 from time t4 to time t6. Also during cycle 1 of synchronization signal 168, digital pulse signal 218 transitions from logic level 0 to logic level 1 at time t6 and remains at logic level 1 from time t6 to time t8.

[0100] Digital pulse signal 218 alternates between logic levels 0 and 1 during cycle 2 of synchronization signal 168. For example, during cycle 2 of synchronization signal 168, digital pulse signal 218 transitions from logic level 1 to logic level 0 at time t8 and maintains logic level 0 from time t8 to time t10. Also, during cycle 2 of synchronization signal 168, digital pulse signal 218 transitions from logic level 0 to logic level 1 at time t10 and maintains logic level 1 from time t10 to time t12. During cycle 2 of synchronization signal 168, digital pulse signal 210 transitions from logic level 1 to logic level 0 at time t12 and maintains logic level 0 from time t12 to time t14. Also, during cycle 1 of synchronization signal 168, digital pulse signal 210 transitions from logic level 0 to logic level 1 at time t14 and maintains logic level 1 from time t14 to time t16.

[0101] Digital pulse signal 218 has states S1 and S0. For example, digital pulse signal 218 has state S1 when it has logic level 1 and state S0 when it has logic level 0. Illustratively, during cycle 1 of synchronization signal 168, digital pulse signal 218 has state S0 during the period between times t0 and t2, state S1 during the period between times t2 and t4, state S0 during the period between times t4 and t6, and state S1 during the period between times t6 and t8. During cycle 1 of synchronization signal 168, digital pulse signal 218 transitions from state S1 to state S0 at time t0, from state S0 to state S1 at time t2, from state S1 to state S0 at time t4, and from state S0 to state S1 at time t6. Similarly, states S1 and S0 of digital pulse signal 218 repeat during cycle 2 of synchronization signal 168.

[0102] 2F shows one embodiment of a graph 220 for illustrating a parameter 222 of RF signal 178 (FIG. 1A) versus time t. Graph 220 plots parameter 222 on the y-axis and time t on the x-axis. During cycle 1 of synchronization signal 168, parameter 222 transitions from parameter levels PRc and PR-c to parameter level zero at time t, remains at parameter level zero for the time period between times t0 and t2, transitions from parameter level zero to parameter levels PRc and PR-c at time t2, and remains at parameter levels PRc and PR-c for the time period between times t2 and t4 (where c is an integer greater than zero). For example, integer c is greater than or less than integer a and greater than zero. As another example, integer c is greater than or less than integer b and greater than zero. Also, during cycle 1 of synchronization signal 168, parameter 222 transitions from parameter levels PRc and PR-c to parameter level zero at time t4, remains at parameter level zero during the period between times t4 and t6, transitions from parameter level zero to parameter levels PRc and PR-c at time t6, and remains at parameter levels PRc and PR-c during the period between times t6 and t8.

[0103] Parameter levels PRc, PR-c, and zero repeat during cycle 2 of synchronization signal 168. For example, during cycle 2 of synchronization signal 168, parameter 222 transitions from parameter levels PRc and PR-c to parameter level zero at time t8, remains at parameter level zero during the time period between times t8 and t10, transitions from parameter level zero to parameter levels PRc and PR-c at time t10, and remains at parameter levels PRc and PR-c during the time period between times t10 and t12. Also during cycle 2 of synchronization signal 168, parameter 222 transitions from parameter levels PRc and PR-c to parameter level zero at time t12, remains at parameter level zero during the time period between times t12 and t14, transitions from parameter level zero to parameter levels PRc and PR-c at time t14, and remains at parameter levels PRc and PR-c during the time period between times t14 and t16. The parameter levels PRc and PR-c represent the state S1 of the RF signal 178, and the parameter level zero represents the state S0 of the RF signal 178.

[0104] In this manner, the parameter of RF signal 178 transitions between parameter levels PRc and zero at a pulsed frequency during cycles 1 and 2 of synchronization signal 168. For example, to generate a pulsed frequency of RF signal 178, four pulses of the parameter of RF signal 178 are generated during cycles 1 and 2 of synchronization signal 168, or two pulses of the parameter of RF signal 178 are generated during each cycle of synchronization signal 168.

[0105] Note that the pulsing frequency of the parameter of RF signal 178 is greater than the pulsing frequency of the parameter of pulsed signal 172 ( FIG. 2B ). For example, during each cycle of process recipe signal 168 in which one pulse of the parameter of RF signal 172 is generated, two pulses of the parameter of RF signal 178 are generated. As another example, the pulsing frequency of the parameter of RF signal 178 is an integer multiple (two, three, or four) of the pulsing frequency of the parameter of RF signal 172. Illustratively, if the pulsing frequency of the parameter of RF signal 178 is 1, the pulsing frequency of the parameter of RF signal 178 is 2, 5, or 8. As another example, if the pulsing frequency of the parameter of RF signal 172 is 2, the pulsing frequency of the parameter of RF signal 178 is 6 or 10. As another example, parameter 222 has a pulsing frequency that is an integer multiple of the pulsing frequency of parameter 206. By way of example, if the pulsing frequency of parameter 206 is 100 hertz, the pulsing frequency of parameter 222 ranges from 200 hertz to 10,000 hertz. By way of further example, if the pulsing frequency of parameter 206 is 100 hertz, the pulsing frequency of parameter 222 may be 200 hertz, or 300 hertz, or 400 hertz, and so on, up to 10,000 hertz.

[0106] If the parameters of RF signals 172 and 178 transition simultaneously (e.g., at time t0) during cycle 1 of synchronization signal 168, the parameters are synchronously pulsed at start time t0, and the start times t0 of the transitions of the parameters of RF signals 172 and 178 are synchronized with one another. Similarly, if the parameters of RF signals 172 and 178 transition simultaneously (e.g., at time t8) during cycle 1 of synchronization signal 168, the parameters are synchronously pulsed at end time t8, and the end times t8 of the transitions of the parameters of RF signals 172 and 178 are synchronized with one another.

[0107] Also, if the parameters of RF signals 172 and 178 transition simultaneously (e.g., at time t8) during cycle 2 of pulsed recipe signal 169, the parameters are pulsed synchronously at start time t8, and the start times t8 of the transitions of the parameters of RF signals 172 and 178 are synchronized with one another. Similarly, if the parameters of RF signals 172 and 178 transition simultaneously (e.g., at time t16) during cycle 2 of pulsed recipe signal 169, the parameters are pulsed synchronously at end time t16, and the end times t16 of the transitions of the parameters of RF signals 172 and 178 are synchronized with one another.

[0108] Parameter 222 has a 50% duty cycle. For example, parameter 222 has a parameter level zero during the period between times t0 and t2 during cycle 1 of synchronization signal 168, and has parameter levels PRc and PR-c during the period between times t2 and t4 during cycle 1 of synchronization signal 168. The period between times t0 and t2 is half, or 50%, of the period between times t0 and t4. Similarly, parameter 222 has a parameter level zero during the period between times t8 and t10 during cycle 2 of synchronization signal 168, and has parameter levels PRc and PR-c during the period between times t10 and t12 during cycle 2 of synchronization signal 168. The period between times t8 and t10 is half, or 50%, of the period between times t8 and t12.

[0109] In one embodiment, parameter 222 has a duty cycle that is different from the duty cycle of parameter 206. For example, parameter 222 has a duty cycle in the range of 10% to 90%, and parameter 206 has a duty cycle in the range of 10% to 90%. Illustratively, parameter 222 has a duty cycle of 70% and parameter 206 has a duty cycle of 40%. Additionally, parameter 222 has a pulsing frequency that is higher than the pulsing frequency of parameter 206. Illustratively, during cycle 1 of synchronization signal 168, parameter 222 has an 80% duty cycle by pulsing from parameter levels PRc and PR-c to parameter level zero at time t0, remaining at parameter level zero from time t0 to time t1, transitioning from parameter level zero to parameter levels PRb and PR-b at time t1, and remaining at parameter levels PRb and PR-b from time t1 to time t4. Parameter 222 also has an 80% duty cycle by pulsing from parameter levels PRc and PR-c to parameter level zero at time t4, remaining at parameter level zero from time t4 to time t5, transitioning from parameter level zero to parameter levels PRb and PR-b at time t5, and remaining at parameter levels PRb and PR-b from time t5 to time t8.

[0110] In one embodiment, the pulsing frequency of parameter 222 of RF signal 184 is different (e.g., greater or less) than the pulsing frequency of parameter 214 of RF signal 184. For example, during each cycle of synchronization signal 168 in which two pulses of parameter 214 of RF signal 184 are generated, three pulses of parameter 222 of RF signal 178 are generated. As another example, during each cycle of synchronization signal 168 in which three pulses of parameter 214 of RF signal 184 are generated, two pulses of parameter 222 of RF signal 178 are generated.

[0111] In one embodiment, the duty cycle of parameter 222 of RF signal 178 is different (e.g., greater or less) than the duty cycle of parameter 214 of RF signal 184. For example, parameter 222 has a 20% duty cycle and parameter 214 has a 50% duty cycle. As another example, parameter 222 has a 50% duty cycle and parameter 214 has a 20% duty cycle.

[0112] In one embodiment, instead of transitioning to parameter level zero, the parameters described herein transition to parameter levels greater than zero. For example, parameter 222 transitions from parameter levels PRc and PR-c to parameter levels PRz and PR-z, where z is an integer less than c and greater than zero. As another example, z is an integer greater than c.

[0113] In one embodiment, digital pulse signal 210 (FIG. 2C) is an example of process recipe signal 176 (FIG. 1A), and digital pulse signal 218 (FIG. 2E) is an example of process recipe signal 182 (FIG. 1A). In that embodiment, parameter 214 (FIG. 2D) is a parameter of RF signal 178 (FIG. 1A), and parameter 222 is a parameter of RF signal 184 (FIG. 1A).

[0114] In one embodiment, parameter 222 is pulsed at a frequency that is a greater integer multiple of the pulsing frequency of parameter 206 (FIG. 2B) than the integer multiple shown in FIG. 2F. As shown in FIG. 2F, parameter 222 is pulsed at twice the integer multiple of the pulsing frequency of parameter 206. For example, the frequency of occurrence of parameter levels PRc and PR-c is greater than that shown in FIG. 2F. Illustratively, during cycle 1 of synchronization signal 168, parameter 222 transitions from parameter levels PRc and PR-c to parameter level zero at time t0, remains at parameter level zero for the time period between times t0 and t1, transitions from parameter level zero to parameter levels PRc and PR-c at time t1, and remains at parameter levels PRc and PR-c for the time period between times t1 and t2. Also during cycle 1 of synchronization signal 168, parameters 222 transition from parameter levels PRc and PR-c to parameter level zero at time t2, remain at parameter level zero during the time period between times t2 and t3, transition from parameter level zero to parameter levels PRc and PR-c at time t3, and remain at parameter levels PRc and PR-c during the time period between times t3 and t4. Also during cycle 1 of synchronization signal 168, parameters 222 transition from parameter levels PRc and PR-c to parameter level zero at time t4, remain at parameter level zero during the time period between times t4 and t5, transition from parameter level zero to parameter levels PRc and PR-c at time t5, and remain at parameter levels PRc and PR-c during the time period between times t5 and t6. During cycle 1 of synchronization signal 168, parameter 222 transitions from parameter levels PRc and PR-c to parameter level zero at time t6, remains at parameter level zero for the period between times t6 and t7, transitions from parameter level zero to parameter levels PRc and PR-c at time t7, and remains at parameter levels PRc and PR-c for the period between times t7 and t8, thereby achieving a pulsing frequency of 4. Parameter levels PRc, PR-b, and zero repeat during cycle 2 of synchronization signal 168 at a greater pulsing frequency.Also, instead of digital pulse signal 218, a digital pulse signal having the same frequency as the larger pulsing frequency of parameter 222 is used.

[0115] In one embodiment, instead of pulsed parameters 222 transitioning from two parameter levels PRc or PR-c to parameter level zero and vice versa, parameters of a continuous wave RF signal are generated. For example, in response to receiving synchronization signal 168, source RF generator 104 generates a continuous wave RF signal. In this embodiment, digital pulsed signal 218 is not generated by processor 118.

[0116] In one embodiment, the first TCP pulse cycle of the parameters 222 begins at time t0 and ends at time t4. The second TCP pulse cycle of the parameters 222 begins at time t4 and ends at time t8. The third TCP pulse cycle of the parameters 222 begins at time t8 and ends at time t12. The fourth TCP pulse cycle of the parameters 222 begins at time t12 and ends at time t16.

[0117] In one embodiment, parameters 222 are synchronized with parameters 214 (FIG. 2D) instead of being asynchronous with parameters 214. For example, during cycle 1 of synchronization signal 168, parameters 222 transition from parameter level zero to parameter levels PRc and PR-c at time t0, remain at parameter levels PRc and PR-c from time t0 to time t2, transition from parameter levels PRc and PR-c to parameter level zero at time t2, remain at parameter level zero from time t2 to time t4, transition from parameter level zero to parameter levels PRc and PR-c at time t4, remain at parameter levels PRc and PR-c from time t4 to time t6, transition from parameter levels PRc and PR-c to parameter level zero at time t6, and remain at parameter level zero from time t6 to time t8. Similarly, parameters 222 transition between parameter level zero and the set of parameter levels PRc and PR-c during cycle 2 of synchronization signal 168.

[0118] In one embodiment, a second bias RF generator is connected to another input of the matcher 112 (FIG. 1A) via an RF cable. The second bias RF generator receives a digital pulse signal from the processor 118 via the cable system and a synchronization signal 168 via the cable system. The digital pulse signal provides the duty cycle and pulsing frequency of the parameters of the RF signal generated by the second bias RF generator. Upon receiving the synchronization signal 168, the second bias RF generator generates an RF signal similar to how the RF signal 172 is generated by the bias RF generator 106 based on the digital pulse signal 169 and the synchronization signal 168. The pulsing frequency of the parameter of the RF signal is an integer multiple of the pulsing frequency of the parameter 206 of the RF signal 172. For example, the pulsing frequency of the parameter of the RF signal generated by the second bias RF generator is two or three times the pulsing frequency of the parameter 206 of the RF signal 172. Also, during each cycle of synchronization signal 168, a pulse cycle of the parameters of the RF signal generated by the second bias RF generator begins at the time that parameter 206 begins that pulse cycle and ends at the time that parameter 206 ends that pulse cycle. For example, a pulse cycle of the parameters of the RF signal generated by the second bias RF generator begins at time t0 and ends at time t8. Another pulse cycle of the parameters of the RF signal generated by the second bias RF generator begins at time t8 and ends at time t16.

[0119] 2G shows one embodiment of a graph 224 for illustrating synchronization signal 168. Graph 224 plots the logic level of synchronization signal 168 on the y-axis and time t on the x-axis. Synchronization signal 168 has a pulse at time t0, which indicates the start of cycle 1 of synchronization signal 168. Synchronization signal 168 has another pulse at time t8, which indicates the start of cycle 2 of synchronization signal 168. The start of cycle 2 also indicates the end of cycle 1 of synchronization signal 168.

[0120] 3 shows one embodiment of a graph 300 for illustrating a parameter 302 of RF signal 172 (FIG. 1A), a parameter 304 of RF signal 178 (FIG. 1A), and a parameter 306 of RF signal 184 (FIG. 1A). Parameters 302, 304, and 306 are plotted along the y-axis, and time t is plotted on the x-axis. Pulse 302_1 of parameter 302 occurs during cycle 1 of synchronization signal 168 (FIG. 2A), and multiple pulses of parameter 304 (e.g., pulses 304A and 304B) occur during cycle 1. Similarly, multiple pulses of parameter 306 (e.g., pulses 306A and 306B) occur during cycle 1 of synchronization signal 168.

[0121] As an example, a pulse of a parameter has a first set of two parameter levels that form an envelope that is larger than the envelope formed by a second set of parameter levels of the parameter. For example, pulse 304A has parameter levels PRL1 and PRL-1. Parameter level PRL1 is larger or higher than parameter level PRL2 of parameter 304, and parameter level PRL-2 is larger or higher than parameter level PRL-1 of parameter 304. Parameter levels PRL1 and PRL-1 form an envelope that is larger than the envelope formed by parameter levels PRL2 and PRL-2.

[0122] During cycle 1 of synchronization signal 168, pulses of parameter 304 alternate with pulses of parameter 306. For example, pulse 304A of parameter 304 is followed by pulse 306A of parameter 306, which is followed by pulse 304B of parameter 304. Pulse 306B of parameter 306 is followed by pulse 304B of parameter 304. Illustratively, pulse 306A of parameter 306 occurs immediately after pulse 304A of parameter 304, which is followed by pulse 304B of parameter 306. Pulse 304B of parameter 306 occurs immediately after pulse 304A of parameter 304, which is followed by pulse 306A of parameter 306. Pulse 304B of parameter 306 occurs immediately after pulse 304B of parameter 304.

[0123] Similarly, during cycle 2 of synchronization signal 168, the pulses of parameters 302, 304, and 306 repeat in the same manner as shown during cycle 1 of synchronization signal 168. For example, during cycle 2 of synchronization signal 168, another pulse 302_2 of parameter 302 occurs, and multiple pulses (e.g., five pulses) of parameter 304 occur. Also during cycle 2 of synchronization signal 168, multiple pulses (e.g., five pulses) of parameter 306 occur. As shown in FIG. 3 , the pulsing frequency of parameter 302 is 100 Hz, parameter 302 has a 20% duty cycle, the pulsing frequency of parameter 304 is 500 Hz, parameter 304 has a 50% duty cycle, and the pulsing frequency of parameter 306 is 500 Hz, and parameter 306 has a 50% duty cycle.

[0124] The parameter levels PR1 and PR-1 represent the state S1 of the RF signal 172, and the parameter levels PRL2 and PRL-2 represent the state S0 of the RF signal 172.

[0125] Each pulse of parameter 302 spans a single pulse of parameter 304 and a single pulse of parameter 306. For example, pulse 302_1 spans pulse 304A and pulse 306A.

[0126] In one embodiment, the pulsing frequency of any of parameters 302-306 is different than that shown in Figure 3. For example, the pulsing frequency of parameter 302 is 200 Hz, the pulsing frequency of parameter 304 is 600 Hz, and the pulsing frequency of parameter 306 is 800 Hz.

[0127] In one embodiment, the duty cycle of any of parameters 302-306 is different from that shown in Figure 3. For example, the duty cycle of parameter 302 is 30%, the duty cycle of parameter 304 is 60%, and the duty cycle of parameter 306 is 70%.

[0128] In one embodiment, parameter 302 is a parameter of RF signal 178 and parameter 304 is a parameter of RF signal 172 .

[0129] In one embodiment, parameter 304 is a parameter of RF signal 184 and parameter 306 is a parameter of RF signal 178 .

[0130] 4 shows one embodiment of a graph 400 for illustrating a parameter 402 of RF signal 172 (FIG. 1A), a parameter 404 of RF signal 178 (FIG. 1A), and a parameter 406 of RF signal 184 (FIG. 1A). Parameters 402, 404, and 406 are plotted along the y-axis, and time t is plotted on the x-axis. Pulse 402_1 of parameter 402 occurs during cycle 1 of synchronization signal 168 (FIG. 2A), and multiple pulses of parameter 404 (e.g., pulses 404A and 404B) occur during cycle 1. Similarly, multiple pulses of parameter 406 (e.g., pulses 406A and 406B) occur during cycle 1 of synchronization signal 168.

[0131] During cycle 1 of synchronization signal 168, pulses of parameter 404 alternate with pulses of parameter 406. For example, pulse 404A of parameter 404 is followed by pulse 406A of parameter 406, which is followed by pulse 404B of parameter 404. Pulse 406B of parameter 406 is followed by pulse 404B of parameter 404. Illustratively, pulse 406A of parameter 406 occurs immediately after pulse 404A of parameter 404, which is followed by pulse 406A of parameter 406. Pulse 406B of parameter 406 occurs immediately after pulse 404B of parameter 404. As another example, pulse 404D of parameter 404 is followed by pulse 406D of parameter 406, which is followed by pulse 404E of parameter 404. A pulse 406E of parameter 406 follows pulse 404E of parameter 404.

[0132] Similarly, during cycle 2 of synchronization signal 168, the pulses of parameters 402, 404, and 406 repeat in the same manner as shown during cycle 1 of synchronization signal 168. For example, during cycle 2 of synchronization signal 168, another pulse 402_2 of parameter 402 occurs, and multiple pulses (e.g., five pulses) of parameter 404 occur. Also during cycle 2 of synchronization signal 168, multiple pulses (e.g., five pulses) of parameter 406 occur. As shown in FIG. 4 , the pulsing frequency of parameter 402 is 100 Hz, parameter 402 has a 20% duty cycle, the pulsing frequency of parameter 404 is 500 Hz, parameter 404 has a 30% duty cycle, and the pulsing frequency of parameter 406 is 500 Hz, and parameter 406 has a 70% duty cycle.

[0133] Each pulse of parameter 402 spans a single pulse of parameter 404 and a single pulse of parameter 406. For example, pulse 402_1 spans pulse 404E and pulse 406E.

[0134] In one embodiment, parameter 402 is a parameter of RF signal 178 and parameter 404 is a parameter of RF signal 172 .

[0135] In one embodiment, parameters 404 are parameters of RF signal 184 and parameters 406 are parameters of RF signal 178 .

[0136] In one embodiment, the pulsing frequency of any of the parameters 402-406 is different than that shown in FIG.

[0137] In one embodiment, the duty cycle of any of the parameters 402-406 is different than that shown in FIG.

[0138] 5 shows one embodiment of a graph 500 for illustrating a parameter 502 of RF signal 172 (FIG. 1A), a parameter 504 of RF signal 178 (FIG. 1A), and a parameter 506 of RF signal 184 (FIG. 1A). Parameters 502, 504, and 506 are plotted along the y-axis, and time t is plotted on the x-axis. Pulse 502_1 of parameter 502 occurs during cycle 1 of synchronization signal 168 (FIG. 2A), and multiple pulses of parameter 504 (e.g., pulses 504A and 504B) occur during cycle 1. Similarly, multiple pulses of parameter 506 (e.g., pulses 506A and 506B) occur during cycle 1 of synchronization signal 168.

[0139] During cycle 1 of synchronization signal 168, pulses of parameter 504 alternate with pulses of parameter 506. For example, pulse 504A of parameter 504 is followed by pulse 506A of parameter 506, which is followed by pulse 504B of parameter 504. Pulse 506B of parameter 506 is followed by pulse 504B of parameter 504. Illustratively, pulse 506A of parameter 506 occurs immediately after pulse 504A of parameter 504, which in turn occurs immediately after pulse 506A of parameter 506. Pulse 504B of parameter 506 occurs immediately after pulse 504B of parameter 504.

[0140] Similarly, during cycle 2 of synchronization signal 168, the pulses of parameters 502, 504, and 506 repeat in the same manner as shown during cycle 1 of synchronization signal 168. For example, during cycle 2 of synchronization signal 168, another pulse 502_2 of parameter 502 occurs, and multiple pulses (e.g., five pulses) of parameter 504 occur. Also during cycle 2 of synchronization signal 168, multiple pulses (e.g., five pulses) of parameter 506 occur. As shown in FIG. 5 , the pulsing frequency of parameter 502 is 100 Hz, parameter 502 has a 40% duty cycle, the pulsing frequency of parameter 504 is 500 Hz, parameter 504 has a 50% duty cycle, and the pulsing frequency of parameter 506 is 500 Hz, parameter 506 has a 50% duty cycle.

[0141] Each pulse of parameter 502 spans multiple pulses (e.g., two pulses) of parameter 404 and multiple pulses of parameter 506. For example, pulse 502_1 spans pulses 504A and 504B and pulses 506A and 506B.

[0142] In one embodiment, parameter 502 is a parameter of RF signal 178 and parameter 504 is a parameter of RF signal 172 .

[0143] In one embodiment, parameter 504 is a parameter of RF signal 184 and parameter 506 is a parameter of RF signal 178 .

[0144] In one embodiment, the pulsing frequency of any of parameters 502-506 is different than that shown in FIG.

[0145] In one embodiment, the duty cycle of any of the parameters 502-506 is different than that shown in FIG.

[0146] 6 shows one embodiment of a graph 600 for illustrating a parameter 602 of RF signal 172 (FIG. 1A), a parameter 604 of RF signal 178 (FIG. 1A), and a parameter 606 of RF signal 184 (FIG. 1A). Parameters 602, 604, and 606 are plotted along the y-axis, and time t is plotted on the x-axis. Pulse 602_1 of parameter 602 occurs during cycle 1 of synchronization signal 168 (FIG. 2A), and multiple pulses of parameter 604 (e.g., pulses 604A and 604B) occur during cycle 1. Similarly, multiple pulses of parameter 606 (e.g., pulses 606A and 606B) occur during cycle 1 of synchronization signal 168.

[0147] During cycle 1 of synchronization signal 168, the pulses of parameter 604 are alternated or asynchronous with respect to the pulses of parameter 606. For example, pulse 604A of parameter 604 is followed by pulse 606A of parameter 606, which is followed by pulse 604B of parameter 604. Pulse 606B of parameter 606 is followed by pulse 604B of parameter 604. Illustratively, pulse 606A of parameter 606 occurs immediately after pulse 604A of parameter 604, which is followed by pulse 604B of parameter 606. Pulse 606B of parameter 606 occurs immediately after pulse 604B of parameter 604. As another example, pulse 604D of parameter 604 is followed by pulse 606D of parameter 606, which is followed by pulse 604E of parameter 604. Pulse 606E of parameter 606 is followed by pulse 604E of parameter 604.

[0148] Similarly, during cycle 2 of synchronization signal 168, the pulses of parameters 602, 604, and 606 repeat in the same manner as shown during cycle 1 of synchronization signal 168. For example, during cycle 2 of synchronization signal 168, another pulse 602_2 of parameter 602 occurs, and multiple pulses (e.g., five pulses) of parameter 604 occur. Also during cycle 2 of synchronization signal 168, multiple pulses (e.g., five pulses) of parameter 606 occur. As shown in FIG. 6 , the pulsing frequency of parameter 602 is 100 Hz, parameter 602 has a 40% duty cycle, the pulsing frequency of parameter 604 is 500 Hz, parameter 604 has a 30% duty cycle, and the pulsing frequency of parameter 606 is 500 Hz, and parameter 606 has a 70% duty cycle.

[0149] Each pulse of parameter 602 spans multiple pulses of parameter 604 and multiple pulses of parameter 606. For example, pulse 602_1 spans pulses 604E and 604E and pulses 606D and 606E.

[0150] In one embodiment, parameter 602 is a parameter of RF signal 178 and parameter 604 is a parameter of RF signal 172 .

[0151] In one embodiment, parameter 604 is a parameter of RF signal 184 and parameter 606 is a parameter of RF signal 178 .

[0152] In one embodiment, the pulsing frequency of any of the parameters 602-606 is different than that shown in FIG.

[0153] In one embodiment, the duty cycle of any of the parameters 602-606 is different than that shown in FIG.

[0154] 7 illustrates an embodiment of a system 700 including a source RF generator 102 connected to a TCP coil 124 and a bias RF generator 106 connected to a substrate support 122. System 700 is the same as system 101 of FIG. 1B, except that system 700 does not include source RF generator 104 and matcher 150 (FIG. 1A). System 700 also includes a matcher 108. An output 132 of source RF generator 102 is connected to an input 136 of matcher 108 via an RF cable 134, and an output 138 of matcher 108 is connected to the TCP coil 124 of plasma chamber 105 via an RF transmission line 140.

[0155] 1A. Furthermore, RF signal 184 is generated in the same manner as described above with respect to FIG. 1A. Upon receiving RF signal 184 via RF cable 134 and input 136, matcher 108 matches the impedance of a load connected to output 138 of matcher 108 to the impedance of a source connected to input 136 of matcher 108. Examples of loads connected to output 138 of matcher 108 include RF transmission line 140 and plasma chamber 105.

[0156] The matcher 108 modulates the impedance of the RF signal 184 by matching the impedance of a load connected to an output 138 of the matcher 108 with the impedance of a source connected to an input 136 of the matcher 108 to output a modulated RF signal 186 at the output 138. The modulated RF signal 186 is transmitted from the output 138 of the matcher 108 via an RF transmission line 140 to the TCP coil 124. Upon receiving the modulated RF signals 186 and 174 and one or more process gases, a plasma is ignited or sustained in a gap formed between the dielectric window 128 and the substrate support 122 of the plasma chamber 105.

[0157] Figures 8A-8D show embodiments of graphs for illustrating the operation of the system 700 of Figure 7. Figure 8A shows one embodiment of a graph 200 for illustrating the process recipe signal 169 of Figure 7. Figure 8B shows one embodiment of a graph 204 for illustrating parameters 206 of the RF signal 172 of Figure 7. The parameters 206 of the RF signal 172 are generated by the bias RF generator 106 of Figure 7 in synchronization with the synchronization signal 168.

[0158] Figure 8C shows an embodiment of a graph 208 for illustrating a digital pulse signal 210, which is an example of the process recipe signal 182 of Figure 7. Figure 8D shows an embodiment of a graph 212 for illustrating parameters 214 of the RF signal 184 of Figure 7. The parameters 214 of the RF signal 184 are generated by the source RF generator 102 of Figure 7 in synchronization with the digital pulse signal 210.

[0159] 9 illustrates one embodiment of a display screen 900 of host computer 114. Display screen 900 is of a display device connected to processor 118. Display screen 900 displays a field 901 for receiving an indication of whether TCP coils 124 or 126 (FIG. 1A) are operated synchronously or asynchronously with one another. As an example, TCP coil 124 operates asynchronously with the operation of TCP coil 126 when RF generators 102 and 104 operate asynchronously with one another. Illustratively, RF generators 102 and 104 are operating asynchronously with one another when RF generator 102 is on and RF generator 104 is off, or when RF generator 102 is off and RF generator 104 is on.

[0160] Display screen 900 displays a field 902 for receiving a bias frequency value (in Hertz) for operation of bias RF generator 106 (FIG. 1A). Display screen 900 also displays a field 904 for receiving a TCP frequency value for operation of RF generators 102 and 104 (FIG. 1A). Display screen 900 displays a field 906 for receiving a duty cycle (DC) percentage for bias RF generator 106. The DC percentage for bias RF generator 106 represents the time that bias RF generator 106 is on as a percentage of the total period of a cycle of synchronization signal 168 (FIG. 2A). For example, the DC percentage for bias RF generator 106 represents the period between times t0 and t4 (FIG. 2B) during which parameter 206 of bias RF generator 106 has parameter levels PRa and PR-a as a percentage of the period between times t0 and t8 of cycle 1 of synchronization signal 168. 2B, the DC percentage of RF signal 172 is 50%. As another example, the DC percentage of RF signal 172 may range from 10% to 90%. Illustratively, the DC percentage of RF signal 172 may be 20%.

[0161] The display screen 900 further displays a field 908 for receiving a DC percentage of the source RF generator 102 connected to the TCP coil 126 (FIG. 1A). The DC percentage of the source RF generator 102 represents the time that the source RF generator 102 is on, expressed as a percentage of the total duration of a cycle of the synchronization signal 168 (FIG. 2A). For example, the DC percentage of the source RF generator 102 represents the sum of the periods between times t0 and t2 (FIG. 2D) and between times t4 and t6 (FIG. 2D) during which the parameter 214 of the source RF generator 102 has parameter levels PRb and PR-b, expressed as a percentage of the period between times t0 and t8 of cycle 1 of the synchronization signal 168. As shown in FIG. 2D, the DC percentage of the RF signal 184 (FIG. 1A) is 50%. As another example, the DC percentage of the RF signal 184 ranges from 10% to 90%. Illustratively, the DC percentage of RF signal 172 is 30%.

[0162] The asynchronous or synchronous indication in field 901, the bias frequency value in field 902, the TCP frequency value in field 904, the bias DC percentage in field 906, and the source DC percentage in field 908 are received by processor 118 from a user via an input device (not shown) connected to processor 118. As an example, processor 902 controls fields 902-908 to enable the bias frequency value to be received first, the TCP frequency value to be received second, the bias DC percentage to be received third, and the source DC percentage to be received last. Examples of input devices include a mouse, a keyboard, a keypad, a touchpad, and a stylus.

[0163] Upon receiving the synchronous or asynchronous indication in field 901, the bias frequency value in field 902, the TCP frequency value in field 904, the bias DC percentage in field 906, and the source DC percentage in field 908, processor 118 fills in fields 910, 912, 914, 916, 918, 920, and 922 displayed on display screen 900. For example, upon receiving the asynchronous indication in field 901, the bias frequency value in field 902, the TCP frequency value in field 904, the bias DC percentage in field 906, and the source DC percentage in field 908, processor 118 determines the period of a cycle of operation of bias RF generator 106 (FIG. 1A) and enters the period in field 910 of display screen 900. Illustratively, processor 118 determines that the period of a cycle of RF signal 172 (FIG. 1A) is the ratio of 1 and the bias frequency value in field 902. As a further example, when the bias frequency value is 200, the period of a cycle of RF signal 172 is 5000 microseconds (μs).

[0164] Processor 118 further determines that bias RF generator 106 will remain on during one cycle of asynchronous operation of TCP coils 124 and 126 and will remain off during the remaining cycles of asynchronous operation of TCP coils 124 and 126, and enters the on time of bias RF generator 106 in field 912 of display screen 900 and the off time of bias RF generator 106 in field 914 of display screen 900. For example, processor 118 identifies a bias DC percentage of 20% from field 906, determines that 1000 microseconds is 20% of 5000 microseconds, and enters 1000 in field 906. Processor 118 further enters the difference between 5000 microseconds and 1000 microseconds, 4000 microseconds, in field 914.

[0165] During a cycle of asynchronous operation of TCP coils 124 and 126, processor 118 determines the duty cycle of operation of TCP coil 124 to be the difference between 100% and the source DC percentage in field 908 and enters the duty cycle in field 916 of display screen 900. For example, the duty cycle of operation of TCP coil 124 is 70%, which is the difference between 100% and 30%. The duty cycle of operation of TCP coil 124 is the same as the duty cycle of RF generator 104 or RF signal 178 (FIG. 1A).

[0166] As one example, the duty cycle of an RF generator or an RF signal generated by an RF generator is the time during which the RF signal has a positive parameter level during a cycle of synchronization signal 168 (FIG. 2A). During the remainder of the cycle of synchronization signal 168, the RF signal has a zero parameter level. As another example, the duty cycle of an RF generator or an RF signal generated by an RF generator is the time during which the RF signal has a first positive parameter level during a cycle of synchronization signal 168 (FIG. 2A). During the remainder of the cycle of synchronization signal 168, the RF signal has a second positive parameter level. The first positive parameter level is greater than the second positive parameter level.

[0167] 2D and 2F , the period of a cycle of operation of TCP coils 124 and 126 is between times t0 and t4, and the period of another cycle of operation of TCP coils 124 or 126 is between times t4 and t8. Illustratively, processor 118 enters 1000 microseconds (μs) into field 918, which is the ratio of 1 to the TCP frequency value in field 904. As a further example, 1000 μs is the total time that the parameter of RF signal 184 has a first positive parameter level and the parameter of RF signal 178 has a second positive parameter level during one cycle of asynchronous operation of TCP coils 124 and 126. The first positive parameter level is greater than the zero parameter level, which is the parameter level of the RF signal 184 during the remainder of the cycle of asynchronous operation of the TCP coils 124 and 126. The second positive parameter level is greater than the zero parameter level, which is the parameter level of the RF signal 178 during the remainder of the cycle of asynchronous operation of the TCP coils 124 and 126. In one embodiment, the positive parameter levels are used in place of the zero parameter levels in the above examples.

[0168] In yet another example, the processor 118 enters into field 920 the amount of time that the TCP coil 126 is on or active during a cycle of the synchronization signal 168. Illustratively, the processor 118 enters 700 μs into field 920, which corresponds to a 70% duty cycle. In another example, the processor 118 enters into field 922 the amount of time that the TCP coil 124 is on or active during a cycle of the synchronization signal 168. Illustratively, the processor 118 enters 300 μs into field 922, which corresponds to a 30% duty cycle.

[0169] In one embodiment, an RF generator off-time is a time during which the RF generator does not generate an RF signal or generates an RF signal having a zero parameter level. In one embodiment, an RF generator off-time is a time during which the RF generator generates an RF signal having a parameter level that is lower or less than the parameter level of the RF signal on-time.

[0170] In one embodiment, field 908 is a field for receiving the DC percentage of source RF generator 104 connected to TCP coil 124 (FIG. 1A). The DC percentage of source RF generator 104 is the time that source RF generator 104 is on, expressed as a percentage of the total duration of a cycle of synchronization signal 168 (FIG. 2A). For example, the DC percentage of source RF generator 104 is the sum of the periods between times t2 and t4 (FIG. 2F) and between times t6 and t8 (FIG. 2F) during which parameter 222 of RF signal 178 has parameter levels PRc and PR-c, expressed as a percentage of the period between times t0 and t8 of cycle 1 of synchronization signal 168. As shown in FIG. 2F, the DC percentage of RF signal 178 (FIG. 1A) is 50%.

[0171] FIG. 10A illustrates one embodiment of a plasma system 1000 for illustrating a multi-state RF generator 1002. The multi-state RF generator 1002 is an example of any of RF generators 102, 104, or 106 (FIG. 1A). The plasma system 1000 includes the RF generator 1002, a matcher 1004, and a host computer 114. The matcher 1004 is an example of any of matchers 108, 110, 112 (FIG. 1A), and 103 (FIG. 1B). For example, if the multi-state RF generator 1002 is the source RF generator 102, the matcher 1004 is an example of matcher 108 or 103. As another example, if the multi-state RF generator 1002 is the source RF generator 104, the matcher 1004 is an example of matcher 110 or 103. As yet another example, if multi-state RF generator 1002 is bias RF generator 106 , then matcher 1004 is an example of matcher 112 .

[0172] The multi-state RF generator 1002 includes a digital signal processor (DSP) 1004, a parameter controller 1018 for state S1, a parameter controller 1020 for state S0, a frequency controller (FC) 1022, a driver system DRVR, and a power supply 1006. An example of a digital signal processor is a microprocessor chip. A controller, as used herein, may be, for example, an application specific integrated circuit (ASIC), a programmable logic device (PLD), a central processing unit (CPU), a microprocessor, a microcontroller, or a processor, or may include a processor and a memory device. The processor of a controller is connected to the memory device of the controller. An example of a driver system, as used herein, includes one or more transistors connected to each other. Another example of a driver system, as used herein, includes one or more transistors connected to an amplifier and to each other. An example of a power supply, as used herein, includes an RF oscillator that generates a high-frequency sinusoidal signal, such as in the range of 400 kHz to 100 MHz.

[0173] Processor 118 is connected to DSP 1004 via cable system 1008. Cable system 1008 is an example of any of cable systems 130, 142, and 154 (FIG. 1A). For example, if RF generator 1002 is an example of RF generator 102, then cable system 1008 is an example of cable system 130. As another example, if RF generator 1002 is an example of RF generator 104, then cable system 1008 is an example of cable system 142. As yet another example, if RF generator 1002 is an example of RF generator 106, then cable system 1008 is an example of cable system 154.

[0174] The DSP 1004 is connected to a parameter controller 1018 and a parameter controller 1020. The DSP 1004 is also connected to a frequency controller 1022. The parameter controllers 1018 and 1020 and the frequency controller 1022 are connected to the driver system DRVR. The driver system DRVR is connected to the power supply 1006.

[0175] Power supply 1006 is connected to matcher 1004 via RF cable 1010. RF cable 1010 is an example of any of RF cables 134, 146, and 158 (FIG. 1A). For example, if RF generator 1002 is source RF generator 102 and matcher 1004 is matcher 108, RF cable 1010 is an example of RF cable 134. As another example, if RF generator 1002 is source RF generator 104 and matcher 1004 is matcher 110, RF cable 1010 is an example of RF cable 146. As yet another example, if RF generator 1002 is bias RF generator 106 and matcher 1004 is matcher 112, RF cable 1010 is an example of RF cable 158. As another example, if RF generator 1002 is source RF generator 102 and matcher 1004 is matcher 103, then RF cable 1010 is an example of RF cable 134 (FIG. 1B).

[0176] Processor 118 accesses parameter levels PRS1 and PRSII in memory device 120 and transmits parameter levels PRS1 and PRSII to DSP 1004 via cable system 1008. Memory device 120 stores parameter levels PRSI and PRSII. Parameter levels PRSI and PRSII are of RF signal 1014 generated by RF generator 1002. RF signal 1014 is an example of any of RF signals 172, 178, and 184 (FIG. 1A). For example, if RF generator 1002 is bias RF generator 106, RF signal 1014 is an example of RF signal 172. As another example, if RF generator 1002 is source RF generator 104, RF signal 1014 is an example of RF signal 178. As yet another example, if RF generator 1002 is source RF generator 102, RF signal 1014 is an example of RF signal 184.

[0177] The parameter level PRSI received by the DSP 1004 is for a first state (e.g., state S1 or state S0) of the process recipe signal 1024, and the parameter level PRSII received is for a second state (e.g., state S0 or state S1) of the process recipe signal 1024. Examples of received parameter level PRSI include parameter levels PRa and PR-a for state S1 of the process recipe signal 1024, parameter levels PRb and PR-b for state S1 of the process recipe signal 1024, parameters PRc and PR-c for state S1 of the process recipe signal 1024, and parameter level zero for state S0 of the process recipe signal 1024. Examples of parameter level PRSII include parameter level zero for state S0 of the process recipe signal 1024, parameter levels PRa and PR-a for state S1 of the process recipe signal 1024, parameters PRb and PR-b for state S1 of the process recipe signal 1024, and parameter levels PRc and PR-c for state S1 of the process recipe signal 1024. For example, if parameter level PRSI is for state S1 of process recipe signal 1024, parameter level PRSII is for state S0 of process recipe signal 1024, and if parameter level PRSI is for state S0 of process recipe signal 1024, parameter level PRSII is for state S1 of process recipe signal 1024.

[0178] DSP 1004 receives parameter levels for the first and second states of process recipe signal 1024 and provides the parameter levels to parameter controllers 1018 and 1020. For example, parameter level PRSI is sent from DSP 1004 to parameter controller 1018, and parameter level PRSII is sent from DSP 1004 to parameter controller 1020. Parameter level PRSI is stored in a memory device of parameter controller 1018, and parameter level PRSII is stored in a memory device of parameter controller 1020.

[0179] The processor 118 also transmits the operating frequency of the RF generator 1002 to the DSP 1004 via the cable system 1008. The operating frequency of the RF generator 1002 is the same as the frequency of the RF signal 1014. The frequency of the RF signal 1014 is greater than the pulsing frequency of the envelope of the RF signal 1014. For example, the frequency of the RF signal 1014 is greater than the pulsing frequency of the parameter of the RF signal 1014.

[0180] The DSP 1004 receives the operating frequency of the RF generator 1002 and transmits the frequency to the frequency controller 1022. The frequency controller 1022 stores the operating frequency of the RF generator 1002 in a memory device of the frequency controller 1022.

[0181] Processor 118 generates and transmits process recipe signal 1024 to DSP 1004 via cable system 1008. An example of process recipe signal 1024 is any of process recipe signals 169, 176, and 182 (FIG. 2A). Illustratively, if RF generator 1002 is an example of source RF generator 102, process recipe signal 1024 is an example of process recipe signal 182 (FIG. 1A). As another example, if RF generator 1002 is an example of source RF generator 104, process recipe signal 1024 is an example of process recipe signal 176 (FIG. 1A), and if RF generator 1002 is an example of bias RF generator 106, process recipe signal 1024 is an example of process recipe signal 169 (FIG. 1A).

[0182] The process recipe signal 1024 provides the parameter duty cycle and parameter pulsing frequency of the RF signal 1014 generated by the RF generator 1002. The DSP 1004 is programmed to receive the process recipe signal 1024 and execute the process recipe signal 1024 when a synchronization signal 168 is received from the processor 118.

[0183] The processor 118 transmits a synchronization signal 168 to the DSP 1004 via the cable system 1008. Upon receiving the synchronization signal 168, during a first cycle (e.g., cycle 1) of the synchronization signal 168, the DSP 1004 transmits an instruction to the power controller 1018 upon a transition from a second state (e.g., state S0 or state S1) of the process recipe signal 1024 to a first state (e.g., state S1 or state S0) of the process recipe signal 1024. The instruction is transmitted to the power controller 1018 in accordance with the process recipe signal 1024. Upon receiving the instruction from the DSP 1004, the power controller 1018 accesses the parameter level PRSI for the first state of the process recipe signal 1024 in its memory device, generates a command signal indicative of the parameter level PRSI, and transmits the command signal to the driver system DRVR.

[0184] Additionally, upon receiving the synchronization signal 168, the DSP 1004 sends instructions to the frequency controller FC. Upon receiving instructions from the DSP 1004, the frequency controller FC accesses the operating frequency of the RF generation 1002 in its memory device, generates a command signal indicative of the operating frequency, and sends the command signal to the driver system DRVR.

[0185] Upon receiving the command signal indicating the parameter level PRSI and the operating frequency, the driver system DRVR generates a current signal for a first state based on the parameter level PRSI and the frequency and transmits the current signal to the power supply 1006. In response to receiving the current signal for the first state, the power supply 1006 generates an RF signal 1014 having the parameter level PRSI and the frequency. The RF signal 1014 having the parameter level PRSI is generated at a transition from the second state of the process recipe signal 1024 during the first cycle of the synchronization signal 168 to the first state of the process recipe signal 1024 during the first cycle of the synchronization signal 168. Thus, the RF signal 1014 having the parameter level PRSI is generated by the transition from the first state of the process recipe signal 1024 during the second cycle of the synchronization signal 168 to the second state of the process recipe signal 1024 during the first cycle of the synchronization signal 168. The parameter level PRSI is generated by the transition time to define the duty cycle of the process recipe signal 1024.

[0186] Upon receiving the synchronization signal 168, the DSP 1004 sends a command to the power controller 1020 upon a transition from a first state of the process recipe signal 1024 during the first cycle of the synchronization signal 168 to a second state of the process recipe signal 1024 during the first cycle of the synchronization signal 168. Upon receiving the command from the DSP 1004, the power controller 1020 accesses the parameter level PRSII for the second state of the process recipe signal 1024 in the memory device of the power controller 1020, generates a command signal indicative of the parameter level PRSII, and sends the command signal to the driver system DRVR.

[0187] Upon receiving the command signal indicating the parameter level PRSII and the operating frequency, the driver system DRVR generates a current signal for the second state of the process recipe signal 1024 during the first cycle of the synchronization signal 168 based on the parameter level PRSII and the frequency and transmits the current signal to the power supply 1006. In response to receiving the current signal for the second state of the process recipe signal 1024 during the first cycle of the synchronization signal 168, the power supply 1006 generates an RF signal 1014 having the parameter level PRSII and the frequency. The RF signal 1014 having the parameter level PRSII and the frequency is generated upon a transition from the first state of the process recipe signal 1024 during the first cycle of the synchronization signal 168 to the second state of the process recipe signal 1024 during the first cycle of the synchronization signal 168. In this manner, an RF signal 1014 having parameter level PRSII is generated by the time a transition occurs from the second state of the process recipe signal 1024 during the second cycle of the synchronization signal 168 to the first state of the process recipe signal 1024 during the second cycle of the synchronization signal 168 to achieve the duty cycle of the process recipe signal 1024. In this manner, an RF signal 1014 that switches or transitions between parameter levels PRSI and PRSII is generated for each cycle of the synchronization signal 168 in accordance with the process recipe signal 1024.

[0188] FIG. 10B illustrates an embodiment of a plasma system 1050 to illustrate a continuous wave (CW) RF generator 1052. The CW RF generator 1052 is an example of any of RF generators 102, 104, or 106 (FIG. 1A). The plasma system 1050 includes the CW RF generator 1052, a matcher 1004, and a host computer 114. The matcher 1004 is an example of any of matchers 108, 110, 112 (FIG. 1A), and 103 (FIG. 1B). For example, if the CW RF generator 1052 is the source RF generator 102, the matcher 1004 is an example of matcher 108 or 103. As another example, if the CW RF generator 1052 is the source RF generator 104, the matcher 1004 is an example of matcher 110 or 103. As yet another example, if CW RF generator 1052 is bias RF generator 106 , then matcher 1004 is an example of matcher 112 .

[0189] CW RF generator 1052 includes DSP 1004, parameter controller 1054, frequency controller 1022, driver system DRVR, and power supply 1006. Cable system 1008 is an example of any of cable systems 130, 142, and 154 (FIG. 1A). For example, if RF generator 1052 is an example of RF generator 102, cable system 1008 is an example of cable system 130. As another example, if RF generator 1052 is an example of RF generator 104, cable system 1008 is an example of cable system 142. As yet another example, if RF generator 1052 is an example of RF generator 106, cable system 1008 is an example of cable system 154. DSP 1004 is connected to parameter controller 1054. Controller 1054 is connected to driver system DRVR.

[0190] DSP 1004 receives parameter level PRL from processor 118 via cable system 1008. Parameter level PRL is a parameter level of RF signal 1058 generated by CW RF generator 1052. RF signal 1058 is an example of any of RF signals 172, 178, and 184 (FIG. 1A). For example, if RF generator 1052 is bias RF generator 106, RF signal 1058 is an example of RF signal 172. As another example, if RF generator 1052 is source RF generator 104, RF signal 1058 is an example of RF signal 178. As yet another example, if RF generator 1052 is source RF generator 102, RF signal 1058 is an example of RF signal 184.

[0191] The received parameter level PRL is the parameter level for both the first and second states of the process recipe signal 1024 (FIG. 10A). For example, during the time period between times t0 and t8 when the RF signal 1014 (FIG. 10A) generated by the RF generator 1002 (FIG. 10A) has the parameter levels PRSI and PRS11, the RF signal 1058 generated by the RF generator 1052 has the parameter level PRL.

[0192] The DSP 1004 receives the parameter levels PRL for the first and second states of the process recipe signal 1024 and provides the parameter levels PRL to the parameter controller 1054. The parameter levels PRL are stored in a memory device of the parameter controller 1054. The processor 118 also transmits the operating frequency of the RF generator 1052 to the DSP 1004 via the cable system 1008, and the DSP 1004 transmits the frequency to the frequency controller 1022 for storage in the memory device of the frequency controller 1022.

[0193] The processor 118 transmits a synchronization signal 168 to the DSP 1004 via the cable system 1008. Upon receiving the synchronization signal 168, during a first cycle (e.g., cycle 1) of the synchronization signal 168, the DSP 1004 transmits an instruction to the power controller 1054. Upon receiving the instruction from the DSP 1004, the power controller 1054 accesses the parameter levels PRL for the first and second state process recipe signals 1024 in the memory device of the power controller 1054, generates a command signal indicative of the parameter levels PRL, and transmits the command signal to the driver system DRVR.

[0194] Additionally, upon receiving the synchronization signal 168, the DSP 1004 sends instructions to the frequency controller FC. Upon receiving instructions from the DSP 1004, the frequency controller FC accesses the operating frequency of the RF generation 1002 in its memory device, generates a command signal indicative of the operating frequency, and sends the command signal to the driver system DRVR.

[0195] Upon receiving the command signal indicating the parameter level PRL and the operating frequency, the driver system DRVR generates current signals for the first and second states of the process recipe signal 1024 based on the parameter level PRL and the frequency and transmits the current signals to the power supply 1006. In response to receiving the current signals for the first and second states of the process recipe signal 1024, the power supply 1006 generates an RF signal 1058 having the parameter level PRL and frequency. The RF signal 1058 having the parameter level PRL and frequency is generated during the first cycle of the synchronization signal 168. In this manner, the RF signal 1058 remaining at the parameter level PRL is generated for each cycle of the synchronization signal 168.

[0196] The embodiments described herein may be practiced with various computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, etc. Embodiments may also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a network.

[0197] In some embodiments, the controller is part of a system, which may be part of the examples described above. Such systems include semiconductor processing equipment, such as one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (e.g., wafer pedestals, gas flow systems, etc.). These systems are integrated with electronics for controlling the operation of the system before, during, and after processing of semiconductor wafers or substrates. The electronics may be referred to as a "controller" and may control various components or subcomponents of one or more systems. Depending on the processing requirements and / or type of system, the controller is programmed to control any of the processes disclosed herein, such as supply of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid supply settings, position and motion settings, and wafer movement in and out of load locks connected or coupled to the tool and other moving tools and / or systems.

[0198] Generally, in various embodiments, a controller is defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. Integrated circuits include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions are instructions that are communicated to the controller in the form of various individual settings (or program files) to define parameters, factors, variables, etc., for or to a system to perform a particular process on or for a semiconductor wafer. Program instructions, in some embodiments, are part of a recipe defined by a process engineer to accomplish one or more process steps during processing of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0199] In some embodiments, the controller is part of or connected to a computer that is integrated with, connected to, or otherwise networked with the system, or a combination thereof. For example, the controller may be in the "cloud" or all or part of a fab host computer system that enables remote access of wafer processing. The computer enables remote access to the system to change parameters of a current process, set process steps according to a current process, or initiate a new process, monitor the current progress of a manufacturing operation, examine the history of past manufacturing operations, or examine trends or performance indicators from multiple manufacturing operations.

[0200] In some embodiments, a remote computer (e.g., a server) provides process recipes to the system over a network (including a local network or the Internet). The remote computer includes a user interface that allows for entry or programming of parameters and / or settings, which are communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of data, which specify parameters, factors, and / or variables for each of the process steps performed during one or more operations. It should be understood that the parameters, factors, and / or variables are specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Thus, as described above, the controller is distributed, such as by having one or more separate controllers that are networked and operate toward a common purpose (such as the process and control described herein). One example of a distributed controller for such purposes includes one or more integrated circuits on the chamber that communicate with one or more remotely located integrated circuits (e.g., located at the platform level or remotely as part of a remote computer) that cooperate to control the process at the chamber.

[0201] In various embodiments, examples of systems to which the methods described herein may be applied include, but are not limited to, plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing systems that may be associated with or utilized in the fabrication and / or manufacturing of semiconductor wafers.

[0202] It should also be noted that in some embodiments, the operations described above apply to several types of plasma chambers, such as plasma chambers with inductively coupled plasma (ICP) reactors, transformer-coupled plasma chambers, plasma chambers with conductor tools, dielectric tools, electron cyclotron resonance (ECR) reactors, capacitively coupled plasma (CCP) plasma chambers, etc. For example, one or more RF generators are connected to an inductor in an ICP reactor. Examples of inductor shapes include a solenoid, a dome-shaped coil, a planar coil, etc.

[0203] As described above, depending on the processing step or steps being performed by the tool, the host computer communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to carry containers of wafers to or from tool locations and / or load ports within the semiconductor fabrication factory.

[0204] With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These operations are operations that physically manipulate physical quantities. Any of the operations described herein that form part of the present embodiments are useful machine operations.

[0205] Some embodiments further relate to hardware units or apparatus for performing these operations, where the apparatus is specifically configured for a special purpose computer. When defined as a special purpose computer, the computer can operate for a specific purpose while performing other processes, program execution, or routines not included in the specific purpose.

[0206] In some embodiments, operations may be processed on a computer selectively activated or configured by one or more computer programs stored in computer memory, cache, or obtained over a computer network. When data is obtained over a computer network, the data may be processed by other computers on the computer network (e.g., a cloud of computing resources).

[0207] One or more embodiments may be fabricated as computer-readable code on a non-transitory computer-readable medium. The non-transitory computer-readable medium is any data storage hardware unit (e.g., a memory device) that stores data, which is then read by a computer system. Examples of non-transitory computer-readable media include hard drives, network-attached storage (NAS), ROM, RAM, compact disc-ROMs (CD-ROMs), CD-recordables (CD-Rs), CD-rewritables (CD-RWs), magnetic tapes, and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer-readable medium comprises a tangible computer-readable medium distributed over network-connected computer systems such that the computer-readable code is stored and executed in a distributed manner.

[0208] Although the method operations described above are presented in a particular order, it should be understood that in various embodiments, other housekeeping processes may be performed between operations, or the method operations may be performed at slightly different times, may be distributed across a system that allows method operations to occur at various intervals, or may be arranged to be performed in an order different from that described above.

[0209] Furthermore, it should be noted that in one embodiment, one or more features of any embodiment described herein may be combined with one or more features of any other embodiment without departing from the scope described in the various embodiments described in this disclosure.

[0210] Although the present embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. The present embodiments are therefore to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims

1. 1. A method for pulsing, comprising: generating a first radio frequency (RF) signal; pulsing a parameter of the first RF signal between a first parameter level and a second parameter level at a pulsing frequency during a cycle of a digital pulse signal; generating a second RF signal; pulsing the parameter of the second RF signal at a pulse frequency higher than the pulse frequency of the parameter of the first RF signal during the cycle; Equipped with wherein during the cycle, a start time of the step of pulsing the parameter of the first RF signal is synchronized with a start time of the step of pulsing the parameter of the second RF signal, and an end time of the step of pulsing the parameter of the first RF signal is synchronized with an end time of the step of pulsing the parameter of the second RF signal.

2. 10. The method of claim 1, wherein the first parameter level of the first RF signal is greater than the second parameter level of the first RF signal, the parameter of the second RF signal is pulsed between a first parameter level and a second parameter level, and the first parameter level of the second RF signal is greater than the second parameter level of the second RF signal.

3. 2. The method of claim 1, wherein the second parameter level of the first RF signal is substantially zero.

4. 2. The method of claim 1, wherein the pulsing frequency of the parameter of the second RF signal is an integer multiple of the pulsing frequency of the parameter of the first RF signal to achieve the synchronization between the start time and the end time.

5. 2. The method of claim 1, wherein the start time is synchronized to a time when the parameter of the first RF signal transitions from the second parameter level to the first parameter level concurrently with a transition of the parameter of the second RF signal from the second parameter level to the first parameter level during the cycle, and the end time is synchronized to a time when the parameter of the first RF signal transitions from the second parameter level to the first parameter level concurrently with a transition of the parameter of the second RF signal from the second parameter level to the first parameter level during the cycle.

6. 10. The method of claim 1 further comprising: providing the first RF signal to a first impedance matching circuit connected to a substrate support; providing the second RF signal to a second impedance matching circuit connected to an RF coil; A method comprising:

7. 10. The method of claim 1 further comprising: generating a third RF signal; pulsing a parameter of the third RF signal between a first parameter level and a second parameter level during the cycle; Equipped with wherein during the cycle, a start time of the step of pulsing the parameter of the third RF signal is synchronized with the start time of the step of pulsing the parameter of the first RF signal, and an end time of the step of pulsing the parameter of the third RF signal is synchronized with the end time of the step of pulsing the parameter of the first RF signal.

8. 8. The method of claim 7, the start time of the parameter of the third RF signal is synchronized with the start time of the parameter of the first RF signal when the parameter of the third RF signal transitions from the first parameter level to the second parameter level simultaneously with the transition of the parameter of the first RF signal from the second parameter level to the first parameter level; the end time of the parameter of the third RF signal is synchronized with the end time of the parameter of the first RF signal when the parameter of the third RF signal transitions from the first parameter level to the second parameter level simultaneously with the transition of the parameter of the first RF signal from the second parameter level to the first parameter level.

9. a controller, a processor configured to control a first radio frequency (RF) generator to generate a first RF signal; the first RF generator is configured to pulse a parameter of the first RF signal between a first parameter level and a second parameter level at a pulsing frequency during a cycle of a digital pulse signal; the processor is configured to control a second RF generator to generate a second RF signal, the second RF generator being configured to pulse a parameter of the second RF signal at a pulsing frequency that is higher than the pulsing frequency of the parameter of the first RF signal during the cycle; a processor, wherein a start time at which the parameter of the first RF signal is pulsed is synchronized with a start time at which the parameter of the second RF signal is pulsed, and an end time at which the parameter of the first RF signal is pulsed is synchronized with an end time at which the parameter of the second RF signal is pulsed; a memory device coupled to the processor for storing the first and second parameter levels of the first RF signal; A controller comprising:

10. 10. The controller of claim 9, wherein the first parameter level of the first RF signal is greater than the second parameter level of the first RF signal, the second RF generator is configured to pulse the second RF signal between a first parameter level and a second parameter level, and the first parameter level of the second RF signal is greater than the second parameter level of the second RF signal.

11. 10. The controller of claim 9, wherein the second parameter level of the first RF signal is substantially zero.

12. 10. The controller of claim 9, wherein the pulsing frequency of the parameter of the second RF signal is an integer multiple of the pulsing frequency of the parameter of the first RF signal to achieve the synchronization between the start time and the end time.

13. 10. The controller of claim 9, wherein the start time is synchronized with a transition of the parameter of the first RF signal from the second parameter level to the first parameter level during the cycle simultaneously with a transition of the parameter of the second RF signal from the second parameter level to the first parameter level, and the end time is synchronized with a transition of the parameter of the first RF signal from the second parameter level to the first parameter level during the cycle simultaneously with a transition of the parameter of the second RF signal from the second parameter level to the first parameter level.

14. 10. The controller of claim 9, wherein the first RF generator is configured to supply the first RF signal to a first impedance matching circuit connected to a substrate support, and the second RF generator is configured to supply the second RF signal to a second impedance matching circuit connected to an RF coil.

15. 10. The controller of claim 9, wherein the processor is configured to control a third RF generator to generate a third RF signal, the third RF generator being configured to pulse a parameter of the third RF signal between a first parameter level and a second parameter level during the cycle, wherein during the cycle, a start time at which the parameter of the third RF signal is pulsed is synchronized with the start time at which the parameter of the first RF signal is pulsed and an end time at which the parameter of the third RF signal is pulsed is synchronized with the end time at which the parameter of the first RF signal is pulsed.

16. 16. The controller of claim 15, the start time of the parameter of the third RF signal is synchronized with the start time of the parameter of the first RF signal when the parameter of the third RF signal transitions from the first parameter level to the second parameter level simultaneously with the transition of the parameter of the first RF signal from the second parameter level to the first parameter level; the end time of the parameter of the third RF signal is synchronized with the end time of the parameter of the first RF signal when the parameter of the third RF signal transitions from the first parameter level to the second parameter level simultaneously with the transition of the parameter of the first RF signal from the second parameter level to the first parameter level.

17. 1. A plasma system for pulsing, comprising: a first radio frequency (RF) generator configured to generate a first RF signal; a first RF generator configured to pulse a parameter of the first RF signal between a first parameter level and a second parameter level at a pulsing frequency during cycles of a digital pulse signal; a second RF generator configured to generate a second RF signal, the second RF generator is configured to pulse a parameter of the second RF signal at a pulsing frequency that is higher than the pulsing frequency of the parameter of the first RF signal during the cycle; a second RF generator, wherein during the cycle, a start time at which the parameter of the first RF signal is pulsed is synchronized with a start time at which the parameter of the second RF signal is pulsed and an end time at which the parameter of the first RF signal is pulsed is synchronized with an end time at which the parameter of the second RF signal is pulsed; A plasma system comprising:

18. 18. The plasma system of claim 17, wherein the first RF generator is configured to transition the parameter of the first RF signal from the second parameter level to the first parameter level simultaneously with the transition of the parameter of the second RF signal from the second parameter level to the first parameter level to synchronize the start times during the cycle; the first RF generator is configured to transition the parameter of the first RF signal from the second parameter level to the first parameter level simultaneously with the transition of the parameter of the second RF signal from the second parameter level to the first parameter level to synchronize the end times during the cycle.

19. 18. The plasma system of claim 17, further comprising: a first impedance matching circuit connected to the first RF generator, the first impedance matching circuit configured to receive the first RF signal, modulate the impedance of the first RF signal, and output a first modulated RF signal; a plasma chamber having an RF coil and a substrate support, the substrate support connected to the first impedance match circuit to receive the first modulated RF signal; a second impedance matching circuit coupled to the second RF generator, the second impedance matching circuit configured to receive the second RF signal, modulate the impedance of the second RF signal, and output a second modulated RF signal; a second impedance matching circuit, the RF coil connected to the second impedance matching circuit to receive the second modulated RF signal; A plasma system comprising:

20. 18. The plasma system of claim 17, further comprising: a third RF generator configured to generate a third RF signal, the third RF generator is configured to pulse a parameter of the third RF signal between a first parameter level and a second parameter level during the cycle; a third RF generator configured to synchronize, during the cycle, a start time at which the parameter of the third RF signal is pulsed with the start time at which the parameter of the first RF signal is pulsed and to synchronize an end time at which the parameter of the third RF signal is pulsed with the end time at which the parameter of the first RF signal is pulsed.

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