Image pickup device

Abstract

To provide an imaging element for simultaneously processing signals output from photodiodes at high speed.SOLUTION: The imaging element includes a photoelectric conversion layer having a first substrate including a first photoelectric conversion unit, a second photoelectric conversion unit, and a third photoelectric conversion unit, a second substrate including a first conversion unit, a second conversion unit, and a third conversion unit, a first circuit layer having a first connection layer, a second circuit layer having a third substrate including a first control unit, a second control unit, and a third control unit, and a connection unit for electrically connecting a first wiring which is a wiring electrically connected to a first through electrode penetrating the third substrate and is different from the first through electrode, and a second wiring which is a wiring electrically connected to a second through electrode penetrating the third substrate and is different from the second through electrode. And a first connection portion having electrode pads disposed to face each other in a direction in which the first circuit layer and the second circuit layer are laminated.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an imaging device. [Background technology]

[0002] An imaging element is known that is configured by stacking a first semiconductor chip having a photodiode, a second semiconductor chip having an analog / digital conversion unit, and a third semiconductor chip having a memory element (Patent Document 1). However, with the conventional technology, it was not possible to simultaneously process signals output from the photodiodes at high speed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2014-195112 Summary of the Invention

[0004] According to a first aspect of the present invention, an imaging element includes a photoelectric conversion layer having a first substrate including a first photoelectric conversion unit that converts light into electric charges, a second photoelectric conversion unit that converts light into electric charges and that is arranged side by side with the first photoelectric conversion unit in a first direction, and a third photoelectric conversion unit that converts light into electric charges and that is arranged side by side with the first photoelectric conversion unit in a second direction that intersects with the first direction; a second substrate that is a circuit layer stacked with the photoelectric conversion layer and includes a first conversion unit that converts a first signal based on the electric charges converted by the first photoelectric conversion unit into a digital signal, a second conversion unit that converts a second signal based on the electric charges converted by the second photoelectric conversion unit into a digital signal, and a third conversion unit that converts a third signal based on the electric charges converted by the third photoelectric conversion unit into a digital signal; and a first wiring that penetrates the second substrate and is electrically connected to a first through electrode and is different from the first through electrode. a third substrate, which is a circuit layer stacked on the first circuit layer and includes a first control unit for performing a first arithmetic operation on a first digital signal converted from the first signal to a digital signal by the first conversion unit, a second control unit for performing a second arithmetic operation on a second digital signal converted from the second signal to a digital signal by the second conversion unit, and a third control unit for performing a third arithmetic operation on a third digital signal converted from the third signal to a digital signal by the third conversion unit; a second circuit layer having a second connection layer including a wiring electrically connected to a second through electrode that penetrates the third substrate, the second wiring being different from the second through electrode; and a first connection unit for electrically connecting the first wiring and the second wiring, the first connection unit having electrode pads arranged to face each other in the direction in which the first circuit layer and the second circuit layer are stacked. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a block diagram showing the configuration of an imaging apparatus according to a first embodiment. [Figure 2] FIG. 1 is a diagram showing a cross-sectional structure of an image sensor according to a first embodiment. [Figure 3] FIG. 1 is a block diagram showing the configuration of an imaging element according to a first embodiment. [Figure 4] FIG. 2 is a circuit diagram showing the configuration of a pixel according to the first embodiment. [Figure 5] FIG. 2 is a block diagram showing the detailed configuration of the imaging element according to the first embodiment. [Figure 6] 2A to 2C are diagrams showing a method for manufacturing an image sensor according to the first embodiment. [Figure 7] 2A to 2C are diagrams showing a method for manufacturing an image sensor according to the first embodiment. [Figure 8] FIG. 10 is a block diagram showing the configuration of an imaging element according to a second embodiment. [Figure 9] FIG. 10 is a block diagram showing the detailed configuration of an imaging element according to a second embodiment. [Figure 10] FIG. 10 is a block diagram showing the configuration of an AD conversion unit of an image sensor according to a third embodiment. [Figure 11] FIG. 10 is a diagram showing a cross-sectional structure of an imaging element according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0006] (First embodiment) FIG. 1 is a block diagram showing the configuration of an imaging device according to a first embodiment. The imaging device 1 includes a photographing optical system 2, an imaging element 3, and a control unit 4. The imaging device 1 is, for example, a camera. The photographing optical system 2 forms a subject image on the imaging element 3. The imaging element 3 captures the subject image formed by the photographing optical system 2 and generates an image signal. The imaging element 3 is, for example, a CMOS image sensor. The control unit 4 outputs a control signal to the imaging element 3 for controlling the operation of the imaging element 3. The control unit 4 also functions as an image generation unit that performs various image processes on the image signal output from the imaging element 3 and generates image data. The photographing optical system 2 may be detachable from the imaging device 1.

[0007] FIG. 2 is a diagram showing a cross-sectional structure of an image sensor according to the first embodiment. The image sensor 3 shown in FIG. 2 is a back-illuminated image sensor. The image sensor 3 includes a first substrate 111, a second substrate 112, a third substrate 113, and a fourth substrate 114. The first substrate 111, the second substrate 112, the third substrate 113, and the fourth substrate 114 are each formed of a semiconductor substrate or the like. The first substrate 111 is stacked on the second substrate 112 via wiring layers 140 and 141. The second substrate 112 is stacked on the third substrate 113 via inter-substrate connection layers 142 and 143. The third substrate 113 is stacked on the fourth substrate 114 via wiring layers 144 and 145. Incident light L, indicated by the outline arrow, is incident in the positive direction of the Z axis. As shown in the coordinate axes, the right direction on the paper, which is perpendicular to the Z axis, is the positive X direction, and the front direction on the paper, which is perpendicular to the Z axis and the X axis, is the positive Y direction. The imaging element 3 has a first substrate 111, a second substrate 112, a third substrate 113, and a fourth substrate 114 stacked in the direction in which incident light L is incident.

[0008] The imaging element 3 further has a microlens layer 101, a color filter layer 102, and a passivation layer 103. The passivation layer 103, the color filter layer 102, and the microlens layer 101 are sequentially stacked on a first substrate 111. The microlens layer 101 has a plurality of microlenses ML. The microlenses ML focus incident light onto a photoelectric conversion unit 12, which will be described later. The color filter layer 102 has a plurality of color filters F. The passivation layer 103 is made of a nitride film or an oxide film.

[0009] First substrate 111, second substrate 112, third substrate 113, and fourth substrate 114 each have a first surface 105a, 106a, 107a, or 108a on which electrodes such as gate electrodes and gate insulating films are provided, and a second surface 105b, 106b, 107b, or 108b different from the first surface. Various elements such as transistors having the gate electrodes described above are provided on each of first surfaces 105a, 106a, 107a, or 108a. Wiring layers 140, 141, 144, and 145 are stacked and provided on first surface 105a of first substrate 111, first surface 106a of second substrate 112, first surface 107a of third substrate 113, and first surface 108a of fourth substrate 114, respectively. Furthermore, inter-substrate connection layers 142 and 143 are respectively laminated on second surface 106b of second substrate 112 and second surface 107b of third substrate 113. Wiring layers 140, 141, 144, and 145 and inter-substrate connection layers 142 and 143 are layers including a conductor film (metal film) and an insulating film, and wiring, vias, and the like are respectively arranged therein.

[0010] Various elements such as transistors provided on first surface 105a of first substrate 111 and various elements such as transistors provided on first surface 106a of second substrate 112 are electrically connected to each other by connecting portions 151, 152 such as bumps or electrodes (e.g., pads) via wiring layers 140, 141. Similarly, various elements such as transistors provided on first surface 107a of third substrate 113 and various elements such as transistors provided on first surface 108a of fourth substrate 114 are electrically connected to each other by connecting portions 155, 156 such as bumps or electrodes via wiring layers 144, 145. Furthermore, second substrate 112 and third substrate 113 each have a plurality of through electrodes 118, 119 such as silicon through electrodes. Through electrode 118 of second substrate 112 connects the circuits provided on first surface 106a and second surface 106b of second substrate 112 to each other, and through electrode 119 of third substrate 113 connects the circuits provided on first surface 107a and second surface 107b of third substrate 113 to each other. In addition, in a plane (XY plane) intersecting the direction of light incidence, connection portion 153 has an area larger than that of through electrode 118, and connection portion 154 has an area larger than that of connection portion 119. This makes it easier for through electrode 118 and through electrode 119 to be electrically connected when the second substrate and the third substrate are stacked. In other words, when the second substrate and the third substrate are stacked, it becomes easier to align the substrates to electrically connect through electrode 118 and through electrode 119. The circuit provided on second surface 106b of second substrate 112 and the circuit provided on second surface 107b of third substrate 113 are electrically connected by connecting parts 153, 154 such as bumps or electrodes via inter-substrate connecting layers 142, 143. Connecting parts 151 to 156 are made of, for example, metal and are metal films or the like.

[0011] The first substrate 111, the second substrate 112, the third substrate 113, and the fourth substrate 114 are also referred to as the semiconductor layer, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer, respectively. The semiconductor layer 111, the wiring layer 140, the connection portion 151, and the passivation layer 103 constitute a photoelectric conversion layer 161. The first semiconductor layer 112, the wiring layer 141, the inter-substrate connection layer 142, and the connection portions 152 and 153 constitute a first circuit layer 162. The second semiconductor layer 113, the wiring layer 144, the inter-substrate connection layer 143, and the connection portions 154 and 155 constitute a second circuit layer 163. The third semiconductor layer 114, the wiring layer 145, and the connection portion 156 constitute a third circuit layer 164.

[0012] FIG. 3 is a block diagram showing the configuration of an image sensor according to the first embodiment. A first substrate 111 has a plurality of pixels 10 arranged two-dimensionally. The pixels 10 are arranged in the X-axis direction and the Y-axis direction shown in FIG. 2. The pixels 10 output photoelectric conversion signals and noise signals (described later) to a second substrate 112. The second substrate 112 has a plurality of analog-to-digital conversion units (AD conversion units) 100. The AD conversion unit 100 is provided for each pixel 10 and is composed of a comparator circuit, a latch circuit, etc. The AD conversion units 100 sequentially convert the photoelectric conversion signals and noise signals output from the pixels 10 into digital signals. The digital signals converted by the AD conversion units 100 are output to a fourth substrate 114 via a third substrate 113.

[0013] The fourth substrate 114 has a plurality of ALUs (Arithmetic and Logic Units), i.e., arithmetic units 80. An arithmetic unit 80 is provided for each pixel 10, and performs signal processing such as correlated double sampling (CDS) by subtracting a digital signal of a photoelectric conversion signal from a digital signal of a noise signal, and calculations between signals generated for each pixel 10. The arithmetic units 80 are configured to include an adder circuit, a subtractor circuit, a flip-flop circuit, a shift circuit, and the like. The arithmetic units 80 are connected to each other via signal lines, switches SW, and the like.

[0014] The third substrate 113 has an ALU control unit 70 (hereinafter referred to as the control unit 70) that controls the arithmetic units 80. The control unit 70 is provided for each pixel 10, and outputs control signals to the arithmetic units 80 and switches SW, etc., arranged on the fourth substrate 114, to control the content of the calculations performed by the arithmetic units 80. For example, the control unit 70 selects pixel signals by controlling to turn on predetermined switches SW, and the arithmetic units 80 corresponding to this control unit 70 perform arithmetic processing on the signals of the selected multiple pixels.

[0015] Each of the pixels 10 and the AD conversion unit 100 is composed of a plurality of transistors, etc. Gate electrodes of the transistors included in the pixels 10 are provided on a first surface 105a of the first substrate 111 shown in FIG. 2, and gate electrodes of the transistors included in the AD conversion unit 100 are provided on a first surface 106a of the second substrate 112. Each of the control unit 70 and the arithmetic unit 80 is composed of a plurality of transistors, etc. Gate electrodes of the transistors included in the control unit 70 are provided on a first surface 107a of the third substrate 113 shown in FIG. 2, and gate electrodes of the transistors included in the arithmetic unit 80 are provided on a first surface 108a of the fourth substrate 114.

[0016] In this embodiment, the image sensor 3 is configured by laminating a photoelectric conversion layer 161 in which the pixels 10 are provided, a first circuit layer 162, a second circuit layer 163, and a third circuit layer 164. Therefore, circuits and the like for processing signals from the pixels 10 can be separately arranged in the first circuit layer 162, the second circuit layer 163, and the third circuit layer 164, which are different from the photoelectric conversion layer 161. As a result, multiple circuits and the like for processing signals from the pixels 10 can be arranged without increasing the chip area. Furthermore, a decrease in the aperture ratio of the pixels 10 can be prevented.

[0017] The first surface 105a on which the gate electrodes of the photoelectric conversion layer 161 are provided and the first surface 106a on which the gate electrodes of the first circuit layer 162 are provided are stacked opposite each other, and the first surface 107a on which the gate electrodes of the second circuit layer 163 are provided and the first surface 108a on which the gate electrodes of the third circuit layer 164 are provided are stacked opposite each other. Therefore, the circuits provided in the photoelectric conversion layer 161 and the circuits provided in the first circuit layer 162 can be electrically connected via, for example, multiple bumps. Because the connection is made using bumps, which can be formed at a narrower pitch than when through-electrodes are generally formed, multiple signals from each pixel 10 in the photoelectric conversion layer 161 can be simultaneously transmitted to the first circuit layer 162. Similarly, multiple signals can be transmitted from the second circuit layer 163 to the third circuit layer 164. 2, in this embodiment, it is possible to form a larger number of connection portions 151, 152, 155, and 156 than the number of through electrodes 118 and 119. Furthermore, in the imaging element 3, it is possible to form a larger number of connection portions 151, 152, 155, and 156 than the number of connection portions 153 and 154. It is also possible to provide more connection portions 151 and 152 than connection portions 153 and 154, and it is also possible to provide more connection portions 155 and 156 than connection portions 153 and 154. In the imaging element 3, a plurality of connection portions 151, 152, 155, and 156 are provided depending on the number of circuits and wirings provided on the first to fourth substrates 111 to 114.

[0018] In this embodiment, each pixel 10 on the first substrate 111 and each AD conversion unit 100 on the second substrate 112 can be connected via multiple bumps. This allows signals from each pixel 10 to be simultaneously output to the AD conversion unit 100 provided for each pixel 10. This allows AD conversion to be performed simultaneously in each AD conversion unit 100. In addition, the control unit 70 on the third substrate 113 supplies a control signal to the arithmetic unit 80 on the fourth substrate 114 from the Z-axis direction shown in FIG. 2 to control the arithmetic unit 80. This allows arithmetic to be performed on the signal of any pixel 10 without increasing the chip area of ​​the image sensor 3.

[0019] In the technology described in Patent Document 1, two through electrodes connecting circuits provided on different substrates are joined so as to abut against each other. This requires a wide pitch to form long through electrodes that penetrate two substrates, making it difficult to provide a large number of through electrodes. Furthermore, the need to form two through electrodes at the same position imposes constraints on the layout within the substrate. In this embodiment, the circuit of the first circuit layer 162 and the circuit of the second circuit layer 163 are connected via through electrodes 118 and 119, inter-substrate connection layers 142 and 143, and connection portions 153 and 154. Because the through electrodes 118 and 119 are connected via the inter-substrate connection layers 142 and 143 and connection portions 153 and 154, the through electrodes 118 and 119 can be provided in different positions. Furthermore, this eliminates the need to form long through electrodes that penetrate two substrates, preventing a decrease in the yield of the image sensor and an increase in chip area.

[0020] 4 is a circuit diagram showing the configuration of a pixel of the image sensor according to the first embodiment. The pixel 10 has a photoelectric conversion unit 12, such as a photodiode (PD), and a readout unit 20. The photoelectric conversion unit 12 converts incident light into electric charges and accumulates the photoelectrically converted electric charges. The readout unit 20 has a transfer unit 13, a discharge unit 14, a floating diffusion (FD) 15, an amplifier unit 16, and a current source 17.

[0021] The transfer unit 13 is controlled by a signal Vtx and transfers the charges photoelectrically converted by the photoelectric conversion unit 12 to the floating diffusion 15. That is, the transfer unit 13 forms a charge transfer path between the photoelectric conversion unit 12 and the floating diffusion 15. The floating diffusion 15 holds (accumulates) the charges. The amplifier 16 amplifies a signal based on the charges held in the floating diffusion 15 and outputs it to a signal line 18. In the example shown in FIG. 4, the amplifier 16 is configured by a transistor M3 whose drain terminal, gate terminal, and source terminal are connected to a power supply VDD, the floating diffusion 15, and a current source 17, respectively.

[0022] The discharge unit (reset unit) 14 is controlled by a signal Vrst to discharge the charge in the floating diffusion 15 and reset the potential of the floating diffusion 15 to a reset potential (reference potential). The transfer unit 13 and the discharge unit 14 are configured by, for example, a transistor M1 and a transistor M2, respectively. The gate electrodes of the transistors M1 to M3 are provided on the first surface 105a of the first substrate 111 shown in FIG. 2.

[0023] The readout unit 20 sequentially reads out to the signal line 18 a signal (photoelectric conversion signal) corresponding to the charge transferred from the photoelectric conversion unit 12 to the floating diffusion 15 by the transfer unit 13 and a dark signal (noise signal) obtained when the potential of the floating diffusion 15 is reset to the reset potential. Note that the pixel configuration shown in FIG. 4 is just an example, and different configurations can be adopted. Furthermore, some of the multiple transistors that make up the pixel may be arranged on a substrate different from the first substrate 111.

[0024] 5 is a block diagram showing the detailed configuration of the image sensor according to the first embodiment. The image sensor 3 includes a plurality of pixels 10, a timing generator 200, a DA converter 210, a global counter 220, a shift register 230, a VSCAN circuit (vertical scanning circuit) 240, an HSCAN circuit (horizontal scanning circuit) 250, a sense amplifier 300, a line memory 310, and an input / output unit 320. The image sensor 3 further includes an AD converter 100, a control unit 70, an arithmetic unit 80, a memory unit 83, a demultiplexer 81, a demultiplexer 84, and a multiplexer 85. The AD converter 100 includes a comparator 30, a memory unit 40, and a demultiplexer 43. The memory unit 40 includes a signal memory unit 41 for storing a digital signal corresponding to the photoelectric conversion signal and a noise memory unit 42 for storing a digital signal corresponding to the noise signal. The signal storage unit 41 and the noise storage unit 42 are each composed of a plurality of latch circuits corresponding to the number of bits of the signal to be stored. For example, the signal storage unit 41 and the noise storage unit 42 are each composed of 12 latch circuits, and the digital signals stored in the signal storage unit 41 and the noise storage unit 42 are each 12-bit parallel signals.

[0025] The first layer of the image sensor 3, i.e., the first substrate 111, is provided with the pixels 10 and a portion of the timing generator 200. The timing generator 200 is composed of multiple circuits, which are arranged on the first to fourth substrates 111 to 114. In FIG. 5, the first substrate 111, the second substrate 112, the third substrate 113, and the fourth substrate 114 are referred to as the first layer, the second layer, the third layer, and the fourth layer, respectively. The circuits that make up the timing generator 200 are arranged on the periphery of an area in which the pixels 10, the AD conversion section 100, the control section 70, and the arithmetic unit 80 are arranged. The second layer, i.e., the second substrate 112, is provided with the comparison section 30, the signal storage section 41, the noise storage section 42, the demultiplexer 43, the DA conversion section 210, the global counter 220, the shift register 230, and a portion of the timing generator 200.

[0026] The third substrate 113 is provided with the control unit 70, the VSCAN circuit 240, the HSCAN circuit 250, and part of the timing generator 200. The fourth substrate 114 is provided with the arithmetic unit 80, the memory unit 83, the demultiplexer 81, the demultiplexer 84, the multiplexer 85, the sense amplifier 300, the line memory 310, and the input / output unit 320. The DA conversion unit 210, the global counter 220, the shift register 230, the VSCAN circuit 240, the HSCAN circuit 250, the sense amplifier 300, the line memory 310, and the input / output unit 320 are arranged in the peripheral portion of each substrate.

[0027] The timing generator 200 is configured with a pulse generation circuit and the like, and generates pulse signals and the like based on register setting values ​​output from the control unit 4 of the imaging device 1. The pulse signals are output to each pixel 10, the DA conversion unit 210, the global counter 220, the shift register 230, the VSCAN circuit 240, and the HSCAN circuit 250. The register setting values ​​are set, for example, according to the shutter speed (charge accumulation time of the photoelectric conversion unit), the ISO sensitivity, whether or not image correction is performed, and the like. The DA conversion unit 210 generates a ramp signal whose signal level changes as a reference signal based on the pulse signal from the timing generator 200. The DA conversion unit 210 is also commonly connected to each comparison unit 30 provided for each pixel 10, and outputs the reference signal to each comparison unit 30. The global counter 220 generates a signal (e.g., a clock signal) indicating a count value based on the pulse signal from the timing generator 200, and outputs the signal to the signal storage unit 41 and the noise storage unit 42. The shift register 230 generates a timing signal based on a pulse signal from the timing generator 200 and outputs the generated timing signal to the signal storage unit 41 and the noise storage unit 42. Based on the timing signal from the shift register 230, the signal storage unit 41 and the noise storage unit 42 convert the parallel signals stored therein into serial signals and output the serial signals to the arithmetic unit 80. The signal storage unit 41 and the noise storage unit 42 function as signal processing units that output digital signals as serial signals.

[0028] The VSCAN circuit 240 and the HSCAN circuit 250 sequentially select each control unit 70 based on a signal from the timing generator 200, and output to each control unit 70 a signal indicating the content of the calculation (arithmetic operation) to be performed in the arithmetic unit 80 and the pixel 10 to be calculated. Signal lines 123 and 124 are connected to each multiplexer 85 provided for each pixel 10. The signal lines 123 and 124 are, for example, arranged two-dimensionally in the row and column directions on the fourth substrate 114. The multiplexer 85 is controlled by the control unit 70, and selects a signal to be calculated by the arithmetic unit 80 from the signals input to the signal lines 123 and 124.

[0029] The sense amplifier 300 is connected to a signal line 122 to which a signal calculated by each calculation unit 80 for each pixel 10 is input, and amplifies and reads out the signal input to the signal line 122, thereby reading out the signal at high speed. The line memory 310 stores the signal read out by the sense amplifier 300. The input / output unit 320 performs signal processing on the signal output from the line memory 310, such as adjusting the bit width of the signal and adding a synchronization code, and outputs the signal as an image signal to the control unit 4 of the imaging device 1. The input / output unit 320 is configured with an input / output circuit or the like compatible with a high-speed interface such as LVDS or SLVS, and transmits signals at high speed.

[0030] The AD conversion unit 100 sequentially performs AD conversion on each of the photoelectric conversion signals and noise signals sequentially read out from the pixels 10. The calculation unit 80 performs CDS processing by subtracting the digital signal based on the photoelectric conversion signal converted by the AD conversion unit 100 from the digital signal based on the noise signal, and then performs calculations between the pixel signals. This will be explained in detail below.

[0031] When the noise signal of each pixel 10 is output to the comparison unit 30, the comparison unit 30, which is configured with a comparator circuit or the like, compares the noise signal output from the pixel 10 with a reference signal supplied by the DA conversion unit 210 and outputs the comparison result to the noise storage unit 42 via the demultiplexer 43. The noise storage unit 42 stores a count value corresponding to the elapsed time from when the comparison unit 30 starts comparison to when the comparison result is output, as a digital signal corresponding to the noise signal, based on the comparison result by the comparison unit 30 and a clock signal from the global counter 220. When the photoelectric conversion signal of each pixel 10 is output to the comparison unit 30, the comparison unit 30 compares the photoelectric conversion signal with the reference signal and outputs the comparison result to the signal storage unit 41 via the demultiplexer 43. The signal storage unit 41 stores a count value corresponding to the elapsed time from when the comparison unit 30 starts comparison to when the comparison result is output, as a digital signal corresponding to the photoelectric conversion signal, based on the comparison result by the comparison unit 30 and the clock signal. Thus, in this embodiment, the signal storage unit 41 and the noise storage unit 42 each store a 12-bit digital signal.

[0032] Based on the timing signal from the shift register 230, the noise storage unit 42 shifts the 12-bit digital signal stored in the noise storage unit 42 in time by one bit at a time, and sequentially outputs the shifted signal to the signal line 121 shown in FIG. 5. The serial signal output to the signal line 121 is input to the arithmetic unit 80 via the demultiplexer 81. The arithmetic unit 80 sequentially stores digital signals corresponding to the noise signal in the storage unit 83. The storage unit 83 stores the 12-bit digital signal related to the noise signal.

[0033] The signal line 121 is a signal line connecting the memory unit 40 of the second substrate 112 and the demultiplexer 81 of the fourth substrate 114, and is a signal line using the through electrodes 118 and 119 shown in FIG. 2, bumps, etc. Generally, it is difficult to form a large number of through electrodes at a narrow pitch, making it difficult to simultaneously transmit a large number of parallel signals from the second substrate 112 to the fourth substrate 114. In this embodiment, the parallel signals stored in the memory unit 40 of the second substrate 112 are converted into serial signals and output to the fourth substrate 114. This reduces the amount of wiring connecting the second substrate 112 and the fourth substrate 114, and enables digital signals for each pixel 10 to be output simultaneously. In addition, it is possible to prevent an increase in chip area due to the formation of a large number of through electrodes, etc.

[0034] After the 12-bit digital signal corresponding to the noise signal is input to the memory unit 83, the signal memory unit 41 converts the digital signal corresponding to the photoelectric conversion signal stored in the signal memory unit 41 into a serial signal based on the timing signal from the shift register 230, and outputs the serial signal to the arithmetic unit 80 via the signal line 121 and the demultiplexer 81. Based on a control signal from the control unit 70, the arithmetic unit 80 outputs (feeds back) the 12-bit digital signal corresponding to the noise signal stored in the memory unit 83 to the arithmetic unit 80 via the demultiplexer 84, one bit at a time.

[0035] The arithmetic unit 80 generates a correction signal by subtracting a digital signal corresponding to the photoelectric conversion signal output bit by bit from the signal storage unit 41 from a digital signal corresponding to the noise signal output bit by bit from the storage unit 83. The arithmetic unit 80 sequentially stores the correction signals generated bit by bit in the storage unit 83. The arithmetic unit 80 performs subtraction multiple times according to the number of bits of the signal stored in the storage unit 40, and sequentially stores the correction signals resulting from the subtraction in the storage unit 83. In this embodiment, the signal storage unit 41 and the noise storage unit 42 constituting the storage unit 40 each store a 12-bit digital signal, so 12 subtraction processes are performed. The storage unit 83 stores a digital signal corresponding to the 12-bit noise signal and a 12-bit correction signal. For this reason, the storage unit 83 is configured with 24 latch circuits, etc. As described above, in this embodiment, digital CDS, which processes the difference between the digital signal of the photoelectric conversion signal and the digital signal of the noise signal, is performed bit by bit in a time-division manner. Furthermore, the calculation unit 80 is provided for each pixel 10, and digital CDS is performed for all pixels 10 simultaneously.

[0036] After performing digital CDS, the arithmetic unit 80 performs an arithmetic operation between the correction signals generated for each pixel 10. In FIG. 5, for example, an arithmetic operation is performed between the correction signals for two pixels 10 arranged in adjacent regions A and B, respectively. That is, the 12-bit correction signal for the pixel 10 in region A stored in the memory unit 83 for region A is input (feedback) bit by bit to the arithmetic unit 80 for region A via the demultiplexer 84. Similarly, the 12-bit correction signal for the pixel 10 in region B stored in the memory unit 83 for region B is input bit by bit to the arithmetic unit 80 for region A via the demultiplexer 84 for region B, the multiplexer 85 for region B, and the multiplexer 85 for region A, respectively. The arithmetic unit 80 for region A performs an arithmetic operation on the 12-bit correction signal for region A and the 12-bit correction signal for region B input bit by bit to generate a pixel signal. The calculation unit 80 performs calculations multiple times according to the number of bits of the correction signal, and sequentially stores the pixel signals that are the calculation results in the storage unit 83. After the calculations between the correction signals, the storage unit 83 stores a 12-bit correction signal and a 12-bit pixel signal.

[0037] The arithmetic unit 80 outputs the pixel signals stored in the memory unit 83 to the signal line 122 via the demultiplexer 84. The sense amplifier 300 amplifies and reads out the pixel signals output to the signal line 122. Each arithmetic unit 80 provided for each pixel 10 sequentially outputs signals to the signal line 122, and the sense amplifier 300 sequentially reads out the signals output to the signal line 122. The pixel signals read out by the sense amplifier 300 are sequentially stored in the line memory 310. The input / output unit 320 performs signal processing on the signals sequentially output from the line memory 310, and outputs the processed signals as image signals.

[0038] 6 and 7 are diagrams illustrating a manufacturing method of an image sensor according to the first embodiment. First, as shown in FIG. 6(a), a first substrate 111 to a fourth substrate 114 are prepared. The first substrate 111 to the fourth substrate 114 are semiconductor substrates, and semiconductor substrates of any conductivity type may be used. Various elements such as transistors are formed on the first surface 105a of the first substrate 111, the first surface 106a of the second substrate 112, the first surface 107a of the third substrate 113, and the first surface 108a of the fourth substrate 114. Gate electrodes and gate insulating films are formed on the first surfaces 105a, 106a, 107a, and 108a, respectively. Then, as shown in FIG. 6(b), wiring layers 140, 141, 144, and 145, each including a conductive film and an insulating film, are formed on the first surfaces 105a, 106a, 107a, and 108a, respectively. For example, a plurality of wires and insulating films between the wires are formed in the wiring layers 140, 141, 144, and 145. After the wiring layers 140, 141, 144, and 145 are formed, connection parts 151, 152, 155, and 156 such as bumps and electrodes are formed. The connection parts 151, 152, 155, and 156 are formed using a metal material. Since general semiconductor processes can be used to form the various elements, wiring layers, and electrodes, a description thereof will be omitted.

[0039] Next, as shown in FIG. 6(c), the first surface 105a of the first substrate 111 and the first surface 106a of the second substrate 112 are arranged to face each other and are joined by connecting portions 151 and 152. Similarly, the first surface 107a of the third substrate 113 and the first surface 108a of the fourth substrate 114 are arranged to face each other and are joined by connecting portions 155 and 156. After the substrates are joined via the connecting portions, as shown in FIG. 6(d), portions of the first substrate 111 and the third substrate 113 are removed by etching, CMP (Chemical Mechanical Polishing), or the like to reduce the thickness of the first substrate 111 and the third substrate 113. In addition, a passivation layer 103 is formed on the second surface 105b of the first substrate 111.

[0040] Next, as shown in FIG. 7(a), a support substrate 400 is bonded to the second surface 105b of the first substrate 111 via the passivation layer 103. Then, portions of the second substrate 112 are removed by etching or the like to reduce the thickness of the second substrate 112. Next, as shown in FIG. 7(b), through electrodes 118 and 119 are formed in the second substrate 112 and the third substrate 113, respectively. A known semiconductor process can be used to form the through electrodes 118 and 119. After the through electrodes 118 and 119 are formed, an inter-substrate connection layer 142 and connection portions 153 such as bumps or electrodes are formed on the second surface 106b of the second substrate 112, and an inter-substrate connection layer 143 and connection portions 154 such as bumps or electrodes are formed on the second surface 107b of the third substrate 113. The through electrodes 118 and 119 may be formed from the first surface 106a side of the second substrate 112 and the first surface 107a side of the third substrate 113, respectively, at the stage of FIG. 6(b).

[0041] Next, as shown in FIG. 7(c), the second surface 106b of the second substrate 112 and the second surface 107b of the third substrate 113 are arranged to face each other and bonded together by the connecting portions 153 and 154. After bonding the substrates together via the connecting portions, the support substrate 400 is removed as shown in FIG. 7(d). Then, the color filter layer 102 and the microlens layer 101 are sequentially formed on the second surface 105b of the first substrate 111 via the passivation layer 103. The imaging element 3 shown in FIG. 2 can be manufactured by the above manufacturing method. Note that the manufacturing method of the imaging element shown in FIGS. 6 and 7 is merely an example, and other manufacturing methods may be used. The imaging element can be manufactured by various manufacturing methods.

[0042] According to the above-described embodiment, the following effects can be obtained. (1) The imaging element 3 includes a photoelectric conversion layer 161 having a photoelectric conversion unit 12 that photoelectrically converts incident light, a first circuit layer 162 stacked on the photoelectric conversion layer 161 and having a first circuit, a second circuit layer 163 stacked on the first circuit layer 162 and having a second circuit, and a third circuit layer 164 stacked on the second circuit layer 163 and having a third circuit. The surface (first surface 105a) of the photoelectric conversion layer 161 on which an electrode (gate electrode) is provided faces the surface (first surface 106a) of the first circuit layer 162 on which an electrode (gate electrode) is provided, and the surface (first surface 107a) of the second circuit layer 163 on which an electrode (gate electrode) is provided faces the surface (first surface 108a) of the third circuit layer 164 on which an electrode (gate electrode) is provided. This allows multiple circuits and the like for processing signals from the pixels 10 to be arranged without increasing the chip area. It also prevents a decrease in the aperture ratio of the pixels 10. Furthermore, the circuits provided in the photoelectric conversion layer 161 and the circuits provided in the first circuit layer 162 can be electrically connected via, for example, multiple bumps, and multiple signals from each pixel 10 in the photoelectric conversion layer 161 can be transmitted to the first circuit layer 162 simultaneously.

[0043] (2) The imaging element 3 includes a photoelectric conversion layer 161 having a semiconductor layer 111 having a photoelectric conversion section 12 that photoelectrically converts incident light, and a wiring layer 140; a first circuit layer 162 stacked on the wiring layer 140 side of the photoelectric conversion layer 161 and having a first wiring layer 141 electrically connected to the first semiconductor layer 112 and the wiring layer 140 of the photoelectric conversion layer 161; a second circuit layer 163 stacked on the first semiconductor layer 112 side of the first circuit layer 162 and having a second wiring layer 144 electrically connected to the second semiconductor layer 113 and the first wiring layer 141; and a third circuit layer 164 stacked on the second wiring layer 144 side of the second circuit layer 163 and having a third wiring layer 145 electrically connected to the third semiconductor layer 114 and the second wiring layer 144. This makes it possible to arrange multiple circuits for processing signals from the pixels 10 without increasing the chip area, and also makes it possible to prevent a decrease in the aperture ratio of the pixels 10.

[0044] (3) The first circuit layer 162 is provided on a surface different from the surface on which the electrodes (gate electrodes) are provided and has a first connection portion 153 electrically connected to the first circuit, and the second circuit layer 163 is provided on a surface different from the surface on which the electrodes (gate electrodes) are provided and has a second connection portion 154 electrically connected to the first connection portion 153 and the second circuit, and the first circuit and the second circuit are connected via the first connection portion 153 and the second connection portion 154. This allows a large number of signals to be transmitted between the circuits of the first circuit layer 162 and the circuits of the second circuit layer 163.

[0045] (4) The image sensor includes a first through electrode 118 provided in the first circuit layer 162 and electrically connecting the first circuit to the first connection portion 153, and a second through electrode 119 provided in the second circuit layer 163 and electrically connecting the second circuit to the second connection portion 154. In this embodiment, the through electrode 118 and the through electrode 119 are connected via the connection portion 153 and the connection portion 154. This allows the through electrode 118 and the through electrode 119 to be provided in different positions. Furthermore, there is no need to form a long through electrode that penetrates two substrates, which can prevent a decrease in the yield of the image sensor and an increase in the chip area.

[0046] (5) The first circuit layer 162 has an AD conversion section 100 that performs AD conversion on the signal output from the photoelectric conversion section 12 and outputs a digital signal, the third circuit layer 164 has an arithmetic section (arithmetic unit 80) that performs arithmetic processing on the digital signal, and the second circuit layer 163 has a control section 70 that controls the arithmetic section. This allows the pixels 10 of the photoelectric conversion layer 161 to be connected to the AD conversion sections 100 of the first circuit layer 162 via multiple bumps. Therefore, signals from each pixel 10 can be simultaneously output to the AD conversion sections 100 provided for each pixel. This allows AD conversion to be performed simultaneously in each AD conversion section 100. Furthermore, the control section 70 of the second circuit layer 163 and the arithmetic unit 80 of the third circuit layer 164 can be connected to each other via multiple bumps. 2 to the arithmetic unit 80 of the third circuit layer 164, thereby controlling the content of the arithmetic operation by the arithmetic unit 80. As a result, arithmetic can be performed on the signal of any pixel 10 without increasing the chip area of ​​the image sensor 3. Calculations can be performed between adjacent pixels or between pixels located in distant regions.

[0047] (6) The first circuit layer 162 has a signal processing unit (a signal storage unit 41, a noise storage unit 42) that outputs a digital signal as a serial signal. This configuration reduces the amount of wiring connecting the first circuit layer 162 and the third circuit layer 164, allowing digital signals for each pixel 10 to be output simultaneously. In addition, it is possible to prevent an increase in chip area due to the formation of a large number of through electrodes, etc.

[0048] (Second embodiment) An image sensor according to a second embodiment will be described with reference to FIGS. 8 and 9. In the drawings, parts that are the same as or equivalent to those in the first embodiment are given the same reference numerals, and differences from the image sensor according to the first embodiment will be mainly described. FIG. 8 is a block diagram showing the configuration of an image sensor according to the second embodiment. A first substrate 111 has a plurality of pixels 10 arranged two-dimensionally, and a second substrate 112 has a plurality of comparison units 30. The comparison units 30 compare signals output from the pixels 10 with a reference signal and output the comparison results to a third substrate 113 and a fourth substrate 114.

[0049] The third substrate 113 has a plurality of first storage units 50. The fourth substrate 114 has a plurality of second storage units 60 and an output unit 90. The first storage unit 50 and the second storage unit 60 are provided for each pixel 10 and are composed of latch circuits and the like. The AD conversion unit 100 includes a comparison unit 30, a first storage unit 50, and a second storage unit 60, and converts signals output from the pixels 10 into digital signals with a predetermined number of bits. The first storage unit 50 stores the digital signals with the lower bits of the digital signals with the predetermined number of bits, and the second storage unit 60 stores the digital signals with the higher bits of the digital signals with the predetermined number of bits. The first storage unit 50 and the second storage unit 60 each receive a clock signal indicating a count value from the global counter 220 shown in FIG. 9. Here, the lower bits refer to bits of the digital signal generated by a relatively high-frequency signal among the clock signals output from the global counter 220. Furthermore, the term "high-order bits" refers to bits of a digital signal generated by a relatively low-frequency signal among the clock signals output from the global counter 220. In other words, the frequency of the clock signal input to the first storage unit 50 is higher than the frequency of the clock signal input to the second storage unit 60.

[0050] FIG. 9 is a block diagram showing the detailed configuration of the image sensor according to the second embodiment. The first substrate 111 is provided with the pixels 10 and a portion of the timing generator 200. The second substrate 112 is provided with the comparison unit 30, the DA conversion unit 210, the global counter 220, and a portion of the timing generator 200. The third substrate 113 is provided with the first memory unit 50 and a portion of the timing generator 200. The fourth substrate 114 is provided with the second memory unit 60, the output unit 90, a portion of the timing generator 200, a sense amplifier 300, a line memory 310, and an input / output unit 320. In FIG. 9, the first substrate 111, the second substrate 112, the third substrate 113, and the fourth substrate 114 are referred to as the first layer, the second layer, the third layer, and the fourth layer, respectively.

[0051] The global counter 220 performs measurements using a signal from the timing generator 200, generates a plurality of signals (e.g., clock signals) with different frequencies that indicate count values, and outputs these to the first storage unit 50 and the second storage unit 60. Based on the signal output from the comparison unit 30, the first storage unit 50 and the second storage unit 60 store, as digital signals, count values ​​that correspond to the time until the magnitude relationship between the level of the signal output from the pixel 10 and the level of the ramp signal (reference signal) changes (inverts). The first storage unit 50 and the second storage unit 60 store, as digital signals, the count values ​​that are the measurement results. In other words, the first storage unit 50 and the second storage unit 60 each store digital signals based on the results of measurements using clock signals with a plurality of different frequencies.

[0052] The first memory unit 50 stores a digital signal based on a result of measuring, using a clock signal of a first frequency, the time until the magnitude relationship between the signal output from the pixel 10 and the reference signal changes when the comparison unit 30 compares the signal output from the pixel 10 with a reference signal from the DA conversion unit 210. The second memory unit 60 stores a digital signal based on a result of measuring, using a clock signal of a second frequency that is lower than the frequency of the clock signal of the first frequency, the time until the magnitude relationship between the signal output from the pixel 10 and the reference signal changes. The digital signals stored in the first memory unit 50 and the second memory unit 60 are output to the output unit 90.

[0053] The signal line 121, through which the output signal of the comparison unit 30 is transmitted, connects the comparison unit 30 on the second substrate 112, the first memory unit 50 on the third substrate 113, and the second memory unit 60 on the fourth substrate 114. This signal line uses the through electrodes 118 and 119 and bumps shown in FIG. 2 . On the fourth substrate 114, which is located far from the comparison unit 30 on the second substrate 112, parasitic capacitance of the wiring, interlayer junction capacitance, and other factors can cause delays and distortions in the comparator output signal, as well as variations between pixels. This can result in a shift in the latch timing of the latch operation. In this embodiment, of the first memory unit 50 and the second memory unit 60, the first memory unit 50, which stores the digital signal of the lower bits, is located closer to the comparison unit 30 than the second memory unit 60. In other words, the first memory unit 50 is located between the comparison unit 30 and the second memory unit 60. 8 and 9, a third substrate 113 having a first storage section 50 is provided between a second substrate 112 having a comparison section 30 and a fourth substrate 114 having a second storage section 60. In FIG.

[0054] The input timing of the output signal from the comparing unit 30 to the second storage unit 60 may be delayed. However, because the frequency of the clock signal indicating the count value input to the second storage unit 60 is low, i.e., the count value of the most significant bits changes slowly, the influence of the deviation in latch timing can be reduced, and conversion errors in AD conversion can be reduced. In this way, by locating the first storage unit 50, which stores a digital signal based on a clock signal of a first frequency higher than the second frequency, closer to the comparing unit 30 than the second storage unit 60, the influence of signal delay of the signal from the comparing unit 30 can be reduced. This makes it possible to achieve highly accurate AD conversion.

[0055] The digital signals stored in the first memory unit 50 and the second memory unit 60 are output to a signal line 122 by an output unit 90 provided for each pixel 10. Each output unit 90 provided for each pixel 10 sequentially outputs signals to the signal line 122, and a sense amplifier 300 sequentially reads out the signals output to the signal line 122. The signals read out by the sense amplifier 300 are sequentially stored in a line memory 310. An input / output unit 320 performs signal processing on the signals sequentially output from the line memory 310, and outputs the processed signals as image signals.

[0056] In this embodiment, the first memory unit 50 for the lower bits is provided on the third layer 113, and the second memory unit 60 for the higher bits is provided on the fourth layer 114. However, the reverse may be true, i.e., the first memory unit 50 for the lower bits is provided on the fourth layer 114, and the second memory unit 60 for the higher bits is provided on the third layer 113. By providing the first memory unit 50 and the second memory unit 60 on different substrates in this manner, multiple memory units can be arranged without increasing the chip area, thereby improving the number of bits (resolution) of AD conversion. Furthermore, the first memory unit 50 and the second memory unit 60 are stacked on the corresponding pixels 10. This prevents a decrease in the aperture ratio of the pixels 10.

[0057] According to the above-described embodiment, in addition to the same effects as those of the first embodiment, the following effects can be obtained. (7) The first circuit layer 162 includes a comparison unit 30 that compares the signal output from the photoelectric conversion unit 12 with a reference signal. The second circuit layer 163 includes a first memory unit 50 that stores a digital signal with a first number of bits among the digital signals with a predetermined number of bits based on the comparison result of the comparison unit 30. The third circuit layer 164 includes a second memory unit 60 that stores a digital signal with a second number of bits among the digital signals with a predetermined number of bits based on the comparison result of the comparison unit 30. The comparison unit 30, the first memory unit 50, and the second memory unit 60 constitute an AD conversion unit 100 that converts the signal read from the photoelectric conversion unit 12 into a digital signal with a predetermined number of bits. In this embodiment, the first memory unit 50 is disposed on the second circuit layer 163, and the second memory unit 60 is disposed on the third circuit layer 164. This allows multiple memory units to be disposed without increasing the chip area, thereby improving the resolution of AD conversion. Furthermore, the first memory section 50 and the second memory section 60 are provided by being stacked on the corresponding pixels 10. This makes it possible to prevent the aperture ratio of the pixels 10 from decreasing.

[0058] (8) The first storage unit 50 stores a digital signal with a first number of bits based on a clock signal with a first frequency, and the second storage unit 60 stores a digital signal with a second number of bits based on a clock signal with a second frequency lower than the first frequency. In this embodiment, of the first storage unit 50 and the second storage unit 60, the first storage unit 50 that stores the digital signal with the lower bits is located closer to the comparing unit 30. This reduces the effect of signal delay on the signal from the comparing unit 30, enabling highly accurate AD conversion to be achieved.

[0059] (Third embodiment) An image sensor according to the third embodiment will be described with reference to Figs. 10 and 11. In the drawings, parts that are the same as or equivalent to those in the first and second embodiments are given the same reference numerals, and differences from the image sensor according to the first and second embodiments will be mainly described. Fig. 10 is a block diagram showing the configuration of an AD conversion unit 100 of an image sensor according to the third embodiment. The AD conversion unit 100 includes a comparison unit 30, a first storage unit 50, a second storage unit 60, and a level conversion unit (level shifter) 180.

[0060] The level conversion unit 180 includes a first capacitor C1, a second capacitor C2, and a buffer (amplification unit) 130. The level conversion unit 180 converts the voltage level of the output signal of the comparison unit 30 from the level of an analog power supply used in the comparison unit 30 and the like to the level of a digital power supply used in the buffer 130, the first storage unit 50, the second storage unit 60, and the like. The first capacitor C1 and the second capacitor C2 are connected in series. A signal corresponding to the voltage level of the output signal of the comparison unit 30 and the ratio of the capacitances of the first capacitor C1 and the second capacitor C2 is input to an input terminal 131 of the buffer 130. The buffer 130 converts the level of the input signal to the level of the digital power supply and outputs it to the first storage unit 50 and the second storage unit 60. The first capacitor C1 is provided in a first capacitance layer 171 shown in FIG. 11, and the second capacitor C2 is provided in a second capacitance layer 172 shown in FIG. 11. The buffer 130 may be disposed on the third substrate 113 or on the fourth substrate 114. The buffer 130 may also be disposed on a substrate different from the third substrate 113 and the fourth substrate 114.

[0061] FIG. 11 is a diagram showing a cross-sectional structure of an imaging element according to a third embodiment. The imaging element according to the third embodiment includes a first capacitance layer 171 and a second capacitance layer 172. The first capacitance layer 171 and the second capacitance layer 172 each have insulating portions 161 and 162. The insulating portions 161 and 162 are made of an insulating material, such as an insulating film. The insulating portion 161 is connected between the connecting portion 153 and the connecting portion 157, such as a bump or an electrode, and the insulating portion 162 is connected between the connecting portion 154 and the connecting portion 157. The connecting portions 153, 154, and 157 are each made of metal. The insulating portion 161, the connecting portion 153, and the connecting portion 157 form a first capacitance C1, and the insulating portion 162, the connecting portion 154, and the connecting portion 157 form a second capacitance C2.

[0062] In this embodiment, the elements of the comparing section 30 provided on the second substrate 112 are connected to elements provided on each of the third substrate 113 and the fourth substrate 114 via the first capacitance layer 171 and the second capacitance layer 172. A first capacitance C1 and a second capacitance C2 for converting from an analog power supply level to a digital power supply level are arranged on the first capacitance layer 171 and the second capacitance layer 172. This eliminates the need to arrange the first capacitance C1 and the second capacitance C2 on the second substrate 112 and the third substrate 113, and allows the area of ​​the circuits arranged on the second substrate 112 and the third substrate 113 to be reduced.

[0063] According to the above-described embodiment, in addition to the same effects as those of the first and second embodiments, the following effects can be obtained. (9) The first capacitance layer 171 is provided on the second circuit layer 163 side of the first circuit layer 162 and has a first capacitance C1 connected to the first connection portion 153, and the second capacitance layer 172 is provided on the first circuit layer 162 side of the second circuit layer 163 and has a second capacitance C2 connected to the second connection portion 154 and connected in series to the first capacitance C1. This makes it possible to reduce the area of ​​the circuits to be arranged on the second substrate 112, the third substrate 113, etc.

[0064] The following modifications are also within the scope of the present invention, and one or more of the modifications may be combined with the above-described embodiment.

[0065] (Variation 1) In the above-described first embodiment, an example has been described in which pixel signals resulting from inter-pixel calculations are sequentially output to the sense amplifier 300 via the signal line 122. However, correction signals stored in the memory unit 83 may be output as pixel signals to the sense amplifier 300 via the signal line 122. Furthermore, digital signals corresponding to the photoelectric conversion signals stored in the signal memory unit 41 and digital signals corresponding to the noise signals stored in the noise memory unit 42 may each be output to the signal line 122 via the demultiplexer 81.

[0066] (Variation 2) In the first embodiment described above, an example has been described in which the CDS processing and inter-pixel calculations are performed in a time-division manner for each bit. However, the control unit 70 may control the calculation unit 80, etc., to perform calculations for each number of bits. For example, calculations may be performed for each two bits, or for each number of bits that is less than the number of bits of the digital signal stored in the noise storage unit 42.

[0067] (Variation 3) In the first embodiment described above, an example has been described in which digital CDS is performed before calculations are performed between signals of each pixel 10. However, analog CDS may also be performed before calculations are performed between signals of each pixel 10. For example, the AD conversion unit 100 performs differential processing between a photoelectrically converted signal and a noise signal, and converts an analog signal based on the difference between the signals into a digital signal. In this case, each storage unit stores a digital signal from which the noise signal component for each pixel 10 has been removed.

[0068] (Variation 4) In the first embodiment described above, an example was described in which the first substrate 111 has a plurality of pixels 10, the second substrate 112 has a plurality of AD conversion units 100, the third substrate 113 has a plurality of control units 70, and the fourth substrate 114 has a plurality of arithmetic units 80, and four substrates are stacked. However, the number of substrates is not limited to four. The image sensor 3 may also be configured with three substrates stacked. Furthermore, in the first embodiment described above, an example was described in which the first surface 105a of the photoelectric conversion layer 161 and the first surface 106a of the first circuit layer 162 are stacked opposite each other, and the first surface 107a of the second circuit layer 163 and the first surface 108a of the third circuit layer 164 are stacked opposite each other. However, the second surface 105b of the photoelectric conversion layer 161 and the second surface 106b of the first circuit layer 162 may be stacked opposite each other, and the second surface 107b of the second circuit layer 163 and the first surface 108a of the third circuit layer 164 may be stacked opposite each other. In the imaging element 3, for example, from the side where the incident light L is incident, the wiring layer 140, the first substrate 111, the second substrate 112, the wiring layer 141, the wiring layer 144, the third substrate 113, the wiring layer 145, and the fourth substrate 114 are provided. In this case, the imaging element 3 may be configured such that three substrates (the first substrate 111 to the third substrate 113) are stacked. An inter-substrate connection layer may be provided between the first substrate 111 and the second substrate 112.

[0069] In the second embodiment described above, an example has been described in which the first substrate 111 has a plurality of pixels 10, the second substrate 112 has a plurality of comparing units 30, the third substrate 113 has a plurality of first memory units 50, and the fourth substrate 114 has a plurality of second memory units 60, and four substrates are stacked. However, the number of substrates is not limited to four. The pixels 10 and the comparing units 30 may be provided on the same substrate. The comparing units 30 and the first memory units 50 may also be provided on the same substrate. The first memory units 50 and the second memory units 60 may also be provided on the same substrate. In this case, the first memory unit 50 is provided closer to the comparing unit 30 than the second memory unit 60. Furthermore, another circuit layer electrically connected to both the photoelectric conversion layer 161 and the first circuit layer 162 may be provided between them.

[0070] Furthermore, there may be three or more substrates having storage units (latch circuits, etc.) including the third substrate 113 and the fourth substrate 114. For example, twelve storage units (latch circuits) for storing a 12-bit digital signal may be provided with four units per three substrates, or one unit per twelve substrates.

[0071] In the second embodiment described above, an example has been described in which the first memory unit 50 corresponding to the lower bits and the second memory unit 60 corresponding to the upper bits are provided. However, a third memory unit may be provided to store digital signals of mid-level bits relative to the upper and lower bits. In this case, based on the signal output from the comparator 30, the time until the magnitude relationship between the signal output from the pixel 10 and the reference signal changes is measured using a clock signal of a third frequency that is lower in frequency than the clock signal of the second frequency. The third memory unit stores a third signal based on the result of the measurement using the clock signal of the third frequency. The digital signal based on the clock signal of the first frequency is the digital signal of the lower bits, the digital signal based on the clock signal of the second frequency is the digital signal of the mid-level bits, and the digital signal based on the clock signal of the third frequency is the digital signal of the upper bits.

[0072] The first memory unit, the second memory unit, and the third memory unit may be arranged on different substrates. The substrate having the second memory unit 60 may be provided between the substrate having the first memory unit 50 and the substrate having the third memory unit, so that the second memory unit 60 is located between the first memory unit 50 and the third memory unit. The first memory unit 50 and the second memory unit 60 may be provided on the same substrate, and only the third memory unit may be provided on a different substrate. The first memory unit 50 is provided closer to the comparison unit 30 than the second memory unit 60. Furthermore, the substrate having the first memory unit 50 and the second memory unit 60 may be provided between the substrate having the comparison unit 30 and the substrate having the third memory unit. The second memory unit 60 and the third memory unit may be provided on the same substrate.

[0073] (Variation 5) In the above embodiment, an example of AD conversion to a 12-bit digital signal has been described. However, the present invention can be applied to AD conversion of any number of bits. A plurality of latch circuits (storage units) may be provided according to the number of bits.

[0074] (Variation 6) In the above-described embodiment, the imaging element 3 is configured as a back-illuminated type. However, the imaging element 3 may be configured as a front-illuminated type in which the wiring layer 140 is provided on the light incident surface side.

[0075] (Variation 7) In the above-described embodiment, an example has been described in which a photodiode is used as the photoelectric conversion unit 12. However, a photoelectric conversion film may be used as the photoelectric conversion unit 12.

[0076] (Variation 8) In the above-described embodiment, an example has been described in which an AD conversion unit 100 is provided for each pixel 10. However, an AD conversion unit 100 may be provided for each set of multiple pixels 10. For example, when pixels are arranged in a four-color Bayer array of RGGB, an AD conversion unit 100 may be provided for each pixel block consisting of four RGGB pixels, or an AD conversion unit 100 may be provided for each pixel block consisting of an even number of pixels arranged in the row and column directions.

[0077] (Variation 9) In the above-described embodiment and modified example, an example has been described in which the AD conversion unit 100 uses an integral AD conversion circuit that performs AD conversion by changing the signal level of a reference signal over time. However, other circuit configurations, such as a successive approximation type, may also be used. For example, a successive approximation type AD conversion unit includes a comparison unit, a storage unit, and a capacitance unit. The capacitance unit is provided with multiple capacitances corresponding to the number of bits of the digital signal according to the resolution of the AD conversion, and multiple switches that switch the connection state of each capacitance. The capacitance unit generates a reference signal determined by the input signal (voltage signal) and the connection state of each capacitance, and outputs the reference signal to the comparison unit.

[0078] The comparator compares the signal (photoelectric conversion signal, noise signal) input from the pixel 10 with the reference signal input from the capacitor, and outputs an output signal that is the comparison result. The memory stores a digital signal corresponding to the signal output from the pixel 10 in the memory based on the output signal from the comparator. The successive approximation type AD converter switches the connection state of each capacitor in the capacitor based on the comparison result by the comparator, thereby sequentially changing the reference signal generated by the capacitor and performing binary search multiple times, thereby generating a digital signal corresponding to the signal output from the pixel 10.

[0079] When a successive approximation type AD conversion unit is disposed on an image sensor, multiple capacitors of the capacitance unit are disposed on multiple substrates. For example, if the capacitance unit has a third capacitor and a fourth capacitor having a capacitance value larger than the third capacitor, the comparison unit is disposed on the first circuit layer 162, the third capacitor is disposed on the second circuit layer 163, and the fourth capacitor is disposed on the third circuit layer 164. The third capacitor is a capacitor for determining the digital signal of the lower bits. This allows the number of bits (resolution) of AD conversion to be improved without increasing the chip area. Furthermore, since capacitors with small capacitance values ​​are significantly affected by parasitic capacitance, they are disposed closer to the comparison unit than capacitors with large capacitance values. This reduces the effect of parasitic capacitance on capacitors with small capacitance values. As a result, high-precision AD conversion can be achieved.

[0080] (Variation 10) The imaging device 3 described in the above embodiment may be applied to cameras, smartphones, tablets, cameras built into PCs, vehicle-mounted cameras, and the like.

[0081] Although various embodiments and modifications have been described above, the present invention is not limited to these. Other embodiments that are conceivable within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention.

[0082] The disclosures of the following priority applications are incorporated herein by reference: Japanese Patent Application No. 2016-70960 (filed March 31, 2016) [Explanation of symbols]

[0083] 3 imaging element, 12 photoelectric conversion unit, 10 pixel, 30 comparison unit, 70 control unit, 80 calculation unit, 100 AD conversion unit

Claims

[Claim 1] a photoelectric conversion layer having a first substrate including a first photoelectric conversion unit that converts light into electric charges, a second photoelectric conversion unit that converts light into electric charges and is arranged alongside the first photoelectric conversion unit in a first direction, and a third photoelectric conversion unit that converts light into electric charges and is arranged alongside the first photoelectric conversion unit in a second direction intersecting the first direction; a first circuit layer including a second substrate which is a circuit layer stacked on the photoelectric conversion layer and includes a first conversion unit which converts a first signal based on the charges converted by the first photoelectric conversion unit into a digital signal, a second conversion unit which converts a second signal based on the charges converted by the second photoelectric conversion unit into a digital signal, and a third conversion unit which converts a third signal based on the charges converted by the third photoelectric conversion unit into a digital signal; and a first connection layer which includes a first wiring electrically connected to a first through electrode which penetrates the second substrate and which is different from the first through electrode; a third substrate, which is a circuit layer stacked on the first circuit layer, including a first control unit for performing a first arithmetic process on a first digital signal converted from the first signal to a digital signal by the first conversion unit, a second control unit for performing a second arithmetic process on a second digital signal converted from the second signal to a digital signal by the second conversion unit, and a third control unit for performing a third arithmetic process on a third digital signal converted from the third signal to a digital signal by the third conversion unit; and a second connection layer including a second wiring electrically connected to a second through electrode that penetrates the third substrate, the second wiring being different from the second through electrode; a connection portion for electrically connecting the first wiring and the second wiring, the first connection portion having electrode pads arranged to face each other in a direction in which the first circuit layer and the second circuit layer are stacked; An imaging element comprising:

Images