Semiconductor device and method of manufacturing the same

Abstract

To deepen a bottom layer while suppressing shielding between adjacent trenches by the bottom layer in a trench gate type semiconductor device.SOLUTION: Insulating films (11b, 12b, 21b, 72b) and electrodes (11a, 12a, 21a, 72a) formed in the plurality of trenches (5152,,,). 5152. The plurality of trenches (51,52) include a first trench (51) and a second trench (52) that is deeper than the first trench (51) and wider than the first trench (51). A second conductivity type bottom layer (60) in contact with a bottom of the second trench (52) and not in contact with the first trench (51) is disposed below the second trench (52).SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Trench-gate semiconductor devices are known, with a structure in which a gate electrode is buried in a trench. For example, Patent Document 1 below discloses a trench-gate IGBT with a bottom layer (also called a "BP layer"), which is a p-type semiconductor layer, located at the bottom of the trench in the gate electrode. The BP layer reduces the electric field at the bottom of the trench and has the effect of suppressing the avalanche phenomenon of the semiconductor, particularly the transient avalanche phenomenon known as dynamic avalanche that occurs when current is turned on and then turned off. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-225566 Summary of the Invention [Problem to be solved by the invention]

[0004] Increasing the depth (thickness) of the BP layer increases the electric field relaxation effect of the BP layer, so the BP layer is formed to a certain depth. However, forming the BP layer too deep increases the lateral extent of the BP layer, so if the BP layer is made too deep, the BP layer will shield the gap between adjacent trenches, preventing the semiconductor device from operating. Therefore, the depth of the BP layer must be designed so that the gap between adjacent trenches is not shielded by the BP layer, and it can be difficult to ensure a sufficient BP layer depth.

[0005] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device in which the bottom layer can be made deeper while preventing the bottom layer from blocking the space between adjacent trenches. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure comprises a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface opposite the first main surface, a plurality of trenches formed in the first main surface of the semiconductor substrate, an insulating film formed on the inner surface of each of the plurality of trenches, and an electrode embedded in each of the plurality of trenches via the insulating film, wherein the plurality of trenches include a first trench and a second trench that is deeper than the first trench and wider than the first trench, and a bottom layer of a second conductivity type is formed below the second trench, contacting the bottom of the second trench but not contacting the first trench. [Effects of the Invention]

[0007] According to the semiconductor device according to the present disclosure, the bottom layer can be made deeper while preventing the bottom layer from blocking the gap between adjacent trenches. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a plan view showing a configuration example of a chip of a semiconductor device according to a first embodiment. [Figure 2] 1 is a plan view showing a configuration example of a chip of a semiconductor device according to a first embodiment. [Figure 3] 1 is a plan view showing a configuration example of a chip of a semiconductor device according to a first embodiment. [Figure 4] FIG. 2 is a plan view showing an example of the structure of an IGBT region. [Figure 5] FIG. 2 is a cross-sectional view showing an example of the structure of an IGBT region. [Figure 6] FIG. 2 is a cross-sectional view showing an example of the structure of an IGBT region. [Figure 7] 1 is a plan view showing the structure of an IGBT region of a semiconductor device according to a first embodiment. [Figure 8] 2 is a cross-sectional view showing the structure of an IGBT region of the semiconductor device according to the first embodiment. FIG. [Figure 9]2 is a cross-sectional view showing the structure of an IGBT region of the semiconductor device according to the first embodiment. FIG. [Figure 10] FIG. 2 is a plan view showing an example of the structure of a diode region. [Figure 11] FIG. 2 is a cross-sectional view showing an example of the structure of a diode region. [Figure 12] FIG. 2 is a cross-sectional view showing an example of the structure of a diode region. [Figure 13] 1 is a plan view showing a structure of a diode region of a semiconductor device according to a first embodiment. [Figure 14] 2 is a cross-sectional view showing the structure of a diode region of the semiconductor device according to the first embodiment. FIG. [Figure 15] 2 is a cross-sectional view showing the structure of a diode region of the semiconductor device according to the first embodiment. FIG. [Figure 16] 1 is a cross-sectional view showing an example of the structure of the boundary between an IGBT region and a diode region. [Figure 17] FIG. 2 is a cross-sectional view showing an example of the structure of the termination region. [Figure 18] FIG. 2 is a cross-sectional view showing an example of the structure of the termination region. [Figure 19] FIG. 2 is a cross-sectional view showing an example of the structure of the termination region. [Figure 20] FIG. 2 is a cross-sectional view showing an example of the structure of the termination region. [Figure 21] 2 is a cross-sectional view showing the structure of a termination region of the semiconductor device according to the first embodiment. [Figure 22] 2 is a cross-sectional view showing the structure of a termination region of the semiconductor device according to the first embodiment. [Figure 23] 1A to 1C are diagrams for explaining an example of a manufacturing method for an RC-IGBT. [Figure 24] 1A to 1C are diagrams for explaining an example of a manufacturing method for an RC-IGBT. [Figure 25] 1A to 1C are diagrams for explaining an example of a manufacturing method for an RC-IGBT. [Figure 26] 1A to 1C are diagrams for explaining an example of a manufacturing method for an RC-IGBT. [Figure 27] 1A to 1C are diagrams for explaining an example of a manufacturing method for an RC-IGBT. [Figure 28] 1A to 1C are diagrams for explaining an example of a manufacturing method for an RC-IGBT. [Figure 29] 1A to 1C are diagrams for explaining an example of a manufacturing method for an RC-IGBT. [Figure 30] 1A to 1C are diagrams for explaining an example of a manufacturing method for an RC-IGBT. [Figure 31] 1A to 1C are diagrams for explaining an example of a manufacturing method for an RC-IGBT. [Figure 32] 1A to 1C are diagrams for explaining an example of a manufacturing method for an RC-IGBT. [Figure 33] 1A to 1C are diagrams for explaining an example of a manufacturing method for an RC-IGBT. [Figure 34] 1A to 1C are diagrams for explaining an example of a manufacturing method for an RC-IGBT. [Figure 35] 2A to 2C are diagrams for explaining a method for manufacturing a semiconductor device according to the first embodiment. [Figure 36] 2A to 2C are diagrams for explaining a method for manufacturing a semiconductor device according to the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] In the following description, n and p indicate the conductivity types of semiconductors, and in this disclosure, the first conductivity type is described as n-type and the second conductivity type is described as p-type, but the first conductivity type may also be p-type and the second conductivity type may also be n-type. - indicates that the impurity concentration is lower than n, and n + indicates that the impurity concentration is higher than n. Similarly, p - indicates that the impurity concentration is lower than p, and p + indicates that the impurity concentration is higher than p.

[0010] The impurity concentration of each region is defined by its peak concentration, i.e., a region with a high (or low) impurity concentration means a region with a high (or low) peak impurity concentration.

[0011] <First Embodiment> The following describes the configuration of the semiconductor device according to embodiment 1. The semiconductor device may include a trench gate type semiconductor element, such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), or an RC-IGBT (Reverse Conducting IGBT).

[0012] The material of the semiconductor element may be silicon (Si) or a wide bandgap semiconductor such as silicon carbide (SiC). A semiconductor device formed using a wide bandgap semiconductor is superior to a semiconductor device using silicon in terms of operation at high voltages, large currents, and high temperatures. In addition to silicon carbide, wide bandgap semiconductors include gallium nitride (GaN)-based materials and diamond.

[0013] 1 to 3 are diagrams showing examples of the planar structure of a chip of a semiconductor device according to embodiment 1. Fig. 1 is a plan view showing a semiconductor device that is an IGBT. Fig. 2 is a plan view showing a semiconductor device that is an RC-IGBT. Fig. 3 is a plan view showing a semiconductor device that is an RC-IGBT with another configuration.

[0014] The RC-IGBT of the semiconductor device 100 shown in Fig. 2 has IGBT regions 10 and diode regions 20 arranged side by side in a stripe pattern, and may be simply called a "stripe type." The RC-IGBT of the semiconductor device 100 shown in Fig. 3 has a plurality of diode regions 20 arranged in the vertical and horizontal directions, and the IGBT regions 10 are arranged around the diode regions 20, and may be simply called an "island type."

[0015] (1) Overall planar structure of IGBT In FIG. 1, a semiconductor device 100 includes an IGBT region 10. A pad region 40 is provided adjacent to the lower side of the IGBT region 10 as viewed in FIG. 1. The pad region 40 is a region where a control pad 41 for controlling the semiconductor device 100 is provided. The IGBT region 10 is also called a cell region. A termination region 30 is provided around the combined region of the cell region and pad region 40 to maintain the breakdown voltage of the semiconductor device 100. A well-known breakdown voltage maintaining structure can be appropriately selected and provided in the termination region 30. The breakdown voltage holding structure may be configured, for example, by providing an FLR (Field Limiting Ring) on ​​the first main surface side, which is the front surface side of the semiconductor device 100, in which a p-type termination well layer of a p-type semiconductor surrounds the combined region of the cell region and the pad region 40, or a VLD (Variation of Lateral Doping) in which a p-type termination well layer with a concentration gradient surrounds the combined region of the cell region and the pad region 40. The number of ring-shaped p-type termination well layers used in the FLR and the concentration distribution used in the VLD may be appropriately selected depending on the breakdown voltage design of the semiconductor device 100. Furthermore, a p-type termination well layer may be provided over almost the entire pad region 40, or an IGBT cell may be provided in the pad region 40.

[0016] The control pad 41 may be, for example, a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, or temperature sense diode pads 41d and 41e. The current sense pad 41a is a control pad for detecting a current flowing in a cell region of the semiconductor device 100, and is electrically connected to a portion of the IGBT cells or diode cells in the cell region so that when a current flows in the cell region of the semiconductor device 100, a current that is one-several to one-tens-of-thousandth of the current flowing in the entire cell region flows.

[0017] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate drive voltage is applied for on / off control of the semiconductor device 100. The Kelvin emitter pad 41b is connected to the p-type base layer and n-type base layer of the IGBT cell. +The Kelvin emitter pad 41b and the p-type base layer are electrically connected to the p-type emitter layer, and the gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. + The temperature sensing diode pads 41d and 41e may be electrically connected to the anode and cathode of a temperature sensing diode provided in the semiconductor device 100 via a mold contact layer. The temperature sensing diode pads 41d and 41e are control pads electrically connected to the anode and cathode of a temperature sensing diode (not shown) provided in the cell region, and the temperature of the semiconductor device 100 is measured by measuring the voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the cell region.

[0018] (2) Overall planar structure of stripe-type RC-IGBT In FIG. 2 , the semiconductor device 100 includes an IGBT region 10 and a diode region 20 within the semiconductor device. The IGBT region 10 and the diode region 20 extend from one end to the other end of the semiconductor device 100 and are arranged in alternating stripes in a direction perpendicular to the extension direction of the IGBT region 10 and the diode region 20. In FIG. 2 , three IGBT regions 10 and two diode regions are shown, and all of the diode regions 20 are sandwiched between the IGBT regions 10. However, the number of IGBT regions 10 and the diode region 20 is not limited to this. The number of IGBT regions 10 may be three or more or less, and the number of diode regions 20 may be two or more or less. Furthermore, the positions of the IGBT regions 10 and the diode regions 20 in FIG. 2 may be interchanged, or all of the IGBT regions 10 may be sandwiched between the diode regions 20. Furthermore, one IGBT region 10 and one diode region 20 may be provided adjacent to each other.

[0019] As shown in FIG. 2 , a pad region 40 is provided adjacent to the lower side of the IGBT region 10. The pad region 40 is a region where a control pad 41 for controlling the semiconductor device 100 is provided. The IGBT region 10 and the diode region 20 are collectively referred to as a cell region. A termination region 30 is provided around the combined region of the cell region and the pad region 40 to maintain the breakdown voltage of the semiconductor device 100. A known breakdown voltage maintaining structure can be appropriately selected and provided in the termination region 30. The breakdown voltage maintaining structure may be configured, for example, by providing, on the first main surface side (the front surface side) of the semiconductor device 100, a field limiting ring (FLR) that surrounds the combined region of the cell region and the pad region 40 with a p-type termination well layer of a p-type semiconductor, or a variation of lateral doping (VLD) that surrounds the combined region of the cell region and the pad region 40 with a p-type termination well layer with a concentration gradient. The number of ring-shaped p-type termination well layers used in the FLR and the concentration distribution used in the VLD may be appropriately selected depending on the breakdown voltage design of the semiconductor device 100. In addition, a p-type termination well layer may be provided over almost the entire area of ​​the pad region 40, and an IGBT cell or a diode cell may be provided in the pad region 40.

[0020] The control pad 41 may be, for example, a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, or temperature sense diode pads 41d and 41e. The current sense pad 41a is a control pad for detecting a current flowing in a cell region of the semiconductor device 100, and is electrically connected to a portion of the IGBT cells or diode cells in the cell region so that when a current flows in the cell region of the semiconductor device 100, a current that is one-several to one-tens-of-thousandth of the current flowing in the entire cell region flows.

[0021] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate drive voltage is applied for on / off control of the semiconductor device 100. The Kelvin emitter pad 41b is connected to the p-type base layer and n-type base layer of the IGBT cell. +The Kelvin emitter pad 41b and the p-type base layer are electrically connected to the p-type emitter layer, and the gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. + The temperature sensing diode pads 41d and 41e may be electrically connected to the anode and cathode of a temperature sensing diode provided in the semiconductor device 100 via a mold contact layer. The temperature sensing diode pads 41d and 41e are control pads electrically connected to the anode and cathode of a temperature sensing diode (not shown) provided in the cell region, and the temperature of the semiconductor device 100 is measured by measuring the voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the cell region.

[0022] (3) Island-type overall planar structure 3, the semiconductor device 100 includes an IGBT region 10 and a diode region 20 within a single semiconductor device. A plurality of diode regions 20 are arranged side by side in both the vertical and horizontal directions within the semiconductor device, and the diode regions 20 are surrounded by the IGBT region 10. In other words, a plurality of diode regions 20 are arranged in an island shape within the IGBT region 10. In FIG. 3, the diode regions 20 are shown arranged in a matrix shape with four columns in the left-right direction of the page and two rows in the upper-right direction of the page, but the number and arrangement of the diode regions 20 are not limited to this. It is sufficient that one or a plurality of diode regions 20 are arranged in a scattered manner within the IGBT region 10, and each diode region 20 is surrounded by the IGBT region 10.

[0023] As shown in FIG. 3 , a pad region 40 is provided adjacent to the lower side of the IGBT region 10. The pad region 40 is a region where a control pad 41 for controlling the semiconductor device 100 is provided. The IGBT region 10 and the diode region 20 are collectively referred to as a cell region. A termination region 30 is provided around the combined region of the cell region and the pad region 40 to maintain the breakdown voltage of the semiconductor device 100. A known breakdown voltage maintaining structure can be appropriately selected and provided in the termination region 30. The breakdown voltage maintaining structure may be configured, for example, by providing, on the first main surface side (the front surface side) of the semiconductor device 100, a field limiting ring (FLR) that surrounds the combined region of the cell region and the pad region 40 with a p-type termination well layer of a p-type semiconductor, or a variation of lateral doping (VLD) that surrounds the combined region of the cell region and the pad region 40 with a p-type termination well layer with a concentration gradient. The number of ring-shaped p-type termination well layers used in the FLR and the concentration distribution used in the VLD may be appropriately selected depending on the breakdown voltage design of the semiconductor device 100. In addition, a p-type termination well layer may be provided over almost the entire area of ​​the pad region 40, and an IGBT cell or a diode cell may be provided in the pad region 40.

[0024] The control pad 41 may be, for example, a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, or temperature sense diode pads 41d and 41e. The current sense pad 41a is a control pad for detecting a current flowing in a cell region of the semiconductor device 100, and is electrically connected to a portion of the IGBT cells or diode cells in the cell region so that when a current flows in the cell region of the semiconductor device 100, a current that is one-several to one-tens-of-thousandth of the current flowing in the entire cell region flows.

[0025] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate drive voltage is applied for on / off control of the semiconductor device 100. The Kelvin emitter pad 41b is connected to the p-type base layer and n-type base layer of the IGBT cell. +The Kelvin emitter pad 41b and the p-type base layer are electrically connected to the p-type emitter layer, and the gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. + The temperature sensing diode pads 41d and 41e may be electrically connected to the anode and cathode of a temperature sensing diode provided in the semiconductor device 100 via a mold contact layer. The temperature sensing diode pads 41d and 41e are control pads electrically connected to the anode and cathode of a temperature sensing diode (not shown) provided in the cell region, and the temperature of the semiconductor device 100 is measured by measuring the voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the cell region.

[0026] (4) Example of the structure of the IGBT region 10 Fig. 4 is a partially enlarged plan view showing the configuration of an IGBT region of a semiconductor device that is an RC-IGBT. Figs. 5 and 6 are cross-sectional views showing the configuration of an IGBT region of a semiconductor device that is an RC-IGBT. Fig. 4 is an enlarged view of the region surrounded by dashed line 82 in semiconductor device 100 shown in Fig. 2 or semiconductor device 100 shown in Fig. 3. Fig. 5 is a cross-sectional view of semiconductor device 100 shown in Fig. 4 taken along dashed line AA, and Fig. 6 is a cross-sectional view of semiconductor device 100 shown in Fig. 4 taken along dashed line BB.

[0027] 4, active trench gates 11 and dummy trench gates 12 are provided in a striped pattern in the IGBT region 10. In a stripe-type RC-IGBT, the active trench gates 11 and dummy trench gates 12 extend in the longitudinal direction of the IGBT region 10, and the longitudinal direction of the IGBT region 10 is the longitudinal direction of the active trench gates 11 and dummy trench gates 12. On the other hand, in an island-type RC-IGBT, there is no particular distinction between the longitudinal direction and the lateral direction of the IGBT region 10, but the longitudinal direction of the active trench gates 11 and dummy trench gates 12 may be the left-right direction on the page, or the vertical direction on the page may be the longitudinal direction of the active trench gates 11 and dummy trench gates 12.

[0028] The active trench gate 11 is configured by providing a gate trench electrode 11a in a trench formed in the semiconductor substrate with a gate trench insulating film 11b interposed therebetween. The dummy trench gate 12 is configured by providing a dummy trench electrode 12a in a trench formed in the semiconductor substrate with a dummy trench insulating film 12b interposed therebetween. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 41c. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to an emitter electrode provided on the first main surface of the semiconductor device 100.

[0029] n + The n-type emitter layer 13 is provided on both sides of the active trench gate 11 in the width direction so as to contact the gate trench insulating film 11b. + The emitter layer 13 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+17 / cm 3 ~1.0E+20 / cm 3 n + The emitter layer 13 is p + The contact layer 14 is formed alternately with the contact layer 14. + The contact layer 14 is also provided between two adjacent dummy trench gates 12. + The contact layer 14 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0E+15 / cm 3 ~1.0E+20 / cm 3 is.

[0030] As shown in FIG. 4 , the IGBT region 10 of the semiconductor device 100 is configured such that three active trench gates 11 are lined up next to three dummy trench gates 12, and three active trench gates 11 are lined up next to three dummy trench gates 12. In this manner, the IGBT region 10 is configured such that sets of active trench gates 11 and sets of dummy trench gates 12 are alternately arranged. In FIG. 4 , the number of active trench gates 11 included in one set of active trench gates 11 is three, but it may be one or more. Furthermore, the number of dummy trench gates 12 included in one set of dummy trench gates 12 may be one or more, and the number of dummy trench gates 12 may be zero. In other words, all trenches provided in the IGBT region 10 may be active trench gates 11.

[0031] 5 is a cross-sectional view of the semiconductor device 100 taken along the dashed line AA in FIG. 4, and is a cross-sectional view of the IGBT region 10. The semiconductor device 100 is an n-type semiconductor device made of a semiconductor substrate. - The n-type drift layer 1 is - The drift layer 1 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+12 / cm 3 ~1.0E+15 / cm 3 In FIG. 5, the semiconductor substrate is + type emitter layer 13 and p + The range is from the p-type contact layer 14 to the p-type collector layer 16. + type emitter layer 13 and p + The upper end of the p-type contact layer 14 on the paper surface is called the first main surface of the semiconductor substrate, and the lower end of the p-type collector layer 16 on the paper surface is called the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the front side of the semiconductor device 100, and the second main surface of the semiconductor substrate is the main surface on the back side of the semiconductor device 100. In the IGBT region 10, which is the cell region, the semiconductor device 100 has an n-type contact layer between the first main surface and the second main surface opposite to the first main surface. - The semiconductor device has a type drift layer 1.

[0032] As shown in FIG. 5, in the IGBT region 10, n- On the first main surface side of the n-type drift layer 1, - The n-type carrier accumulation layer 2 has a higher concentration of n-type impurities than the n-type drift layer 1. The n-type carrier accumulation layer 2 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+13 / cm 3 ~1.0E+17 / cm 3 In the semiconductor device 100, the n-type carrier accumulation layer 2 is not provided, and the n-type carrier accumulation layer 2 shown in FIG. - The n-type drift layer 1 may be provided. By providing the n-type carrier accumulation layer 2, it is possible to reduce the current loss when a current flows through the IGBT region 10. - The combined layer and the type drift layer 1 may be called a drift layer.

[0033] The n-type carrier accumulation layer 2 is - n-type impurities are ion-implanted into the semiconductor substrate that constitutes the n-type drift layer 1, and then annealed to convert the implanted n-type impurities into n-type impurities. - The dopant is formed by diffusing it into the semiconductor substrate, which is the type drift layer 1.

[0034] A p-type base layer 15 is provided on the first main surface side of the n-type carrier accumulation layer 2. The p-type base layer 15 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0E+12 / cm 3 ~1.0E+19 / cm 3 The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11. On the first main surface side of the p-type base layer 15, there is provided an n-type base layer 15 in contact with the gate trench insulating film 11b of the active trench gate 11. + A type emitter layer 13 is provided, and a p + A contact layer 14 is provided. + type emitter layer 13 and p + The p-type contact layer 14 constitutes the first main surface of the semiconductor substrate. + The p-type contact layer 14 is a region having a higher concentration of p-type impurities than the p-type base layer 15.+ When it is necessary to distinguish between the p-type contact layer 14 and the p-type base layer 15, they may be referred to individually. + The p-type contact layer 14 and the p-type base layer 15 may be collectively referred to as a p-type base layer.

[0035] In addition, the semiconductor device 100 has n - On the second main surface side of the n-type drift layer 1, - The n-type buffer layer 3 has a higher concentration of n-type impurities than the p-type drift layer 1. The n-type buffer layer 3 is provided to prevent a depletion layer extending from the p-type base layer 15 toward the second main surface from punching through when the semiconductor device 100 is in an off state. The n-type buffer layer 3 is doped with, for example, phosphorus (P) or protons (H + ) may be injected to form phosphorus (P) and protons (H + The n-type buffer layer 3 may be formed by implanting both n-type impurities. 3 ~1.0E+18 / cm 3 is.

[0036] The semiconductor device 100 does not have the n-type buffer layer 3, and the n-type buffer layer 3 shown in FIG. - The n-type buffer layer 3 and the n-type drift layer 1 may be provided. - The combined layer and the type drift layer 1 may be called a drift layer.

[0037] In the semiconductor device 100, a p-type collector layer 16 is provided on the second main surface side of the n-type buffer layer 3. - A p-type collector layer 16 is provided between the drift layer 1 and the second main surface. The p-type collector layer 16 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0E+16 / cm 3 ~1.0E+20 / cm 3The p-type collector layer 16 forms the second main surface of the semiconductor substrate. The p-type collector layer 16 is provided not only in the IGBT region 10 but also in the termination region 30, and the portion of the p-type collector layer 16 provided in the termination region 30 forms a p-type termination collector layer 16a. Furthermore, the p-type collector layer 16 may be provided so that a portion thereof protrudes from the IGBT region 10 into the diode region 20.

[0038] As shown in FIG. 5, the semiconductor device 100 includes a first main surface of a semiconductor substrate, a p-type base layer 15, and an n-type - A trench is formed in the n-type drift layer 1. A gate trench electrode 11a is provided in the trench via a gate trench insulating film 11b, thereby forming an active trench gate 11. The gate trench electrode 11a is connected to the n-type drift layer 1 via the gate trench insulating film 11b. - The n-type drift layer 1 is opposed to the n-type drift layer 1. A dummy trench electrode 12a is provided in the trench via a dummy trench insulating film 12b, thereby forming a dummy trench gate 12. The dummy trench electrode 12a is connected to the n-type drift layer 1 via the dummy trench insulating film 12b. - The gate trench insulating film 11b of the active trench gate 11 faces the p-type base layer 15 and the n-type drift layer 1. + The active trench gate 11 is in contact with the p-type emitter layer 13. When a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 in contact with the gate trench insulating film 11b of the active trench gate 11.

[0039] As shown in FIG. 5, an interlayer insulating film 4 is provided on the gate trench electrode 11a of the active trench gate 11. A barrier metal 5 is formed on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not provided, and on the interlayer insulating film 4. The barrier metal 5 may be, for example, a conductor containing titanium (Ti), such as titanium nitride, or TiSi, which is an alloy of titanium and silicon (Si). As shown in FIG. 5, the barrier metal 5 is formed of n + p-type emitter layer 13 +ohmic contact with the contact layer 14 and the dummy trench electrode 12a, + p-type emitter layer 13 + The barrier metal 5 is electrically connected to the contact layer 14 and the dummy trench electrode 12a. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 may be formed of an aluminum alloy such as an aluminum silicon alloy (Al-Si alloy), or may be an electrode made of a multi-layer metal film formed by electroless plating or electrolytic plating on an electrode formed of an aluminum alloy. The plating film formed by electroless plating or electrolytic plating may be, for example, a nickel (Ni) plating film. Furthermore, if there are fine regions, such as between adjacent interlayer insulating films 4, where the emitter electrode 6 cannot be satisfactorily embedded, tungsten, which has better embedding properties than the emitter electrode 6, may be disposed in the fine regions, and the emitter electrode 6 may be provided on the tungsten. Note that, in the case where the barrier metal 5 is not provided, n + p-type emitter layer 13 + An emitter electrode 6 may be provided on the contact layer 14 and the dummy trench electrode 12a. + The barrier metal 5 may be provided only on an n-type semiconductor layer such as the n-type emitter layer 13. The barrier metal 5 and the emitter electrode 6 may be collectively referred to as an emitter electrode. Although FIG. 5 shows a diagram in which the interlayer insulating film 4 is not provided on the dummy trench electrode 12a of the dummy trench gate 12, the interlayer insulating film 4 may be formed on the dummy trench electrode 12a of the dummy trench gate 12. When the interlayer insulating film 4 is formed on the dummy trench electrode 12a of the dummy trench gate 12, the emitter electrode 6 and the dummy trench electrode 12a may be electrically connected in another cross section.

[0040] A collector electrode 7 is provided on the second main surface side of the p-type collector layer 16. The collector electrode 7 may be made of an aluminum alloy or an aluminum alloy and a plating film, similar to the emitter electrode 6. The collector electrode 7 may also have a different structure from the emitter electrode 6. The collector electrode 7 is in ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16.

[0041] 6 is a cross-sectional view of the semiconductor device 100 taken along dashed line BB in FIG. 4, and is a cross-sectional view of the IGBT region 10. The cross-sectional view taken along dashed line AA in FIG. 5 is a cross-sectional view of the n-type IGBT region 10 provided on the first main surface side of the semiconductor substrate in contact with the active trench gate 11. + The difference is that the n-type emitter layer 13 is not visible in the cross section taken along the dashed line BB in FIG. + The p-type emitter layer 13 is selectively provided on the first main surface side of the p-type base layer. + The p-type contact layer 14 is collectively called the p-type base layer.

[0042] (5) Structure of the IGBT region 10 according to this embodiment 7 to 9 are diagrams showing the structure of the IGBT region 10 of the semiconductor device 100 according to the first embodiment. FIG. 7 is an enlarged plan view of a portion of the IGBT region 10. FIGS. 8 and 9 are cross-sectional views showing the configuration of an IGBT arranged in the IGBT region 10. FIG. 7 is an enlarged view of the region surrounded by dashed line 82 in the semiconductor device 100 shown in FIG. 1, 2, or 3. FIG. 8 is a cross-sectional view taken along dashed line A1-A1 in FIG. 7, and FIG. 9 is a cross-sectional view taken along dashed line B1-B1 in FIG. 7.

[0043] As shown in FIGS. 7 to 9 , a first trench 51 and a second trench 52 having different widths are arranged in the IGBT region 10 of the semiconductor device 100 according to the first embodiment. The width of the second trench 52 is wider than the width of the first trench 51. An active trench gate 11 made up of a gate trench electrode 11 a and a gate trench insulating film 11 b is formed in the first trench 51, and a dummy trench gate 12 made up of a dummy trench electrode 12 a and a dummy trench insulating film 12 b is formed in the second trench 52. (As can be seen from FIGS. 8 and 9 , the dummy trench electrode 12 a in the second trench 52 is connected to the emitter electrode 6 via the barrier metal 5 and does not function as a gate electrode of the IGBT.) Note that, although the entire upper surface of the dummy trench electrode 12 a is connected to the emitter electrode 6 via the barrier metal 5 in FIGS. 8 and 9 , the upper surface of the dummy trench electrode 12 a may be partially covered with the interlayer insulating film 4.

[0044] Here, the direction from the first main surface (the surface on the upper side of the paper in FIGS. 8 and 9 ) of the semiconductor substrate toward the second main surface (the surface on the lower side of the paper in FIGS. 8 and 9 ), i.e., the depth direction from the first main surface of the semiconductor substrate, is defined as a "first direction." Furthermore, the direction perpendicular to the first direction and perpendicular to the longitudinal directions of the first trench 51 and the second trench 52, i.e., the width direction of the first trench 51 and the second trench 52, is defined as a "second direction." In other words, the first direction is the downward direction of the paper in FIGS. 8 and 9 , and the second direction is the lateral direction of the paper in FIGS. 8 and 9 .

[0045] 8 and 9, the depth of the second trench 52 is deeper than the depth of the first trench 51 in the first direction, and the width of the second trench 52 is wider than the width of the first trench 51 in the second direction. A p-type bottom layer 60 is formed at the bottom of the second trench 52 so as to be in contact with the second trench 52. The p-type bottom layer 60 is not formed at the bottom of the first trench 51. The p-type bottom layer 60 at the bottom of the second trench 52 is formed so as not to be in contact with the first trench 51.

[0046] Since the second trenches 52 are deeper than the first trenches 51, the distance between the bottoms of the second trenches 52 in which the p-type bottom layers 60 are provided is longer, which prevents adjacent p-type bottom layers 60 from being connected to each other and blocking the gap between the trenches with the p-type bottom layers 60. This makes it possible to form the p-type bottom layers 60 deeper. Furthermore, since the width of the second trenches 52 is wider, the area occupied by the p-type bottom layers 60 can be increased, thereby enhancing the effect of the p-type bottom layers 60 in alleviating the electric field.

[0047] In this embodiment, the n-type carrier accumulation layer 2 is disposed between the p-type base layer 15 and the p-type bottom layer 60, and the p-type bottom layer 60 is in contact with the n-type carrier accumulation layer 2. This arrangement further suppresses lateral diffusion of the p-type bottom layer 60, improving the effect of suppressing the p-type bottom layer 60 from blocking the spaces between the trenches.

[0048] Furthermore, the bottom of the n-type carrier accumulation layer 2 is made deeper than the bottom of the first trench 51. This configuration further suppresses lateral diffusion of the p-type bottom layer 60. However, if the bottom of the n-type carrier accumulation layer 2 is deeper than the bottom of the p-type bottom layer 60, the electric field generated in the n-type carrier accumulation layer 2 becomes stronger. Therefore, it is preferable that the bottom of the n-type carrier accumulation layer 2 is shallower than the bottom of the p-type bottom layer 60.

[0049] Here, an example has been shown in which the active trench gate 11 is formed in the first trench 51 and the dummy trench gate 12 is formed in the second trench 52, but the opposite may also be true, in which the dummy trench gate 12 is formed in the first trench 51 and the dummy trench gate 12 is formed in the second trench 52.

[0050] 7, the first trenches 51 and the second trenches 52 are alternately arranged one by one. However, the IGBT region 10 may include a region where a plurality of first trenches 51 are continuously arranged and a region where a plurality of second trenches 52 are continuously arranged. In other words, it is not necessary for all first trenches 51 to be adjacent to the second trenches 52, as long as at least some of the first trenches 51 are adjacent to the second trenches 52. Similarly, it is not necessary for all second trenches 52 to be adjacent to the first trenches 51, as long as at least some of the second trenches 52 are adjacent to the first trenches 51. When dummy trench gates 12 are formed in the second trenches 52, the p-type bottom layers 60 at the bottoms of adjacent second trenches 52 may be connected to each other in the region where the second trenches 52 are continuously arranged.

[0051] (6) Example of the structure of the diode region 20 Fig. 10 is a partially enlarged plan view showing the configuration of a diode region of a semiconductor device that is an RC-IGBT. Figs. 11 and 12 are cross-sectional views showing the configuration of a diode region of a semiconductor device that is an RC-IGBT. Fig. 10 is an enlarged view of the region surrounded by dashed line 83 in semiconductor device 100 shown in Fig. 2. Fig. 11 is a cross-sectional view taken along dashed line CC of semiconductor device 100 shown in Fig. 10. Fig. 12 is a cross-sectional view taken along dashed line DD of semiconductor device 100 shown in Fig. 10.

[0052] The diode trench gate 21 extends from one end side of the diode region 20, which is a cell region, to the other opposing end side along the first main surface of the semiconductor device 100. The diode trench gate 21 is configured by providing a diode trench electrode 21a via a diode trench insulating film 21b in a trench formed in the semiconductor substrate of the diode region 20. The diode trench electrode 21a is connected to the n-type MOS transistor 100 via the diode trench insulating film 21b. - The p-type drift layer 1 is opposed to the p-type drift layer 1. + A p-type contact layer 24 and a p-type anode layer 25 are provided. +The contact layer 24 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0E+15 / cm 3 ~1.0E+20 / cm 3 The p-type anode layer 25 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+12 / cm 3 ~1.0E+19 / cm 3 p + The p-type contact layers 24 and the p-type anode layers 25 are alternately provided in the longitudinal direction of the diode trench gate 21 .

[0053] 11 is a cross-sectional view of the semiconductor device 100 taken along the dashed line CC in FIG. 10, and is a cross-sectional view of the diode region 20. The semiconductor device 100 has an n-type semiconductor layer made of a semiconductor substrate in the diode region 20 as well as in the IGBT region 10. - The n-type drift layer 1 is formed in the diode region 20. - n-type drift layer 1 and IGBT region 10 - The p-type drift layer 1 is formed integrally and continuously from the same semiconductor substrate. + Type contact layer 24 to n + The area extends to the cathode layer 26. + The upper end of the n-type contact layer 24 in the drawing corresponds to the first main surface of the semiconductor substrate. + The lower end of the cathode layer 26 in the drawing is called the second main surface of the semiconductor substrate. The first main surface of the diode region 20 and the first main surface of the IGBT region 10 are flush with each other, and the second main surface of the diode region 20 and the second main surface of the IGBT region 10 are flush with each other.

[0054] As shown in FIG. 11, in the diode region 20, similarly to the IGBT region 10, n - An n-type carrier accumulation layer 2 is provided on the first main surface side of the n-type drift layer 1, -An n-type buffer layer 3 is provided on the second main surface side of the n-type drift layer 1. The n-type carrier accumulation layer 2 and n-type buffer layer 3 provided in the diode region 20 have the same configuration as the n-type carrier accumulation layer 2 and n-type buffer layer 3 provided in the IGBT region 10. Note that it is not always necessary to provide the n-type carrier accumulation layer 2 in the IGBT region 10 and the diode region 20, and even if the n-type carrier accumulation layer 2 is provided in the IGBT region 10, the diode region 20 may not have the n-type carrier accumulation layer 2. Also, like the IGBT region 10, - The n-type drift layer 1, the n-type carrier accumulation layer 2, and the n-type buffer layer 3 may be collectively referred to as a drift layer.

[0055] A p-type anode layer 25 is provided on the first major surface side of the n-type carrier accumulation layer 2. The p-type anode layer 25 is - The p-type anode layer 25 is provided between the first main surface and the first drift layer 1. The p-type anode layer 25 may have the same p-type impurity concentration as the p-type base layer 15 of the IGBT region 10, and the p-type anode layer 25 and the p-type base layer 15 may be formed simultaneously. Alternatively, the p-type impurity concentration of the p-type anode layer 25 may be set lower than the p-type impurity concentration of the p-type base layer 15 of the IGBT region 10, thereby reducing the number of holes injected into the diode region 20 during diode operation. Reducing the number of holes injected during diode operation can reduce recovery loss during diode operation.

[0056] The first main surface side of the p-type anode layer 25 is + A contact layer 24 is provided. + The concentration of the p-type impurity in the contact layer 24 is + The concentration of the p-type impurity in the contact layer 14 may be the same as or different from the p-type impurity in the contact layer 14. + The p-type contact layer 24 constitutes the first main surface of the semiconductor substrate. + The p-type contact layer 24 is a region having a higher concentration of p-type impurities than the p-type anode layer 25. +When it is necessary to distinguish between the p-type contact layer 24 and the p-type anode layer 25, they may be referred to individually. + The p-type contact layer 24 and the p-type anode layer 25 may be collectively referred to as a p-type anode layer.

[0057] In the diode region 20, an n-type buffer layer 3 is provided on the second main surface side thereof. + A cathode layer 26 is provided. + The cathode layer 26 is an n-type - The n-type drift layer 1 is provided between the n-type drift layer 1 and the second main surface. + The cathode layer 26 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+16 / cm 3 ~1.0E+21 / cm 3 As shown in Figure 3, n + The cathode layer 26 is provided on part or all of the diode region 20. + The cathode layer 26 forms the second main surface of the semiconductor substrate. + The p-type impurity is further selectively implanted into the region where the p-type cathode layer 26 is formed, + A part of the region where the p-type cathode layer 26 is formed may be made into a p-type semiconductor to provide a p-type cathode layer.

[0058] As shown in FIG. 11, the diode region 20 of the semiconductor device 100 includes an n-type anode layer 25 extending from the first main surface of the semiconductor substrate. - A trench is formed in the diode region 20, reaching the n-type drift layer 1. A diode trench electrode 21a is provided in the trench of the diode region 20 via a diode trench insulating film 21b, thereby forming a diode trench gate 21. The diode trench electrode 21a is connected to the n-type drift layer 1 via the diode trench insulating film 21b. - The semiconductor layer 1 faces the semiconductor layer 2 .

[0059] As shown in FIG. 11, the diode trench electrode 21a and p +A barrier metal 5 is provided on the contact layer 24. The barrier metal 5 is formed between the diode trench electrode 21a and the p + ohmic contact with the contact layer 24, and the diode trench electrode and p + The barrier metal 5 is electrically connected to the diode trench electrode 21a and the p-type contact layer 24. The barrier metal 5 may have the same configuration as the barrier metal 5 in the IGBT region 10. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 provided in the diode region 20 is formed continuously with the emitter electrode 6 provided in the IGBT region 10. As in the case of the IGBT region 10, the barrier metal 5 is not provided and the diode trench electrode 21a and the p-type contact layer 24 are electrically connected to the diode trench electrode 21a and the p-type contact layer 24. + The contact layer 24 and the emitter electrode 6 may be in ohmic contact. Although FIG. 11 shows a case where the interlayer insulating film 4 is not provided on the diode trench electrode 21a of the diode trench gate 21, the interlayer insulating film 4 may be formed on the diode trench electrode 21a of the diode trench gate 21. When the interlayer insulating film 4 is formed on the diode trench electrode 21a of the diode trench gate 21, the emitter electrode 6 and the diode trench electrode 21a may be electrically connected in another cross section.

[0060] n + A collector electrode 7 is provided on the second main surface side of the cathode layer 26. Similar to the emitter electrode 6, the collector electrode 7 of the diode region 20 is formed continuously with the collector electrode 7 provided in the IGBT region 10. The collector electrode 7 is an n-type + ohmic contact with the n-type cathode layer 26, + The cathode layer 26 is electrically connected to the cathode layer 26 .

[0061] 12 is a cross-sectional view of the semiconductor device 100 taken along dashed line DD in FIG. 10, and is a cross-sectional view of the diode region 20. The cross-sectional view taken along dashed line CC in FIG. 11 is a cross-sectional view of the semiconductor device 100 taken along dashed line CC in FIG. 11, and is a cross-sectional view of the diode region 20. + The difference is that the p-type contact layer 24 is not provided, and the p-type anode layer 25 constitutes the first main surface of the semiconductor substrate.+ The p-type contact layer 24 is selectively provided on the first major surface side of the p-type anode layer 25 .

[0062] (7) Structure of the Diode Region 20 According to the Present Embodiment 13 to 15 are diagrams showing the structure of the diode region 20 of the semiconductor device 100 according to the first embodiment. FIG. 13 is an enlarged plan view of a portion of the diode region 20. FIGS. 14 and 15 are cross-sectional views showing the configuration of a diode arranged in the diode region 20. FIG. 13 is an enlarged view of the region surrounded by the dashed line 83 in the semiconductor device 100 shown in FIG. 2 or 3. FIG. 14 is a cross-sectional view taken along dashed line C1-C1 in FIG. 13, and FIG. 15 is a cross-sectional view taken along dashed line D1-D1 in FIG. 13.

[0063] 13 to 15, in the semiconductor device 100 according to the first embodiment, a first trench 51 and a second trench 52 having different widths are also arranged in the diode region 20. The width of the second trench 52 is wider than the width of the first trench 51. A diode trench gate 21 made up of a diode trench electrode 21a and a diode trench insulating film 21b is formed in both the first trench 51 and the second trench 52.

[0064] 14 and 15 , in the first direction (downward in the plane of the paper), the depth of the second trench 52 is deeper than the depth of the first trench 51, and in the second direction (lateral in the plane of the paper), the width of the second trench 52 is wider than the width of the first trench 51. A p-type bottom layer 60 is formed at the bottom of the second trench 52 so as to be in contact with the second trench 52. The p-type bottom layer 60 also has the effect of alleviating the electric field in the diode region 20. The p-type bottom layer 60 is not formed at the bottom of the first trench 51. The p-type bottom layer 60 at the bottom of the second trench 52 is formed so as not to be in contact with the first trench 51.

[0065] Since the second trenches 52 are deeper than the first trenches 51, the distance between the bottoms of the second trenches 52 in which the p-type bottom layers 60 are provided is longer, which prevents adjacent p-type bottom layers 60 from being connected to each other and blocking the gap between the trenches with the p-type bottom layers 60. This makes it possible to form the p-type bottom layers 60 deeper. Furthermore, since the width of the second trenches 52 is wider, the area occupied by the p-type bottom layers 60 can be increased, thereby enhancing the effect of the p-type bottom layers 60 in alleviating the electric field.

[0066] 13, the first trenches 51 and the second trenches 52 are arranged alternately, but the diode region 20 may include a region where a plurality of first trenches 51 are arranged continuously and a region where a plurality of second trenches 52 are arranged continuously. In other words, it is not necessary for all the first trenches 51 to be adjacent to the second trenches 52, as long as at least some of the first trenches 51 are adjacent to the second trenches 52. Similarly, it is not necessary for all the second trenches 52 to be adjacent to the first trenches 51, as long as at least some of the second trenches 52 are adjacent to the first trenches 51.

[0067] The proportion of the region in the diode region 20 where the p-type bottom layer 60 is arranged and the proportion of the region in the IGBT region 10 where the p-type bottom layer 60 is arranged may be different from each other.

[0068] 14 and 15 show an example in which the n-type carrier accumulation layer 2 is formed in the diode region 20, but the n-type carrier accumulation layer 2 does not necessarily have to be provided in the diode region 20.

[0069] (8) Boundary region between the IGBT region 10 and the diode region 20 16 is a cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of a semiconductor device that is an RC-IGBT. FIG. 16 is a cross-sectional view taken along dashed line GG in the semiconductor device 100 shown in FIG.

[0070] 16, the p-type collector layer 16 provided on the second main surface side of the IGBT region 10 is provided so as to protrude into the diode region 20 by a distance U1 from the boundary between the IGBT region 10 and the diode region 20. By providing the p-type collector layer 16 so as to protrude into the diode region 20, the n-type collector layer 16 of the diode region 20 can be + The distance between the cathode layer 26 and the active trench gate 11 can be increased, and even when a gate drive voltage is applied to the gate trench electrode 11a during freewheeling diode operation, n + This can prevent current from flowing through the cathode layer 26. The distance U1 may be, for example, 100 μm. Depending on the application of the semiconductor device 100, which is an RC-IGBT, the distance U1 may be zero or a distance less than 100 μm.

[0071] (9) Example of the structure of the termination region 30 17 and 18 are cross-sectional views showing the configuration of the termination region of a semiconductor device that is an RC-IGBT. Fig. 17 is a cross-sectional view taken along dashed line EE in Fig. 2 or 3, and is a cross-sectional view from the IGBT region 10 to the termination region 30. Fig. 18 is a cross-sectional view taken along dashed line FF in Fig. 2, and is a cross-sectional view from the diode region 20 to the termination region 30.

[0072] As shown in FIGS. 17 and 18, the termination region 30 of the semiconductor device 100 has n-type junctions between the first and second main surfaces of the semiconductor substrate. - The termination region 30 has a n-type drift layer 1. The first and second main surfaces of the termination region 30 are flush with the first and second main surfaces of the IGBT region 10 and the diode region 20, respectively. - The n-type drift layer 1 is formed in the IGBT region 10 and the diode region 20. - It has the same configuration as the drift layer 1 and is formed continuously and integrally.

[0073] n - The first main surface side of the n-type drift layer 1, i.e., the first main surface of the semiconductor substrate,- A p-type termination well layer 31 is provided between the n-type drift layer 1 and the n-type drift layer 1. The p-type termination well layer 31 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+14 / cm 3 ~1.0E+19 / cm 3 The p-type termination well layer 31 is provided to surround the cell region including the IGBT region 10 and the diode region 20. The p-type termination well layer 31 is provided in a ring shape, and the number of p-type termination well layers 31 provided is appropriately selected depending on the breakdown voltage design of the semiconductor device 100. In addition, on the outer edge side of the p-type termination well layer 31, there is an n + A type channel stopper layer 32 is provided, and an n + The p-type channel stopper layer 32 surrounds the p-type termination well layer 31 .

[0074] n - A p-type termination collector layer 16a is provided between the drift layer 1 and the second main surface of the semiconductor substrate. The p-type termination collector layer 16a is formed integrally and continuously with the p-type collector layer 16 provided in the cell region. Therefore, the p-type collector layer 16 may be collectively referred to as the p-type collector layer 16. In a configuration that can accommodate the diode region 20 adjacent to the termination region 30, such as the semiconductor device 100 shown in FIG. 2, the end of the p-type termination collector layer 16a on the diode region 20 side is provided so as to protrude into the diode region 20 by a distance U2, as shown in FIG. 18. In this way, by providing the p-type termination collector layer 16a so as to protrude into the diode region 20, the n-type collector layer 16a of the diode region 20 can be reduced. + This increases the distance between the p-type cathode layer 26 and the p-type termination well layer 31, thereby preventing the p-type termination well layer 31 from functioning as the anode of a diode. The distance U2 may be, for example, 100 μm.

[0075] A collector electrode 7 is provided on the second main surface of the semiconductor substrate. The collector electrode 7 is formed continuously and integrally from the cell region including the IGBT region 10 and the diode region 20 to the termination region 30. On the other hand, an emitter electrode 6 continuing from the cell region and a termination electrode 6a separated from the emitter electrode 6 are provided on the first main surface of the semiconductor substrate in the termination region 30.

[0076] The emitter electrode 6 and the termination electrode 6a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 may be, for example, a semi-insulating silicon nitride (sinSiN) film. The termination electrode 6a, the p-type termination well layer 31, and the n-type termination well layer 32 are electrically connected via a semi-insulating film 33. + The emitter electrode 6 is electrically connected to the channel stopper layer 32 via a contact hole formed in the interlayer insulating film 4 provided on the first main surface of the termination region 30. In addition, a termination protective film 34 is provided in the termination region 30 to cover the emitter electrode 6, the termination electrode 6a, and the semi-insulating film 33. The termination protective film 34 may be made of, for example, polyimide.

[0077] 19 is a cross-sectional view showing another example of the configuration of the termination region of a semiconductor device that is an RC-IGBT, showing a cross section across diode region 20, IGBT region 10, and termination region 30. A wiring region 70 is provided in the inner peripheral portion of termination region 30. Here, wiring region 70 is considered to be included in termination region 30, but wiring region 70 and termination region 30 may also be defined as separate regions.

[0078] Wiring electrodes 6b such as gate wiring are arranged in the wiring region 70. The termination electrodes 6a in the termination region 30 and the wiring electrodes 6b in the wiring region 70 are covered with a protective insulating film .

[0079] The semiconductor substrate of the termination region 30 contains n - A p-type termination well layer 31 is formed on the first main surface side of the drift layer 1. In the example of Fig. 19, the p-type termination well layer 31 has a VLD structure.

[0080] Furthermore, a wiring region 70, which is the inner peripheral portion of the termination region 30, is provided with a plurality of trenches, similar to the IGBT region 10 and the diode region 20. Here, the outermost trench among the trenches provided in the termination region 30 is defined as the "outermost trench." An outermost trench gate 71 having a configuration similar to that of the active trench gate 11 and the dummy trench gate 12 is formed in the outermost trench. That is, the outermost trench gate 71 includes an insulating film (outermost trench insulating film 71b) formed on the inner surface of the outermost trench, and an electrode (outermost trench electrode 71a) formed on the insulating film.

[0081] In a trench-gate semiconductor device, an electric field tends to concentrate near the bottom of the outermost trench gate 71, and alleviating the electric field in that area is one of the challenges. In the example of Fig. 19, the depth of the p-type termination well layer 31 is deeper than the depth of the trench, and the bottom of the outermost trench gate 71 is covered with the p-type termination well layer 31. This alleviates the electric field near the bottom of the outermost trench gate 71.

[0082] 20 shows the configuration of FIG. 19 in which the p-type termination well layer 31 is shallower than the trench. In this case, the bottom of the outermost trench gate 71 is not covered with the p-type termination well layer 31, so the electric field near the bottom of the outermost trench gate 71 tends to become strong.

[0083] (10) Structure of the termination region 30 of this embodiment 21 is a cross-sectional view showing the structure of termination region 30 of the semiconductor device according to the present embodiment. As shown in FIG. 21, in the present embodiment, wiring region 70, which is the inner periphery portion of termination region 30 (the boundary portion between the cell region and termination region 30), is provided with first trenches 51 and second trenches 52, similar to IGBT region 10 and diode region 20. An outermost trench gate 71 is disposed in second trench 52. A p-type bottom layer 60 is provided below second trench 52 in which outermost trench gate 71 is disposed, and is in contact with the bottom of second trench 52.

[0084] In this embodiment, the bottom of the p-type termination well layer 31 is shallower than the bottom of the second trench 52 in which the outermost trench gate 71 is disposed. Therefore, the bottom of the outermost trench gate 71 is not covered with the p-type termination well layer 31.

[0085] 21, the p-type bottom layer 60 below the outermost trench can reduce the electric field near the bottom of the outermost trench gate 71. Therefore, even if the bottom of the p-type termination well layer 31 is shallower than the bottom of the outermost trench, the electric field near the bottom of the outermost trench gate 71 is prevented from becoming high.

[0086] In FIG. 21, the outermost end of the n-type carrier accumulation layer 2 is located outside the outermost trench gate 71 (on the right side of the paper), but as shown in FIG. 22, the outermost end of the n-type carrier accumulation layer 2 may be located inside the outermost trench gate 71 (on the left side of the paper).

[0087] Furthermore, multiple outermost trench gates 71 having p-type bottom layers 60 at their bottoms may be arranged in succession. That is, the multiple trenches arranged on the outermost sides of the trenches provided in the termination region 30 may be defined as "outermost trenches," and an outermost trench gate 71 and a p-type bottom layer 60 may be provided in each of the multiple outermost trenches. The effect of alleviating the electric field can be further improved by gradually increasing the spacing between the multiple outermost trench gates 71 toward the outside. The multiple outermost trench gates 71 may be provided in only some of the trenches in the termination region 30, or may be provided in all of the trenches in the termination region 30.

[0088] (11) Examples of manufacturing methods for IGBT and RC-IGBT 23 to 34 are diagrams showing a method for manufacturing a semiconductor device that is an RC-IGBT. Note that the method for manufacturing an IGBT is obtained by extracting the manufacturing process of the IGBT region from the method for manufacturing an RC-IGBT. In other words, the method for manufacturing an IGBT is essentially included in the method for manufacturing an RC-IGBT, so here we will explain the method for manufacturing an RC-IGBT.

[0089] 23 to 30 are diagrams showing the steps of forming the front surface side of the semiconductor device 100, and FIGS. 31 to 34 are diagrams showing the steps of forming the back surface side of the semiconductor device 100. FIG.

[0090] First, as shown in Figure 23, - A semiconductor substrate that constitutes the n-type drift layer 1 is prepared. The semiconductor substrate may be, for example, a so-called FZ wafer produced by the FZ (Floating Zone) method or a so-called MCZ wafer produced by the MCZ (Magnetic field applied CZochralski) method, and may be an n-type wafer containing n-type impurities. The concentration of the n-type impurities contained in the semiconductor substrate is appropriately selected depending on the withstand voltage of the semiconductor device to be fabricated. For example, in a semiconductor device with a withstand voltage of 1200 V, the n-type impurities constituting the semiconductor substrate - The concentration of n-type impurities is adjusted so that the resistivity of the n-type drift layer 1 is about 40 to 120 Ω·cm. As shown in FIG. 23, in the step of preparing the semiconductor substrate, the entire semiconductor substrate is - The semiconductor device 100 is fabricated by implanting p-type or n-type impurity ions into the semiconductor substrate from the first or second main surface side thereof and then diffusing the ions into the semiconductor substrate by heat treatment or the like to form a p-type or n-type semiconductor layer.

[0091] As shown in Figure 23, n -The semiconductor substrate constituting the drift layer 1 includes regions that will become the IGBT region 10 and the diode region 20. Furthermore, although not shown, a region that will become the termination region 30 is also provided around the regions that will become the IGBT region 10 and the diode region 20. The following mainly describes a manufacturing method for the IGBT region 10 and the diode region 20 of the semiconductor device 100, but the termination region 30 of the semiconductor device 100 may be fabricated by a well-known manufacturing method. For example, when forming an FLR having a p-type termination well layer 31 as a breakdown voltage retention structure in the termination region 30, the FLR may be formed by implanting p-type impurity ions before processing the IGBT region 10 and the diode region 20 of the semiconductor device 100, or by implanting p-type impurity ions simultaneously when implanting p-type impurity ions into the IGBT region 10 or the diode region 20 of the semiconductor device 100.

[0092] Next, as shown in FIG. 24 , n-type impurities such as phosphorus (P) are implanted from the first main surface side of the semiconductor substrate to form an n-type carrier accumulation layer 2. Furthermore, p-type impurities such as boron (B) are implanted from the first main surface side of the semiconductor substrate to form a p-type base layer 15 and a p-type anode layer 25. The n-type carrier accumulation layer 2, p-type base layer 15, and p-type anode layer 25 are formed by implanting impurity ions into the semiconductor substrate and then diffusing the impurity ions by heat treatment. The n-type impurities and p-type impurities are implanted after masking the first main surface of the semiconductor substrate, so they are selectively formed on the first main surface side of the semiconductor substrate. The n-type carrier accumulation layer 2, p-type base layer 15, and p-type anode layer 25 are formed in the IGBT region 10 and the diode region 20 and are connected to a p-type termination well layer 31 in the termination region 30. The mask process refers to a process of forming a mask on a semiconductor substrate by applying a resist onto the semiconductor substrate, forming openings in predetermined areas of the resist using photolithography, and then performing ion implantation or etching on the predetermined areas of the semiconductor substrate through the openings.

[0093] The p-type base layer 15 and the p-type anode layer 25 may be formed simultaneously by ion implantation of p-type impurities. In this case, the p-type base layer 15 and the p-type anode layer 25 have the same depth and p-type impurity concentration, resulting in the same configuration. Alternatively, the p-type base layer 15 and the p-type anode layer 25 may have different depths and p-type impurity concentrations by ion implanting p-type impurities into them separately using mask processing.

[0094] Furthermore, the p-type termination well layer 31 formed in another cross section may be formed by ion implantation of p-type impurities at the same time as the p-type anode layer 25. In this case, the p-type termination well layer 31 and the p-type anode layer 25 have the same depth and p-type impurity concentration, making them identical in configuration. Alternatively, the p-type termination well layer 31 and the p-type anode layer 25 may be formed by ion implantation of p-type impurities at the same time, making the p-type termination well layer 31 and the p-type anode layer 25 have different p-type impurity concentrations. In this case, the aperture ratio can be changed by using a mesh mask for one or both of the masks.

[0095] Alternatively, the p-type termination well layer 31 and the p-type anode layer 25 may be ion-implanted with p-type impurities separately using a mask process, thereby making the depths and p-type impurity concentrations of the p-type termination well layer 31 and the p-type anode layer 25 different. The p-type termination well layer 31, the p-type base layer 15, and the p-type anode layer 25 may be formed by ion-implanting p-type impurities simultaneously.

[0096] Next, as shown in FIG. 25, n-type impurities are selectively implanted into the first main surface side of the p-type base layer 15 of the IGBT region 10 by mask processing. + The n-type emitter layer 13 is formed. The n-type impurity to be implanted may be, for example, arsenic (As) or phosphorus (P). Furthermore, a mask process is used to selectively implant p-type impurities into the first main surface side of the p-type base layer 15 in the IGBT region 10. + A p-type contact layer 14 is formed, and p-type impurities are selectively implanted into the first main surface side of the p-type anode layer 25 in the diode region 20 to form a p +A p-type contact layer 24 is formed. The implanted p-type impurity may be, for example, boron (B) or aluminum (Al).

[0097] Next, as shown in FIG. 26, a semiconductor substrate is formed from the first main surface side thereof through the p-type base layer 15 and the p-type anode layer 25, and n - A trench 8 is formed in the IGBT region 10, reaching the n-type drift layer 1. + The trench 8 penetrating the emitter layer 13 has n-type sidewalls. + The trenches 8 form a part of the emitter layer 13. The trenches 8 may be formed by depositing an oxide film such as SiO2 on the semiconductor substrate, then forming openings in the oxide film at the portions where the trenches 8 are to be formed by masking, and etching the semiconductor substrate using the oxide film with the openings as a mask. In FIG. 26, the trenches 8 are formed with the same pitch in the IGBT region 10 and the diode region 20, but the pitch of the trenches 8 may be different in the IGBT region 10 and the diode region 20. The pitch of the trenches 8 in a plan view can be changed as appropriate by changing the mask pattern used in the masking process.

[0098] The process of forming the trench 8 is + type source layer 13 and p + This step may be performed before the step of forming the mold contact layer 14 .

[0099] 27, the semiconductor substrate is heated in an atmosphere containing oxygen to form oxide films 9 on the inner walls of trenches 8 and on the first main surface of the semiconductor substrate. Of the oxide films 9 formed on the inner walls of trenches 8, the oxide films 9 formed in trenches 8 in the IGBT region 10 are gate trench insulating films 11b of active trench gates 11 and dummy trench insulating films 12b of dummy trench gates 12. Furthermore, the oxide films 9 formed in trenches 8 in the diode region 20 are diode trench insulating films 21b. The oxide films 9 formed on the first main surface of the semiconductor substrate are removed in a later process.

[0100] Next, as shown in FIG. 28, polysilicon doped with n-type or p-type impurities is deposited by CVD (chemical vapor deposition) or the like in the trench 8 having an oxide film 9 formed on its inner wall to form a gate trench electrode 11a, a dummy trench electrode 12a, and a diode trench electrode 21a.

[0101] Next, as shown in FIG. 29, the oxide film 9 formed on the first main surface of the semiconductor substrate after forming the interlayer insulating film 4 on the gate trench electrode 11a of the active trench gate 11 in the IGBT region 10 is removed. The interlayer insulating film 4 may be, for example, SiO2. Then, a contact hole is formed in the deposited interlayer insulating film 4 by a mask process. The contact hole is formed by n + On the p-type emitter layer 13, + On the contact layer 14, + It is formed on the mold contact layer 24, the dummy trench electrode 12a, and the diode trench electrode 21a.

[0102] 30, a barrier metal 5 is formed on the first main surface of the semiconductor substrate and on a single interlayer insulating film or an interlayer insulating film 4 of a multilayer structure including an insulating film, and an emitter electrode 6 is further formed on the barrier metal 5. The barrier metal 5 can be omitted, and can be formed by depositing titanium nitride by PVD (physical vapor deposition) or CVD.

[0103] The emitter electrode 6 may be formed by depositing an aluminum silicon alloy (Al-Si alloy) on the barrier metal 5 by PVD such as sputtering or vapor deposition. Alternatively, a nickel alloy (Ni alloy) may be further formed on the formed aluminum silicon alloy by electroless plating or electrolytic plating to form the emitter electrode 6. When the emitter electrode 6 is formed by plating, a thick metal film can be easily formed as the emitter electrode 6, thereby increasing the heat capacity of the emitter electrode 6 and improving its heat resistance. Note that when a nickel alloy is further formed by plating after forming the emitter electrode 6 made of an aluminum silicon alloy by PVD, the plating process to form the nickel alloy may be performed after processing the second main surface of the semiconductor substrate.

[0104] Next, the second main surface side of the semiconductor substrate is ground to thin the semiconductor substrate to a predetermined designed thickness, as shown in Fig. 31. The thickness of the semiconductor substrate after grinding may be, for example, 80 µm to 200 µm.

[0105] 32 , n-type impurities are implanted from the second main surface side of the semiconductor substrate to form an n-type buffer layer 3. Furthermore, p-type impurities are implanted from the second main surface side of the semiconductor substrate to form a p-type collector layer 16. The n-type buffer layer 3 may be formed in the IGBT region 10, the diode region 20, and the termination region 30, or may be formed only in the IGBT region 10 or the diode region 20.

[0106] The n-type buffer layer 3 may be formed by implanting, for example, phosphorus (P) ions. + ) may be implanted. Furthermore, it may be formed by implanting both protons and phosphorus. Protons can be implanted deep into the second main surface of the semiconductor substrate with a relatively low acceleration energy. Furthermore, the depth to which protons are implanted can be changed relatively easily by changing the acceleration energy. Therefore, when forming the n-type buffer layer 3 with protons, if the protons are implanted multiple times while changing the acceleration energy, an n-type buffer layer 3 that is wider in the thickness direction of the semiconductor substrate than when formed with phosphorus can be formed.

[0107] Furthermore, phosphorus can have a higher activation rate as an n-type impurity than protons, so punch-through of the depletion layer can be more reliably suppressed even in a thinned semiconductor substrate by forming the n-type buffer layer 3 with phosphorus. To further thin the semiconductor substrate, it is preferable to form the n-type buffer layer 3 by implanting both protons and phosphorus, and in this case, the protons are implanted deeper from the second main surface than the phosphorus.

[0108] The p-type collector layer 16 may be formed by implanting boron (B), for example. The p-type collector layer 16 is also formed in the termination region 30, and the p-type collector layer 16 in the termination region 30 becomes the p-type termination collector layer 16a. After ion implantation from the second main surface of the semiconductor substrate, the implanted boron is activated by irradiating the second main surface with a laser for laser annealing, thereby forming the p-type collector layer 16. At this time, phosphorus for the n-type buffer layer 3, which is implanted relatively shallow from the second main surface of the semiconductor substrate, is also activated at the same time. Meanwhile, since protons are activated at a relatively low annealing temperature of 350°C to 500°C, care must be taken to prevent the entire semiconductor substrate from being heated to a temperature higher than 350°C to 500°C after the proton implantation, except during the proton activation process. Laser annealing can be used to activate n-type impurities and p-type impurities even after proton implantation, because it can heat only the vicinity of the second main surface of the semiconductor substrate to a high temperature.

[0109] Next, as shown in FIG. + The cathode layer 26 is formed. + 33, the p-type cathode layer 26 may be formed by implanting phosphorus (P). As shown in FIG. 33, the p-type collector layer 16 and the n-type cathode layer 26 are formed at a distance U1 from the boundary between the IGBT region 10 and the diode region 20 toward the diode region 20. + Phosphorus is selectively implanted from the second main surface side by mask processing so that the boundary with the cathode layer 26 is located. +The amount of n-type impurities implanted to form the n-type cathode layer 26 is greater than the amount of p-type impurities implanted to form the p-type collector layer 16. In FIG. 33, the p-type collector layer 16 and the n-type + The depth of the cathode layer 26 is shown as the same, but + The depth of the n-type cathode layer 26 is equal to or greater than the depth of the p-type collector layer 16. + The region where the cathode layer 26 is to be formed must be made into an n-type semiconductor by implanting n-type impurities into the region where p-type impurities have been implanted. + In the entire region where the cathode layer 26 is to be formed, the concentration of the implanted p-type impurities is made higher than the concentration of the n-type impurities.

[0110] Next, as shown in FIG. 34, a collector electrode 7 is formed on the second main surface of the semiconductor substrate. The collector electrode 7 is formed over the entire surfaces of the IGBT region 10, the diode region 20, and the termination region 30 on the second main surface. Alternatively, the collector electrode 7 may be formed over the entire surface of the second main surface of an n-type wafer, which is the semiconductor substrate. The collector electrode 7 may be formed by depositing an aluminum silicon alloy (Al-Si alloy), titanium (Ti), or the like by PVD such as sputtering or vapor deposition, or by laminating multiple metals such as an aluminum silicon alloy, titanium, nickel, or gold. Furthermore, the collector electrode 7 may be formed by forming an additional metal film on a metal film formed by PVD by electroless plating or electrolytic plating.

[0111] The above-described process is used to manufacture the semiconductor device 100. A plurality of semiconductor devices 100 are manufactured in a matrix on a single n-type wafer, and the semiconductor devices 100 are completed by cutting the wafer into individual semiconductor devices 100 by laser dicing or blade dicing.

[0112] (12) A Manufacturing Method of a Semiconductor Device According to the Present Embodiment The semiconductor device according to this embodiment can be formed by forming a first trench 51 and a second trench 52 as trenches 8 in the manufacturing method described above, and then ion-implanting p-type impurities into the bottom of the second trench 52 to form a p-type bottom layer 60. In the step of forming the p-type bottom layer 60, the p-type impurities may be ion-implanted into the entire bottom surface of the second trench 52; however, it is preferable to ion-implant the p-type impurities only into the central portion of the second trench 52 in order to reduce the lateral spread of the p-type bottom layer 60.

[0113] The method for manufacturing the semiconductor device according to this embodiment will be described in more detail with reference to the flow chart of FIG. 35. The semiconductor device according to this embodiment can be formed by a method similar to the example of the manufacturing method described above, so differences from the example of the manufacturing method will be described here. FIG. 35 representatively shows a manufacturing method for forming first trench 51 and second trench 52 in IGBT region 10. The same method as FIG. 35 may also be used when forming first trench 51 and second trench 52 in diode region 20 or termination region 30.

[0114] In the method for manufacturing a semiconductor device according to this embodiment, first trench 51 and second trench 52 are formed in the step of forming trench 8 on the first main surface of a semiconductor substrate (step S1). In this step, second trench 52 needs to be deeper than first trench 51. Generally, the wider a trench is, the deeper it is formed. Therefore, if first trench 51 and second trench 52 are formed under the same etching conditions, second trench 52 will be deeper than first trench 51. Therefore, first trench 51 and second trench 52 can be formed simultaneously, and there is no need to consider alignment between first trench 51 and second trench 52.

[0115] Next, oxide films 9 that will become gate trench insulating films 11b and dummy trench insulating films 12b are formed on the inner surfaces of the first trench 51 and the second trench 52 (step S2). Then, polysilicon doped with n-type or p-type impurities is deposited to form gate trench electrodes 11a and dummy trench electrodes 12a in the first trench 51 and the second trench 52, respectively (step S3).

[0116] Next, using photolithography, a resist mask 80 having an opening in the center of the second trench 52 is formed on the first main surface of the semiconductor substrate, and the central portions of the dummy trench electrodes 12a in the second trenches 52 are removed by etching using the resist mask 80 as a mask (Step S4). Furthermore, using the resist mask 80 as a mask, p-type impurity ions are implanted to form a p-type bottom layer 60 in the portion where the dummy trench electrodes 12a have been removed, i.e., at the bottom of the central portions of the second trenches 52 (Step S5).

[0117] Thereafter, polysilicon doped with n-type or p-type impurities is deposited again to form the dummy trench electrode 12a again in the portion from which the dummy trench electrode 12a was removed in step S4 (step S6). Furthermore, a heat treatment is performed to activate the impurities in the p-type bottom layer 60. Note that in step S6, the portion of the dummy trench electrode 12a removed in step S4 may be filled with a metal film such as aluminum or tungsten, or with an insulating film such as a thermally oxidized film of polysilicon or a CVD oxide film.

[0118] According to this method, the p-type impurity can be ion-implanted only into the central portion of the second trench 52, and therefore, the lateral spread of the p-type bottom layer 60 can be suppressed.

[0119] Another example of the manufacturing method for the semiconductor device according to the present embodiment is shown in Fig. 36. In the manufacturing method of Fig. 36, the step of forming first trench 51 and second trench 52 (step S1) is performed on a semiconductor substrate on which p-type base layer 15 is not formed.

[0120] After the first trench 51 and the second trench 52 are formed, an oxide film 9 that will become a gate trench insulating film 11b and a dummy trench insulating film 12b is formed on their inner surfaces (step S2). Then, polysilicon doped with n-type or p-type impurities is deposited to form a gate trench electrode 11a and a dummy trench electrode 12a in the first trench 51 and the second trench 52, respectively (step S3). At this time, the thickness of the deposited polysilicon is adjusted so that the gate trench electrode 11a fills the entire first trench 51 and the dummy trench electrode 12a is formed on the sidewalls and bottom of the second trench 52.

[0121] Next, when the polysilicon is etched back, the central portion of the dummy trench electrode 12a in the second trench 52 is removed while leaving the gate trench electrode 11a in the first trench 51 and the dummy trench electrode 12a formed on the sidewall of the second trench 52 (Step S4). In this state, p-type impurity ions are implanted into the first main surface of the semiconductor substrate to form a p-type bottom layer 60 in the portion from which the dummy trench electrode 12a has been removed, i.e., at the bottom of the central portion of the second trench 52 (Step S5). At the same time, a p-type base layer 15 is formed near the first main surface of the semiconductor substrate.

[0122] Thereafter, polysilicon doped with n-type or p-type impurities is deposited again to form the dummy trench electrode 12a again in the portion where the dummy trench electrode 12a was removed in step S4 (step S6). Furthermore, a heat treatment is performed to activate the impurities in the p-type bottom layer 60.

[0123] In the manufacturing method of FIG. 36 as well, the p-type impurity can be ion-implanted only into the central portion of the second trench 52, so that the lateral spread of the p-type bottom layer 60 can be suppressed.

[0124] In particular, the manufacturing method of FIG. 36 can selectively remove the central portion of the dummy trench electrode 12a without using a resist mask 80, eliminating the need for an additional photolithography process. Furthermore, the p-type bottom layer 60 can be self-aligned with respect to the second trench 52. Another advantage is that the p-type bottom layer 60 and the p-type base layer 15 can be formed simultaneously, eliminating the need for an impurity implantation process. Therefore, the manufacturing method of FIG. 36 can significantly contribute to simplifying the manufacturing process and reducing manufacturing costs.

[0125] In the above description of the embodiment, an RC-IGBT having an IGBT region and a diode region has been mainly shown as an example of a semiconductor device, but the semiconductor device may be an IGBT alone without a diode region as shown in FIG. 1. Furthermore, the semiconductor device may be a semiconductor device in which the p-type collector layer 16 of the IGBT region is connected to an n-type collector region 16 of the IGBT region. + The semiconductor device may have a MOSFET region in which the diode region is replaced by the cathode layer 26, or may be a MOSFET alone without a diode region. In either case, the same effects as those of the RC-IGBT embodiment can be obtained.

[0126] The above embodiment can be modified or omitted as appropriate.

[0127] <Additional Notes> Various aspects of the present disclosure are summarized below as appendices.

[0128] (Appendix 1) a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface opposite to the first main surface; a plurality of trenches formed in the first main surface of the semiconductor substrate; an insulating film formed on the inner surface of each of the plurality of trenches; an electrode embedded in each of the plurality of trenches via the insulating film; Equipped with The plurality of trenches include: A first trench; a second trench that is deeper and wider than the first trench; Including, a second conductivity type bottom layer is formed below the second trench, the bottom layer being in contact with a bottom of the second trench and not in contact with the first trench; Semiconductor device.

[0129] (Appendix 2) a second conductivity type base layer formed on the first main surface side of the drift layer in the semiconductor substrate; a carrier accumulation layer of a first conductivity type formed between the base layer and the drift layer; Furthermore, the bottom layer is in contact with the carrier accumulation layer; 2. The semiconductor device according to claim 1.

[0130] (Appendix 3) a bottom of the carrier accumulation layer is deeper than a bottom of the first trench and shallower than a bottom of the bottom layer; 3. The semiconductor device according to claim 2.

[0131] (Appendix 4) the semiconductor substrate has a termination region on its outer periphery; the semiconductor substrate in the termination region includes a termination well layer of a second conductivity type formed on the first main surface side of the drift layer, an outermost trench that is the outermost trench disposed in the termination region is the second trench; the bottom layer is formed below the outermost trench; a bottom of the termination well layer is shallower than a bottom of the outermost trench; 4. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0132] (Appendix 5) the semiconductor substrate includes a cathode layer of a first conductivity type on the second main surface side of the drift layer and in contact with the second main surface; 4. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0133] (Appendix 6) the semiconductor substrate includes a collector layer of a second conductivity type on the second main surface side of the drift layer and in contact with the second main surface; 4. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0134] (Appendix 7) The semiconductor substrate is an IGBT region in which an IGBT is formed, the IGBT having the electrode embedded in the first trench or the second trench as a gate electrode; a diode region in which an anode layer of a first conductivity type is arranged on the first main surface side of the drift layer and in contact with the first main surface, and a cathode layer of a second conductivity type is arranged on the second main surface side of the drift layer and in contact with the second main surface; Equipped with 7. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0135] (Appendix 8) the first trench, the second trench, and the bottom layer are also disposed in the diode region; 8. The semiconductor device according to claim 7.

[0136] (Appendix 9) (a) preparing a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface opposite to the first main surface; (b) forming a first trench and a second trench wider than the first trench in the first main surface of the semiconductor substrate; (c) forming an insulating film on the inner surfaces of the first trench and the second trench; (d) forming electrodes in the first trench and the second trench after forming the insulating film; (e) removing a central portion of the electrode in the second trench; (f) forming a bottom layer by ion-implanting impurities of a second conductivity type into the bottom of the second trench in the portion where the electrode has been removed; (g) after forming the bottom layer, forming the electrode again in the area where the electrode was removed; (h) performing a heat treatment to activate the bottom layer; A method for manufacturing a semiconductor device comprising:

[0137] (Appendix 10) The step (e) is carried out by etching back the electrode, By the ion implantation in the step (f), a base layer of the second conductivity type is formed on the first main surface side of the drift layer together with the bottom layer. 10. A method for manufacturing a semiconductor device according to claim 9. [Explanation of symbols]

[0138] 1n - 1. N-type drift layer, 2. n-type carrier accumulation layer, 3. n-type buffer layer, 4. interlayer insulating film, 5. barrier metal, 6. emitter electrode, 6a. termination electrode, 6b. wiring electrode, 7. collector electrode, 8. trench, 9. oxide film, 10. IGBT region, 11. active trench gate, 11a. gate trench electrode, 11b. gate trench insulating film, 12. dummy trench gate, 12a. dummy trench electrode, 12b. dummy trench insulating film, 13. n + Type emitter layer, 14p + 16a p-type collector termination layer; 20 diode region; 21 diode trench gate; 21a diode trench electrode; 21b diode trench insulating film; 24 p + p-type contact layer, 25 p-type anode layer, 26 n + p-type cathode layer, 30 termination region, 31 p-type termination well layer, 32 n +type channel stopper layer, 33 semi-insulating film, 34 termination protective film, 35 protective insulating film, 40 pad region, 41 control pad, 41a current sense pad, 41b Kelvin emitter pad, 41c gate pad, 41d temperature sense diode pad, 41e temperature sense diode pad, 51 first trench, 52 second trench, 60 p-type bottom layer, 70 wiring region, 71 outermost trench gate, 71a outermost trench electrode, 71b outermost trench insulating film, 80 resist mask, 100 semiconductor device.

Claims

1. a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface opposite to the first main surface; a plurality of trenches formed in the first main surface of the semiconductor substrate; an insulating film formed on the inner surface of each of the plurality of trenches; an electrode embedded in each of the plurality of trenches via the insulating film; Equipped with The plurality of trenches include: a first trench; a second trench that is deeper and wider than the first trench; Including, a bottom layer of a second conductivity type is formed below the second trench, the bottom layer being in contact with a bottom of the second trench but not in contact with the first trench; Semiconductor device.

2. a second conductivity type base layer formed on the first main surface side of the drift layer in the semiconductor substrate; a carrier accumulation layer of a first conductivity type formed between the base layer and the drift layer; Furthermore, the bottom layer is in contact with the carrier accumulation layer; The semiconductor device according to claim 1 .

3. a bottom of the carrier accumulation layer is deeper than a bottom of the first trench and shallower than a bottom of the bottom layer; The semiconductor device according to claim 2 .

4. the semiconductor substrate has a termination region on its outer periphery; the semiconductor substrate in the termination region includes a termination well layer of a second conductivity type formed on the first main surface side of the drift layer, an outermost trench that is the outermost trench disposed in the termination region is the second trench; the bottom layer is formed below the outermost trench; a bottom of the termination well layer is shallower than a bottom of the outermost trench; The semiconductor device according to claim 1 .

5. the semiconductor substrate includes a cathode layer of a first conductivity type on the second main surface side of the drift layer and in contact with the second main surface; The semiconductor device according to claim 1 .

6. the semiconductor substrate includes a collector layer of a second conductivity type on the second main surface side of the drift layer and in contact with the second main surface; The semiconductor device according to claim 1 .

7. The semiconductor substrate is an IGBT region in which an IGBT is formed, the IGBT having the electrode embedded in the first trench or the second trench as a gate electrode; a diode region in which an anode layer of a first conductivity type is arranged on the first main surface side of the drift layer and in contact with the first main surface, and a cathode layer of a second conductivity type is arranged on the second main surface side of the drift layer and in contact with the second main surface; Equipped with The semiconductor device according to claim 1 .

8. the first trench, the second trench, and the bottom layer are also disposed in the diode region; The semiconductor device according to claim 7 .

9. (a) preparing a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface opposite to the first main surface; (b) forming a first trench and a second trench wider than the first trench in the first main surface of the semiconductor substrate; (c) forming an insulating film on the inner surfaces of the first trench and the second trench; (d) forming an electrode in the first trench and the second trench after forming the insulating film; (e) removing a central portion of the electrode in the second trench; (f) forming a bottom layer by ion-implanting impurities of a second conductivity type into the bottom of the second trench in the portion where the electrode has been removed; (g) after forming the bottom layer, forming the electrode again in the area where the electrode was removed; (h) performing a heat treatment to activate the bottom layer; A method for manufacturing a semiconductor device comprising:

10. The step (e) is carried out by etching back the electrode, By the ion implantation in the step (f), a base layer of the second conductivity type is formed on the first main surface side of the drift layer together with the bottom layer. The method for manufacturing a semiconductor device according to claim 9 .

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