Driving device for switching element

Abstract

To provide active control in which a resistance value of a resistor connected in series to a control terminal is easily set.SOLUTION: The driving device 10 includes a driver 11, a gate resistor R1, and a resistor R2. The driver 11 generates a drive signal S1 based on a control signal S2 that changes between a low level and a high level, and outputs the drive signal S2 to the gate G of the switching device Q2, thereby switching the switching device Q2 on and off. The gate resistor R1 connects the input terminal To and the gate G. The resistor R2 connects the gate G and the source S. The switching device driving apparatus 10 performs active control by setting the driver 11 to a high impedance state during a switching transition period of the switching device Q2. The high impedance state is a state in which the drive signal S2 is not input to the gate G.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a driving device for a switching element. [Background technology]

[0002] The driving device described in Patent Document 1 drives a switching element. The switching element has a control terminal, a first terminal, and a second terminal. When a voltage is applied to the control terminal, a current flows between the first terminal and the second terminal.

[0003] The driving device includes a driver and a resistor. The driver includes two switches connected in series. The connection point of the two switches is connected to a control terminal of the switching element via a resistor. The driver outputs a driving signal that changes between low and high levels to the control terminal.

[0004] When a high-level drive signal is output, a voltage is applied to the control terminal, turning the switching element on. When a low-level drive signal is output, the charge stored in the control terminal is consumed by the resistor, turning the switching element off. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2011 / 052398 Summary of the Invention [Problem to be solved by the invention]

[0006] Drive devices may use active gate control (hereinafter referred to as active control). Active control is a control that suppresses surge voltages by changing the voltage applied to the control terminal during the switching transition of a switching element. For example, there is active control that suppresses the rate of change of voltage at the control terminal at the end of the transition period by temporarily outputting a reverse drive signal. In this active control, when turning on a switching element, a high-level drive signal is output to the control terminal, causing the switching element to transition from off to on, but a low-level drive signal is temporarily output during this transition period. When turning off a switching element, a low-level drive signal is output to the control terminal, causing the switching element to transition from on to off, but a high-level drive signal is temporarily output during this transition period. Here, the rate of change of the voltage applied to the control terminal also changes depending on the resistance value of the resistor connected in series with the control terminal.

[0007] The lower the resistance value of the resistor connected in series to the control terminal, the faster the switching speed of the switching element. Switching elements such as SiC and GaN, which have recently become practical, have fast switching speeds. To take advantage of this characteristic, the resistance value of the resistor connected to the control terminal tends to be low. On the other hand, if the resistance value of the resistor connected to the control terminal is low, the voltage applied to the control terminal changes over a short period of time during active control. This increases the impact of voltage changes at the control terminal due to the temporarily output reverse drive signal in the above-mentioned active control. Keeping the change in voltage applied to the control terminal within an appropriate range complicates control of the output time of the temporarily applied reverse drive signal. In other words, strict time control is required. While increasing the resistance value of the resistor connected in series to the control terminal could be considered to suppress the complexity of controllability in consideration of active control, this could result in a decrease in switching speed. In other words, setting the resistance value of the resistor connected to the control terminal is difficult. The present invention has been made to solve the above-mentioned problems and aims to provide active control that makes it easy to set the resistance value of the resistor connected in series to the control terminal. [Means for solving the problem]

[0008] A driving device for a switching element that solves the above problem comprises a driver that generates a driving signal based on a control signal that changes between low and high levels for a switching element having a first terminal, a second terminal, and a control terminal, and switches the switching element on and off by inputting the driving signal from an output terminal to the control terminal, a first resistor that connects the output terminal to the control terminal, and a second resistor that connects the control terminal to the second terminal, and performs active control that adjusts the voltage applied to the control terminal during a switching transition period of the switching element, wherein the driver has a high output state in which the driving signal is at a high level from the output terminal to the control terminal, a low output state in which the driving signal is at a low level from the output terminal to the control terminal, and a high impedance state in which the driving signal is not input to the control terminal, and performs the active control by putting the driver in the high impedance state during the switching transition period of the switching element.

[0009] When active control is performed, the driver enters a high-impedance state during the switching transition period of the switching element. In the high-impedance state, the voltage applied to the control terminal changes depending on the resistance value of the second resistor. The resistance value of the first resistor connected in series to the control terminal does not contribute to the change in the voltage at the control terminal during active control. This makes it possible to provide active control that makes it easy to set the resistance value of the first resistor.

[0010] Regarding the above-described switching element drive device, the switching element drive device executes at least one of a turn-on process that is performed when the switching element is turned on and a turn-off process that is performed when the switching element is turned off, and the turn-on process may be a process that stores an on-delay time from when the control signal starts to rise until when the voltage between the first terminal and the second terminal starts to drop, and performs the active control by setting a period during which the driver is put into the high-impedance state within a period during which the control signal is at a high level based on the on-delay time at the previous turn-on, and the turn-off process may be a process that stores an off-delay time from when the control signal starts to fall until when the voltage between the first terminal and the second terminal starts to rise, and performs the active control by setting a period during which the driver is put into the high-impedance state within a period during which the control signal is at a low level based on the off-delay time at the previous turn-off.

[0011] In the above-mentioned driving device for a switching element, the driver may include a first switch connected to a control power supply and a second switch connected in series to the first switch, a connection point between the first switch and the second switch is connected to the output terminal, and the high impedance state may be a state in which the first switch and the second switch are off.

[0012] The driving device for the switching element may further include a switch provided between the output terminal and the control terminal, and the high impedance state may be a state in which the switch is off. [Effects of the Invention]

[0013] According to the present invention, it is possible to provide active control that makes it easy to set the resistance value of the resistor connected in series to the control terminal. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a diagram showing the configuration of a driving device for a switching element. [Figure 2] FIG. 2 shows the high output state of the driver. [Figure 3] FIG. 3 shows the low output state of the driver. [Figure 4] FIG. 4 is a diagram showing the high impedance state of the driver. [Figure 5] FIG. 5 is a time chart showing the relationship between time and voltage. [Figure 6] FIG. 6 is a diagram showing the high impedance state of the driver. DETAILED DESCRIPTION OF THE INVENTION

[0015] An embodiment of a driving device for a switching element will be described. As shown in FIG. 1, the power conversion device PC includes a high-side switching element Q1 and a low-side switching element Q2. A load (not shown) or the like is connected to the connection point between the switching element Q1 and the switching element Q2. The power conversion device PC converts input power and outputs the converted power to the load. The switching elements Q1 and Q2 are, for example, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The switching elements Q1 and Q2 may be made of, for example, a silicon carbide compound semiconductor (SiC) or a gallium nitride compound semiconductor (GaN). The switching element Q2 includes a gate G, a drain D, and a source S. The gate G is an example of a control terminal. The drain D is an example of a first terminal. The source S is an example of a second terminal. The switching elements Q1 and Q2 may be switching elements other than MOSFETs, such as insulated gate bipolar transistors. In the case of an insulated gate bipolar transistor, the base is an example of a control terminal, the collector is an example of a first terminal, and the emitter is an example of a second terminal.

[0016] The power conversion device PC includes a switching element driver 10. The switching element driver 10 switches on and off switching elements Q1 and Q2. As an example, the switching element driver 10 provided for switching element Q2 will be described, but a similar switching element driver 10 is also provided for switching element Q1.

[0017] The switching element driving device 10 includes a driver 11. The driver 11 includes, for example, a driver control circuit 12, a first switch 13, a second switch 14 connected in series to the first switch 13, and an output terminal To. The switches 13 and 14 are, for example, transistors. One of the terminals of the first switch 13, other than the terminal connected to the second switch 14, is connected to a control power supply. The connection point of the two switches 13 and 14 is connected to the output terminal To.

[0018] The switching element driver 10 includes a first connection line L1 that connects the output terminal To and the gate G, and a second connection line L2 that connects the second switch 14 and the source S. The second connection line L2 connects the source S to a terminal of the second switch 14 that is different from the terminal that is connected to the first switch 13.

[0019] The switching element driver 10 includes a gate resistor R1 as a first resistor, a resistor R2 as a second resistor, and a capacitor C. The gate resistor R1 is provided on a first connection line L1. The gate resistor R1 connects an output terminal To and a gate G. The resistor R2 and the capacitor C connect the first connection line L1 and the second connection line L2 on the gate G side of the gate resistor R1. The resistor R2 connects the gate G and a source S. The resistance value of the gate resistor R1 is lower than the resistance value of the resistor R2. The gate resistor R1 is a gate resistor connected to the gate G. The resistor R2 is a gate-source resistor connecting the gate G and the source S.

[0020] A control signal S1 is input to the driver control circuit 12. The control signal S1 is, for example, a signal determined by comparing a voltage command with a carrier signal. The control signal S1 is, for example, output from an IC. The control signal S1 is a pulse signal that changes between low and high levels. When the control signal S1 changes from low to high, it is called a rising edge of the control signal S1. When the control signal S1 changes from high to low, it is called a falling edge of the control signal S1.

[0021] The driver 11 generates a drive signal S2 based on the control signal S1 and outputs the drive signal S2 from the output terminal To. The drive signal S2 output from the output terminal To is input to the gate G of the switching element Q2 via the first connection line L1. The drive signal S2 is a signal that switches the switching element Q2 between on and off. The drive signal S2 is a pulse signal that changes between low and high levels. The rise of the drive signal S2 occurs when the drive signal S2 changes from low to high level. The fall of the drive signal S2 occurs when the drive signal S2 changes from high to low level.

[0022] The driver control circuit 12 controls the switches 13 and 14 in response to the control signal S1 and the output of a turn-on one-shot unit 25 or a turn-off one-shot unit 35 (described later). The state of the driver 11 changes according to the control of the switches 13 and 14 by the driver control circuit 12. The states of the driver 11 include a high output state, a low output state, and a high impedance state.

[0023] 2, the high output state is a state in which a high-level drive signal S2 is input from the output terminal To to the gate G. In the high output state, the first switch 13 is turned on and the second switch 14 is turned off. When the first switch 13 is turned on and the second switch 14 is turned off, a high-level drive signal S2 is output from the driver 11. As a result, the voltage from the control power supply turns on the switching element Q2.

[0024] 3, the low output state is a state in which a low-level drive signal S2 is input from the output terminal To to the gate G. In the low output state, the first switch 13 is turned off and the second switch 14 is turned on. When the first switch 13 is turned off and the second switch 14 is turned on, a low-level drive signal S2 is output from the driver 11. As a result, a current flows to the source S via the gate resistor R1, and the voltage applied to the gate G decreases.

[0025] As shown in FIG. 4, the high-impedance state is a state in which the drive signal S2 is not input to the gate G. In the high-impedance state, the first switch 13 and the second switch 14 are turned off. As a result, the output terminal To is in a high-impedance state in which it is not connected to either the control power supply or ground. In the high-impedance state, the output terminal To and the gate G are electrically insulated, so that a current flows to the source S via the resistor R2, thereby reducing the voltage applied to the gate G. In addition, a current flows from the capacitor C to the source S via the resistor R2.

[0026] <Turn-on processing circuit> 1, the switching element driver 10 includes a turn-on processing circuit 20. The turn-on processing circuit 20 performs turn-on processing, which is processing for performing active control when the switching element Q2 is turned on.

[0027] Active control is a control that suppresses surge voltages by adjusting the voltage applied to the gate G during a switching transition period of the switching element Q2. The switching transition period of the switching element Q2 includes at least one of a transition period from on to off of the switching element Q2 and a transition period from off to on of the switching element Q2. The surge voltage includes ringing and overshoot of the drain-source voltage Vds.

[0028] The active control performed at the time of turn-on is a control that sets the period during which the driver 11 is in a high impedance state during the transition period from OFF to ON of the switching element Q2. The turn-on processing circuit 20 includes a turn-on detection unit 21 that detects the turn-on of the switching element Q2. The turn-on detection unit 21 detects the turn-on by comparing the drain-source voltage Vds with an ON threshold. When the drive signal S2 goes high, the gate-source voltage Vgs increases. When the gate-source voltage Vgs reaches a predetermined value or higher, the switching element Q2 turns on. When the switching element Q2 turns on, the drain-source voltage Vds decreases. Therefore, the turn-on can be detected by determining whether the drain-source voltage Vds has become less than the ON threshold.

[0029] The on-threshold is a predetermined value. The on-threshold is set so that the start of a drop in the drain-source voltage Vds can be detected. The start of the drop in the drain-source voltage Vds refers to the time when the drain-source voltage Vds starts to drop but before the drain-source voltage Vds has completely dropped. By setting the on-threshold in this manner, the turn-on detection unit 21 detects the start of a drop in the drain-source voltage Vds. The drain-source voltage Vds is an example of the voltage between the first terminal and the second terminal.

[0030] The turn-on detection unit 21 includes, for example, a comparator. The drain-source voltage Vds and an ON threshold are input to the comparator. When the drain-source voltage Vds is equal to or greater than the ON threshold, the comparator outputs a low-level signal. When the drain-source voltage Vds is less than the ON threshold, the comparator outputs a high-level signal. Note that a rise occurs when the output of the turn-on detection unit 21 changes from low level to high level.

[0031] The turn-on processing circuit 20 includes on-delay time memories 22 and 23. The on-delay time memories 22 and 23 include a first on-delay time memory 22 and a second on-delay time memory 23. The control signal S1 and the output of the turn-on detection unit 21 are input to the on-delay time memories 22 and 23. The on-delay time memories 22 and 23 store the time from the rising edge of the control signal S1 to the rising edge of the output of the turn-on detection unit 21 as the on-delay time of the switching element Q2. The on-delay time is the time from the start of the rising edge of the control signal S1 to the start of the decrease in the drain-source voltage Vds. In the switching element Q2, a transition period exists from the time when the drive signal S2 rises in response to the rising edge of the control signal S1 until the time when the drain-source voltage Vds begins to decrease, i.e., until the drain-source voltage Vds becomes less than the on-threshold value. This transition period is the on-delay time.

[0032] The on-delay time memories 22 and 23 are, for example, integrating circuits using capacitors. When a constant current flows through the capacitor during the time from the rising edge of the control signal S1 to the rising edge of the output of the turn-on detection unit 21, a charge corresponding to the on-delay time is stored in the capacitor. Therefore, the on-delay time memories 22 and 23 can store the on-delay time as a capacitor voltage.

[0033] The turn-on processing circuit 20 includes a turn-on delay unit 24. The turn-on delay unit 24 receives the control signal S1 and reads the on delay time from the on delay time memories 22 and 23. For example, the turn-on delay unit 24 reads the on delay time by generating a current corresponding to the voltage of the capacitor in the on delay time memories 22 and 23. The turn-on delay unit 24 may correct the on delay time read from the on delay time memories 22 and 23 according to a response delay time until the turn-on detection unit 21 detects the start of a drop in the drain-source voltage Vds. For example, the turn-on delay unit 24 may perform the correction by subtracting the response delay time from the on delay time read from the on delay time memories 22 and 23. The response delay time may be determined in advance through experiments or simulations. The turn-on delay unit 24 outputs the timing at which the on delay time elapses after the control signal S1 rises.

[0034] The turn-on processing circuit 20 includes a turn-on one-shot unit 25. The turn-on one-shot unit 25 outputs a negative pulse to the driver control circuit 12 at the timing output from the turn-on delay unit 24. The negative pulse is input to the control signal S1 to put the driver 11 into a high impedance state.

[0035] Driver control circuit 12 controls switches 13 and 14 so that driver 11 is in a high impedance state even when control signal S1 is at a high level while a negative pulse is being input from turn-on one-shot unit 25. When control signal S1 is at a high level and a negative pulse is not being input from turn-on one-shot unit 25, driver control circuit 12 controls switches 13 and 14 so that driver 11 is in a high output state.

[0036] In this way, the turn-on one-shot circuit 25 sets the period during which the driver 11 is in a high impedance state within the period during which the control signal S1 is at a high level. The width of the negative pulse may be constant or variable. When the width of the negative pulse is variable, for example, the width of the negative pulse may be changed according to the load state.

[0037] The switching element driver 10 includes a timing control unit 40. The timing control unit 40 controls the switching element driver 10. When turning on, the timing control unit 40 stores an on delay time in one of the first on delay time memory 22 and the second on delay time memory 23, and causes the turn-on delay unit 24 to read the on delay time from the other memory.

[0038] One control cycle is defined as the time from when the control signal S1 rises to high level, to when it goes to low level, and to when it rises to high level again. The timing control unit 40 alternately switches between the on delay time memories 22, 23 that store the on delay time and the on delay time memories 22, 23 that cause the turn-on delay unit 24 to read the on delay time. That is, the timing control unit 40 switches between the first on delay time memory 22 and the second on delay time memory 23 to store the on delay time each time the device is turned on. As a result, the on delay time from the first on delay time memory 22 or the second on delay time memory 23 that is read into the turn-on delay unit 24 is also switched each time the device is turned on.

[0039] During a control cycle in which an ON delay time is stored in the first ON delay time memory 22, the timing control unit 40 causes the turn-on delay unit 24 to read the ON delay time from the second ON delay time memory 23. During a control cycle in which an ON delay time is stored in the second ON delay time memory 23, the timing control unit 40 causes the turn-on delay unit 24 to read the ON delay time from the first ON delay time memory 22. Thus, at turn-on, the ON delay time stored in the ON delay time memories 22 and 23 at the previous turn-on is read into the turn-on delay unit 24. Therefore, the timing at which the turn-on one-shot unit 25 outputs a negative pulse is set based on the ON delay time at the previous turn-on of the switching element Q2. The turn-on detection unit 21, the first ON delay time memory 22, and the second ON delay time memory 23 are reset, for example, after a predetermined time has elapsed or by a predetermined signal from the control signal S1 or the drive signal S2.

[0040] As described above, the turn-on process is a process in which, when the switching element Q2 is turned on, the on delay time is stored and the period during which the driver 11 is in a high impedance state is set within the period during which the control signal S1 is at a high level, based on the on delay time when the switching element Q2 was turned on the previous time.

[0041] <Turn-off processing circuit> The switching element driver 10 includes a turn-off processing circuit 30. The turn-off processing circuit 30 performs turn-off processing. The turn-off processing is processing that performs active control when the switching element Q2 is turned off. The active control performed when the switching element Q2 is turned off is control that suppresses surge voltage by adjusting the voltage applied to the gate G during the transition period from on to off of the switching element Q2.

[0042] The turn-off processing circuit 30 includes a turn-off detection unit 31 that detects the turn-off of the switching element Q2. The turn-off detection unit 31 detects the turn-off by comparing the drain-source voltage Vds with an off threshold. When the drive signal S2 goes low, the gate-source voltage Vgs decreases. When the gate-source voltage Vgs falls below a predetermined value, the switching element Q2 turns off. When the switching element Q2 turns off, the drain-source voltage Vds increases. Therefore, the turn-off can be detected by determining whether the drain-source voltage Vds is equal to or greater than the off threshold.

[0043] The off-threshold is a predetermined value. The off-threshold is set so that the start of the rise in the drain-source voltage Vds can be detected. The start of the rise in the drain-source voltage Vds refers to the time when the drain-source voltage Vds starts to rise but before it reaches its maximum. By setting the off-threshold in this way, the turn-off detection unit 31 detects the start of the rise in the drain-source voltage Vds.

[0044] The turn-off detection unit 31 includes, for example, a comparator. The drain-source voltage Vds and an off threshold are input to the comparator. When the drain-source voltage Vds is equal to or greater than the off threshold, the comparator outputs a high-level signal. When the drain-source voltage Vds is less than the off threshold, the comparator outputs a low-level signal. Note that a rise occurs when the output of the turn-off detection unit 31 changes from low to high.

[0045] The turn-off processing circuit 30 includes off delay time memories 32 and 33. The off delay time memories 32 and 33 include a first off delay time memory 32 and a second off delay time memory 33. The control signal S1 and the output of the turn-off detection unit 31 are input to the off delay time memories 32 and 33. The off delay time memories 32 and 33 store the time from the falling edge of the control signal S1 to the rising edge of the output of the turn-off detection unit 31 as the off delay time of the switching element Q2. The off delay time is the time from the start of the falling edge of the control signal S1 to the start of the rise of the drain-source voltage Vds. In the switching element Q2, there is a transition period from the time when the drive signal S2 falls in response to the falling edge of the control signal S1 until the drain-source voltage Vds starts to rise, i.e., until the drain-source voltage Vds reaches or exceeds the off threshold. This transition period is the off delay time.

[0046] The off-delay time memories 32 and 33 are, for example, integrating circuits using capacitors. When a constant current flows through the capacitor during the period from the falling edge of the control signal S1 to the rising edge of the output of the turn-off detection unit 31, a charge corresponding to the off-delay time is stored in the capacitor. Therefore, the off-delay time memories 32 and 33 can store the off-delay time as a capacitor voltage.

[0047] The turn-off processing circuit 30 includes a turn-off delay unit 34. The turn-off delay unit 34 receives the control signal S1 and reads the off delay time from the off delay time memories 32 and 33. For example, the turn-off delay unit 34 reads the off delay time by generating a current corresponding to the voltage of the capacitor in the off delay time memories 32 and 33. The turn-off delay unit 34 may correct the off delay time read from the off delay time memories 32 and 33 according to a response delay time until the turn-off detection unit 31 detects the start of the rise in the drain-source voltage Vds. For example, the turn-off delay unit 34 may perform the correction by subtracting the response delay time from the off delay time read from the off delay time memories 32 and 33. The response delay time may be determined in advance through experiments or simulations. The turn-off delay unit 34 outputs the timing at which the off delay period elapses after the control signal S1 falls.

[0048] The turn-off processing circuit 30 includes a turn-off one-shot unit 35. The turn-off one-shot unit 35 outputs a positive pulse to the driver control circuit 12 at the timing output from the turn-off delay unit 34. The positive pulse is input to the control signal S1 to put the driver 11 into a high impedance state.

[0049] The driver control circuit 12 controls the switches 13 and 14 so that the driver 11 is in a high impedance state even when the control signal S1 is at a low level while a positive pulse is being input from the turn-off one-shot unit 35. When the control signal S1 is at a low level and no positive pulse is being input from the turn-off one-shot unit 35, the driver control circuit 12 controls the switches 13 and 14 so that the driver 11 is in a low output state.

[0050] In this way, the turn-off one-shot circuit 35 sets the period during which the driver 11 is in a high impedance state within the period during which the control signal S1 is at a low level. The width of the positive pulse may be constant or variable. When the width of the positive pulse is variable, for example, the width of the positive pulse may be changed according to the load state.

[0051] At the time of turn-off, the timing control section 40 stores the OFF delay time in one of the first OFF delay time memory 32 and the second OFF delay time memory 33, and causes the turn-off delay section 34 to read the OFF delay time from the other memory.

[0052] The timing control section 40 alternately switches between the OFF delay time memories 32, 33 that store the OFF delay time and the OFF delay time memories 32, 33 that cause the turn-off delay section 34 to read the OFF delay time. That is, the timing control section 40 switches whether the OFF delay time is stored in the first OFF delay time memory 32 or the second OFF delay time memory 33 at each turn-off. As a result, at each turn-off, the OFF delay time is also switched from the first OFF delay time memory 32 or the second OFF delay time memory 33 to be read into the turn-off delay section 34.

[0053] During a control cycle in which an OFF delay time is stored in the first OFF delay time memory 32, the timing control unit 40 causes the turn-off delay unit 34 to read the OFF delay time from the second OFF delay time memory 33. During a control cycle in which an OFF delay time is stored in the second OFF delay time memory 33, the timing control unit 40 causes the turn-off delay unit 34 to read the OFF delay time from the first OFF delay time memory 32. Thus, at turn-off, the OFF delay time stored in the OFF delay time memories 32 and 33 at the time of the previous turn-off is read into the turn-off delay unit 34. Therefore, the timing at which the turn-off one-shot unit 35 outputs a positive pulse is set based on the OFF delay time at the previous turn-off of the switching element Q2. The turn-off detection unit 31, the first OFF delay time memory 32, and the second OFF delay time memory 33 are reset, for example, after a predetermined time has elapsed or by a predetermined signal from the control signal S1 or the drive signal S2.

[0054] As described above, the turn-off process is a process in which, when the switching element Q2 is turned off, the off delay time is stored and the period during which the driver 11 is in a high impedance state is set within the period during which the control signal S1 is at a low level, based on the off delay time when the switching element Q2 was previously turned off.

[0055] [Operation of this embodiment] The operation of this embodiment will be described below. As an example, assume that active control is not performed in the first control cycle, active control of the comparative example is performed in the second control cycle, and active control of this embodiment is performed in the third control cycle.

[0056] The active control of the comparative example is a control that suppresses surge voltages by switching the drive signal S2 between high and low levels. In the active control of the comparative example, the driver 11 is in a low output state when the turn-on one-shot unit 25 outputs a negative pulse, and the driver 11 is in a high output state when the turn-off one-shot unit 35 outputs a positive pulse. As a result, in the active control of the comparative example, the period during which the drive signal S2 is at a low level at turn-on is set within the period during which the control signal S1 is at a high level. Also, the period during which the drive signal S2 is at a high level at turn-off is set within the period during which the control signal S1 is at a low level.

[0057] As shown in FIG. 5, when the first control cycle begins at time T11, the control signal S1 rises to high level. Accordingly, when the drive signal S2 rises to high level, the gate-source voltage Vgs increases. When the drain-source voltage Vds reaches the on threshold at time T12, the output of the turn-on detection unit 21 rises to high level at time T13. The first on-delay time memory 22 stores the on-delay time T1 from time T11 to time T13 as the capacitor voltage V1 of the integrating circuit. The time from time T12 to time T13 is the response delay time T7 of the turn-on detection unit 21. The response delay time T7 is the time required for the turn-on detection unit 21 to detect the start of a drop in the drain-source voltage Vds.

[0058] When the control signal S1 falls to low level at time T14, the drive signal S2 goes low. Accordingly, the gate-source voltage Vgs decreases. When the drain-source voltage Vds reaches the off threshold at time T15, the output of the turn-off detection unit 31 goes high at time T16. The first off delay time memory 32 stores the off delay time T3 from time T14 to time T16 as the capacitor voltage V3 of the integrating circuit. The time from time T15 to time T16 is the response delay time T8 of the turn-off detection unit 31. The response delay time T8 is the time required for the turn-off detection unit 31 to detect the start of the rise in the drain-source voltage Vds.

[0059] At time T17, the second control period (active control in the comparative example) begins, and the control signal S1 rises to a high level. Accordingly, the drive signal S2 rises to a high level, causing the gate-source voltage Vgs to increase. The turn-on delay unit 24 reads the on-delay time T1 stored in the first on-delay time memory 22 during the first control period. The on-delay time T1 is the on-delay time during the previous turn-on. The turn-on one-shot unit 25 outputs a negative pulse to the driver 11 at time T18, after the on-delay time T1' has elapsed since time T17. This allows the period during which the drive signal S2, which is the opposite drive signal, is at a low level to be set within the period during which the control signal S1 is at a high level. The drive signal S2 is at a low level from time T18 to time T20. The on-delay time T1' may be the same as the on-delay time T1, or may be the on-delay time T1 minus the response delay time T7.

[0060] Time T18 coincides with the time when the drain-source voltage Vds reaches the ON threshold. This is because the load state fluctuates little between adjacent control cycles, so the time the control signal S1 is maintained at a high level is the same or nearly the same. Therefore, based on the ON delay time T1 from the previous turn-on, it is possible to estimate the time when the drain-source voltage Vds reaches the ON threshold during this turn-on. At this time, the drive signal S2 can be set to a low level.

[0061] At time T19, the output of the turn-on detection unit 21 goes high. The second on-delay time memory 23 stores the on-delay time T2 from time T17 to time T19 as the capacitor voltage V2 of the integrating circuit.

[0062] When the control signal S1 falls to low level at time T21, the drive signal S2 goes low. Accordingly, the gate-source voltage Vgs decreases. The turn-off delay unit 34 reads the off delay time T3 stored in the first off delay time memory 32 during the first control cycle. The off delay time T3 is the off delay time during the previous turn-off. The turn-off one-shot unit 35 outputs a positive pulse to the driver 11 at time T23, after the off delay time T3' has elapsed since time T21. This allows the period during which the drive signal S2, which is the opposite drive signal, is at high level to be set within the period during which the control signal S1 is at low level. The drive signal S2 is at high level from time T23 to time T25. The off delay time T3' may be the same as the off delay time T3, or may be the off delay time T3 minus the response delay time T8.

[0063] There is a small difference between time T23 and time T22 when the drain-source voltage Vds reaches the off threshold. In this way, time T23 when the drive signal S2 reaches high level and time T22 may not coincide, but the time from when the drain-source voltage Vds reaches the off threshold until when the drive signal S2 reaches high level can be shortened compared to when the turn-off detection unit 31 detects turn-off and then turns the drive signal S2 to high level.

[0064] At time T24, the output of the turn-off detection unit 31 goes high. The second off delay time memory 33 stores the off delay time T4 from time T21 to time T24 as the capacitor voltage V4 of the integrating circuit.

[0065] At time T26, the third control period (active control in this embodiment) begins, and the control signal S1 rises to high level. Accordingly, when the drive signal S2 rises to high level, the gate-source voltage Vgs increases. The turn-on delay unit 24 reads the on-delay time T2 stored in the second on-delay time memory 23 during the second control period. The on-delay time T2 is the on-delay time at the previous turn-on. The turn-on one-shot unit 25 outputs a negative pulse to the driver 11 at time T27, which is the on-delay time T2' after time T26. The on-delay time T2' may be the same as the on-delay time T2, or may be the on-delay time T2 minus the response delay time T7. This places the driver 11 in a high-impedance state. The driver 11 remains in a high-impedance state from time T27 to time T29.

[0066] When the driver 11 enters a high-impedance state, the gate-source voltage Vgs is maintained at its previous voltage by the gate capacitance and capacitor C. The rate of change of the gate-source voltage Vgs is determined by the resistance value of resistor R2. The lower the resistance value of resistor R2, the faster the rate of change of the gate-source voltage Vgs. Therefore, the rate of change of the gate-source voltage Vgs when the driver 11 is in a high-impedance state can be adjusted by the resistance value of resistor R2. By making the resistance value of resistor R2 higher than the resistance value of gate resistor R1, fluctuations in the gate-source voltage Vgs when the driver 11 is in a high-impedance state are suppressed.

[0067] At time T28, the output of the turn-on detection unit 21 goes high. The first on-delay time memory 22 stores the on-delay time T5 from time T26 to time T28 as the capacitor voltage V5 of the integrating circuit. This on-delay time T5 is used the next time the switch is turned on.

[0068] When the control signal S1 falls to low level at time T30, the drive signal S2 also falls to low level. Accordingly, the gate-source voltage Vgs decreases. The turn-off delay unit 34 reads the off delay time T4 stored in the second off delay time memory 33 in the second control cycle. The off delay time T4 is the off delay time at the previous turn-off. The turn-off one-shot unit 35 outputs a positive pulse to the driver 11 at time T31, which is an off delay time T4' after time T30. The off delay time T4' may be the same as the off delay time T4, or may be the off delay time T4 minus the response delay time T8. This places the driver 11 in a high-impedance state. The driver 11 remains in a high-impedance state from time T31 to time T32. The high-impedance state of the driver 11 suppresses fluctuations in the gate-source voltage Vgs.

[0069] At time T31, the output of the turn-off detection unit 31 goes high. The first off delay time memory 32 stores the off delay time T6 from time T30 to time T31 as the capacitor voltage V6 of the integrating circuit. This off delay time T6 is used at the next turn-off.

[0070] As shown by reference symbol A1 in FIG. 5 , active control is not performed during the first control cycle, and therefore a surge voltage occurs in the drain-source voltage Vds at turn-on. In contrast, during the second control cycle, the active control of the comparative example is performed, and therefore the increase in the gate-source voltage Vgs is temporarily suppressed. As shown by reference symbol A2, the occurrence of a surge voltage in the drain-source voltage Vds is suppressed. Even when the active control of this embodiment is performed, the increase in the gate-source voltage Vgs is temporarily suppressed, and therefore the occurrence of a surge voltage in the drain-source voltage Vds is suppressed. Comparing the active control of the comparative example with the active control of this embodiment, the active control of the comparative example outputs a reverse drive signal, which has a significant effect, and therefore the gate-source voltage Vgs decreases during the active control period. In contrast, the active control of this embodiment results in less fluctuation in the gate-source voltage Vgs during the active control period.

[0071] As shown by reference symbol A4 in FIG. 5 , active control is not performed during the first control cycle, and therefore a surge voltage occurs in the drain-source voltage Vds at turn-off. In contrast, during the second control cycle, the active control of the comparative example is performed, and therefore the decrease in the gate-source voltage Vgs is temporarily suppressed. As shown by reference symbol A5, the occurrence of a surge voltage in the drain-source voltage Vds is suppressed. Even when the active control of this embodiment is performed, the decrease in the gate-source voltage Vgs is temporarily suppressed, and therefore the occurrence of a surge voltage in the drain-source voltage Vds is suppressed, as shown by reference symbol A6 in FIG. 2 . Comparing the active control of the comparative example with the active control of this embodiment, the active control of the comparative example outputs a reverse drive signal, which has a significant effect, and therefore the gate-source voltage Vgs increases during the active control period. In contrast, the active control of this embodiment results in less fluctuation in the gate-source voltage Vgs during the active control period.

[0072] [Effects of this embodiment] (1) When active control is performed, the driver 11 enters a high-impedance state during the switching transition period of the switching element Q2. In the high-impedance state, the voltage applied to the gate G changes depending on the resistance value of the resistor R2. The resistance value of the gate resistor R1 does not contribute to the change in the voltage applied to the gate G during active control. This makes it possible to provide active control that makes it easy to set the resistance value of the gate resistor R1.

[0073] The resistance value of resistor R2 can be set to a value suitable for active control. By making the resistance value of resistor R2 larger than the resistance value of gate resistor R1, the gate-source voltage Vgs is less likely to change when active control is performed, compared to the active control of the comparative example. Since it is easier to keep the change in the gate-source voltage Vgs within an appropriate range, it is possible to suppress the complexity of control.

[0074] (2) The switching element driver 10 performs a turn-on process. In the turn-on process, the period during which the driver 11 is in a high-impedance state is set based on the on-delay time within the period during which the control signal S1 is at a high level. By setting the period during which the driver 11 is in a high-impedance state using the on-delay time of the previous turn-on, it is not necessary to put the driver 11 into a high-impedance state immediately after detecting the turn-on of the switching element Q2. Because there is little change in the load state between adjacent control cycles, the time during which the control signal S1 is maintained at a high level is the same or almost the same. Therefore, the on-delay time of the previous turn-on can be considered to be the same as the on-delay time of the current turn-on. The period during which the driver 11 is in a high-impedance state can be set using the on-delay time of the previous turn-on.

[0075] When feedback control is performed to place the driver 11 in a high impedance state after detecting the turn-on of the switching element Q2, if the switching speed of the switching element Q2 is fast, the feedback may not be able to keep up and the surge voltage may not be suppressed. In contrast, by using the on delay time from the previous turn-on, the surge voltage can be suppressed regardless of the switching speed of the switching element Q2.

[0076] The on-delay time is the time from when the control signal S1 starts to rise until the drain-source voltage Vds starts to drop. After the drain-source voltage Vds drops, a surge voltage may occur. For this reason, if the on-delay time is set to the time until the drain-source voltage Vds has dropped to its lowest point, the surge voltage may not be suppressed. In contrast, by setting the on-delay time to the time until the drain-source voltage Vds starts to drop, the surge voltage can be suppressed.

[0077] (3) The switching element driver 10 performs a turn-off process. In the turn-off process, the period during which the driver 11 is in a high-impedance state is set based on the off delay time within the period during which the control signal S1 is at a low level. By setting the period during which the driver 11 is in a high-impedance state using the off delay time at the previous turn-off, it is not necessary to put the driver 11 into a high-impedance state immediately after detecting the turn-off of the switching element Q2. Because there is little change in the load state between adjacent control cycles, the time during which the control signal S1 is maintained at a high level is the same or almost the same. Therefore, the off delay time at the previous turn-off can be considered to be the same as the off delay time at the current turn-off. The period during which the driver 11 is in a high-impedance state can be set using the off delay time at the previous turn-off.

[0078] When feedback control is performed to put the driver 11 into a high impedance state after detecting the turn-off of the switching element Q2, if the switching speed of the switching element Q2 is fast, the feedback may not be able to be completed in time and the surge voltage may not be suppressed. In contrast, by using the off delay time from the previous turn-off, the surge voltage can be suppressed regardless of the switching speed of the switching element Q2.

[0079] The off delay time is the time from when the control signal S1 starts to fall to when the drain-source voltage Vds starts to rise. After the drain-source voltage Vds rises, a surge voltage may occur. For this reason, if the off delay time is set to the time until the drain-source voltage Vds has risen to its maximum, the surge voltage may not be suppressed. In contrast, by setting the off delay time to the time until the drain-source voltage Vds starts to rise, the surge voltage can be suppressed.

[0080] (4) The high-impedance state is a state in which the first switch 13 and the second switch 14 are off. The driver 11 can be put into the high-impedance state by turning off the two switches 13 and 14 provided in the driver 11. Because the driver 11 can be put into the high-impedance state using existing components, there is no need to add components to put the driver 11 into the high-impedance state.

[0081] (5) At the time of turn-on, the timing control unit 40 stores the ON delay time in one of the first ON delay time memory 22 and the second ON delay time memory 23, and causes the turn-on delay unit 24 to read the ON delay time from the other memory. Furthermore, at each turn-on, the timing control unit 40 switches whether the ON delay time is stored in the first ON delay time memory 22 or the second ON delay time memory 23. This allows the current ON delay time to be stored in either the ON delay time memory 22 or 23 at the time of turn-on, and the period during which the driver 11 is in a high impedance state to be set based on the ON delay time at the previous turn-on.

[0082] (6) The turn-on delay unit 24 corrects the on-delay time read from the on-delay time memories 22 and 23 in accordance with the response delay time of the turn-on detection unit 21. There is a delay between when the drain-source voltage Vds starts to decrease and when the turn-on detection unit 21 detects that the drain-source voltage Vds has started to decrease. By correcting the on-delay time in accordance with the response delay time caused by this delay, the driver 11 can be put into a high-impedance state at the appropriate time.

[0083] (7) At the time of turn-off, the timing control unit 40 stores the off delay time in one of the first off delay time memory 32 and the second off delay time memory 33, and causes the turn-off delay unit 34 to read the off delay time from the other memory. Furthermore, at each turn-off, the timing control unit 40 switches whether to store the off delay time in the first off delay time memory 32 or the second off delay time memory 33. This allows the current off delay time at the time of turn-off to be stored in either the off delay time memory 32 or 33, and the period during which the driver 11 is in a high impedance state to be set based on the off delay time at the previous turn-off.

[0084] (8) The turn-off delay unit 34 corrects the off delay time read from the off delay time memories 32 and 33 in accordance with the response delay time of the turn-off detection unit 31. There is a delay from when the drain-source voltage Vds starts to rise until the turn-off detection unit 31 detects that start of the rise in the drain-source voltage Vds. By correcting the off delay time in accordance with the response delay time caused by this delay, the driver 11 can be put into a high impedance state at an appropriate timing.

[0085] (9) When the switching element Q2 is turned on, the driver 11 is in a high-impedance state for a period within the period when the control signal S1 is at a high level. Also, when the switching element Q2 is turned off, the driver 11 is in a high-impedance state for a period within the period when the control signal S1 is at a low level. Therefore, compared to a configuration in which the resistance connected to the gate G is variable, it is not necessary to provide multiple resistors, and a switch for switching resistors is also not required.

[0086] (10) The switching element driver 10 includes a capacitor C. When SiC is used for the switching elements Q1 and Q2, an increase in the drain-source voltage Vds of one of the switching elements Q1 and Q2 may cause the drain-source voltage Vds of the other switching element to change. This may cause an unintended change in the voltage of the gate G, which may result in malfunction of the switching elements Q1 and Q2. By providing the capacitor C, the voltage of the gate G can be stabilized, thereby preventing malfunction of the switching elements Q1 and Q2.

[0087] [Example of change] The embodiment can be modified as follows: The embodiment and the following modifications can be combined with each other to the extent that they are not technically inconsistent.

[0088] As shown in FIG. 6, the switching element driver 10 may include a switch 15 provided between the output terminal To and the gate G. In this case, the high impedance state is a state in which the switch 15 is off. When the switch 15 is off, the output terminal To and the gate G are electrically isolated. In this case, the switching element driver 10 includes a switch control unit that switches the switch 15 on and off. The switch control unit turns off the switch 15 when a negative pulse is input from the turn-on one-shot unit 25. The switch control unit turns off the switch 15 when a positive pulse is input from the turn-off one-shot unit 35. The switch control unit turns on the switch 15 when neither a negative pulse from the turn-on one-shot unit 25 nor a positive pulse from the turn-off one-shot unit 35 is input.

[0089] By turning off switch 15, driver 11 can be put into a high impedance state. Therefore, even if driver 11 itself does not have a function of going into a high impedance state by turning off both of two switches 13 and 14, driver 11 can be put into a high impedance state.

[0090] The switching element driver 10 only needs to perform at least one of the turn-on process and the turn-off process. If the switching element driver 10 only performs the turn-on process, the switching element driver 10 does not need to include the turn-off process circuit 30. If the switching element driver 10 only performs the turn-off process, the switching element driver 10 does not need to include the turn-on process circuit 20.

[0091] When the switching element driver 10 does not perform the turn-on process, it may perform the active control of the comparative example when the switching element Q2 is turned on. That is, when the switching element Q2 is turned on, the switching element driver 10 may perform control such that the driver 11 is in a low output state if the turn-on one-shot unit 25 outputs a negative pulse.

[0092] When the switching element driver 10 does not perform the turn-off process, it may perform the active control of the comparative example when the switching element Q2 is turned off. That is, when the switching element Q2 is turned off, the switching element driver 10 may perform control such that the driver 11 is in a high output state if the turn-off one-shot unit 35 is outputting a positive pulse.

[0093] When performing the turn-on process, the switching element driver 10 may set the driver 11 to a high impedance state after the turn-on detection unit 21 detects that the switching element Q2 has been turned on. In other words, the turn-on delay time does not need to be the same as the turn-on delay time at the previous turn-on.

[0094] When performing the turn-off process, the switching element driver 10 may set the driver 11 to a high impedance state after the turn-off detection unit 31 detects that the switching element Q2 has been turned off. In other words, the turn-off delay time at the previous turn-off does not need to be used as the turn-off delay time.

[0095] The ON delay time memories 22 and 23 may have any configuration as long as they can store the ON delay time. For example, they may be configured with a digital circuit using a counter. Similarly, the OFF delay time memories 32 and 33 may have any configuration as long as they can store the OFF delay time.

[0096] The switching element driver 10 does not have to include the capacitor C. In this case, the switching elements Q1 and Q2 are preferably made of a material other than SiC. [Definition] The phrase "at least one" as used herein means "one or more" of the desired options. As an example, the phrase "at least one" as used herein means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" as used herein means "only one option" or "any combination of two or more options" when the number of options is three or more. [Explanation of symbols]

[0097] D...drain which is an example of a first terminal, G...gate which is an example of a control terminal, Q1, Q2...switching elements, R1...gate resistor which is an example of a first resistor, R2...resistor which is an example of a second resistor, S...source which is an example of a second terminal, 10...driving device for switching element, 11...driver, 13...first switch, 14...second switch, 15...switch.

Claims

1. a driver that generates a drive signal based on a control signal that changes between a low level and a high level for a switching element having a first terminal, a second terminal, and a control terminal, and switches the switching element on and off by inputting the drive signal from an output end to the control terminal; a first resistor connecting the output terminal and the control terminal; a second resistor connecting the control terminal and the second terminal; A driving device for a switching element that performs active control to adjust a voltage applied to the control terminal during a switching transition period of the switching element, The driver a high output state in which the drive signal at a high level is input from the output terminal to the control terminal; a low output state in which the drive signal at a low level is input from the output terminal to the control terminal; a high impedance state in which the drive signal is not input to the control terminal; The driving device for a switching element performs the active control by putting the driver into the high impedance state during a switching transition period of the switching element.

2. the driving device for the switching element executes at least one of a turn-on process that is performed when the switching element is turned on and a turn-off process that is performed when the switching element is turned off; the turn-on process is a process of storing an on-delay time from when the control signal starts to rise until when the voltage between the first terminal and the second terminal starts to drop, and setting a period during which the driver is put into the high impedance state based on the on-delay time at the previous turn-on within a period during which the control signal is at a high level, thereby executing the active control; 2. The driving device for a switching element according to claim 1, wherein the turn-off process is a process of performing the active control by storing an off delay time from when the control signal starts to fall until when the voltage between the first terminal and the second terminal starts to rise, and setting a period during which the driver is in the high impedance state based on the off delay time at the previous turn-off within a period during which the control signal is at a low level.

3. The driver a first switch connected to a control power supply; a second switch connected in series to the first switch, a connection point between the first switch and the second switch is connected to the output terminal; 3. The switching element drive device according to claim 1, wherein the high impedance state is a state in which the first switch and the second switch are off.

4. a switch provided between the output terminal and the control terminal; 3. The driving device for a switching element according to claim 1, wherein the high impedance state is a state in which the switch is off.

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