Semiconductor optical device and method of manufacturing the same

Abstract

To provide a semiconductor optical element capable of shortening a lead time, and to provide a method of manufacturing the same.SOLUTION: Bonding a semiconductor element having an optical gain to a waveguide in a third layer of a substrate including a first layer, the second layer, and the third layer that are sequentially stacked, providing an insulating film that covers the substrate and the bonded semiconductor element, forming an emission end surface that faces a tip of the waveguide, and forming a heat dissipation structure that is provided at a position separated from the waveguide, the step of forming the heat dissipation structure includes a step of etching the second layer and the insulating film at a position away from the waveguide, and a step of providing a metal layer extending between the etched portion and the semiconductor element, and the step of etching in the step of forming the emitting end surface and the step of etching in the step of forming the heat dissipation structure are performed simultaneously.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor optical device and a method for manufacturing the same. [Background technology]

[0002] There is a known technique for bonding a semiconductor element made of a compound semiconductor and having optical gain to a substrate such as an SOI (Silicon On Insulator) substrate (silicon photonics) on which a waveguide is formed (see, for example, Non-Patent Document 1). Light generated in the semiconductor element propagates through the waveguide in the substrate and is emitted. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Martin Schnarrenberger et al. “Facet Preparation of SOI Waveguides by Ethching and Cleaving Compared to Dicing and Polishing”, First IEEE International Conference on Group IV Photonics, 29 September 2004-01 October 2004 Summary of the Invention [Problem to be solved by the invention]

[0004] The substrate is provided with an output end face for emitting light and a heat dissipation structure for dissipating heat generated during operation. Forming the output end face and the heat dissipation structure in separate processes results in a complex process and a long lead time. Therefore, the objective of this invention is to provide a semiconductor optical device and a method for manufacturing the same that can shorten the lead time. [Means for solving the problem]

[0005] The method for manufacturing a semiconductor optical device according to the present disclosure is a method for manufacturing a semiconductor optical device including a substrate including a first layer, a second layer, and a third layer stacked in that order, and a semiconductor element having optical gain, wherein the third layer has a waveguide, and the method includes the steps of bonding the semiconductor element to the waveguide of the third layer, providing an insulating film covering the substrate and the bonded semiconductor element, forming an emitting end face facing the tip of the waveguide, and forming a heat dissipation structure provided at a position spaced from the waveguide, wherein the step of forming the emitting end face includes a step of etching portions of the second layer and the insulating film facing the tip of the waveguide, and the step of forming the heat dissipation structure includes a step of etching portions of the second layer and the insulating film facing the tip of the waveguide, and a step of providing a metal layer extending between the etched portion and the semiconductor element, and the etching step in the step of forming the emitting end face and the etching step in the step of forming the heat dissipation structure are performed simultaneously. [Effects of the Invention]

[0006] According to the present disclosure, it is possible to provide a semiconductor optical device and a method for manufacturing the same that can shorten the lead time. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a perspective view illustrating a semiconductor optical device according to an embodiment. [Figure 2A] FIG. 2A is a cross-sectional view illustrating an example of a semiconductor optical device. [Figure 2B] FIG. 2B is a cross-sectional view illustrating an example of a semiconductor optical device. [Figure 3] FIG. 3 is a diagram illustrating the coupling efficiency. [Figure 4] FIG. 4 is a flowchart illustrating a method for manufacturing a semiconductor optical device. [Figure 5] FIG. 5 is a flowchart illustrating a method for manufacturing a semiconductor optical device. [Figure 6] 6A to 6C are cross-sectional views illustrating a method for manufacturing a semiconductor optical device. [Figure 7A] FIG. 7A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 7B] FIG. 7B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 8A] FIG. 8A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 8B] FIG. 8B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 9A] FIG. 9A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 9B] FIG. 9B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 10A] FIG. 10A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 10B] FIG. 10B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 11A] FIG. 11A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 11B] FIG. 11B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 12A] FIG. 12A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 12B] FIG. 12B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 13A] FIG. 13A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 13B] FIG. 13B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 14A] FIG. 14A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 14B] FIG. 14B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 15A] FIG. 15A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 15B] FIG. 15B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 16A]FIG. 16A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 16B] FIG. 16B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 17A] FIG. 17A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 17B] FIG. 17B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 18A] FIG. 18A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 18B] FIG. 18B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 19] FIG. 19 is a flowchart illustrating the manufacturing process in the comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0008] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described.

[0009] One aspect of the present disclosure is (1) a method for manufacturing a semiconductor optical device including a substrate including a first layer, a second layer, and a third layer stacked in order, and a semiconductor element having optical gain, wherein the third layer has a waveguide, the method including the steps of: bonding the semiconductor element to the waveguide of the third layer; providing an insulating film covering the substrate and the bonded semiconductor element; forming an emission end face facing a tip of the waveguide; and forming a heat dissipation structure provided at a position spaced apart from the waveguide, wherein the step of forming the emission end face includes a step of etching a portion of the second layer and the insulating film facing the tip of the waveguide, and the step of forming the heat dissipation structure includes a step of etching a portion of the second layer and the insulating film facing a position spaced apart from the waveguide, and a step of providing a metal layer extending between the etched portion and the semiconductor element, and the etching step in the step of forming the emission end face and the etching step in the step of forming the heat dissipation structure are performed simultaneously. Since etching is performed simultaneously, the lead time can be shortened. (2) In the above (1), the etching step in the step of forming the light-emitting end face and the etching step in the step of forming the heat dissipation structure may include a step of performing dry etching using a gas containing carbon. The light-emitting end face can be made flat. (3) In either of the above (1) or (2), the angle of the output end face with respect to the extension direction of the waveguide may be 80 degrees or more and 90 degrees or less, thereby increasing the coupling efficiency. (4) In any of the above (1) to (3), the output end face may be formed by the end faces of the insulating film and the second layer. The insulating film and the second layer are located between the waveguide and air. The refractive index gradually changes from the waveguide to the air. This increases the coupling efficiency. (5) In any of (1) to (4) above, the second layer and the insulating film may be formed of silicon oxide, and the first layer and the third layer may be formed of silicon. Because the second layer and the insulating film are formed of the same material, it is easy to control the etching rate, etc. Because the silicon waveguide is surrounded by the second layer and the insulating film, light is distributed in the waveguide, and loss is suppressed. (6) In any of the above (1) to (5), the etching step in the step of forming the light-emitting end face and the etching step in the step of forming the heat dissipation structure may include a step of etching the second layer and the insulating film until the first layer is exposed. Since the light-emitting end face and the heat dissipation structure can be etched simultaneously and to the same depth, manufacturing is easy. (7) In any of the above (1) to (6), after the step of forming the light-emitting end face, a step of etching the first layer exposed at a position facing the tip of the waveguide may be included, so that emitted light is less likely to hit the first layer. (8) In any of the above (1) to (7), the method may further include a step of dicing the first layer after the step of forming the heat dissipation structure and the step of forming the light emitting end face, and the step of dicing may include a step of dicing a portion of the first layer outside the light emitting end face. This makes it difficult for emitted light to hit the first layer. (9) In any one of the above (1) to (8), the metal layer may be an electrode and may be electrically connected to the semiconductor element, and heat generated in the semiconductor element may be dissipated through the electrode. (10) A semiconductor optical device includes a substrate including a first layer, a second layer, and a third layer stacked in order, a semiconductor element having optical gain, and a heat dissipation structure for dissipating heat from the semiconductor element, wherein the third layer has a waveguide, the semiconductor element is bonded to the waveguide in the third layer, the substrate has an output end face for emitting light propagating through the waveguide, and the first layer has a protrusion on the output end face facing the extension direction of the waveguide. This can shorten lead time. Light is less likely to hit the first layer of the substrate.

[0010] [Details of the embodiments of the present disclosure] Specific examples of semiconductor optical devices and manufacturing methods thereof according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0011] (semiconductor optical element) FIG. 1 is a perspective view illustrating a semiconductor optical device 100 according to an embodiment. As shown in FIG. 1, the semiconductor optical device 100 is a hybrid laser device and includes a substrate 10 and a semiconductor device 20. The semiconductor optical device 100 has an output facet 40 for emitting light and a heat dissipation structure 50 for dissipating heat. FIGS. 2A and 2B are cross-sectional views illustrating the semiconductor optical device 100. FIG. 2A illustrates a cross section including the output facet 40. FIG. 2B illustrates a cross section including the heat dissipation structure 50 and the semiconductor device 20. The output facet 40 and the heat dissipation structure 50 will be described later. The X-axis direction is the direction in which light propagates. The Y-axis direction is the width direction of the semiconductor optical device 100. The Z-axis direction is the normal direction to the top surface of the substrate 10. The X-axis direction, Y-axis direction, and Z-axis direction are perpendicular to each other.

[0012] As shown in FIGS. 1 to 2B, substrate 10 is an SOI (Silicon on Insulator) substrate and includes substrate 12 (first layer), box layer 14 (second layer), and silicon layer 16 (third layer). Substrate 12, box layer 14, and silicon layer 16 are stacked in this order in the Z-axis direction. Substrate 12 is made of, for example, silicon (Si). Box layer 14 is made of, for example, silicon oxide (SiO2). Box layer 14 has a thickness of, for example, 3 μm. Silicon layer 16 has a thickness of, for example, 220 nm.

[0013] As shown in FIG. 2B , the silicon layer 16 has a waveguide 11 and a terrace 15. The waveguide 11 is parallel to the X-axis direction. The terraces 15 are plate-shaped and are located on both sides of the waveguide 11 in the Y-axis direction. The upper surfaces of the waveguide 11 and the terraces 15 are at the same height in the Z-axis direction. A recess 13 is provided between the waveguide 11 and the terrace 15. The recess 13 is recessed below the upper surface of the waveguide 11 in the Z-axis direction. The recess 13 may penetrate the silicon layer 16 or may extend partway through the silicon layer 16.

[0014] The semiconductor element 20 is a light-emitting element having optical gain and made of a III-V compound semiconductor. As shown in Figures 1 and 2B, the semiconductor element 20 is bonded to the upper surface of the silicon layer 16 and is located above the waveguide 11.

[0015] 2B, the semiconductor device 20 has a cladding layer 22, an active layer 24, a cladding layer 26, and a contact layer 28. The cladding layer 22 is in contact with the silicon layer 16. The active layer 24, the cladding layer 26, and the contact layer 28 are stacked in this order on the opposite side of the silicon layer 16 from the cladding layer 22. The semiconductor device 20 may have semiconductor layers other than those described above.

[0016] The cladding layer 22 is formed of, for example, n-type indium phosphide (n-InP). The active layer 24 has, for example, a multi-quantum well (MQW) structure. The active layer 24 includes a plurality of well layers and barrier layers. The well layers and barrier layers are alternately stacked. The well layers and barrier layers are formed of, for example, undoped gallium indium arsenide phosphide (i-GaInAsP). The cladding layer 26 is formed of, for example, p-type InP (p-InP). The contact layer 28 is formed of, for example, p+-type gallium indium arsenide ((p+)-GaInAs). A separate confinement heterostructure (SCH) structure may be formed by providing guide layers between the active layer 24 and the cladding layer 22 and between the active layer 24 and the cladding layer 26.

[0017] As shown in FIG. 1, the semiconductor device 20 has a mesa 21 and a tapered portion 23. The mesa 21 is located on the waveguide 11 and extends parallel to the X-axis direction. Both ends of the mesa 21 in the X-axis direction are tapered. The cladding layer 22 and the active layer 24 are plate-shaped and extend from below the mesa 21 to the outside of the mesa 21. The cladding layer 22 protrudes beyond the active layer 24. The tapered portion 23 is provided in the cladding layer 22 and extends in the X-axis direction. The tapered end of the mesa 21 and the tapered portion 23 become thinner as they move away from the semiconductor device 20. As shown in FIG. 2B, the mesa 21 includes a cladding layer 26 and a contact layer 28 and protrudes from the active layer 24 in the Z-axis direction.

[0018] As shown in FIG. 2B, the upper surface of the substrate 10 and the semiconductor element 20 are covered with an insulating film 18. The insulating film 18 is made of an insulator such as SiO2 and functions as a cladding layer. The insulating film 18 has a thickness of, for example, 1.2 μm. The insulating film 18 fills the recess 13 of the substrate 10. The insulating film 18 has an opening above the cladding layer 22 at a position spaced apart from the mesa 21, and also has an opening above the mesa 21.

[0019] 1, the semiconductor optical device 100 has an electrode 30 and an electrode 32. The electrode 30 is provided on the cladding layer 22 at a position spaced apart from the mesa 21. The electrode 30 is electrically connected to the cladding layer 22 through an opening in the insulating film 18. The electrode 32 (metal layer) is provided on the mesa 21 and is electrically connected to the contact layer 28 through an opening in the insulating film 18. The electrodes 30 and 32 are made of metal.

[0020] A voltage is applied to the semiconductor element 20 using electrodes 30 and 32. The active layer 24 of the semiconductor element 20 has optical gain and generates light in response to carrier injection. The semiconductor element 20 and the substrate 10 are evanescently optically coupled. The refractive index gradually changes at the tapered end and tapered portion 23 of the mesa 21. Light generated in the semiconductor element 20 transitions to the waveguide 11 at the end and tapered portion 23 of the mesa 21. The light propagates through the waveguide 11 and is emitted from the output end facet 40 to the outside of the semiconductor optical element 100. The semiconductor optical element 100 has two output end faces 40. The two output end faces 40 are located opposite the tapered portions 23 at both ends of the semiconductor element 20.

[0021] (Output end face) As shown in FIG. 2A, a recess 42 is formed in the substrate 10, and an output end face 40 is provided in the recess 42. The output end face 40 is an end face of the box layer 14 and the insulating film 18, is perpendicular to the X-axis, and faces the tip of the waveguide 11. The distance D1 from the tip of the waveguide 11 to the output end face 40 is, for example, 3 μm. The insulating film 18 made of SiO2 and the box layer 14 are provided between the tip of the waveguide 11 and the output end face 40. The wavelength of the output light is, for example, 1.55 μm. At this wavelength, the refractive index of the box layer 14 and the insulating film 18 is lower than that of the silicon layer 16 and higher than that of air. Because the refractive index changes gradually from the waveguide 11 to air, light loss is low.

[0022] The optical mode spreads over a range of, for example, about 2.5 μm. Near the emission end face 40, the height H1 from the upper surface of the substrate 12 to the upper surface of the insulating film 18 is, for example, 3.2 μm. The mode can be confined to the vicinity of the waveguide 11.

[0023] The substrate 12 has a protrusion 17. The protrusion 17 protrudes in the X-axis direction beyond the emitting end face 40. The distance D2 between the tip of the protrusion 17 and the emitting end face 40 is, for example, 5 μm. The depth H2 from the surface of the substrate 12 that contacts the box layer 14 to the upper surface of the protrusion 17 is, for example, 1 μm. Light emitted from the emitting end face 40 is less likely to hit the protrusion 17 of the substrate 12, reducing loss.

[0024] Figure 3 is a diagram illustrating the coupling efficiency. The horizontal axis represents the angle θ between the output facet 40 and the upper surface of the substrate 12. In Figure 3, the angle θ ranges from 45 degrees to 90 degrees. The vertical axis represents the calculated coupling efficiency. The wavelength of light is changed from 1.5 μm to 1.6 μm in 0.25 μm increments. The thin solid line represents an example with a wavelength of 1.5 μm. The dotted line represents an example with a wavelength of 1.525 μm. The dashed line represents an example with a wavelength of 1.55 μm. The dotted line represents an example with a wavelength of 1.575 μm. The thick solid line represents an example with a wavelength of 1.6 μm. For all wavelengths, the closer the angle θ is to 90 degrees, the higher the coupling efficiency. To achieve a coupling efficiency of -2 dB or higher, the angle θ should be set to be between 80 degrees and 90 degrees.

[0025] To improve the coupling efficiency, the output end face 40 is made closer to vertical as described above. Furthermore, the output end face 40 is made flat. However, polishing to form a flat output end face 40 increases the lead time. To form one output end face, approximately 100 μm of the wafer is polished. This may reduce the number of semiconductor optical devices 100 that can be obtained from the wafer.

[0026] (heat dissipation structure) When the semiconductor element 20 is operated, heat is generated. The heat is dissipated from the semiconductor element 20 through the heat dissipation structure 50. The heat dissipation structure 50 includes a recess 52 and an electrode 32. As shown in FIG. 2B , the recess 52 extends to the substrate 12 in the Z-axis direction and is spaced apart from the semiconductor element 20 in the Y-axis direction. The insulating film 18, silicon layer 16, and box layer 14 are not provided in the recess 52. The box layer 14, the terrace 15 of the silicon layer 16, and the insulating film 18 are provided on the opposite side of the recess 52 from the semiconductor element 20. The electrode 32 extends between the mesa 21 of the semiconductor element 20 and the recess 52, and also extends from the inside of the recess 52 to the surface of the insulating film 18 opposite the semiconductor element 20. The electrode 32 contacts the mesa 21 of the semiconductor element 20 and the surface of the substrate 12 at the recess 52. Heat generated in the semiconductor element 20 is conducted to the substrate 12 through the electrode 32 and dissipated from the substrate 12.

[0027] If the process of forming the light-emitting end face 40 and the process of forming the heat dissipation structure 50 are performed separately, the process becomes complicated and the lead time becomes long. As described above, the lead time for polishing is also long. In the first embodiment, the light-emitting end face 40 and the heat dissipation structure 50 are formed through a simple process without polishing.

[0028] (Manufacturing method) 4 and 5 are flow charts illustrating a method for manufacturing the semiconductor optical device 100. Fig. 5 shows the steps of forming the light emitting end face 40 and the heat dissipation structure 50 in the manufacturing method.

[0029] FIG. 6 is a cross-sectional view illustrating a method for manufacturing the semiconductor optical device 100. FIGS. 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, and 18A are plan views illustrating a method for manufacturing the semiconductor optical device 100. FIGS. 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, and 18B are cross-sectional views illustrating a method for manufacturing the semiconductor optical device 100, showing cross sections taken along line L in the corresponding plan views. FIGS. 7A and 7B, 9A and 9B, 11A and 11B, 13A and 13B, 15A and 15B, and 18A and 18B illustrate the portion where the output end face 40 is formed. 8A and 8B, 10A and 10B, 12A and 12B, 14A and 14B, 16A and 16B, and 17A and 17B illustrate the portion where the heat dissipation structure 50 is formed.

[0030] Steps S10 and S12 in FIG. 4 may be performed in parallel. Here, step S10 will be described first. As shown in FIG. 6, a contact layer 28, a cladding layer 26, an active layer 24, and a cladding layer 22 are epitaxially grown in this order on an InP substrate 25, for example, by metal organic chemical vapor deposition (MOCVD) (step S10 in FIG. 4). The substrate 25 is diced to form a rectangular parallelepiped semiconductor element 20. In this process, the semiconductor element 20 does not have a mesa 21, a tapered portion 23, or the like.

[0031] The processes of steps S12 to S24 in FIG. 4 are performed on a wafer of substrate 10. As shown in FIGS. 7A to 8B, etching is performed on silicon layer 16 of substrate 10 (step S12). Recesses 13 are formed in silicon layer 16. Waveguides 11 are formed at positions sandwiched between the recesses 13. Terraces 15 are formed outside the recesses 13. As shown in FIGS. 7A and 7B, recesses 42 are formed by etching at positions opposite the tips of waveguides 11. The recesses 42 penetrate the silicon layer 16, exposing the box layer 14. The length D3 of recesses 42 in the X-axis direction is, for example, 30 μm. As shown in FIGS. 8A and 8B, recesses 52 are formed by etching at positions spaced apart from the waveguide 11 in the Y-axis direction. The recesses 52 penetrate the silicon layer 16, exposing the box layer 14.

[0032] 9A to 10B, the insulating film 18a is formed by, for example, plasma enhanced CVD (Plasma CVD) (step S14). The insulating film 18a covers the upper surface of the silicon layer 16 and is embedded in the recesses 42 and 52.

[0033] As shown in FIGS. 12A and 12B, the insulating film 18a is removed from the waveguide 11, and the semiconductor element 20 is bonded onto the waveguide 11 (step S16 in FIG. 4). The bonding method is hydrophilic bonding or plasma activation bonding, for example. After bonding, etching is performed to remove the substrate 25 from the semiconductor element 20. Further etching is performed to form the mesa 21 and tapered portion 23 in the semiconductor element 20 (step S18). The active layer 24 and the cladding layer 22 are molded into a plate shape. As shown in FIGS. 11A to 12B, an insulating film is formed on the insulating film 18a and the semiconductor element 20 (step S20). The added insulating film and the insulating film 18a form the insulating film 18.

[0034] The heat dissipation structure 50 and the light emitting end surface 40 are formed (step S22). As shown in FIGS. 13A to 14B, etching is performed simultaneously at a position facing the tip of the waveguide 11 and at a position spaced apart from the waveguide 11 (step S30 in FIG. 5). The insulating film 18 and the box layer 14 are etched. The substrate 12 is exposed inside the recesses 42 and 52.

[0035] Specifically, etching is performed twice. Resist is applied and photolithography is performed, and the waveguide 11 and the semiconductor element 20 are covered with resist (not shown). Dry etching is performed to a depth of, for example, 2.5 μm. After the first etching, the box layer 14 remains in the recesses 42 and 52.

[0036] After removing the resist, another resist 60 is provided on the insulating film 18. The resist 60 is patterned by photolithography. As shown in FIGS. 13A and 13B, the resist 60 covers the waveguide 11. As shown in FIGS. 14A and 14B, the resist 60 covers the semiconductor element 20. Dry etching is performed to remove the box layer 14 remaining in the recesses 42 and 52. Examples of etching conditions are shown below. Both the first and second etchings are performed under these conditions. Gas: tetrafluoromethane (CF4) Antenna power: 100W Bias power: 50W Pressure: 1.0Pa Time: 25 minutes

[0037] By the second etching, substrate 12 is exposed in recesses 42 and 52. As shown in FIGS. 13A and 13B, emission end face 40 is formed in insulating film 18 and box layer 14 at a position facing the tip of waveguide 11. Portion 14a of box layer 14 covered with resist 60 remains unetched. After etching, resist 60 is removed.

[0038] As shown in FIGS. 15A to 16B, a resist 62 is provided on the substrate 10 and the insulating film 18. As shown in FIGS. 16A and 16B, the resist 62 covers the semiconductor element 20 and the inside of the recess 52. As shown in FIGS. 15A and 15B, the resist 62 covers the waveguide 11. The portion of the substrate 12 exposed from the recess 42 is not covered by the resist 62. The portion of the substrate 12 exposed from the resist 62 is dry-etched (step S32). In the recess 42, the substrate 12 is etched to a depth of, for example, about 1 μm. After etching, the resist 62 is removed.

[0039] As shown in Figures 17A and 17B, an opening is provided in the insulating film 18 above the mesa 21. An electrode 32 is formed by vacuum deposition and lift-off (step S34). The electrode 32 is formed in the shaded area in Figure 17A. The electrode 32 extends from above the mesa 21 to the recess 52, and also extends from the semiconductor element 20 to the top of the insulating film 18 on the opposite side from the recess 52. A heat dissipation structure 50 is formed. The electrode 30 shown in Figure 1 is also provided.

[0040] As shown in Figures 18A and 18B, dicing is performed to divide the wafer into chips (step S24 in Figure 4). Dicing may be performed by laser dicing or by using a blade. The portion of substrate 12 located within recess 42 is cut off and remains as protrusion 17. Emitting end surface 40 does not come into contact with the dicing cutting means (laser, blade, etc.). Through the above steps, semiconductor optical device 100 is formed.

[0041] (Comparative Example) FIG. 19 is a flowchart illustrating a manufacturing process in a comparative example. Steps S10 to S20 are the same as those in the example of FIG. 4. A heat dissipation structure 50 is formed (step S40). The insulating film 18 and the box layer 14 are etched at a position spaced apart from the waveguide 11. Electrodes 30 and 32 are provided. Etching is not performed at a position facing the tip of the waveguide 11. After providing the heat dissipation structure 50, dicing is performed (step S42). The diced surface is polished to form an output end face (step S44).

[0042] In the comparative example, the process of forming the emission end face and the process of forming the heat dissipation structure 50 are performed separately. Because the diced surface is rough, a flat emission end face is formed by polishing. The process is complicated, and individual chips are polished, resulting in a long lead time. In the polishing process, the chip is polished to, for example, about 100 μm. In the dicing process, the chip is formed, including the polished portion. This reduces the number of chips that can be manufactured from a wafer.

[0043] According to the embodiment, etching in the step of forming the light-emitting end face 40 and etching in the step of forming the heat dissipation structure 50 are performed simultaneously. Because the process is simplified, the lead time can be shortened.

[0044] Specifically, as shown in FIGS. 13A to 14B, the insulating film 18 and the box layer 14 are etched at a position facing the tip of the waveguide 11 and at a position spaced apart from the waveguide 11. The emission end face 40 is formed by dry etching, resulting in a flat surface. Because polishing of the emission end face 40 is not required, the lead time can be shortened. The length D3 of the recess 42 is, for example, 30 μm, which is shorter than the length of the polished portion. This increases the number of chips manufactured from a wafer.

[0045] By simultaneously etching multiple chips in a wafer, the emission facets 40 and heat dissipation structures 50 are formed on multiple chips, thereby shortening the lead time.

[0046] The etching is dry etching using a gas containing carbon, such as CF4. Because deposits are generated from the gas, side etching is unlikely to occur. The output end face 40 becomes flat and approaches verticality. As shown in Figure 3, the coupling efficiency is improved.

[0047] The angle θ of the output end face 40 with respect to the X-axis direction is, for example, not less than 80 degrees and not more than 90 degrees. As shown in Fig. 3, the closer the angle of the output end face 40 is to 90 degrees, the higher the coupling efficiency becomes, for example, 3 dB or more.

[0048] As shown in FIG. 2A, the output facet 40 is the end face of the insulating film 18 and the box layer 14. The insulating film 18 and the box layer 14 are located between the waveguide 11 and the output facet 40. The difference in refractive index between the Si waveguide 11 and the SiO2 insulating film 18 and box layer 14 is smaller than the difference in refractive index between the waveguide 11 and air. The refractive index gradually changes from the waveguide 11 to air. The insulating film 18 covers the tip of the waveguide 11 and functions as an anti-reflection film, reducing light loss.

[0049] The substrate 10 is an SOI substrate. The box layer 14 and the insulating film 18 are made of SiO2. Because the same material is etched, the etching rate and other factors can be easily controlled, and the desired shapes of the recesses 42 and 52 can be formed. The emission end face 40 can be made flat and nearly vertical. The substrate 12 and the silicon layer 16 are made of Si. The waveguide 11 in the silicon layer 16 is also made of Si. The Si waveguide 11 is surrounded by the SiO2 box layer 14 and the insulating film 18. The insulating film 18 functions as a cladding layer, distributing light in the waveguide 11 and suppressing light loss.

[0050] 13A to 14B, etching is performed until the substrate 12 is exposed, forming the recesses 42 and 52. Etching can be performed simultaneously in two locations to the same depth, which shortens the lead time.

[0051] 15A and 15B, the substrate 12 in the recess 42 is etched. In the Z-axis direction, the substrate 12 is moved away from the waveguide 11. This makes it difficult for light to hit the substrate 12, reducing loss.

[0052] As shown in Figures 18A and 18B, after forming the light emitting end surface 40 and the heat dissipation structure, the substrate 10 is diced. A portion of the substrate 12 in the recess 42 remains as a protrusion 17. If the protrusion 17 is long, light will be incident on the protrusion 17. By setting the length of the protrusion 17 to, for example, 5 µm or less, the light is not blocked by the protrusion 17 and is emitted to the outside. Light loss is reduced.

[0053] 17A and 17B, the heat dissipation structure 50 is formed by providing an electrode 32 after etching. The electrode 32 extends from the mesa 21 of the semiconductor element 20 to the substrate 12 exposed in the recess 52. Heat generated in the semiconductor element 20 is conducted to the substrate 12 through the electrode 32 and released. This makes it difficult for the temperature to rise and performance to deteriorate.

[0054] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present disclosure as described in the claims. [Explanation of symbols]

[0055] 10, 12 board 11 Waveguide 13 Recess 15 Terrace 14 Box Layer 14a part 16 Silicon Layer 17 Protrusion 18, 18a insulating film 20 Semiconductor elements 21 Mesa 22, 26 Cladding layer 23 Tapered section 24 Active layer 28 Contact layer 30, 32 electrodes 40 Output end face 42, 52 recess 50 Heat dissipation structure 60, 62 Resist 100 Semiconductor optical element

Claims

1. A method for manufacturing a semiconductor optical device comprising a substrate including a first layer, a second layer, and a third layer stacked in order, and a semiconductor device having optical gain, the method comprising: the third layer has a waveguide; bonding the semiconductor element to the waveguide of the third layer; providing an insulating film covering the substrate and the bonded semiconductor element; forming an output end face facing the tip of the waveguide; forming a heat dissipation structure spaced apart from the waveguide; the step of forming the light emitting end surface includes a step of etching portions of the second layer and the insulating film that face the tip of the waveguide; the step of forming the heat dissipation structure includes a step of etching the second layer and the insulating film at positions spaced from the waveguide, and a step of providing a metal layer extending between the etched portions and the semiconductor element; A method for manufacturing a semiconductor optical device, wherein the etching step of forming the light-emitting end face and the etching step of forming the heat dissipation structure are performed simultaneously.

2. 2. The method for manufacturing a semiconductor optical device according to claim 1, wherein the etching step in the step of forming the light-emitting end face and the etching step in the step of forming the heat dissipation structure include a step of performing dry etching using a gas containing carbon.

3. 3. The method for manufacturing a semiconductor optical device according to claim 1, wherein the angle of the light-emitting end face with respect to the extending direction of the waveguide is between 80 degrees and 90 degrees.

4. 3. The method for manufacturing a semiconductor optical device according to claim 1, wherein the light-emitting end face is formed by end faces of the insulating film and the second layer.

5. the second layer and the insulating film are formed of silicon oxide; 3. The method for manufacturing a semiconductor optical device according to claim 1, wherein the first layer and the third layer are made of silicon.

6. 3. The method for manufacturing a semiconductor optical device according to claim 1, wherein the etching step in the step of forming the light-emitting end face and the etching step in the step of forming the heat dissipation structure include a step of etching the second layer and the insulating film until the first layer is exposed.

7. 7. The method for manufacturing a semiconductor optical device according to claim 6, further comprising the step of etching the first layer exposed at a position opposite to the tip of the waveguide after the step of forming the light-emitting end face.

8. a step of dicing the first layer after the step of forming the heat dissipation structure and the step of forming the light emitting end face, 7. The method for manufacturing a semiconductor optical device according to claim 6, wherein the dicing step includes the step of dicing a portion of the first layer outside the light-emitting end face.

9. 3. The method for manufacturing a semiconductor optical device according to claim 1, wherein the metal layer is an electrode and is electrically connected to the semiconductor device.

10. a substrate including a first layer, a second layer, and a third layer stacked in order; a semiconductor element having optical gain; a heat dissipation structure for dissipating heat from the semiconductor element, the third layer has a waveguide; the semiconductor element is bonded to the waveguide of the third layer; the substrate has an exit end surface for emitting light propagating through the waveguide, The first layer has a protrusion on the light-emitting end face that faces in the direction in which the waveguide extends.

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