Image sensing device

Abstract

To provide an image sensing device which operates in a plurality of modes.SOLUTION: The image sensing device includes a pixel array configured to generate a pixel signal, a first rampgenerator configured to generate a first ramp signal, a second rampgenerator configured to generate a second ramp signal, and an analog-to-digital converter (ADC) circuit including a comparator configured to compare the pixel signal with one of the first ramp signal and the second ramp signal and configured to generate image data based on a result of the comparison. And a processor configured to control the ADC circuit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technical concept of the present disclosure relates to an image sensing device that can operate in various modes. [Background technology]

[0002] Image sensing devices are devices that capture optical images using the properties of photosensitive semiconductor materials that react to light. With the development of industries such as automobiles, medicine, computers, and communications, there is an increasing demand for high-performance image sensing devices in various fields, such as smartphones, digital cameras, game consoles, the Internet of Things, robots, security cameras, and medical microcameras.

[0003] Image sensing devices can be broadly divided into charge-coupled device (CCD) image sensing devices and complementary metal oxide semiconductor (CMOS) image sensing devices. CCD image sensing devices provide better image quality than CMOS image sensing devices, but tend to be larger in size and consume more power. In contrast, CMOS image sensing devices can be smaller in size and consume less power than CCD image sensing devices. Furthermore, because CMOS image sensing devices are fabricated using CMOS fabrication technology, the light sensing element and signal processing circuitry can be integrated into a single chip, thereby producing inexpensive and compact image sensing devices. For this reason, CMOS image sensing devices are being developed for many applications, including mobile devices. Summary of the Invention [Problem to be solved by the invention]

[0004] The technical problem of the present disclosure is to provide an image sensing device that operates in multiple modes. An object of the present disclosure is to provide an image sensing device including a reference signal source that consumes less power.

[0005] The technical problem of the present disclosure is to provide an image sensing device with a small mounting area by including a reference signal source that uses elements already provided in the ADC circuit. The technical problem of the present disclosure is to provide an image sensing device that generates low-quality images or high-quality images as needed.

[0006] The technical problems to be solved by the present disclosure are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the technical field to which the present disclosure pertains from the following description. [Means for solving the problem]

[0007] An image sensing device according to an exemplary embodiment of the present disclosure may include: a pixel array configured to generate a pixel signal; a first ramp generator configured to generate a first ramp signal; a second ramp generator configured to generate a second ramp signal; an ADC (Analog-to-Digital Converter) circuit including a comparator configured to compare the pixel signal with one of the first ramp signal and the second ramp signal, and configured to generate image data based on a comparison result; and a processor configured to control the ADC circuit such that the first ramp signal is input to the comparator when operating in a first mode, and the second ramp signal is input to the comparator when operating in a second mode.

[0008] According to one embodiment, the ADC circuit further includes a buffer coupled to the first ramp generator and configured to output a first ramp signal in response to an enable signal, a first capacitor coupled between the buffer and the comparator, a second capacitor coupled between the pixel array and the comparator, and a ground switch coupled between an output node of the buffer and a ground terminal and configured to be turned on in response to an inverted enable signal having an opposite state to the enable signal.

[0009] According to one embodiment, the comparator includes a first amplifier having a positive input terminal connected to a first capacitor, a negative input terminal connected to a second capacitor, a positive output terminal, and a negative output terminal; a second amplifier connected to the positive output terminal; a first switch connected to the positive input terminal; a second switch connected between the first switch and the negative output terminal; a third switch connected to a first node between the first switch and the second switch and a second ramp generator; a fourth switch connected to the negative input terminal; a fifth switch connected between the fourth switch and the positive output terminal; and a sixth switch connected between a second node between the fourth switch and the fifth switch and a ground terminal.

[0010] In one embodiment, when operating in the first mode, the processor is configured to generate an enable signal having a logic high level to activate the buffer and turn off the ground switch so that the comparator receives the first ramp signal.

[0011] In one embodiment, when operating in the first mode, the processor is configured to perform auto-zero by turning on the first switch, the second switch, the fourth switch, and the fifth switch and turning off the third switch and the sixth switch.

[0012] According to one embodiment, when operating in the first mode, the processor is configured to read a reset voltage level of a pixel included in the pixel array or read a voltage level of a pixel signal corresponding to an amount of light received by the pixel by turning off the first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch.

[0013] According to one embodiment, when operating in the second mode, the processor is configured to generate an enable signal having a logic low level to deactivate the buffer, turn on the ground switch, and turn on the first switch and the third switch so that the comparator receives the second ramp signal.

[0014] In one embodiment, when operating in the second mode, the processor is configured to reset the positive input node of the first amplifier and the output node of the second ramp generator by turning on the second switch, the fourth switch, and the fifth switch.

[0015] In one embodiment, when operating in the second mode, the processor is configured to perform auto-zero by turning on the fourth switch and the fifth switch and turning off the second switch and the sixth switch.

[0016] According to one embodiment, when operating in the second mode, the processor is configured to read a reset voltage level of a pixel included in the pixel array or read a voltage level of a pixel signal corresponding to an amount of light received by the pixel by turning off the second switch, the fourth switch, the fifth switch, and the sixth switch.

[0017] According to one embodiment, the first ramp generator includes a digital-to-analog converter (DAC) configured to output a current.

[0018] According to one embodiment, the second ramp generator is characterized by including a first current source configured to generate a source current and a second current source configured to generate a sink current.

[0019] According to one embodiment, the image sensing device further includes a first capacitor connected to the positive input terminal of the comparator, and the processor charges the first capacitor using a first current source and discharges the first capacitor using a second current source.

[0020] In one embodiment, the image sensing device further includes an interface configured to communicate with an external processor, the processor configured to activate the interface when operating in the first mode and deactivate the interface when operating in the second mode.

[0021] In one embodiment, the ADC circuit is characterized in that when operating in the first mode, it transmits image data to the interface. In one embodiment, when operating in the second mode, the processor is configured to detect, based on the image data, a moving object from an image corresponding to the image data.

[0022] In one embodiment, the processor is capable of controlling the ADC circuitry in a first mode to generate image data corresponding to a full resolution image. In one embodiment, the first ramp signal may be a different ramp signal than the second ramp signal.

[0023] An image sensing device according to an exemplary embodiment of the present disclosure may include a pixel array that generates a pixel signal, a comparator that compares the pixel signal with one of a first ramp signal and a second ramp signal, a first ramp generator that includes a Digital-to-Analog Converter (DAC) and generates the first ramp signal, a second ramp generator that includes a first current source and a second current source and generates the second ramp signal, a buffer connected to the first ramp generator, a first capacitor connected between the buffer and the comparator, and a second capacitor connected between the pixel array and the comparator.

[0024] According to one embodiment, the comparator includes a first amplifier having a positive input terminal connected to a first capacitor, a negative input terminal connected to a second capacitor, a positive output terminal, and a negative output terminal; a second amplifier connected to the positive output terminal; a first switch connected to the positive input terminal; a second switch connected between the first switch and the negative output terminal; a third switch connected to a first node between the first switch and the second switch and a second ramp generator; a fourth switch connected to the negative input terminal; a fifth switch connected between the fourth switch and the positive output terminal; and a sixth switch connected between a second node between the fourth switch and the fifth switch and a ground terminal. According to an embodiment, the image sensing device further includes a ground switch coupled between the output node of the buffer and a ground terminal.

[0025] An image sensing device according to an exemplary embodiment of the present disclosure includes a pixel array configured to generate a pixel signal; a first ramp generator configured to generate a first ramp signal; a second ramp generator configured to generate a second ramp signal; an analog-to-digital converter (ADC) circuit configured to generate first image data based on the first ramp signal and the pixel signal and to generate second image data based on the second ramp signal and the pixel signal; and a processor configured to control the ADC circuit such that, when operating in a first mode, the second ramp generator is put to sleep and the ADC circuit receives the first ramp signal, and when operating in a second mode, the first ramp generator is put to sleep and the ADC circuit receives the second ramp signal, wherein a first image corresponding to the first image data is a higher quality image than a second image corresponding to the second image data. The above briefly summarized features of the present disclosure are illustrative aspects of the detailed description of the present disclosure that follows and are not intended to limit the scope of the present disclosure. [Effects of the Invention]

[0026] Image sensing devices according to exemplary embodiments of the present disclosure can operate in multiple modes. An image sensing device according to an exemplary embodiment of the present disclosure can generate images while consuming less power.

[0027] Image sensing devices according to exemplary embodiments of the present disclosure can generate high quality images or low quality images as required. The image sensing device according to the exemplary embodiment of the present disclosure can have a small footprint.

[0028] The effects obtained by the present disclosure are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by a person having ordinary skill in the art to which the present disclosure pertains from the following description. [Brief explanation of the drawings]

[0029] [Figure 1] FIG. 1 is a block diagram of an image sensing device according to an exemplary embodiment of the present disclosure. [Figure 2] FIG. 1 is a circuit diagram for an image sensing device according to an exemplary embodiment of the present disclosure. [Figure 3] FIG. 1 is a circuit diagram for an image sensing device according to an exemplary embodiment of the present disclosure. [Figure 4] FIG. 2 is a timing diagram for a method of operating an image sensing device according to an exemplary embodiment of the present disclosure. [Figure 5a] FIG. 1 is a circuit diagram for an image sensing device according to an exemplary embodiment of the present disclosure. [Figure 5b] FIG. 1 is a circuit diagram for an image sensing device according to an exemplary embodiment of the present disclosure. [Figure 6] FIG. 2 is a timing diagram for a method of operating an image sensing device according to an exemplary embodiment of the present disclosure. [Figure 7a] FIG. 1 is a circuit diagram for an image sensing device according to an exemplary embodiment of the present disclosure. [Figure 7b] FIG. 1 is a circuit diagram for an image sensing device according to an exemplary embodiment of the present disclosure. [Figure 7c] FIG. 1 is a circuit diagram for an image sensing device according to an exemplary embodiment of the present disclosure. [Figure 8] FIG. 1 is a block diagram of an image sensing device according to an exemplary embodiment of the present disclosure. [Figure 9] FIG. 2 is a diagram illustrating the operation of an image sensing device according to an exemplary embodiment of the present disclosure. [Figure 10] FIG. 1 is a block diagram of an image sensing device according to an exemplary embodiment of the present disclosure. [Figure 11] FIG. 2 is a diagram illustrating the operation of an image sensing device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0030] Hereinafter, with reference to the accompanying drawings, detailed descriptions of embodiments of the present disclosure will be given so that those skilled in the art can easily implement the present disclosure, however, the present disclosure may be embodied in various different forms and is not limited to the embodiments described herein.

[0031] In describing embodiments of the present disclosure, if a detailed description of known configurations or functions is deemed to unnecessarily obscure the gist of the present disclosure, the detailed description will be omitted. In addition, in the drawings, parts that are not related to the description of the present disclosure will be omitted, and similar parts will be designated by similar reference numerals.

[0032] In this disclosure, when a component is "coupled," "coupled," or "connected" to another component, it means not only a direct connection, but also an indirect connection where there is another component between them. Furthermore, when a component "includes" or "has" another component, it does not mean that the other component is excluded, and that the component may further include the other component, unless otherwise specified.

[0033] In this disclosure, terms such as first and second are used only to distinguish one component from another, and do not limit the order or importance of the components unless otherwise specified. Therefore, within the scope of this disclosure, a first component in one embodiment may be referred to as a second component in another embodiment, and similarly, a second component in one embodiment may be referred to as a first component in another embodiment.

[0034] In this disclosure, components that are distinguished from one another are used to clearly describe the characteristics of each component and do not necessarily mean that the components are separate. That is, multiple components may be integrated and consist of a single hardware or software unit, or a single component may be distributed and consist of multiple hardware or software units. Therefore, even if not otherwise specified, such integrated or distributed embodiments are also included within the scope of this disclosure.

[0035] In this disclosure, the components described in various embodiments do not necessarily mean essential components, and some may be optional components. Therefore, an embodiment consisting of a subset of the components described in one embodiment is also included in the scope of this disclosure. Furthermore, an embodiment including other components in addition to the components described in various embodiments is also included in the scope of this disclosure.

[0036] In this disclosure, expressions of positional relationships used in this specification, such as upper, lower, left side, right side, etc., are described for the convenience of explanation, and when the drawings shown in this specification are viewed upside down, the positional relationships described in this specification may be interpreted in reverse.

[0037] In this disclosure, each of the phrases such as "A or B," "at least one of A and B," "at least one of A or B," "A, B, or C," "at least one of A, B, and C," and "at least one of A, B, or C" may include any one or all possible combinations of the items listed along with the corresponding phrase.

[0038] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to FIGS. FIG. 1 is a block diagram of an image sensing device according to an exemplary embodiment of the present disclosure.

[0039] 1 , an image sensing device 100 according to an exemplary embodiment of the present disclosure may include a pixel array 11, a first ramp generator 12, a second ramp generator 13, an analog-to-digital converter (ADC) circuit 14, and an internal processor 15. The image sensing device 100 may also be connected to an external processor 110.

[0040] The image sensing device 100 may be, but is not limited to, a complementary metal oxide semiconductor image sensor (CIS) that converts incident light into an electrical signal.

[0041] The image sensing device 100 may operate in various operation modes. For example, the image sensing device 100 may operate in a first mode or a second mode as needed. A first image generated by the image sensing device 100 when operating in the first mode may have higher image quality than a second image generated by the image sensing device 100 when operating in the second mode. The image sensing device 100 may consume less power when operating in the second mode than when operating in the first mode. That is, the first mode may prioritize image quality, and the second mode may target low power consumption. The image sensing device 100 may generate image data corresponding to a full-resolution image in the first mode. The image sensing device 100 may perform motion detection in the second mode. The operation modes of the image sensing device 100 are not limited to those described above. The image sensing device 100 may adaptively change modes as needed to generate images, thereby efficiently using power.

[0042] The pixel array 11 may include a plurality of pixels continuously arranged in a two-dimensional matrix structure (e.g., continuously arranged in a column direction and / or a row direction). The pixel array 11 may be configured to generate a pixel signal. For example, the pixel array 11 may generate the pixel signal based on incident light incident on each of the plurality of pixels.

[0043] The first ramp generator 12 may be configured to generate a first ramp signal. The second ramp generator 13 can be configured to generate a second ramp signal, which may be a different ramp signal from the first ramp signal.

[0044] The first ramp generator 12 and the second ramp generator 13 can be connected to the ADC circuit 14, and the first ramp generator 12 can send a first ramp signal to the ADC circuit 14, and the second ramp generator 13 can send a second ramp signal to the ADC circuit 14.

[0045] The first ramp generator 12 may include a digital-to-analog converter (DAC). Specifically, the first ramp generator 12 may include a DAC that outputs a current. For example, the first ramp generator 12 may include a current DAC with k-bit precision. Furthermore, the first ramp generator 12 may generate the first ramp signal using the DAC that outputs a current and a resistor.

[0046] The second ramp generator 13 may include a first current source and a second current source, where the first current source may be configured to generate a source current, and the second current source may be configured to generate a sink current.

[0047] The ADC circuit 14 can be configured to generate image data. The ADC circuit 14 can generate image data by performing various signal processing on an input signal. For example, the ADC circuit 14 can perform, but is not limited to, an analog binning operation, a digital binning operation, a correlated double sampling (CDS) operation, a noise reduction process, and the like.

[0048] The ADC circuit 14 may include a comparator, a buffer, at least one capacitor, and / or a ground switch coupled to a ground terminal. The configuration of the ADC circuit 14 will be described in more detail below.

[0049] The internal processor 15 can operate in a first mode or a second mode by using any one of the multiple ramp generators 12, 13 as necessary. For example, in the first mode, the internal processor 15 can control the ADC circuit 14 so that a first ramp signal is input to a comparator included in the ADC circuit 14. In addition, in the second mode, the internal processor 15 can control the ADC circuit 14 so that a second ramp signal is input to a comparator included in the ADC circuit 14. More specific details of how the internal processor 15 controls the ADC circuit 14 will be described later.

[0050] The external processor 110 can determine the mode in which the image sensing device 100 operates. For example, if a high-quality image is required, the external processor 110 can instruct the image sensing device 100 to operate in a first mode. The internal processor 15 can then operate in the first mode by activating the first ramp generator 12 and deactivating the second ramp generator 13 based on the instruction. Although not shown in FIG. 1 , the internal processor 15 can also activate an interface for communicating with the external processor 110 in the first mode. This allows the ADC circuit 14 to transfer image data corresponding to a high-quality image to the external processor 110 via the interface. Furthermore, if a reduction in power consumption is required, the external processor 110 can instruct the image sensing device 100 to operate in a second mode. The internal processor 15 can then deactivate the first ramp generator 12 and activate the second ramp generator 13 based on the instruction.

[0051] FIG. 2 is a circuit diagram of an image sensing device according to an exemplary embodiment of the present disclosure. 2, an image sensing device 200 according to an exemplary embodiment of the present disclosure may include a pixel array 210, a first ramp generator 220, a second ramp generator 230, and an ADC circuit 240. The pixel array 210, the first ramp generator 220, the second ramp generator 230, and the ADC circuit 240 may correspond to the pixel array 11, the first ramp generator 12, the second ramp generator 13, and the ADC circuit 14 of FIG.

[0052] The pixel array 210 may generate pixel signals (VPX[0] to VPX[n]). For example, the pixel array 210 may generate pixel signals (VPX[0] to VPX[n]) corresponding to each column of the pixel array. The pixel signals (VPX[0] to VPX[n]) may be input to an ADC circuit 240 connected to the pixel array 210.

[0053] The first ramp generator 220 may include a DAC 221 and a resistor 222. The DAC 221 may be a DAC that generates a current. The current generated by the DAC 221 and the resistor 222 may generate a first ramp signal (VRAMP).

[0054] The second ramp generator 230 may include a first current source 231 and a second current source 232. A voltage may be applied to the first current source 231, and the second current source 232 may be connected to a ground terminal. The second ramp generator 230 may generate a second ramp signal (VRAMP_1) using the first current source 231 and the second current source 232.

[0055] The ADC circuit 240 may include an ADC connected to each column of the pixel array 210. The ADC circuit 240 may also include a plurality of buffers, a plurality of capacitors, a plurality of switches, and a plurality of comparators. The plurality of comparators may generate comparison signals (COUT[0] to COUT[n]), respectively. Regarding the column to which the pixel signal (VPX[0]) is input, the ADC circuit 240 may include a buffer 241, a first capacitor 242, a second capacitor 243, a switch 244, and a comparator 245. The comparator 245 may generate the comparison signal (COUT[0]) by comparing the input signal. For example, the comparator 245 may generate the comparison signal (COUT[0]) by comparing the input first ramp signal (VRAMP) with the pixel signal (VPX[0]) or by comparing the input second ramp signal (VRAMP_1) with the pixel signal (VPX[0]). Specifically, the comparator 245 can generate a comparison signal (COUT[0]) corresponding to the magnitude relationship between either one of the first ramp signal (VRAMP) and the second ramp signal (VRAMP_1) and the pixel signal (VPX[0]).

[0056] 2, the ADC circuit 240 may include a counter. The counter counts in synchronization with an edge (e.g., a rising edge or a falling edge) of the clock signal (CLK) until the comparison signal (COUT[0]) transitions from a first level (e.g., a logic high level) to a second level (e.g., a logic low level), and may output the accumulated count value as pixel data, but is not limited to this. The image data may be generated by performing signal processing on the pixel data, but is not limited to this.

[0057] FIG. 3 is a circuit diagram of an image sensing device according to an exemplary embodiment of the present disclosure. 3, the image sensing device 300 may include an ADC circuit 390 and a second ramp generator 380. Although omitted from FIG. 3, the image sensing device 300 may also include a first ramp generator that generates a first ramp signal (VRAMP) and a pixel array that generates a pixel signal (VPX).

[0058] The ADC circuit 390 may include a buffer 310 , a ground switch 320 , a first capacitor 330 , a second capacitor 340 , and a comparator 350 .

[0059] The buffer 310 may be configured to be activated in response to an enable signal (EN). Specifically, the buffer 310 may be connected to a first ramp generator and configured to output a first ramp signal in response to the enable signal (EN). The buffer 310 is activated when operating in the first mode, thereby suppressing noise from being added to the first ramp signal. As a result, in the first mode, the ADC circuit 390 may generate image data corresponding to higher image quality.

[0060] JPEG2026010661000002.jpg18170

[0061] The first capacitor 330 may be coupled between the buffer 310 and the comparator 350 . The second capacitor 340 may be coupled between the pixel array and the comparator 350 .

[0062] The comparator 350 may include a first amplifier 360, a second amplifier 370, a first switch (SP0) 351, a second switch (SP1) 352, a third switch (SP2) 353, a fourth switch (SN0) 354, a fifth switch (SN1) 355, and a sixth switch (SN2) 356.

[0063] The first amplifier 360 may have a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal. The first capacitor 330 may be connected to the positive input terminal of the first amplifier 360 , and the second capacitor 340 may be connected to the negative input terminal of the first amplifier 360 .

[0064] The second amplifier 370 may be connected to the positive output terminal of the first amplifier 360 and may output a comparison signal COUT. The first switch 351 may be connected to the positive input terminal of the first amplifier 360. For example, the first switch 351 may be connected to a VP node between the positive input terminal of the first amplifier 360 and the first capacitor 330.

[0065] The second switch 352 may be connected between the first switch 351 and the negative output terminal of the first amplifier 360 . The third switch 353 may be coupled to the first node between the first switch 351 and the second switch 352 and the second ramp generator 380 .

[0066] The fourth switch 354 may be connected to the negative input terminal of the first amplifier 360. For example, the fourth switch 354 may be connected to a VM node between the negative input terminal of the first amplifier 360 and the second capacitor 340.

[0067] The fifth switch 355 may be coupled between the fourth switch 354 and the positive output terminal of the first amplifier 360 . The sixth switch 356 may be coupled between a second node between the fourth switch 354 and the fifth switch 355 and a ground terminal.

[0068] The second ramp generator 380 may include a first current source 381 and a second current source 382. The second ramp generator 380 may be controlled by a DN signal and an UP signal.

[0069] The processor included in the image sensing device 300 can operate in a first mode or a second mode by turning on or off the plurality of switches 320, 351, 352, 353, 354, 355, and 356 and activating or deactivating the buffer 310. For example, the processor can input a first ramp signal (VRAMP) to the comparator 350 when operating in the first mode and input a second ramp signal (VRAMP_1) to the comparator 350 when operating in the second mode by controlling the plurality of switches 320, 351, 352, 353, 354, 355, and 356 and the buffer 310. More specific details regarding the control of the plurality of switches 320, 351, 352, 353, 354, 355, and 356 and the buffer 310 will be described later.

[0070] FIG. 4 is a timing diagram illustrating a method of operation of an image sensing device according to an exemplary embodiment of the present disclosure. FIG. 5a is a circuit diagram of an image sensing device according to an exemplary embodiment of the present disclosure. FIG. 5b is a circuit diagram of an image sensing device according to an exemplary embodiment of the present disclosure.

[0071] FIG. 4 will now be described with reference to FIGS. 5a and 5b. Referring to Figures 5a and 5b, an image sensing device 500 according to an exemplary embodiment of the present disclosure may include a ground switch 510, a first capacitor 520, a second capacitor 530, a first amplifier 540, a first switch (SP0) 541, a second switch (SP1) 542, a third switch (SP2) 543, a fourth switch (SN0) 544, a fifth switch (SN1) 545, and a sixth switch (SN2) 546.

[0072] 4, the processor included in the image sensing apparatus 500 may operate in a first mode. For example, when operating in the first mode, the processor may generate an enable signal (EN) having a logic high level to activate a buffer and turn off the ground switch 510 so that the comparator 540 receives a first ramp signal (VRAMP). Specifically, the processor may generate the enable signal (EN) having a logic high level to activate the buffer, thereby controlling the buffer that receives the first ramp signal (VRAMP) to output the first ramp signal (VRAMP).

[0073] In addition, when operating in the first mode, the processor may turn off the third switch (SP2) 543 and the sixth switch (SN2) 546 to prevent an unnecessary input differential component from being generated due to a switching operation. In addition, when operating in the first mode, the processor may control the second ramp generator to couple the ICP line to the ground node.

[0074] The processor can perform auto-zero. When operating in the first mode, the processor can perform auto-zero by turning on a first switch (SP0) 541, a second switch (SP1) 542, a fourth switch (SN0) 544, and a fifth switch (SN1) 545, and turning off a third switch (SP2) 543 and a sixth switch (SN2) 546. The self-bias voltages of the first amplifier 540 appearing at nodes (VM) and (VP) can be maintained on the first capacitor 520 and the second capacitor 530, respectively.

[0075] The processor may read the reset voltage level of a pixel included in the pixel array or the voltage level of a pixel signal corresponding to the amount of light received by the pixel. For example, when operating in the first mode, the processor may turn off the first switch (SP0) 541, the second switch (SP1) 542, the third switch (SP2) 543, the fourth switch (SN0) 544, the fifth switch (SN1) 545, and the sixth switch (SN2) 546 to read the reset voltage level of a pixel included in the pixel array or the voltage level of a pixel signal (VPX) corresponding to the amount of light received by the pixel. Specifically, after auto-zero is completed, the processor may use the first ramp generator to further increase the voltage level of the first ramp signal (VRAMP) by an offset voltage level. Also, as shown in FIG. 4, the start of the first ramp waveform may result in a point in time when the voltage level of the pixel signal (VPX) and the voltage level of the first ramp signal (VRAMP) match. The processor can obtain a digital value corresponding to the reset voltage level of the pixel by quantizing the time when the comparator outputs the comparison signal (COUT) when the voltage level of the pixel signal (VPX) matches the voltage level of the first ramp signal (VRAMP). In other words, the processor can read the reset voltage level of the pixel.

[0076] The voltage level of the pixel signal (VPX) can change depending on the amount of light received by the pixel. After reading the reset voltage level of the pixel, the processor can read the changed voltage level of the pixel signal (VPX). For example, as shown in Figure 4, when the second ramp waveform starts, the changed voltage level of the pixel signal (VPX) can match the voltage level of the first ramp signal (VRAMP). This allows the processor to obtain a digital value for the voltage level of the pixel signal (VPX) by quantizing the time at which the comparator outputs the comparison signal (COUT). In other words, the processor can read the voltage level of the pixel signal (VPX) according to the amount of light received by the pixel.

[0077] FIG. 6 is a timing diagram illustrating a method of operation of an image sensing device according to an exemplary embodiment of the present disclosure. FIG. 7a is a circuit diagram of an image sensing device according to an exemplary embodiment of the present disclosure. FIG. 7b is a circuit diagram of an image sensing device according to an exemplary embodiment of the present disclosure. FIG. 7c is a circuit diagram of an image sensing device according to an exemplary embodiment of the present disclosure.

[0078] FIG. 6 will be described below with reference to FIGS. 7a to 7c. Referring to Figures 7a to 7c, an image sensing device 700 according to an exemplary embodiment of the present disclosure may include a ground switch 710, a first capacitor 720, a second capacitor 730, a first amplifier 740, a first switch (SP0) 741, a second switch (SP1) 742, a third switch (SP2) 743, a fourth switch (SN0) 744, a fifth switch (SN1) 745, and a sixth switch (SN2) 746.

[0079] 6, the processor included in the image sensing device 700 may operate in a second mode. For example, when operating in the second mode, the processor may generate an enable signal (EN) having a logic low level to deactivate the buffer, turn on the ground switch 710, and turn on the first switch (SP0) 741 and the third switch (SP2) 743 so that the comparator 740 receives the second ramp signal (VRAMP_1). Specifically, the processor may generate an enable signal (EN) having a logic low level to power down the buffer, turn on the ground switch 710 to ground the node (VX), and turn on the first switch (SP0) 741 and the third switch (SP2) 743 to input the second ramp signal (VRAMP_1) to the comparator 740. Because the buffer can be powered down in the second mode, the image sensing device 700 may reduce power consumption. The processor can also turn off the sixth switch (SN2) 746 when operating in the second mode.

[0080] In the second mode, the IV conversion by the second ramp generator does not require any additional elements and utilizes the first capacitor 720 that is already provided in the ADC circuit configuration, allowing the image sensing device 700 to be implemented with a small mounting area.

[0081] When operating in the second mode, the processor can reset the output node (ICP line) and node (VP) of the second ramp generator. For example, the processor can reset the node (VP) and the ICP line by turning on the second switch (SP1) 742, the fourth switch (SN0) 744, and the fifth switch (SN1) 745. Specifically, the node (VP) and the ICP line can be reset to the average value of the self-bias voltage generated by the first amplifier 740.

[0082] When operating in the second mode, the processor can perform autozero after node (VP) and the ICP line are reset. For example, when operating in the second mode, the processor can perform autozero by turning on the first switch (SP0) 741, the third switch (SP2) 743, the fourth switch (SN0) 744, and the fifth switch (SN1) 745, and turning off the second switch (SP1) 742 and the sixth switch (SN2) 746. Opening the second switch (SP1) 742 cuts off the feedback of the negative output and the positive input, and the potential maintained at node (VP) can be copied to node (VM) through the feedback of the positive output and the negative output.

[0083] The processor may also read the reset voltage levels of pixels included in the pixel array or the voltage levels of pixel signals corresponding to the amount of light received by the pixels. For example, when operating in the second mode, the processor may turn on the first switch (SP0) 741 and the third switch (SP2) 743 and turn off the second switch (SP1) 742, the fourth switch (SN0) 744, the fifth switch (SN1) 745, and the sixth switch (SN2) 746 to read the reset voltage levels of pixels included in the pixel array or the voltage levels of pixel signals (VPX) corresponding to the amount of light received by the pixels. Specifically, after auto-zero is completed, the processor may use the second ramp generator to further increase the voltage level of the second ramp signal (VRAMP_1) by an offset voltage level. For example, a logic high UP signal may be input to the second ramp generator to inject a source current into the first capacitor 720, thereby increasing the voltage level of the second ramp signal (VRAMP_1) input to the first amplifier 740. Furthermore, when the voltage level of the second ramp signal (VRAMP_1) reaches the target value, the processor can fix the voltage level of the second ramp signal (VRAMP_1) input to the first amplifier 740 by stopping the injection of the source current using the UP signal at a logic low level. Furthermore, when the DN signal at a logic high level causes the sink current to discharge the first capacitor 720, the initial ramp waveform can be initiated. The processor can obtain a digital value corresponding to the reset voltage level of the pixel by quantizing the time when the comparator outputs the comparison signal (COUT) as the voltage level of the pixel signal (VPX) matches the voltage level of the second ramp signal (VRAMP_1). In other words, the processor can read the reset voltage level of the pixel.

[0084] The voltage level of the pixel signal (VPX) can change depending on the amount of light received by the pixel. After reading the reset voltage level of the pixel, the processor can read the changed voltage level of the pixel signal (VPX). For example, as shown in FIG. 6, after reading the reset voltage level of the pixel, the processor can stop injecting a sink current into the first capacitor 720 using the DN signal and inject a source current using the UP signal, thereby returning the potentials of the node (VP) and the ICP line to the offset level. The processor can also stop injecting a source current using the UP signal and inject a sink current into the first capacitor 720 using the DN signal, thereby starting a second ramp waveform. This allows the changed voltage level of the pixel signal (VPX) to match the voltage level of the second ramp signal (VRAMP_1), and the processor can obtain a digital value for the voltage level of the pixel signal (VPX) by quantizing the time at which the comparator outputs the comparison signal (COUT). That is, the processor can read the voltage level of the pixel signal (VPX) according to the amount of light received by the pixel.

[0085] Once the voltage level of the pixel signal (VPX) has been read, the potential of the node (VP) and the ICP line can be maintained until the second switch (SP1) 742, the fourth switch (SN0) 744, and the sixth switch (SN2) 746 are turned on in the next cycle.

[0086] FIG. 8 is a block diagram of an image sensing device according to an exemplary embodiment of the present disclosure. FIG. 9 is a diagram for explaining the operation of the image sensing device according to the exemplary embodiment of the present disclosure.

[0087] FIG. 8 will be described below with reference to FIG. 8, an image sensing device 800 may include a pixel array 810, a first ramp generator 820, a second ramp generator 830, an ADC circuit 840, a processor 850, and an interface 860, and may communicate with an APU (Application Processing Unit) 870. Here, the APU may be referred to as an external processor. The image sensing device 800, the pixel array 810, the first ramp generator 820, the second ramp generator 830, the ADC circuit 840, and the processor 850 may correspond to the image sensing device 100, the pixel array 11, the first ramp generator 12, the second ramp generator 13, the ADC circuit 14, and the internal processor 15, respectively, of FIG.

[0088] In the second mode, the processor 850 can input the second ramp signal of the second ramp generator 830 to the ADC circuit 840. The ADC circuit 840 can generate second image data based on the second ramp signal. When operating in the second mode, the processor 850 can detect a moving object from an image corresponding to the second image data based on the second image data. That is, the processor 850 can perform motion detection. For example, the ADC circuit 840 can generate second image data corresponding to a second image of relatively low image quality, and the processor 850 can detect a moving object by performing motion detection based on the second image data.

[0089] Additionally, when operating in the second mode, the processor 850 can put the first ramp generator 820 and the interface 860 to sleep, i.e., when operating in the second mode, the processor 850 can deactivate the interface 860.

[0090] In the second mode, the first ramp generator 820 and the interface 860 are deactivated, so that the image sensing device 800 can reduce power consumption.

[0091] The interface 860 can communicate with the APU 870. The processor 850 can activate the interface 860 when operating in a first mode and deactivate the interface 860 when operating in a second mode. Deactivating the interface 860 allows the APU 870 to sleep. The interface 860 can be, for example, but is not limited to, a High-Speed ​​Serial Interface (HSSI).

[0092] The APU 870 may determine the mode in which the image sensing device 800 operates. For example, if power consumption needs to be reduced, the APU 870 may instruct the image sensing device 800 to operate in a second mode.

[0093] FIG. 10 is a block diagram of an image sensing device according to an exemplary embodiment of the present disclosure. FIG. 11 is a diagram for explaining the operation of the image sensing device according to the exemplary embodiment of the present disclosure.

[0094] FIG. 10 will be described below with reference to FIG. 10, an image sensing device 800 may include a pixel array 810, a first ramp generator 820, a second ramp generator 830, an ADC circuit 840, a processor 850, and an interface 860, and may communicate with an APU (Application Processing Unit) 870. Here, the APU may be referred to as an external processor. The image sensing device 800, the pixel array 810, the first ramp generator 820, the second ramp generator 830, the ADC circuit 840, and the processor 850 may correspond to the image sensing device 100, the pixel array 11, the first ramp generator 12, the second ramp generator 13, the ADC circuit 14, and the internal processor 15, respectively, of FIG.

[0095] In the first mode, the processor 850 can input the first ramp signal of the first ramp generator 820 to the ADC circuit 840. The ADC circuit 840 can generate first image data based on the first ramp signal. As shown in FIG. 11 , when operating in the first mode, the first image corresponding to the first image data may be a higher quality image than the second image corresponding to the second image data described above.

[0096] Furthermore, when operating in the first mode, the processor 850 can put the second ramp generator 830 to sleep. For example, the processor 850 can control the ADC circuit 840 to prevent the second ramp signal generated by the second ramp generator 830 from being input to the ADC circuit 840.

[0097] The interface 860 can communicate with the APU 870. The processor 850 can activate the interface 860 when operating in a first mode and deactivate the interface 860 when operating in a second mode. The ADC circuit 840 can transmit first image data to the interface 860 when operating in the first mode. The interface 860 can be, for example, but is not limited to, a High-Speed ​​Serial Interface (HSSI).

[0098] The APU 870 can determine the mode in which the image sensing device 800 operates. For example, if a high quality image is required, the APU 870 can instruct the image sensing device 800 to operate in a first mode.

[0099] The above description merely exemplifies the technical concept of the present disclosure, and various modifications and variations are possible within the scope of the essential characteristics of the present disclosure, provided that such modifications and variations are made by a person skilled in the art to which the present disclosure pertains. Therefore, the embodiments disclosed in the present disclosure are intended to illustrate, rather than limit, the technical concept of the present disclosure, and the scope of the technical concept of the present disclosure is not limited by such embodiments. The scope of protection of the present disclosure should be interpreted by the scope of the claims below, and all technical concepts within the scope equivalent thereto should be interpreted as being within the scope of the present disclosure.

Claims

1. a pixel array for generating pixel signals; a first ramp generator for generating a first ramp signal; a second ramp generator that generates a second ramp signal; an ADC (Analog-to-Digital Converter) circuit including a comparator that compares one of the first ramp signal and the second ramp signal with the pixel signal, and generates image data based on a comparison result; a processor that controls the ADC circuit such that in a first mode, the first ramp signal is input to the comparator, and in a second mode, the second ramp signal is input to the comparator; An image sensing device comprising:

2. The ADC circuit a buffer coupled to the first ramp generator and configured to output the first ramp signal in response to an enable signal; a first capacitor coupled between the buffer and the comparator; a second capacitor coupled between the pixel array and the comparator; 2. The image sensing device of claim 1, further comprising: a ground switch connected between an output node of the buffer and a ground terminal, the ground switch being turned on in response to an inverted enable signal having an opposite state to the enable signal.

3. The comparator a first amplifier having a positive input terminal connected to the first capacitor, a negative input terminal connected to the second capacitor, a positive output terminal, and a negative output terminal; a second amplifier connected to the positive output terminal; a first switch connected to the positive input terminal; a second switch connected between the first switch and the negative output terminal; a third switch coupled to a first node between the first switch and the second switch and to the second ramp generator; a fourth switch connected to the negative input terminal; a fifth switch connected between the fourth switch and the positive output terminal; The image sensing device of claim 2 , further comprising: a sixth switch coupled between a second node between the fourth switch and the fifth switch and the ground terminal.

4. The processor:

4. The image sensing device of claim 3, wherein in the first mode, the enable signal having a logic high level is generated to activate the buffer and turn off the ground switch so that the comparator receives the first ramp signal.

5. The processor:

5. The image sensing device of claim 4, wherein in the first mode, the first switch, the second switch, the fourth switch, and the fifth switch are turned on, and the third switch and the sixth switch are turned off, thereby performing auto-zero.

6. The processor:

5. The image sensing device of claim 4, wherein in the first mode, the first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch are turned off to read a reset voltage level of a pixel included in the pixel array or to read a voltage level of the pixel signal according to an amount of light received by the pixel.

7. The processor:

4. The image sensing device of claim 3, wherein in the second mode, the enable signal having a logic low level is generated to deactivate the buffer, turn on the ground switch, and turn on the first switch and the third switch so that the comparator receives the second ramp signal.

8. The processor:

8. The image sensing device of claim 7, wherein in the second mode, turning on the second switch, the fourth switch, and the fifth switch resets the positive input node of the first amplifier and the output node of the second ramp generator.

9. The processor: The image sensing device according to claim 7 , wherein in the second mode, auto-zero is performed by turning on the fourth switch and the fifth switch and turning off the second switch and the sixth switch.

10. The processor:

8. The image sensing device of claim 7, wherein in the second mode, the second switch, the fourth switch, the fifth switch, and the sixth switch are turned off to read a reset voltage level of a pixel included in the pixel array or to read a voltage level of the pixel signal according to an amount of light received by the pixel.

11. The first ramp generator 10. The image sensing device of claim 1, comprising a digital-to-analog converter (DAC) configured to output a current.

12. The second ramp generator a first current source that generates a source current; 10. The image sensing device of claim 1, further comprising: a second current source that generates a sink current.

13. a first capacitor connected to the positive input terminal of the comparator; The processor: The image sensing device of claim 12 , wherein the first current source is used to charge the first capacitor and the second current source is used to discharge the first capacitor.

14. further including an interface for communicating with an external processor; The processor: activating the interface in the first mode; The image sensing device according to claim 1 , wherein the interface is deactivated in the second mode.

15. The ADC circuit The image sensing device of claim 14 , wherein in the first mode, the image data is transmitted to the interface.

16. The processor: The image sensing device according to claim 1 , wherein in the second mode, a moving object is detected from an image corresponding to the image data based on the image data.

17. The processor:

2. The image sensing device of claim 1, wherein in the first mode, the ADC circuit is controlled to generate the image data corresponding to a full resolution image.

18. The first ramp signal is The image sensing device of claim 1 , wherein the second ramp signal is a different ramp signal.

19. a pixel array for generating pixel signals; a comparator that compares the pixel signal with one of a first ramp signal and a second ramp signal; a first ramp generator including a digital-to-analog converter (DAC) for generating the first ramp signal; a second ramp generator including a first current source and a second current source for generating the second ramp signal; a buffer coupled to the first ramp generator; a first capacitor coupled between the buffer and the comparator; a second capacitor coupled between the pixel array and the comparator; An image sensing device comprising:

20. a pixel array for generating pixel signals; a first ramp generator for generating a first ramp signal; a second ramp generator that generates a second ramp signal; an ADC circuit (Analog-to-Digital Converter circuit) that generates first image data based on the first ramp signal and the pixel signal, and generates second image data based on the second ramp signal and the pixel signal; a processor that controls the ADC circuit such that in a first mode, the second ramp generator is put to sleep and the ADC circuit receives the first ramp signal, and in a second mode, the first ramp generator is put to sleep and the ADC circuit receives the second ramp signal; Including, The first image corresponding to the first image data is an image sensing device, the image being of higher quality than a second image corresponding to the second image data;

Images