Semiconductor device and method of manufacturing the same

Abstract

To improve performance of a semiconductor device having a ferroelectric memory cell provided with a selection transistor and a memory transistor.SOLUTION: A semiconductor device includes a selection transistor SQ having a paraelectric film IL1, a ferroelectric film FE, a metal film MF and a selection gate electrode SG formed in order on a semiconductor substrate SB, and a memory transistor MQ having a paraelectric film IL2, a ferroelectric film FE, a metal film MF and a memory gate electrode MG formed in order on a semiconductor substrate SB. Here, the thickness of the paraelectric film IL1 is larger than the thickness of the paraelectric film IL2. Each of the paraelectric films IL1 and IL2 contains nitride, and the nitride concentration in the paraelectric film IL1 decreases from the upper surface of the paraelectric film IL1 toward the lower surface of the paraelectric film IL1.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a ferroelectric memory cell and a manufacturing method thereof. [Background technology]

[0002] Ferroelectric memory cells have been developed as semiconductor memory elements that operate at relatively low voltages. A ferroelectric memory cell has a ferroelectric film formed on a semiconductor substrate and a gate electrode formed on the ferroelectric film. By controlling the direction of polarization of the ferroelectric, the state of the ferroelectric memory cell changes between a written state and an erased state. Patent Document 1 (JP 2019-201172 A) describes the structure and manufacturing method of a ferroelectric memory cell. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-201172 Summary of the Invention [Problem to be solved by the invention]

[0004] In a ferroelectric memory cell, oxygen contained in a ferroelectric film may diffuse to the upper surface of a semiconductor substrate, where the oxygen reacts with the upper surface of the semiconductor substrate to form an oxide film, which may degrade the performance of the semiconductor device.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] A brief summary of a representative embodiment of the present invention will be given below.

[0007] In one embodiment, a semiconductor device has a select transistor and a memory transistor. The select transistor includes a first paraelectric film, a first ferroelectric film, and a first gate electrode formed in this order on a semiconductor substrate. The memory transistor includes a second paraelectric film, a second ferroelectric film, and a second gate electrode formed in this order on the semiconductor substrate. Here, the thickness of the first paraelectric film is greater than the thickness of the second paraelectric film. Each of the first paraelectric film and the second paraelectric film contains nitrogen, and the nitrogen concentration in the first paraelectric film decreases from the upper surface of the first paraelectric film toward the lower surface of the first paraelectric film.

[0008] In one embodiment, a method for manufacturing a semiconductor device includes the steps of: forming a first paraelectric film on a semiconductor substrate; forming a second paraelectric film on the semiconductor substrate, the second paraelectric film having a thickness smaller than that of the first paraelectric film; introducing nitrogen into each of the first paraelectric film and the second paraelectric film by a plasma nitridation method; forming a first ferroelectric film and a first gate electrode in this order on the first paraelectric film, and forming a second ferroelectric film and a second gate electrode in this order on the second paraelectric film; and forming the first source region and the first drain region in the semiconductor substrate. [Effects of the Invention]

[0009] According to one embodiment, the performance of a semiconductor device can be improved. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a planar layout of a semiconductor device according to an embodiment. [Figure 2] 1 is a cross-sectional view of a semiconductor device according to an embodiment; [Figure 3] 1 is a planar layout of a semiconductor device according to an embodiment. [Figure 4] 10 is a table showing applied voltages during each operation of a ferroelectric memory cell; [Figure 5] 1 is a cross-sectional view of a semiconductor device during a manufacturing process according to an embodiment; [Figure 6] 6 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 5. [Figure 7] FIG. 7 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 6. [Figure 8] 8 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. 7. [Figure 9] 9 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 8. [Figure 10] FIG. 10 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. [Figure 11] 11 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 10. [Figure 12] 12 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 11. [Figure 13] 13 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 12. [Figure 14] 14 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 13. [Figure 15] FIG. 15 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. [Figure 16] FIG. 16 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. [Figure 17] FIG. 17 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. [Figure 18] 1 is a cross-sectional view of a main part of a semiconductor device according to an embodiment; [Figure 19] 1 is a graph showing the concentration distribution in the depth direction of nitrogen introduced into an insulating film by a DPN method. [Figure 20] 1 is a graph showing current-voltage characteristics of a memory transistor. [Figure 21] FIG. 10 is a cross-sectional view of a semiconductor device according to a modified example of the embodiment. [Figure 22] 10A and 10B are cross-sectional views of a semiconductor device according to a modified example of the embodiment during a manufacturing process. [Figure 23] 10 is a graph showing current-voltage characteristics of a memory transistor subjected to channel dosing. [Figure 24]10 is a graph showing the current-voltage characteristics of a memory transistor to which channel dosing has not been performed. [Figure 25] FIG. 10 is a cross-sectional view of a main part of a semiconductor device according to a comparative example. [Figure 26] FIG. 10 is a cross-sectional view of a main part of a semiconductor device according to a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0011] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the mentioned number, and may be more or less than the mentioned number, unless otherwise specified or when it is clearly limited in principle to a specific number.

[0012] Furthermore, in the following embodiments, the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numerical values ​​and ranges.

[0013] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0014] The X direction and the Y direction in this application are along the main surface of the semiconductor substrate and are orthogonal to each other in a plan view.

[0015] (Embodiment) <Structure of semiconductor device> A semiconductor device 100 according to this embodiment will be described below with reference to Figures 1 to 3. The semiconductor device 100 has ferroelectric memory cells MC as electrically rewritable nonvolatile memory cells.

[0016] 1 shows a planar layout of a semiconductor device 100 according to this embodiment. The semiconductor device 100 has a circuit region C1, a circuit region C2, and a circuit region C3.

[0017] Circuit area C1 has, for example, a logic circuit including a CPU and an SRAM. The semiconductor elements constituting the circuit included in circuit area C1 are low-voltage MOSFETs that operate at a voltage of about 1.0 V. Circuit area C2 has, for example, an I / O circuit. The semiconductor elements constituting the circuit included in circuit area C2 are high-voltage MOSFETs that operate at a voltage of about 3.3 V. Circuit area C3 has ferroelectric memory cells MC.

[0018] The semiconductor device 100 has regions 1A and 2A. Fig. 2 is a cross-sectional view showing a ferroelectric memory cell MC formed in the region 1A and a low-voltage MOSFET 1Q formed in the region 2A. Fig. 3 is a planar layout showing the ferroelectric memory cell MC and the low-voltage MOSFET 1Q.

[0019] The ferroelectric memory cell MC will now be described.

[0020] 2, the semiconductor substrate SB is made of, for example, p-type single crystal silicon (Si), etc. In the region 1A, a p-type well region PW1 is formed in the semiconductor substrate SB.

[0021] The ferroelectric memory cell MC includes a select transistor SQ and a memory transistor MQ. The select transistor SQ includes a paraelectric film IL1, a ferroelectric film FE, a metal film MF, and a select gate electrode SG. The select transistor SQ selects the ferroelectric memory cell MC for performing a write operation, an erase operation, or a read operation. The memory transistor MQ has an MFIS (Metal Ferroelectric Insulator Semiconductor) structure in which the ferroelectric film FE is applied to a transistor. The memory transistor MQ includes a paraelectric film IL2, a ferroelectric film FE, a metal film MF, and a memory gate electrode MG.

[0022] A channel region CH, which is a p-type semiconductor region, is formed in the well region PW1. The channel region CH has a higher impurity concentration than the well region PW1. In FIG. 3, the lower end of the channel region CH is indicated by a dashed line. The channel region CH has a predetermined depth from the upper surface of the semiconductor substrate SB to partway through the depth of the semiconductor substrate SB (well region PW1). The channel region CH is formed directly below each of the select gate electrode SG and the memory gate electrode MG.

[0023] The paraelectric films IL1 and IL2 are formed on a semiconductor substrate SB including a well region PW1. The paraelectric films IL1 and IL2 are, for example, silicon oxide films. The paraelectric film IL1 has a thickness greater than that of the paraelectric film IL2. This is to prevent the occurrence of polarization in the ferroelectric film FE of the select transistor SQ. The paraelectric film IL1 has a thickness of, for example, 6 nm or more. The paraelectric film IL2 has a thickness of, for example, 1 nm or more.

[0024] The ferroelectric film FE is formed on each of the paraelectric film IL1 and the paraelectric film IL2. The ferroelectric film FE is made of a metal oxide film and is a high-dielectric-constant film having a higher dielectric constant than, for example, a silicon nitride film. The thickness of the ferroelectric film FE is, for example, 4 nm or more and 20 nm or less.

[0025] The ferroelectric film FE in this embodiment is made of, for example, a material containing a metal oxide and a first element. The metal oxide is, for example, hafnium oxide (HfO2) or gallium oxide (Ga2O3). The first element is, for example, zirconium (Zr). The first element may be silicon (Si), nitrogen (N), yttrium (Y), germanium (Ge), lanthanum (La), or ytterbium (Yb) instead of zirconium.

[0026] The metal film MF is formed on the ferroelectric film FE. The metal film MF is made of, for example, a titanium nitride film, a tantalum nitride film, or a tungsten film. The thickness of the metal film MF is, for example, 2 nm or more and 20 nm or less.

[0027] The metal film MF is used to apply stress to the ferroelectric film FE during the manufacturing process of the ferroelectric film FE and control the crystal orientation of the ferroelectric film FE. Therefore, the metal film MF may be removed after the ferroelectric film FE is formed. However, removing the metal film MF may cause variations in the characteristics of the ferroelectric film FE. For this reason, it is more preferable to leave the metal film MF. Note that if the metal film MF is left, the metal film MF of the select transistor SQ also functions as part of the select gate electrode SG described later. Furthermore, if the metal film MF is left, the metal film MF of the memory transistor MQ also functions as part of the memory gate electrode MG described later.

[0028] The select gate electrode SG is formed on a metal film MF arranged above the paraelectric film IL1. The select gate electrode SG is made of, for example, a polycrystalline silicon film doped with n-type impurities. An insulating film IF2 is also formed on the select gate electrode SG. Sidewall spacers SW are formed on the side surfaces of the select gate electrode SG. The sidewall spacers SW are made of, for example, a silicon oxide film and a silicon nitride film formed on the silicon oxide film. As described above, the select transistor SQ includes a first stacked body having a paraelectric film IL1 on the semiconductor substrate SB, a ferroelectric film FE on the paraelectric film IL1, a metal film MF on the ferroelectric film FE, and a select gate electrode SG on the metal film MF. The first stacked body may have an insulating film IF2 on the select gate electrode SG. The insulating film IF2 is made of, for example, a silicon nitride film.

[0029] The memory gate electrode MG is formed on a metal film MF arranged on a paraelectric film IL2. The memory gate electrode MG is made of, for example, a polycrystalline silicon film doped with n-type impurities. In addition, an insulating film IF2 is formed on the memory gate electrode MG. Sidewall spacers SW are formed on the side surfaces of the memory gate electrode MG. In this way, the memory transistor MQ includes a second stacked body having a paraelectric film IL2 on the semiconductor substrate SB, a ferroelectric film FE on the paraelectric film IL2, a metal film MF on the ferroelectric film FE, and a memory gate electrode MG on the metal film MF. The second stacked body may have an insulating film IF2 on the memory gate electrode MG. The insulating film IF2 is made of, for example, a silicon nitride film.

[0030] A low-concentration region LDD, which is a low-concentration n-type impurity region, is formed in the semiconductor substrate SB and located below the sidewall spacer SW. A diffusion region ND, a source region MS, and a drain region MD, which are also n-type impurity regions, are formed in the semiconductor substrate SB (in the well region PW1) exposed from the sidewall spacer SW. The impurity concentrations of the diffusion region ND, the source region MS, and the drain region MD are higher than the impurity concentration of the low-concentration region LDD. The low-concentration region LDD and the drain region MD are connected to each other and each constitute a part of the drain region of the ferroelectric memory cell MC. The low-concentration region LDD and the source region MS are also connected to each other and each constitute a part of the source region of the ferroelectric memory cell MC. A channel region CH is located between the source region MS and the drain region MD.

[0031] 3 shows the semiconductor substrate SB, the select gate electrode SG, the memory gate electrode MG, the gate electrode GE, the diffusion region ND, the source region MS, and the drain region MD. In FIG. 3, hatching is applied to portions of the semiconductor substrate SB that do not overlap with the select gate electrode SG, the memory gate electrode MG, the gate electrode GE, the diffusion region ND, the source region MS, and the drain region MD.

[0032] As shown in FIG. 3, the select gate electrode SG extends in the Y direction. The memory gate electrode MG also extends in the Y direction. The diffusion region ND, the source region MS, and the drain region MD also extend in the Y direction. In plan view, the source region MS, the select gate electrode SG, the diffusion region ND, the memory gate electrode MG, and the drain region MD are arranged in this order in the X direction. In other words, in plan view, the first stacked body and the second stacked body are both disposed between the source region MS and the drain region MD.

[0033] 3, the lightly doped region LDD and the diffusion region ND formed directly below the region between the select gate electrode SG and the memory gate electrode MG are connected to each other. The lightly doped region LDD and the diffusion region ND electrically connect the memory transistor MQ and the select transistor SQ to each other.

[0034] Although not shown here, a silicide layer may be formed on the select gate electrode SG, the memory gate electrode MG, the diffusion region ND, the source region MS, and the drain region MD. The silicide layer is made of, for example, cobalt silicide, nickel silicide, or nickel platinum silicide.

[0035] The first stacked body, the source region MS, and the drain region MD constitute a select transistor SQ. The second stacked body, the source region MS, and the drain region MD constitute a memory transistor MQ. The first stacked body, the second stacked body, the source region MS, and the drain region MD constitute a ferroelectric memory cell MC.

[0036] Here, each of the paraelectric films IL1 and IL2 contains nitrogen. That is, each of the paraelectric films IL1 and IL2 is a silicon oxide film into which nitrogen has been introduced. The nitrogen concentration in the paraelectric film IL1 decreases from the upper surface of the paraelectric film IL1 toward the lower surface of the paraelectric film IL1. That is, the nitrogen concentration in the paraelectric film IL1 is highest near the upper surface of the paraelectric film IL1. Moreover, the nitrogen concentration in the paraelectric film IL2 is almost constant in the depth direction in the paraelectric film IL1. However, the nitrogen concentration in the paraelectric film IL1 may decrease from the upper surface of the paraelectric film IL1 toward the lower surface of the paraelectric film IL1.

[0037] The nitrogen concentration in the paraelectric film IL1 near the upper surface of the paraelectric film IL1 and the nitrogen concentration in the paraelectric film IL2 near the upper surface of the paraelectric film IL2 are almost the same. On the other hand, the nitrogen concentration in the paraelectric film IL1 near the lower surface of the paraelectric film IL1 is lower than the nitrogen concentration in the paraelectric film IL2 near the lower surface of the paraelectric film IL2.

[0038] Next, the low voltage MOSFET 1Q will be described.

[0039] In the region 2A, a p-type well region PW2 is formed in the semiconductor substrate SB. The low-voltage MOSFET 1Q includes a gate insulating film IF1 and a gate electrode GE.

[0040] A channel region CH, which is a p-type semiconductor region, is formed in the well region PW2. The channel region CH has a higher impurity concentration than the well region PW1. The channel region CH has a predetermined depth from the upper surface of the semiconductor substrate SB to the middle depth of the semiconductor substrate SB (well region PW2). The channel region is formed directly below the gate electrode GE.

[0041] The gate insulating film IF1 is, for example, a silicon oxide film. The thickness of the gate insulating film IF1 is greater than the thickness of the paraelectric film IL2. The gate electrode GE is, for example, made of a polycrystalline silicon film doped with n-type impurities. An insulating film IF2 is formed on the gate electrode GE. Sidewall spacers SW are formed on the side surfaces of the gate electrode GE.

[0042] A low-concentration region LDD, which is a low-concentration n-type impurity region, is formed in the semiconductor substrate SB and located below the sidewall spacer SW. Furthermore, a source region MS and a drain region MD, which are n-type impurity regions, are formed in the semiconductor substrate SB (in the well region PW2) exposed from the sidewall spacer SW. The impurity concentrations of the source region MS and the drain region MD are higher than that of the low-concentration region LDD. The low-concentration region LDD and the drain region MD are connected to each other and each constitute a part of the drain region of the low-voltage MOSFET 1Q. The low-concentration region LDD and the source region MS are also connected to each other and each constitute a part of the source region of the low-voltage MOSFET 1Q. A channel region CH is disposed between the source region MS and the drain region MD. As shown in FIG. 3, the gate insulating film IF1 and the gate electrode GE are disposed between the source region MS and the drain region MD in a plan view.

[0043] The source region MS, the drain region MD, the gate insulating film IF1, and the gate electrode GE constitute a low-voltage MOSFET 1 Q. The gate insulating film IF1 contains nitrogen, and the nitrogen concentration in the gate insulating film IF1 is lower than the nitrogen concentration in the paraelectric film IL2.

[0044] <Operation of ferroelectric memory cell MC> During each operation of the ferroelectric memory cell MC, the voltages shown in FIG. 4 are applied. The voltage Vmg is applied to the memory gate electrode MG, and the voltage Vcg is applied to the select gate electrode SG. The voltage Vs is applied to the source region MS, and the voltage Vd is applied to the drain region MD. The voltage Vb is applied to the well region PW1. Here, the operation of the selected ferroelectric memory cell MC will be described.

[0045] In a write operation, the voltages shown in the "Write Operation" column in Figure 4 are applied to the ferroelectric memory cell MC. This leaves a positive remanent polarization in the ferroelectric film FE of the memory transistor MQ, and the polarization direction becomes upward. As a result, the threshold voltage of the memory transistor MQ increases, and the ferroelectric memory cell MC enters a write state until an erase operation is performed.

[0046] In the erase operation, the voltages shown in the "Erase Operation" column in Figure 4 are applied to the ferroelectric memory cell MC. This leaves a negative remanent polarization in the ferroelectric film FE of the memory transistor MQ, and the polarization direction becomes downward. As a result, the threshold voltage of the memory transistor MQ decreases, and the ferroelectric memory cell MC is in the erased state until a write operation is performed.

[0047] In a read operation, the voltages shown in the "Read Operation" column of FIG. 4 are applied to the ferroelectric memory cell MC. The voltage applied to the memory gate electrode MG during a read operation is set to be smaller than the threshold voltage of the memory transistor MQ in the written state and larger than the threshold voltage of the memory transistor MQ in the erased state. As a result, no current or a relatively small current flows in the ferroelectric memory cell MC in the written state. On the other hand, a relatively large current flows in the ferroelectric memory cell MC in the erased state. In this way, the memory state of the ferroelectric memory cell MC can be determined based on the magnitude of the current flowing in the ferroelectric memory cell MC.

[0048] Here, by forming a paraelectric film IL2 having a thickness smaller than that of the paraelectric film IL1, polarization is likely to occur in the ferroelectric film FE of the memory transistor MQ. Also, although the select transistor SQ has a ferroelectric film FE, the select transistor SQ is a selection element and not a memory element. If polarization occurs in the ferroelectric film FE of the select transistor SQ, the select transistor SQ becomes uncontrollable, so it is necessary to prevent the occurrence of polarization in the ferroelectric film FE of the select transistor SQ. Here, by forming a paraelectric film IL1 having a thickness greater than that of the paraelectric film IL2, polarization is prevented from occurring in the ferroelectric film FE of the select transistor SQ due to the influence of an electric field.

[0049] <Method of manufacturing a semiconductor device> A method for manufacturing a semiconductor device according to this embodiment will be described below with reference to Figures 5 to 17. Figures 5 to 17 show region 1A on the left side and region 2A on the right side. Note that illustrations and descriptions of a method for manufacturing a high-voltage MOSFET in circuit region C2 shown in Figure 1 will be omitted.

[0050] First, as shown in Figure 5, a semiconductor substrate SB made of single crystal silicon doped with p-type impurities is prepared. Next, by photolithography and ion implantation, a well region PW1 is formed in the semiconductor substrate SB in region 1A, and a well region PW2 is formed in the semiconductor substrate SB in region 2A. The well regions PW1 and PW2 are formed to a predetermined depth from the top surface of the semiconductor substrate SB.

[0051] 6, p-type impurities are implanted into the semiconductor substrate SB by ion implantation to form a channel region CH, which is a p-type semiconductor region, in the semiconductor substrate SB in the regions 1A and 2A. The depth of the channel region CH is shallower than the depths of the well regions PW1 and PW2.

[0052] Next, a gate insulating film IF1 is formed on the semiconductor substrate SB in regions 1A and 2A by thermal oxidation. Next, nitrogen is introduced into the gate insulating film IF1 by DPN (Decoupled Plasma Nitridation). The power (energy) used in the nitrogen introduction by DPN (plasma nitridation) here is, for example, 200 W or more and 300 W or less.

[0053] Next, as shown in FIG. 7, a protective film PVF is formed on the gate insulating film IF1 in region 2A, and the gate insulating film IF1 formed in region 1A is selectively removed. First, a protective film PVF is formed on the gate insulating film IF1 formed in region 1A and region 2A by, for example, a CVD (Chemical Vapor Deposition) method. The protective film PVF is, for example, a polycrystalline silicon film. The thickness of the protective film PVF is, for example, 20 nm or more and 50 nm or less. Next, a resist pattern RP1 that opens region 1A is formed on the protective film PVF. Next, an etching process is performed using the resist pattern RP1 as a mask, thereby selectively removing the protective film PVF and gate insulating film IF1 formed in region 1A. After the etching process, the protective film PVF and gate insulating film IF1 remain on the semiconductor substrate SB in region 2A.

[0054] Here, when the protective film PVF is a polycrystalline silicon film, the etching process is performed by dry etching. The etching process for the gate insulating film IF1 is performed by wet etching using a solution containing hydrofluoric acid, for example.

[0055] 8, a paraelectric film IL1 is formed on the semiconductor substrate SB in the region 1A by, for example, thermal oxidation. The paraelectric film IL1 is made of, for example, a silicon oxide film.

[0056] Next, as shown in FIG. 9, the resist pattern RP1 is removed by ashing. Next, a resist pattern (not shown) that opens the region 2A and a part of the region 1A is formed on the paraelectric film IL1. The resist pattern covers the region in the region 1A where the select transistor SQ is to be formed and exposes the region where the memory transistor MQ is to be formed. Next, an etching process is performed using the resist pattern as a mask to remove the paraelectric film IL1 exposed from the resist pattern, exposing the upper surface of the semiconductor substrate SB. Next, the resist pattern is removed by ashing to expose the paraelectric film IL1. Next, a paraelectric film IL2 is formed on the semiconductor substrate SB exposed from the paraelectric film IL1 in the region 1A by, for example, thermal oxidation. The thickness of the paraelectric film IL2 is smaller than both the thickness of the paraelectric film IL1 and the thickness of the gate insulating film IF1. In this way, the paraelectric film IL1 and the paraelectric film IL2 having different thicknesses are formed in the region 1A.

[0057] Next, as shown in FIG. 10 , nitrogen is introduced into the paraelectric films IL1 and IL2 using the DPN method. The power used for introducing nitrogen by the DPN method here is, for example, 90 W or more and 300 W or less. However, the power used for the plasma nitridation of the paraelectric films IL1 and IL2 here is greater than the power used for the plasma nitridation of the gate insulating film IF1 described with reference to FIG. 6 . In this manner, in this embodiment, the amount of nitrogen introduced into the paraelectric films IL1 and IL2 is greater than the amount of nitrogen introduced into the gate insulating film IF1 described with reference to FIG. 6 . This is because an excessively large amount of nitrogen introduced into the gate insulating film IF1 reduces the electron mobility in the low-voltage MOSFET 1Q. Specifically, if the power used for the plasma nitridation in the process described with reference to FIG. 6 is made equal to the power for the plasma nitridation described with reference to FIG. 10 , nitrogen is more likely to pass through the gate insulating film IF1 and reach the upper surface of the semiconductor substrate SB. As a result, the upper surface of the semiconductor substrate SB is damaged and the electron mobility decreases, so it is necessary to suppress the amount of nitrogen introduced into the gate insulating film IF1.

[0058] In contrast, considering the decrease in the electric field applied to the ferroelectric film FE (see FIG. 3) due to the increase in the thickness of the paraelectric film IL2 and the decrease in the threshold voltage shift width, the power used in the plasma nitridation described with reference to FIG. 10 is preferably smaller than the power used in the plasma nitridation described with reference to FIG. 6. The threshold voltage shift width is the width of the hysteresis loop shown by the drain current versus gate voltage characteristics (current-voltage characteristics) in the select transistor SQ. The current-voltage curve measured by increasing the gate voltage from negative to positive and the current-voltage curve measured by decreasing the gate voltage from positive to negative show different loci. In other words, these current-voltage curves form a hysteresis loop. This shows that the threshold voltage of the select transistor SQ differs when the gate voltage is increased from negative to positive and when it is decreased from positive to negative. The difference between these threshold voltages is the threshold voltage shift width (memory window).

[0059] Next, as shown in FIG. 11, an amorphous film is formed on the protective film PVF formed in the region 2A and on the paraelectric films IL1 and IL2 formed in the region 1A. The amorphous film can be formed by, for example, ALD (Atomic Layer Deposition). The amorphous film is composed of, for example, a material containing a metal oxide and a first element. The metal oxide is, for example, hafnium oxide (HfO2) or gallium oxide (Ga2O3). The first element is, for example, zirconium (Zr). Instead of zirconium, the first element may be silicon (Si), nitrogen (N), yttrium (Y), germanium (Ge), lanthanum (La), or ytterbium (Yb).

[0060] Next, a metal film MF is formed on the amorphous film formed in the region 1A and the region 2A by, for example, a CVD method.

[0061] Next, the amorphous film is crystallized by heat treatment to form a ferroelectric film FE. The heat treatment is performed at a temperature of 600°C or less by RTA (Rapid Thermal Annealing). The heat treatment may be performed using microwaves with a frequency of 1 GHz or more and 10 GHz or less, or may be performed using microwaves with a frequency of 2.45 GHz. Heat treatment using microwaves allows crystallization at a lower temperature than lamp heating treatment, and may be performed at a temperature of 400°C or less, for example.

[0062] In addition, in this crystallization process, the orientation of the ferroelectric film FE is controlled by the stress from the metal film MF. That is, when the amorphous film is crystallized into the ferroelectric film FE, the metal film MF has the function of orienting the crystalline phase of the ferroelectric film FE in a rectangular crystal.

[0063] 12, a resist pattern RP2 that opens the region 2A is formed on the metal film MF formed in the region 1A. Next, a dry etching process is performed using the resist pattern RP2 as a mask. As a result, the metal film MF and the ferroelectric film FE formed in the region 2A are selectively removed.

[0064] Next, as shown in FIG. 13, the resist pattern RP2 is removed by ashing. Next, a conductive film CF is formed on the metal film MF formed in region 1A and on the protective film PVF formed in region 2A, for example, by CVD. The conductive film CF is, for example, a polycrystalline silicon film doped with n-type impurities. The thickness of the conductive film CF is, for example, 95 nm. In FIG. 13, the protective film PVF and the polycrystalline silicon film formed on the protective film PVF are integrated and shown as the conductive film CF. The polycrystalline silicon film may be formed by forming an amorphous film and then crystallizing the amorphous film by heat treatment. Next, n-type impurities are implanted into the conductive film CF by ion implantation.

[0065] Next, as shown in FIG. 14, an insulating film IF2 is formed on the conductive film CF by, for example, a CVD method. The insulating film IF2 is made of, for example, a silicon nitride film. Next, the insulating film IF2 is patterned by performing a dry etching process using a resist pattern (not shown) as a mask. This removes a portion of the insulating film IF2 in region 1A and a portion of the insulating film IF2 in region 2A, exposing the upper surface of a portion of the conductive film CF. Next, the resist pattern is removed by ashing, and then a dry etching process is performed using the insulating film IF2 as a mask to remove a portion of the conductive film CF.

[0066] In this way, by patterning the conductive film CF, a select gate electrode SG is formed on the metal film MF in the region 1A, a memory gate electrode MG is formed on the metal film MF in the region 1A, and a gate electrode GE is formed on the gate insulating film IF1 in the region 2A. The select gate electrode SG is formed at a position overlapping with the paraelectric film IL1 in a planar view, and the memory gate electrode MG is formed at a position overlapping with the paraelectric film IL2 in a planar view.

[0067] Next, as shown in FIG. 15, a resist pattern RP3 is formed to cover the semiconductor substrate SB, gate insulating film IF1, and gate electrode GE in region 2A and to open region 1A. Next, a dry etching process is performed with the gate electrode GE, semiconductor substrate SB, and gate insulating film IF1 in region 2A covered with the resist pattern RP3. That is, the metal film MF and ferroelectric film FE exposed from the select gate electrode SG and memory gate electrode MG in region 1A are removed. At this time, the thicknesses of the paraelectric films IL1 and IL2 in region 1A are reduced by the dry etching process. As a result, the semiconductor substrate SB may or may not be exposed. Here, a case where the semiconductor substrate SB is exposed will be described.

[0068] 16, the resist pattern RP3 is removed by ashing. Next, low-concentration regions LDD are formed by ion implantation in the semiconductor substrate SB exposed from the gate electrode GE, the select gate electrode SG, and the memory gate electrode MG.

[0069] 17, a stacked film including, for example, a silicon oxide film and a silicon nitride film is formed on the insulating film IF2 and the semiconductor substrate SB by, for example, a CVD method so as to cover the gate electrode GE, the select gate electrode SG, and the memory gate electrode MG. Next, the silicon oxide film and the silicon nitride film are processed by an anisotropic etching process. As a result, sidewall spacers SW made of the stacked film are formed on the side surfaces of the gate electrode GE, the select gate electrode SG, and the memory gate electrode MG.

[0070] Next, in the semiconductor substrate SB exposed from the sidewall spacers SW in the regions 1A and 2A, a diffusion region ND, a source region MS, and a drain region MD are formed by photolithography and ion implantation. In the region 1A, the diffusion region ND, the source region MS, and the drain region MD are formed in the well region PW1. In the region 2A, the source region MS and the drain region MD are formed in the well region PW2. Here, the source region MS and the drain region MD are formed in the semiconductor substrate SB so that the select gate electrode SG and the memory gate electrode MG are disposed between the source region MS and the drain region MD in a plan view.

[0071] Thereafter, if necessary, a silicide layer may be formed on the gate electrode GE, the select gate electrode SG, the memory gate electrode MG, the diffusion region ND, the source region MS, and the drain region MD. The silicide layer can be formed by salicide (Self Aligned Silicide) technology and is made of, for example, cobalt silicide, nickel silicide, or nickel platinum silicide. In this manner, a semiconductor device including a low-voltage MOSFET 1Q and a ferroelectric memory cell MC is manufactured.

[0072] <Effects of this embodiment> 25 and 26 are cross-sectional views of a main part of a semiconductor device according to a comparative example.

[0073] 25 and 26, in the semiconductor device according to the comparative example, a paraelectric film ILA, a ferroelectric film FE, and a metal film MF are formed in this order on a semiconductor substrate SB. However, this example differs from the present embodiment in that nitrogen is not introduced into the paraelectric film ILA.

[0074] As shown in Fig. 25, during the manufacturing process of the ferroelectric memory cell, the ferroelectric film FE contains oxygen OX. As shown in Fig. 26, this oxygen OX migrates toward the semiconductor substrate SB due to heat treatment performed during the manufacturing process of the semiconductor device. The heat treatment is, for example, heat treatment performed when forming a gate electrode or heat treatment performed when forming a source region and a drain region. The migrated oxygen OX reacts with silicon on the surface of the semiconductor substrate SB, and an oxide film IFA is formed as shown in Fig. 26.

[0075] In this case, oxygen vacancies OH are generated in the ferroelectric film FE where oxygen OX was previously present. The oxygen vacancies OH degrade the performance and reliability of the ferroelectric film FE. Furthermore, the formation of the oxide film IFA due to the migration of oxygen OX means an increase in the thickness of the paraelectric film between the ferroelectric film FE and the semiconductor substrate SB, which causes variations in the characteristics of the ferroelectric memory cells. Therefore, in the semiconductor device of the comparative example, the diffusion of oxygen OX from the ferroelectric film FE may degrade the performance and reliability of the semiconductor device.

[0076] Therefore, in this embodiment, nitrogen is introduced into each of the paraelectric film IL1 and the paraelectric film IL2. Fig. 18 shows a cross-sectional view of a main part of the semiconductor device of this embodiment. Fig. 19 shows a graph of the concentration distribution of nitrogen in the depth direction when nitrogen (N) is introduced into the insulating film by the DPN method. The horizontal axis of Fig. 19 represents the depth from the top surface of the insulating film, and the vertical axis represents the nitrogen concentration.

[0077] As shown in FIG. 19, the concentration of nitrogen introduced into the insulating film by the DPN method is highest near the upper surface of the insulating film and decreases from the upper surface toward the lower surface of the insulating film. As shown in FIG. 18, high-concentration regions NR into which nitrogen has been introduced are formed in the paraelectric films IL1 and IL2 of this embodiment. The high-concentration regions NR are formed near the upper surfaces of the paraelectric films IL1 and IL2, respectively. The nitrogen concentration in the paraelectric film IL1 decreases from the upper surface of the paraelectric film IL1 toward the lower surface of the paraelectric film IL1. Here, the thickness of the paraelectric film IL2 is, for example, 1 nm or more and 2 nm or less. Therefore, the nitrogen concentration in the paraelectric film IL2 does not decrease toward the lower surface of the paraelectric film IL2, and only the high-concentration regions NR are formed. However, the nitrogen concentration in the paraelectric film IL2 may decrease from the upper surface of the paraelectric film IL2 toward the lower surface of the paraelectric film IL2. Nitrogen is introduced into the upper surfaces of the paraelectric films IL1 and IL2 under the same conditions, and the thickness of the paraelectric film IL2 is smaller than that of the paraelectric film IL1. Therefore, the nitrogen concentration in the paraelectric film IL1 near the lower surface of the paraelectric film IL1 is lower than the nitrogen concentration in the paraelectric film IL2 near the lower surface of the paraelectric film IL2.

[0078] In this embodiment, by introducing nitrogen into each of the paraelectric films IL1 and IL2, oxygen OX in the ferroelectric film FE can be prevented from diffusing into the paraelectric films IL1 and IL2. In particular, by forming high-concentration regions NR containing nitrogen near the upper surfaces of each of the paraelectric films IL1 and IL2, the high-concentration regions NR act as barriers to the movement of oxygen OX, effectively preventing the diffusion of oxygen OX. Therefore, an increase in the thickness of the paraelectric film due to the diffusion of oxygen OX can be prevented. As a result, variations in the characteristics of the ferroelectric memory cells MC can be prevented. Furthermore, since the generation of oxygen vacancies OH can be prevented, the characteristics of the ferroelectric film FE can be stabilized. Therefore, the performance and reliability of the semiconductor device can be improved.

[0079] In this embodiment, nitrogen is introduced into the paraelectric film IL2, and an increase in the thickness of the paraelectric film IL2 is prevented, thereby reducing the threshold voltage of the memory transistor MQ, and as a result, the current characteristics of the memory transistor MQ can be improved.

[0080] Fig. 20 is a graph showing the current-voltage characteristics of a memory transistor. The horizontal axis of the graph shown in Fig. 20 represents the voltage applied to the memory gate electrode MG, and the vertical axis represents the current flowing through the ferroelectric memory cell MC. Fig. 20 shows a graph in which the power used in the DPN method to introduce nitrogen into the paraelectric film IL1 and the paraelectric film IL2 is 90 W, 200 W, and 300 W. As shown in Fig. 20, the current-voltage characteristics of the memory transistor MQ can be improved by increasing the power used in the plasma nitridation.

[0081] Furthermore, since the thickness of the paraelectric film IL1 is greater than that of the paraelectric film IL2, the introduction of nitrogen has little effect on the characteristics of the select transistor SQ. If the nitrogen introduced into the paraelectric film IL1 reaches the upper surface of the semiconductor substrate SB, damage or defects may occur on the upper surface of the semiconductor substrate SB, scattering electrons and reducing electron mobility, which may result in a decrease in the on-current of the select transistor SQ. In this embodiment, since the thickness of the paraelectric film IL1 is greater than that of the paraelectric film IL2, the nitrogen introduced into the paraelectric film IL1 is prevented from reaching the upper surface of the semiconductor substrate SB. This prevents a decrease in the current characteristics of the select transistor SQ. On the other hand, since the current flowing through the memory transistor MQ is smaller than the current flowing through the select transistor SQ, the nitrogen introduced into the paraelectric film IL2 has little effect on the current characteristics of the memory transistor MQ.

[0082] <Modification> In the present embodiment, as shown in FIG. 2, the channel region CH is formed under the memory gate electrode MG, but the channel region CH does not necessarily have to be formed.

[0083] FIG. 21 shows a cross-sectional view of a semiconductor device according to this modification. The semiconductor device according to this modification differs from the present embodiment in that a channel region CH is formed below the select gate electrode SG, but no channel region CH is formed below the memory gate electrode MG. Here, no channel region CH is formed in the semiconductor substrate SB within region 2A. Therefore, the impurity concentration of the portion of the semiconductor substrate SB located directly below the select gate electrode SG is higher than the impurity concentration of the portion of the semiconductor substrate SB located directly below the memory gate electrode MG. In other words, the impurity concentration in the channel region CH is higher than the impurity concentration in the portion of the well region PW1 located directly below the second stack and between the source region MS and the drain region MD.

[0084] FIG. 22 shows a cross-sectional view of a semiconductor device during a manufacturing process of the modified example. The process shown in FIG. 22 corresponds to the process of forming a channel region CH among the processes described with reference to FIG. 6. In the manufacturing process of the semiconductor device of the modified example, after the process described with reference to FIG. 5, a resist pattern RP4 is formed to cover the semiconductor substrate SB in region 2A and to open a portion of region 1A, as shown in FIG. 22. Here, the portion of region 1A where the resist pattern RP4 opens is a region where a select transistor SQ will later be formed. Furthermore, the other portion of region 1A covered by the resist pattern RP4 is a region where a memory transistor MQ will later be formed. Furthermore, although the resist pattern RP4 also covers the semiconductor substrate SB in region 2A here, the resist pattern RP4 may also expose the semiconductor substrate SB in region 2A.

[0085] Next, using the resist pattern RP4 as a mask, p-type impurities are implanted into the semiconductor substrate SB by ion implantation. This forms a channel region CH in the semiconductor substrate SB in the region 1A exposed by the resist pattern RP4. At this time, no channel region is formed in the semiconductor substrate SB in the region 1A covered by the resist pattern RP4.

[0086] Thereafter, the resist pattern RP4 is removed by ashing. Next, as explained using FIG. 6, a gate insulating film IF1 is formed by thermal oxidation, and plasma nitridation is performed on the gate insulating film IF1. The subsequent steps are the same as those explained using FIG. 7 to FIG. 17. In the step explained using FIG. 9, a paraelectric film IL1 is formed on the channel region CH, and a paraelectric film IL2 is formed on the well region PW1 so as not to overlap with the channel region CH. This makes it possible to manufacture the ferroelectric memory cell MC shown in FIG. 21. That is, it is possible to form a memory transistor MQ that does not have a channel region CH.

[0087] In the memory transistor of a ferroelectric memory cell, electrons may be trapped at the interface between the ferroelectric film and the metal film on the ferroelectric film. The threshold voltage of the memory transistor is higher than that of a low-voltage MOSFET formed in the circuit region C1 (see FIG. 1), for example, and the amount of electrons in the semiconductor substrate is likely to be less than when the memory transistor has a channel region. In this state, electrons in the semiconductor substrate are further trapped in the ferroelectric film, reducing the mobility of electrons in the semiconductor substrate. In other words, the charge in the channel of the memory transistor decreases, making it difficult for current to flow.

[0088] Here, whether or not a channel region is formed under the memory gate electrode does not affect the polarization state and trapped charge density in the ferroelectric film of the memory transistor, i.e., the polarization state and trapped charge density in the ferroelectric film are not affected by either the dose of p-type impurities in the channel region or the threshold voltage of the memory transistor.

[0089] Therefore, by reducing the dose of p-type impurities, the threshold voltage of the memory transistor can be reduced without changing the polarization state and trapped charge density in the ferroelectric film. In other words, reducing the dose of p-type impurities increases the inversion charge density in the semiconductor substrate.

[0090] In this modification, the channel region CH of the memory transistor MQ is not formed, thereby reducing the threshold voltage of the memory transistor MQ. This improves the current characteristics of the memory transistor MQ. Compared to when the channel region CH is formed, the amount of electrons in the semiconductor substrate SB is greater in this modification, so high electron mobility can be achieved even if electrons are trapped in the ferroelectric film FE due to polarization.

[0091] FIG. 23 is a graph showing the current-voltage characteristics of a memory transistor that has undergone channel dosing. FIG. 24 is a graph showing the current-voltage characteristics of a memory transistor that has not undergone channel dosing. In each of the graphs in FIGS. 23 and 24, the horizontal axis indicates the gate voltage applied to the memory gate electrode MG, and the vertical axis indicates the current flowing through the ferroelectric memory cell MC. In FIGS. 23 and 24, the off-current is indicated by a triangular plot, and the on-current is indicated by a circular plot. The plots in FIGS. 23 and 24 show data measured under the same conditions for the gate length, gate width, and drain voltage of the memory transistor. Comparing FIGS. 23 and 24, it can be seen that the on-current increases when the memory transistor MQ is not channel-dosed and no channel region CH is formed.

[0092] Therefore, in this modification, the threshold voltage of the memory transistor is reduced to lower the resistance of the memory transistor, thereby improving the current characteristics of the memory transistor.

[0093] Furthermore, in this modification, the presence or absence of the channel region CH in the memory transistor MQ does not affect the characteristics of the select transistor SQ. That is, in this modification, the characteristics of the memory transistor MQ can be improved while suppressing the effect on the characteristics of the select transistor SQ.

[0094] The present invention has been specifically described above based on the form for implementing the present invention, but the present invention is not limited to the above-described embodiment and can be modified in various ways without departing from the spirit of the present invention.

[0095] 17, for example, a channel region, a source region, and a drain region are formed in a semiconductor substrate in region 2A. Alternatively, an SOI (Silicon On Insulator) substrate having a semiconductor substrate, a buried oxide film formed on the semiconductor substrate, and a semiconductor layer formed on the buried oxide film may be used as the substrate. When an SOI substrate is used, the channel region, the source region, and the drain region are formed in the semiconductor layer of the SOI substrate in region 2A.

[0096] In the above embodiment, the selection transistor, memory transistor, and low-voltage MOSFET are n-channel MOSFETs, but each MOSFET may be a p-channel MOSFET. [Explanation of symbols]

[0097] 1Q low voltage MOSFET 100 Semiconductor device CH channel region FE ferroelectric film GE gate electrode IL1, IL2, ILA Paraelectric films LDD low concentration area MC ferroelectric memory cell MD drain region MF metal film MG memory gate electrode MQ memory transistor MS source region ND diffusion area PW1, PW2 well regions SB semiconductor substrate SG Select gate electrode SQ Select Transistor

Claims

1. a semiconductor substrate; a first source region of a first conductivity type formed in the semiconductor substrate; a first drain region of the first conductivity type formed in the semiconductor substrate; a first stacked body formed on the semiconductor substrate and disposed between the first source region and the first drain region in a plan view; a second stacked body formed on the semiconductor substrate and disposed between the first source region and the first drain region in a plan view; Equipped with The first laminate is a first paraelectric film formed on the semiconductor substrate; a first ferroelectric film formed on the first paraelectric film; a first gate electrode formed on the first ferroelectric film; and The second laminate is a second paraelectric film formed on the semiconductor substrate; a second ferroelectric film formed on the second paraelectric film; a second gate electrode formed on the second ferroelectric film; and the first stacked body, the second stacked body, the first source region, and the first drain region constitute a nonvolatile memory cell; the thickness of the first paraelectric film is greater than the thickness of the second paraelectric film, each of the first paraelectric film and the second paraelectric film contains nitrogen; a nitrogen concentration in the first paraelectric film decreases from an upper surface of the first paraelectric film toward a lower surface of the first paraelectric film.

2. 2. The semiconductor device according to claim 1, the first paraelectric film and the second paraelectric film are each a silicon oxide film containing nitrogen.

3. 2. The semiconductor device according to claim 1, a first semiconductor region of a second conductivity type different from the first conductivity type formed in the semiconductor substrate; a second semiconductor region of the second conductivity type disposed between the first source region and the first drain region, located directly below the first stacked body, and having a predetermined depth from the top surface of the first semiconductor region; and the first source region and the first drain region are formed in the first semiconductor region; a semiconductor device in which the impurity concentration in the second semiconductor region is higher than the impurity concentration in a portion of the first semiconductor region that is located directly below the second stack and between the first source region and the first drain region;

4. 2. The semiconductor device according to claim 1, a second source region formed in the semiconductor substrate; a second drain region formed in the semiconductor substrate; a gate insulating film formed on the semiconductor substrate and disposed between the second source region and the drain region in a plan view; a third gate electrode formed on the gate insulating film; Equipped with the second source region, the second drain region, the gate insulating film, and the third gate electrode constitute a transistor, the gate insulating film contains nitrogen, The semiconductor device, wherein the nitrogen concentration in the gate insulating film is lower than the nitrogen concentration in the second paraelectric film.

5. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the first ferroelectric film and the second ferroelectric film each contain hafnium oxide.

6. (a) forming a first paraelectric film on a semiconductor substrate; (b) after the step (a), forming a second paraelectric film on the semiconductor substrate, the second paraelectric film having a thickness smaller than that of the first paraelectric film; (c) introducing nitrogen into each of the first paraelectric film and the second paraelectric film by using a plasma nitridation method; (d) forming a first ferroelectric film and a first gate electrode in this order on the first paraelectric film, and forming a second ferroelectric film and a second gate electrode in this order on the second paraelectric film; (e) forming the first source region and the first drain region in the semiconductor substrate such that the first gate electrode and the second gate electrode are disposed between a first source region of a first conductivity type and a first drain region of the first conductivity type in a plan view; The method for manufacturing a semiconductor device includes the steps of:

7. 7. The method for manufacturing a semiconductor device according to claim 6, A method for manufacturing a semiconductor device, wherein a nitrogen concentration in the first paraelectric film decreases from an upper surface of the first paraelectric film toward a lower surface of the first paraelectric film.

8. 7. The method for manufacturing a semiconductor device according to claim 6, The method for manufacturing a semiconductor device, wherein each of the first paraelectric film and the second paraelectric film is a silicon oxide film containing nitrogen.

9. 7. The method for manufacturing a semiconductor device according to claim 6, (a1) before the step (a), forming a first semiconductor region of a second conductivity type different from the first conductivity type in the semiconductor substrate; (a2) before the step (a), forming a second semiconductor region of the second conductivity type having an impurity concentration higher than that of the first semiconductor region in a state in which a portion of the semiconductor substrate on which the second paraelectric film is to be formed is covered with a protective film, within the first semiconductor region; (a3) removing the protective film before the step (a); and In the step (a), the first paraelectric film is formed on the second semiconductor region; In the step (b), the second paraelectric film is formed on the first semiconductor region so as not to overlap with the second semiconductor region; In the step (e), the first source region and the first drain region are formed in the first semiconductor region. A method for manufacturing a semiconductor device.

10. 7. The method for manufacturing a semiconductor device according to claim 6, (a4) forming an insulating film on the semiconductor substrate before the step (a); (a5) before the step (a), introducing nitrogen into the insulating film by using a plasma nitridation method; and A method for manufacturing a semiconductor device, wherein the power used in the plasma nitridation method in the step (a5) is lower than the power used in the plasma nitridation method in the step (c).

11. 11. The method for manufacturing a semiconductor device according to claim 10, In the step (d), a third gate electrode is formed on the insulating film; In the step (e), the second source region and the second drain region are formed in the semiconductor substrate so that the third gate electrode is positioned between the second source region of the first conductivity type and the second drain region of the first conductivity type in a planar view.

12. 7. The method for manufacturing a semiconductor device according to claim 6, The method for manufacturing a semiconductor device, wherein the first ferroelectric film and the second ferroelectric film each contain hafnium oxide.

Images