Semiconductor device

Abstract

To obtain a semiconductor device whose lead time is at the same level as that of a general high frequency device and which can be manufactured without requiring a special process.SOLUTION: The semiconductor device 100 includes the highly radiative multilayer substrate 1, the package substrate 2, and the resin mold 4, and on the component mounting surface 11 of the highly radiative multilayer substrate 1, a plurality of first ground pads 114 are provided and arranged in an annular shape, and inside the ring of the first ground pads 114, the first signal pattern 111, the first signal pad 112, and the first ground pattern 113 are arranged and the semiconductor chip 15 is die-bonded. The first ground pad 114 and the second ground pad 214 are electrically connected via the first conductive member 3a, and the first signal pad 112 and the second signal pad 212 are electrically connected via the second conductive member 3b.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device in which an electrical interface and a thermal interface are provided on different surfaces. [Background technology]

[0002] In wireless communication equipment such as MIMO (Multiple-Input and Multiple-Output) systems used in mobile communication base stations, and AESA (Active Electronically Scanned Array) radar or active phased array radar, multiple radiating elements must be arranged at high density.

[0003] In these wireless communication devices, high frequency devices, which are semiconductor devices that perform power amplification of high frequency signals, must be arranged at high density, just like radiating elements, and therefore miniaturization is required.

[0004] The spacing between radiating elements is determined by the frequency of the electromagnetic waves emitted by the radiating elements, so the higher the frequency of the radiated electromagnetic waves, the more densely the radiating elements must be arranged.The high-frequency devices must also be arranged at a high density to match the density of the radiating elements.

[0005] When the distance between high-frequency devices becomes narrow, unwanted radiation of high-frequency signals generated by the high-frequency devices can degrade the performance of adjacent high-frequency devices. For this reason, it is desirable to provide electromagnetic shielding for high-frequency devices at the package level.

[0006] Patent Document 1 discloses a high-frequency device that has been made smaller without impairing heat dissipation by separating the electrical interface and the thermal interface on different surfaces. The high-frequency device disclosed in Patent Document 1 has a package surface covered with a conductive film that is connected to ground, and has an electromagnetic shield at the package level. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] International Publication No. 2023 / 127091 Summary of the Invention [Problem to be solved by the invention]

[0008] However, the high-frequency device disclosed in Patent Document 1 requires many special processes to form a conductive film on the package surface, making the manufacturing process complicated. As a result, the high-frequency device disclosed in Patent Document 1 has a problem in that the lead time is longer than that of general high-frequency devices.

[0009] The present disclosure has been made in consideration of the above, and aims to obtain a semiconductor device that has a lead time at the same level as that of a general high-frequency device and can be manufactured without requiring any special processes. [Means for solving the problem]

[0010] In order to solve the above-mentioned problems and achieve the object, the semiconductor device according to the present disclosure includes: a high heat dissipation multilayer substrate including: a component mounting surface having a first signal pattern, a first signal pad electrically connected to the first signal pattern, a first ground pattern, and a first ground pad; and a ground surface having a solid ground, wherein the first ground pattern and the first ground pad are electrically connected to the solid ground by a first ground via; an electrode surface having a ground electrode and a signal electrode; and a component mounting surface having a second signal pattern, a second signal pad, a second ground pattern, and a second ground pad, wherein the second signal pad and the signal electrode are electrically connected by the signal via, and the second ground pad, the second ground pattern, and the ground electrode are electrically connected by the second ground via; and a resin mold filled in side surfaces of the high heat dissipation multilayer substrate and in a space between the component mounting surface of the high heat dissipation multilayer substrate and the component mounting surface of the package substrate. A plurality of first ground pads are provided and arranged in a ring on the component mounting surface of the high heat dissipation multilayer substrate, and a first signal pattern, a first signal pad, and a first ground pattern are arranged inside the ring of the first ground pads, and a semiconductor chip is die-bonded to the first ground pad. The signal terminal of the semiconductor chip is electrically connected to the first signal pattern, and the ground terminal of the semiconductor chip is electrically connected to the first ground pattern. The first ground pad and the second ground pad are electrically connected via a first conductive member, and the first signal pad and the second signal pad are electrically connected via a second conductive member. [Effects of the Invention]

[0011] According to the present disclosure, it is possible to obtain a semiconductor device that can be manufactured in a lead time that is the same as that of a general high-frequency device and that does not require any special process. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a cross-sectional view perpendicular to the stacking direction of a substrate of a semiconductor device according to a first embodiment; [Figure 2]1 is a cross-sectional view of a semiconductor device according to a first embodiment, taken along a plane parallel to a stacking direction of a substrate; [Figure 3] 1 is a flowchart of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 4] 10 is a cross-sectional view perpendicular to the stacking direction of the substrate of the semiconductor device according to the second embodiment. [Figure 5] 10 is a cross-sectional view parallel to the stacking direction of the substrate of the semiconductor device according to the second embodiment. [Figure 6] 10 is a flowchart of a method for manufacturing a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Semiconductor devices according to embodiments will be described in detail below with reference to the drawings.

[0014] Embodiment 1 FIG. 1 is a cross-sectional view perpendicular to the stacking direction of the substrates of the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view parallel to the stacking direction of the substrates of the semiconductor device according to the first embodiment. FIG. 1 shows a cross-section taken along line II in FIG. 2, and FIG. 2 shows a cross-section taken along line II-II in FIG. 1. The semiconductor device 100 according to the first embodiment includes a high heat dissipation multilayer substrate 1, a package substrate 2, solder balls 3 that electrically connect the high heat dissipation multilayer substrate 1 and the package substrate 2, and a resin mold 4 that seals the high heat dissipation multilayer substrate 1, the package substrate 2, and the solder balls 3. Examples of wireless communication devices that include the substrate of the semiconductor device 100 according to the first embodiment include a MIMO system, an AESA radar, or an active phased array radar, but the semiconductor device 100 can also be applied to wireless communication devices other than the examples.

[0015] The high heat dissipation multilayer substrate 1 has a component mounting surface 11 and a ground surface 12. A first signal pattern 111, a first signal pad 112, a first ground pattern 113, and a first ground pad 114 are arranged on the component mounting surface 11 of the high heat dissipation multilayer substrate 1. A solid ground 121 is arranged on the ground surface 12 of the high heat dissipation multilayer substrate 1.

[0016] The first ground pattern 113 and the first ground pad 114 are electrically connected to the solid ground 121 by the first ground via 14. The semiconductor chip 15 is mounted on the component mounting surface 11 of the high heat dissipation multilayer substrate 1 by a die bond material 16. The signal terminal of the semiconductor chip 15 is electrically connected to the first signal pattern 111 via the die bond material 16. The ground terminal of the semiconductor chip 15 is electrically connected to the first ground pattern 113 via the die bond material 16. A plurality of first ground pads 114 are arranged on the outer periphery of the component mounting surface 11 of the high heat dissipation multilayer substrate 1. The first signal pads 112 are arranged inside the first ground pads 114.

[0017] The package substrate 2 has a component mounting surface 21 and an electrode surface 22. A ground electrode 221 and a signal electrode 222 are arranged on the electrode surface 22 of the package substrate 2. The ground electrode 221 is arranged around the signal electrode 222. A second signal pattern 211, a second signal pad 212, a second ground pattern 213, and a second ground pad 214 are arranged on the component mounting surface 21 of the package substrate 2. The second signal pad 212 is electrically connected to the signal electrode 222 through a signal via 24. The second ground pad 214 and the second ground pattern 213 are electrically connected to the ground electrode 221 through a second ground via 25. Surface mount components 26 such as chip capacitors and chip resistors are mounted on the second signal pattern 211 on the component mounting surface 21 by soldering.

[0018] The solder balls 3 include a first conductive member 3a electrically connecting a first ground pad 114 on the component mounting surface 11 of the high heat dissipation multilayer substrate 1 to a second ground pad 214 on the component mounting surface 21 of the package substrate 2, and a second conductive member 3b electrically connecting a first signal pad 112 on the component mounting surface 11 of the high heat dissipation multilayer substrate 1 to a second signal pad 212 on the component mounting surface 21 of the package substrate 2. A resin mold 4 is filled to cover the side surfaces of the high heat dissipation multilayer substrate 1 and the solder balls 3, and the ground surface 12 of the high heat dissipation multilayer substrate 1 and the electrode surface 22 of the package substrate 2 are exposed from the resin mold 4. The solder balls 3 may have a metal core therein. Using solder balls 3 with a metal core therein ensures a gap equal to or larger than the metal core between the high heat dissipation multilayer substrate 1 and the package substrate 2, and also prevents adjacent solder balls 3 from coming into contact with each other due to crushing of the solder balls 3.

[0019] The semiconductor device 100 includes a plurality of ground structures 17 arranged around its periphery, each of which includes a ground electrode 221, a second ground via 25, a second ground pad 214, a first conductive member 3a, a first ground pad 114, and a first ground via 14 arranged in the thickness direction. The ground plane 12 of the high-heat-dissipation multilayer substrate 1 includes a solid ground 121. Therefore, by making the dimensions of the gaps between the first conductive members 3a on the periphery and the gaps between the ground electrodes 221 on the periphery of the signal electrodes 222 equal to or less than half the wavelength of the operating frequency, the signal path is surrounded by ground at the package level, preventing unwanted waves from radiating from the signal path from leaking outside the package. This provides the semiconductor device 100 with electromagnetic shielding at the package level. The electromagnetic shielding of the semiconductor device 100 can be improved by reducing the gaps between the first conductive members 3a and the gaps between the ground electrodes 221 on the periphery of the signal electrodes 222. Furthermore, because the ground surface 12 of the high heat dissipation multilayer substrate 1 is exposed, the semiconductor device 100 has a heat dissipation function from the ground surface 12 of the high heat dissipation multilayer substrate 1. For example, by thermally connecting an external heat dissipation mechanism such as a heat sink to the ground surface 12 of the high heat dissipation multilayer substrate 1, heat generated in the semiconductor chip 15 is transferred to the external heat dissipation mechanism via the die bond material 16 and the high heat dissipation multilayer substrate 1, thereby providing good heat dissipation performance.

[0020] An example of a material for the high heat dissipation multilayer substrate 1 is aluminum nitride (AlN). Aluminum nitride has a thermal conductivity of 150 W / (m·K) or more, and a linear expansion coefficient of 4.5 ppm / K, which is close to the linear expansion coefficient of a typical semiconductor chip 15. Therefore, using aluminum nitride as the material for the high heat dissipation multilayer substrate 1 can improve mechanical reliability. Generally, the linear expansion coefficient of a semiconductor chip 15 based on silicon is 3.0 ppm / K, the linear expansion coefficient of a semiconductor chip 15 based on gallium arsenide is 5.9 ppm / K, and the linear expansion coefficient of a semiconductor chip 15 based on silicon carbide is 3.1 ppm / K.

[0021] Next, a description will be given of a method for manufacturing the semiconductor device 100. Fig. 3 is a flowchart of the method for manufacturing the semiconductor device according to embodiment 1. The method for manufacturing the semiconductor device 100 according to embodiment 1 includes a die bond cure step, a solder printing step, a mounting step, a reflow cleaning step, a molding step, and a singulation step.

[0022] The die bond curing process of step S1 is a process of applying die bond material 16 to component mounting surface 11 of high heat dissipation multilayer substrate 1, mounting semiconductor chip 15, and curing die bond material 16. The solder printing process of step S2 is a process of applying solder material to component mounting surface 21 of package substrate 2. The mounting process of step S3 is a process of mounting surface-mounted components 26, solder balls 3, and high heat dissipation multilayer substrate 1 on component mounting surface 21 of package substrate 2. The reflow cleaning process of step S4 is a process of placing package substrate 2 in a reflow oven to melt the solder material, solder-bonding surface-mounted components 26, solder balls 3, and high heat dissipation multilayer substrate 1, and then washing away flux residue and other contaminants contained in the solder material. The molding process of step S5 is a process of filling a resin molding material into the side surfaces of high heat dissipation multilayer substrate 1 and into the gap between component mounting surface 21 of package substrate 2 and component mounting surface 11 of high heat dissipation multilayer substrate 1. When transfer molding is used as a method for filling the resin molding material, the resin molding material also fills the upper surface of the ground plane 12 of the high heat dissipation multilayer substrate 1, so it is necessary to mask the ground plane 12 by sandwiching an elastic material such as rubber between the mold during molding. Another possible molding method is underfilling. The singulation process in step S6 is a process of cutting the molded package substrate 2 and separating it into individual semiconductor devices 100. Generally, from the perspective of mass production, the package substrate 2 is a multi-panel substrate, and a singulation process is required.

[0023] The semiconductor device 100 according to the first embodiment does not require cutting and shielding processes during manufacturing, thereby enabling a reduction in lead time. Furthermore, the semiconductor device 100 according to the first embodiment does not require special processes such as forming a conductive film on the package surface, making it easy to manufacture. Therefore, the semiconductor device 100 according to the first embodiment has a high yield and can reduce manufacturing costs.

[0024] Although the semiconductor device 100 having one semiconductor chip 15 mounted thereon has been given as an example here, the semiconductor device 100 can also have a configuration in which multiple semiconductor chips 15 are mounted thereon. In the configuration shown in Patent Document 1, the size of the heat spreader is restricted by the dimensions of the semiconductor chip due to constraints imposed by the manufacturing method, so if multiple semiconductor chips are mounted, it may not be possible to ensure the required heat dissipation performance. On the other hand, in the semiconductor device 100 according to the first embodiment, the size of the high heat dissipation multilayer substrate 1 is not restricted by the dimensions of the semiconductor chip 15, so good heat dissipation performance can be ensured even in a configuration in which multiple semiconductor chips 15 are mounted thereon.

[0025] Embodiment 2 FIG. 4 is a cross-sectional view perpendicular to the stacking direction of the substrates of the semiconductor device according to the second embodiment. FIG. 5 is a cross-sectional view parallel to the stacking direction of the substrates of the semiconductor device according to the second embodiment. FIG. 4 shows a cross-section taken along line IV-IV in FIG. 5, and FIG. 5 shows a cross-section taken along line VV in FIG. 4. In the semiconductor device 100 according to the second embodiment, the first signal pad 112 and the second signal pad 212 are solder-joined, and the first ground pad 114 and the second ground pad 214 are solder-joined. As a result, in the semiconductor device 100 according to the second embodiment, the component mounting surface 11 of the high heat dissipation multilayer substrate 1 and the component mounting surface 21 of the package substrate 2 are directly connected by solder.

[0026] The high heat dissipation multilayer substrate 1 has a cavity 18 surrounded by a sidewall 19 on the component mounting surface 11. A semiconductor chip 15 is mounted inside the cavity 18 by die-bonding. A signal terminal of the semiconductor chip 15 is electrically connected to a first signal pattern 111, and a ground terminal of the semiconductor chip 15 is electrically connected to a first ground pattern 113. A first signal pad 112 and a first ground pad 114 are arranged on the sidewall 19. An inner layer ground pattern 19a is provided inside the sidewall 19. A portion of the first signal pattern 111 is also provided inside the sidewall 19. The inner layer ground pattern 19a and the first ground pad 114 are electrically connected by a third ground via 13b.

[0027] The portion of the first signal pattern 111 provided inside the side wall 19 of the cavity 18 is electrically connected to the first signal pad 112 by the signal via 13a. The solid ground 121 and the first ground pad 114 are electrically connected via the first ground via 14, the inner layer ground pattern 19a, and the third ground via 13b. The first ground pad 114 is disposed on the outer periphery of the first signal pad 112. The high heat dissipation multilayer substrate 1 and the package substrate 2 are made of a ceramic material with excellent airtightness.

[0028] A plurality of ground structures 17 are arranged on the periphery of the semiconductor device 100, each of which includes a ground electrode 221, a second ground via 25, a second ground pad 214, a first ground pad 114, a third ground via 13b, an inner-layer ground pattern 19a, and a first ground via 14 connected in the thickness direction. A solid ground 121 is arranged on the ground surface 12 of the high heat-dissipation multilayer substrate 1. Therefore, by setting the dimensions of the gap between the first ground pad 114 and the second ground pad 214 on the periphery and the gap between the ground electrodes 221 on the periphery of the signal electrode 222 to be equal to or less than half the wavelength of the operating frequency, the signal path is surrounded by ground at the package level, and unwanted waves radiated from the signal path are less likely to leak out of the package.

[0029] 6 is a flowchart of a method for manufacturing a semiconductor device according to embodiment 2. The method for manufacturing semiconductor device 100 according to embodiment 2 includes a die bond cure step S1, a solder printing step S2, a mounting step S3, a reflow cleaning step S4, and a singulation step S6, and omits the molding step S5 compared to the method for manufacturing semiconductor device 100 according to embodiment 1.

[0030] In the semiconductor device 100 according to the second embodiment, a ceramic material with excellent airtightness is used for the materials of the high heat dissipation multilayer substrate 1 and the package substrate 2, thereby making it possible to hermetically seal the inside of the cavity 18. Therefore, a molding process is not required when manufacturing the semiconductor device 100 according to the second embodiment, and it is possible to achieve reduced manufacturing costs and shorter lead times compared to the semiconductor device 100 according to the first embodiment.

[0031] The configurations shown in the above embodiments are merely examples of the content, and may be combined with other known technologies, and parts of the configurations may be omitted or modified as long as they do not deviate from the gist of the invention. [Explanation of symbols]

[0032] 1 high heat dissipation multilayer substrate, 2 package substrate, 3 solder ball, 3a first conductive member, 3b second conductive member, 4 resin mold, 11, 21 component mounting surface, 12 ground surface, 13a, 24 signal via, 13b third ground via, 14 first ground via, 15 semiconductor chip, 16 die bond material, 17 ground structure, 18 cavity, 19 side wall, 19a inner layer ground pattern, 22 electrode surface, 25 second ground via, 26 surface mounted component, 100 semiconductor device, 111 first signal pattern, 112 first signal pad, 113 first ground pattern, 114 first ground pad, 121 solid ground, 211 second signal pattern, 212 second signal pad, 213 second ground pattern, 214 second ground pad, 221 ground electrode, 222 signal electrode.

Claims

1. a high heat dissipation multilayer substrate comprising: a component mounting surface having a first signal pattern, a first signal pad electrically connected to the first signal pattern, a first ground pattern, and a first ground pad; and a ground surface having a solid ground, wherein the first ground pattern and the first ground pad are electrically connected to the solid ground by a first ground via; a package substrate comprising: an electrode surface having a ground electrode and a signal electrode; and a component mounting surface having a second signal pattern, a second signal pad, a second ground pattern, and a second ground pad, wherein the second signal pad and the signal electrode are electrically connected by a signal via, and the second ground pad and the second ground pattern are electrically connected to the ground electrode by a second ground via; a resin mold filled into a side surface of the high heat dissipation multilayer substrate and a space between a component mounting surface of the high heat dissipation multilayer substrate and a component mounting surface of the package substrate; a plurality of first ground pads are provided and arranged in a ring shape on the component mounting surface of the high heat dissipation multilayer substrate, and the first signal pattern, the first signal pads, and the first ground pattern are arranged inside the ring of the first ground pads, and a semiconductor chip is die-bonded thereto; a signal terminal of the semiconductor chip is electrically connected to the first signal pattern, and a ground terminal of the semiconductor chip is electrically connected to the first ground pattern; a first conductive member electrically connecting the first ground pad and the second ground pad, and a second conductive member electrically connecting the first signal pad and the second signal pad.

2. the first conductive member and the second conductive member are solder balls; 2. The semiconductor device according to claim 1, wherein the component mounting surface of the high heat dissipation multilayer substrate and the component mounting surface of the package substrate are joined by the solder balls.

3. 3. The semiconductor device according to claim 2, wherein the solder ball has a metal core therein.

4. a high heat dissipation multilayer substrate comprising: a component mounting surface having a first signal pattern, a first signal pad electrically connected to the first signal pattern, a first ground pattern, and a first ground pad; and a ground surface having a solid ground, wherein the first ground pattern and the first ground pad are electrically connected to the solid ground by a first ground via; a package substrate comprising: an electrode surface having a ground electrode and a signal electrode; and a component mounting surface having a second signal pad, a second signal pattern, a second ground pattern, and a second ground pad, the second signal pad and the signal electrode being electrically connected by a signal via, and the second ground pad and the second ground pattern being electrically connected to the ground electrode by a second ground via; a cavity is formed on the component mounting surface of the high heat dissipation multilayer substrate; a semiconductor chip is die-bonded inside the cavity, a signal terminal of the semiconductor chip is electrically connected to the first signal pattern, and a ground terminal of the semiconductor chip is electrically connected to the first ground pattern; the first signal pad and the first ground pad are disposed on a sidewall of the cavity; a first signal pad and a second signal pad connected by soldering, and a first ground pad and a second ground pad connected by soldering;

5. 5. The semiconductor device according to claim 4, wherein the high heat dissipation multilayer substrate and the package substrate are made of a ceramic material, and the inside of the cavity is hermetically sealed.

6. 6. The semiconductor device according to claim 1, wherein a plurality of semiconductor chips are die-bonded to a component mounting surface of the high heat dissipation multilayer substrate.

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