Fan-out type wafer level package unit

Abstract

To provide a fan-out type wafer level package unit.SOLUTION: A fan-out type wafer level package unit, comprising a carrier substrate, a first dielectric layer, at least one antenna, at least one bare die, a second dielectric layer, at least one conductive pillar, a plurality of first conductive traces, a third dielectric layer, a plurality of second conductive traces, and an outer protection layer, wherein each of the first conductive traces and each of the second conductive traces are formed by filling a metal paste into a groove and polishing the metal paste to form a conductive trace; Each bare die is electrically connected to each antenna, and the bare dies can be electrically connected to the outside through the solder pads around the chip area provided on the second surface, so as to form a fan-out type wafer level package unit, which can effectively solve the problems of high cost and environmental load that are prone to occur when forming connecting wires in the conventional fan-out type package technology.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a chip packaging unit, and more particularly to a fan-out wafer level packaging unit (FOWLP). [Background technology]

[0002] Packaging technology that is small, thin, high-performance, and highly reliable is a trend in the semiconductor industry, and FOWLP is one of the existing advanced packaging technologies. In advanced FOWLP structures, the redistribution layer (RDL) is particularly important. The wiring in the RDL allows electrical expansion and interconnection in the XY plane to multiple pads on the bare chip, and by realizing a more dispersed pad arrangement around the bare chip, it contributes to improving the design freedom and reliability of the wiring. However, in order to achieve these goals simultaneously with a lighter and thinner design, the manufacturing method for the wiring is extremely important. The current FOWLP technology uses electroless plating and electrolytic plating to manufacture RDL wiring, which not only increases material and manufacturing costs but also does not meet the requirements for environmental protection. Furthermore, wireless communication technology is now widely used in electronic products, enabling the transmission and reception of various wireless signals. However, in order to make electronic products smaller and thinner, a new challenge is how to incorporate the antenna into the FOWLP unit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2023-551401 Summary of the Invention [Problem to be solved by the invention]

[0004] The primary objective of the present invention is to provide a FOWLP unit comprising a carrier substrate, a first intermediate layer, at least one antenna, at least one bare die, a second intermediate layer, at least one conductive pillar, a plurality of first conductive wires, a third intermediate layer, a plurality of second conductive wires, and an external protective layer, wherein each of the first conductive wires and each of the second conductive wires are formed by filling a recess with metal paste and then polishing to form conductive wires, and each of the bare dies is electrically connected to each of the antennas, and the bare die can be electrically connected to the outside via solder pads around the chip area on the second surface, thereby forming a FOWLP unit, which can effectively solve the problems of high cost and environmental load that are often encountered when forming conductive wires in conventional fan-out packaging technology. [Means for solving the problem]

[0005] To achieve the above object, the present invention provides a FOWLP unit, The FOWLP unit includes a carrier substrate, a first intermediate layer, at least one antenna, at least one bare die, a second intermediate layer, at least one conductive pillar, a plurality of first conductive lines, a third intermediate layer, a plurality of second conductive lines, and an outer protective layer; the first intermediate layer is disposed on the carrier substrate, and the first intermediate layer has at least one first recess formed to extend in a horizontal direction; Each of the antennas is installed in each of the first recesses, Each of the bare dies is formed by being separated from a wafer, each of the bare dies having a first surface and a second surface opposite to the first surface, the first surface of each of the bare dies being fixedly mounted on the first via layer and each of the antennas, the second surface of each of the bare dies having a plurality of chip pads, and a vertical extent of a chip on the second surface being defined as a chip area; the second interposer layer is disposed on the second surfaces of the first interposer layer, the antennas, and the bare dies, the second interposer layer having a plurality of second recesses formed to extend horizontally and at least one through-hole penetrating the second interposer layer, the chip pads of the bare dies being exposed to the outside from the second recesses, and the antennas being exposed to the outside from the through-holes; each of the conductive pillars is formed in each of the through holes, and each of the conductive pillars is electrically connected to each of the antennas; each of the first conductive wires is made of metal paste filled in each of the second recesses, and each of the first conductive wires is electrically connected to each of the chip pads of each of the bare dies; the third intermediate layer is disposed on the second intermediate layer, and the third intermediate layer has a plurality of third recesses formed to extend horizontally, and each of the third recesses is in communication with each of the second recesses; Each of the second conductive wires is formed by a metal paste filled in each of the third recesses, and each of the second conductive wires is electrically connected to each of the first conductive wires and each of the conductive pillars; the external protective layer is disposed on the third intermediate layer, the external protective layer has a plurality of openings, and at least one of the openings is located around the chip area on the second surface of the bare die; Each of the second conductive wires is exposed to the outside through each of the openings, and a solder pad is formed within each of the openings; each of the bare dies is electrically connected to each of the antennas in turn by each of the first conductive wires and each of the conductive pillars, and the bare dies is electrically connected to the outside in turn by each of the chip pads, each of the first conductive wires, each of the second conductive wires, and each of the solder pads around the chip area located on the second surface of the bare dies, thereby forming a FOWLP unit; The method for manufacturing the FOWLP unit includes the following steps: Step S1: Prepare a carrier substrate; Step S2: placing a first intermediate layer on the carrier substrate, and forming a plurality of first recesses on the first intermediate layer; Step S3: forming an antenna in each of the first recesses; Step S4: Place a plurality of bare dies separated from at least one wafer on the first intermediate layer and each of the antennas at intervals, each of the bare dies having a first surface and a second surface opposite to the first surface, the first surface of each of the bare dies being placed on the first intermediate layer and each of the antennas, each of the bare dies having a plurality of chip pads on the second surface, and a chip area in the vertical direction on the second surface being defined as a chip area; Step S5: forming a plurality of first conductive wires on the second surface of each of the bare dies using a technique of filling a metal paste into a recessed portion in advance and then polishing it to form conductive wires; First, a second intermediate layer is laid on the first intermediate layer, the antennas, and the bare dies, and then a plurality of second recesses and a plurality of through holes are formed horizontally on the second intermediate layer, so that the chip pads of the bare dies are exposed to the outside through the second recesses, and the antennas are exposed to the outside through the through holes; Then, first, a conductive pillar is formed in each of the through holes, then a metal paste is filled into each of the second recesses, and the thickness of the metal paste is higher than the surface of the second intermediate layer. Finally, the metal paste higher than the surface of the second intermediate layer is polished to make the surface of the metal paste and the surface of the second intermediate layer flat, thereby forming a plurality of the first conductive wirings; Step S6: Using a technique of first filling metal paste into recesses and then polishing to form conductive wiring, a plurality of second conductive wirings are formed on the second intermediate layer and each of the first conductive wirings; first laying a third intermediate layer on the second intermediate layer and each of the first conductive wirings; then forming a plurality of third recesses horizontally on the third intermediate layer, so that each of the first conductive wirings is exposed to the outside from each of the third recesses; then filling each of the third recesses with metal paste, and the thickness of the metal paste is higher than the surface of the third intermediate layer; finally, polishing the metal paste that is higher than the surface of the third intermediate layer to flatten the surface of the metal paste and the surface of the third intermediate layer, thereby forming a plurality of second conductive wirings; Step S7: Laying an outer protective layer on the third intermediate layer; Step S8: forming a plurality of openings in the outer protective layer, so that at least one of the openings is formed around the chip area on the second surface of the bare die, so that each of the second conductive wires is exposed to the outside through each of the openings, and a solder pad is formed within each of the openings; Step S9: A division operation is performed to form multiple FOWLP units.

[0006] In one embodiment according to the present invention, the carrier substrate includes a silicon carrier substrate, a glass carrier substrate, or a ceramic carrier substrate.

[0007] In one embodiment of the present invention, the metal paste forming each of the first conductive lines includes silver paste, nano silver paste, copper paste, or nano copper paste.

[0008] In one embodiment of the present invention, the metal paste forming each of the second conductive wires includes silver paste, nano silver paste, copper paste, or nano copper paste.

[0009] In one embodiment of the present invention, the first surface of each of the bare dies is further attached to the first intermediate layer and each of the antennas using a die attach film (DAF).

[0010] In one embodiment according to the present invention, a solder ball is further disposed on each of the openings, and each of the solder balls is electrically connected to each of the solder pads in each of the openings.

[0011] In one embodiment of the present invention, the fan-out type wafer level package unit is mounted on a printed circuit board (PCB) so as to be electrically connected using the solder balls. [Effects of the Invention]

[0012] The present invention comprises a carrier substrate, a first intermediate layer, at least one antenna, at least one bare die, a second intermediate layer, at least one conductive pillar, a plurality of first conductive wires, a third intermediate layer, a plurality of second conductive wires, and an external protective layer, wherein each of the first conductive wires and each of the second conductive wires are formed by filling a recess with metal paste and then polishing to form conductive wires, and each of the bare dies is electrically connected to each of the antennas, and the bare die can be electrically connected to the outside via solder pads around the chip area on the second surface, thereby forming a FOWLP unit and effectively solving the problems of high cost and environmental impact that tend to occur when forming conductive wires in conventional fan-out packaging technology. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a side cross-sectional view of an application embodiment of a FOWLP unit of the present invention. [Figure 2] 1 is a schematic plan view of a side cross section of a carrier substrate of the present invention. [Figure 3] 3 is a side cross-sectional view of a state in which an antenna is installed in a first intermediate layer on the carrier substrate shown in FIG. 2. FIG. [Figure 4] 4 is a side cross-sectional view of a state in which a bare die is mounted on the first intermediate layer shown in FIG. 3. FIG. [Figure 5] 5 is a side cross-sectional view of a state in which a second intermediate layer is provided on the bare die shown in FIG. 4. FIG. [Figure 6] 6 is a cross-sectional side view of a state in which conductive pillars are formed on the second intermediate layer shown in FIG. 5. FIG. [Figure 7] 7 is a side cross-sectional view of the second recess shown in FIG. 6 filled with metal paste. FIG. [Figure 8] 8 is a side cross-sectional view of a state in which the metal paste in the second recess shown in FIG. 7 has been polished to form a first conductor wiring. FIG. [Figure 9] 9 is a cross-sectional side view of a state in which a third intermediate layer is provided on the second intermediate layer shown in FIG. 8. FIG. [Figure 10] 10 is a side cross-sectional view of the state in which the third recess shown in FIG. 9 is filled with metal paste. FIG. [Figure 11] 11 is a side cross-sectional view of a state in which the metal paste in the third recess shown in FIG. 10 has been polished to form a second conductive wiring. FIG. [Figure 12] 12 is a cross-sectional side view of a state in which an outer protective layer is provided on the third intermediate layer shown in FIG. 11. FIG. [Figure 13] 13 is a side cross-sectional view of a state in which a solder ball is formed in the opening shown in FIG. 12. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0014] As shown in FIG. 12, the fan-out wafer level package (FOWLP) unit 1 according to the present invention includes a carrier substrate 10, a first intermediate layer 20, at least one antenna 30, at least one bare die 40, a second intermediate layer 50, at least one conductive pillar 60, a plurality of first conductive wires 70, a third intermediate layer 80, a plurality of second conductive wires 90, and an outer protective layer 100.

[0015] The first intermediate layer 20 is disposed on the carrier substrate 10, and the first intermediate layer 20 has at least one first recess 21 formed to extend in a horizontal direction (see FIG. 2).

[0016] Each of the antennas 30 is installed in each of the first recesses 21 (see FIG. 3), that is, each of the antennas 30 is buried inside the FOWLP unit 1. Each of the antennas 30 is configured by a patterned wiring layer formed in each of the first recesses 21, but since the structure of the patterned wiring layer of an antenna is a well-known technique, a detailed description thereof will be omitted here.

[0017] Each of the bare dies 40 is formed by being separated from a wafer. Each of the bare dies 40 has a first surface 41 and a second surface 42 opposite to the first surface 41, and the first surface 41 of each of the bare dies 40 is fixedly installed on the first interposer layer 20 and each of the antennas 30. Each bare die 40 has a plurality of chip pads 43 on the second surface 42, and the vertical extent of the chip on the second surface 42 is defined as a chip area 1a (see FIG. 4). In FIG. 1, the bare die 40 included in the FOWLP unit 1 will be described as one bare die 40, but this is not intended to limit the present invention. In FIG. 4, each bare die 40 has two chip pads 43, but this is not a limitation of the present invention.

[0018] As shown in FIG. 5, the second intermediate layer 50 is disposed on the first intermediate layer 20, the antennas 30, and the second surfaces 42 of the bare dies 40. The second intermediate layer 50 has a plurality of second recesses 51 formed to extend in the horizontal direction and at least one through-hole 52 penetrating the second intermediate layer 50 . The chip pads 43 of the bare dies 40 are exposed to the outside from the second recesses 51 . Each of the antennas 30 is exposed to the outside from each of the through holes 52 .

[0019] Each of the conductive pillars 60 is formed in each of the through holes 52, and each of the conductive pillars 60 is electrically connected to each of the antennas 30 (see FIG. 6).

[0020] Each of the first conductive wires 70 is formed of a metal paste 70 a filled in each of the second recesses 51 . Each of the first conductive wires 70 is electrically connected to each of the chip pads 43 of each of the bare dies 40 (see FIG. 8).

[0021] The third intermediate layer 80 is disposed on the second intermediate layer 50 . The third intermediate layer 80 has a plurality of third recesses 81 formed to extend in the horizontal direction, and each of the third recesses 81 communicates with each of the second recesses 51 (see FIG. 9).

[0022] Each of the second conductive wires 90 is formed of a metal paste 90 a filled in each of the third recesses 81 . Each of the second conductive wires 90 is electrically connected to each of the first conductive wires 70 and is electrically connected to each of the conductive pillars 60 (see FIG. 11).

[0023] As shown in FIG. 12, the external protective layer 100 is disposed on the third intermediate layer 80, and the external protective layer 100 has a plurality of openings 101, and at least one of the openings 101 is located around the chip area 1a on the second surface 42 of the bare die 40. Each of the second conductive wires 90 is exposed to the outside through each of the openings 101 . A solder pad 91 is formed in each of the openings 101 . In FIG. 12, the openings 101 of the outer protective layer 100 are explained by taking four openings 101 as an example.

[0024] Each of the bare dies 40 is electrically connected to each of the antennas 30 in turn via each of the first conductive wirings 70 and each of the conductive pillars 60, and is used to process the radiation or reception and transmission of electromagnetic signals of the antennas 30 (see Figure 12). The bare die 40 is electrically connected to the outside by each of the chip pads 43, each of the first conductive wirings 70, each of the second conductive wirings 90 and each of the solder pads 43 around the chip area 1a located on the second surface of the bare die 40, thereby forming a FOWLP unit 1 (see Figure 12).

[0025] The manufacturing method of the FOWLP unit 1 includes the following steps.

[0026] Step S1: Prepare a carrier substrate 10 (see FIG. 2).

[0027] Step S2: A first intermediate layer 20 is disposed on the carrier substrate 10, and a plurality of first recesses 21 are formed on the first intermediate layer 20 (see FIG. 2).

[0028] Step S3: An antenna 30 is formed in each of the first recesses 21 (see FIG. 3).

[0029] Step S4: A plurality of bare dies 40 separated from at least one wafer are placed on the first intermediate layer 20 and each of the antennas 30 at intervals (see FIG. 4). Each of the bare dies 40 has a first surface 41 and a second surface 42 opposite to the first surface 41, the first surface 41 of each of the bare dies 40 is installed on the first interposer layer 20 and each of the antennas 30, and each of the bare dies 40 has a plurality of chip pads 43 on the second surface 42, and the vertical extent of the chip on the second surface 42 is defined as a chip area 1a.

[0030] Step S5: A plurality of first conductive wires 70 are formed on the second surface 42 of each of the bare dies 40 using a technique of forming conductive wires by filling a metal paste into a recess in advance and then polishing it. First, the second intermediate layer 50 is laid on the first intermediate layer 20, the antennas 30, and the bare dies 40. Next, a plurality of second recesses 51 and a plurality of through holes 52 are formed horizontally on the second intermediate layer 50, so that each of the chip pads 43 of each of the bare dies 40 is exposed to the outside from each of the second recesses 51, and each of the antennas 30 is exposed to the outside from each of the through holes 52 (see Figure 5). Then, first, conductive pillars 60 are formed in each of the through holes 52 (see FIG. 6), and then metal paste 70a is filled into each of the second recesses 51, and the thickness of the metal paste 70a is higher than the surface of the second intermediate layer 50 (see FIG. 7). Finally, the metal paste 70a, which is higher than the surface of the second intermediate layer 50, is polished to make the surface of the metal paste 70a and the surface of the second intermediate layer 50 flat, thereby forming the plurality of first conductive wirings 70 (see FIG. 8).

[0031] Step S6: First, a metal paste is filled into the recess, and then polished to form conductive wirings. A plurality of second conductive wirings 90 are formed on the second intermediate layer 50 and each of the first conductive wirings 60 using this technique. First, a third intermediate layer 80 is laid on the second intermediate layer 50 and each of the first conductive wirings 60, and then a plurality of third recesses 81 are formed horizontally on the third intermediate layer 80, so that each of the first conductive wirings 70 is exposed to the outside from each of the third recesses 81 (see Figure 9). Thereafter, a metal paste 90a is filled into each of the third recesses 81, and the thickness of the metal paste 90a is higher than the surface of the third intermediate layer 80 (see FIG. 10). Finally, the metal paste 90a, which is higher than the surface of the third intermediate layer 80, is polished to flatten the surface of the metal paste 90a and the surface of the third intermediate layer 80, thereby forming a plurality of the second conductive wirings 90 (see FIG. 11).

[0032] Step S7: The outer protective layer 100 is laid on the third intermediate layer 80 (see FIG. 12).

[0033] Step S8: forming a plurality of openings 101 in the outer protective layer 100, so that at least one opening 101 is formed around the chip area 1a on the second surface 42 of the bare die 40; In this way, each of the second conductive wires 90 is exposed to the outside from each of the openings 101, and a solder pad 91 is formed in each of the openings 101 (see FIG. 12).

[0034] Step S9: A division operation is performed to form a plurality of FOWLP units 1 (see FIG. 12).

[0035] Each of the FOWLP units 1 shown in FIG. 12 will be described as an example of one FOWLP unit 1, but this does not limit the present invention.

[0036] As shown in FIG. 1, the carrier substrate 10 includes, but is not limited to, a silicon carrier substrate, a glass carrier substrate, or a ceramic carrier substrate.

[0037] As shown in FIGS. 8 and 11, the metal paste 70a forming each of the first conductive wires 70 or each of the second conductive wires 90 includes silver paste, nano-silver paste, copper paste, or nano-copper paste. The nanosilver paste material has properties such as low cost, high conductivity, and low-temperature sintering. The nanosilver paste material is a known material and will not be described in detail here.

[0038] As shown in FIG. 4, the first surface 41 of each bare die 40 is further attached to the first intermediate layer 20 and each antenna 30 using a die attach film (DAF) 110 .

[0039] As shown in FIG. 13, a solder ball 120 is further disposed on each of the openings 101 , and each of the solder balls 120 is electrically connected to each of the solder pads 91 in each of the openings 101 .

[0040] As shown in FIG. 1, the FOWLP unit 1 is mounted on a printed circuit board (PCB) 2 so as to be electrically connected using the solder balls 120 .

[0041] Compared with the conventional FOWLP unit technology, the FOWLP unit 1 of the present invention has the following advantages: (1) Steps S5 to S6 in the method for manufacturing the FOWLP unit 1 according to the present invention are important steps in fabricating the redistribution layer (RDL) of the FOWLP unit 1. Because steps S5 to S6 are both easily performed with high precision, they simplify the manufacturing process and allow each conductive wiring in the RDL to have electrical extension and interconnection functions in the XY plane, while simultaneously achieving the specific effect of making the package structure lighter, thinner, shorter, and more compact. This is particularly advantageous in terms of reducing the thickness of the FOWLP unit 1, which not only reduces manufacturing costs but also improves the utilization efficiency and reliability of the FOWLP unit 1. (2) The first conductive wirings 70 and the second conductive wirings 90 of the present invention are both formed by filling a metal paste into a recessed chamber and then polishing it to form conductive wiring. Therefore, the present invention can effectively solve the problems of high costs and environmental loads that tend to occur when forming conductive wiring in conventional FOWLP technology. (3) Each of the antennas 30 of the present invention is embedded inside the FOWLP unit 1, and is not added from the outside after the sealing process is completed. This simplifies the manufacturing process and reduces the thickness of the package unit, thereby meeting the demand for light, thin, short, and small electronic device designs. [Explanation of symbols]

[0042] 1 Fan-out type wafer level package unit 1a Chip area 10 Carrier Board 20 1st electrically conductive layer 21 1st concave tank 30 Antenna 40 Bare Dies 41 Page 1 42 Side 2 43 Chip Pad 50 2nd electrically conductive layer 51 2nd concave tank 52 Through hole 60 Conductive Pillar 70 1st continuity wiring 70a Metal Paste 80 Third galvanic layer 81 Third concave tank 90 2nd continuity wiring 90a Metal Paste 91 solder pads 100 outer protective layer 101 Aperture 110 Die attach film 120 solder balls 2 Printed circuit board

Claims

1. A fan-out wafer level package (FOWLP) unit includes a carrier substrate, a first intermediate layer, at least one antenna, at least one bare die, a second intermediate layer, at least one conductive pillar, a plurality of first conductive lines, a third intermediate layer, a plurality of second conductive lines, and an outer protective layer; the first interposer is disposed on the carrier substrate, and the first interposer has at least one first recess formed to extend in a horizontal direction; Each of the antennas is installed in each of the first recesses, Each of the bare dies is formed by being separated from a wafer, each of the bare dies having a first surface and a second surface opposite to the first surface, the first surface of each of the bare dies being fixedly mounted on the first intermediate layer and each of the antennas, each of the bare dies having a plurality of chip pads on the second surface, and a chip area in the vertical direction on the second surface being defined as a chip area; the second interposer layer is disposed on the second surfaces of the first interposer layer, the antennas, and the bare dies, and the second interposer layer has a plurality of second recesses formed to extend in a horizontal direction and at least one through-hole penetrating the second interposer layer; The chip pads of the bare dies are exposed to the outside from the second recesses, and the antennas are exposed to the outside from the through holes, Each of the conductive pillars is formed in each of the through holes, and each of the conductive pillars is electrically connected to each of the antennas; Each of the first conductive wires is formed by a metal paste filled in each of the second recesses, and each of the first conductive wires is electrically connected to each of the chip pads of each of the bare dies; the third intermediate layer is disposed on the second intermediate layer, and the third intermediate layer has a plurality of third recesses formed to extend horizontally, each of the third recesses communicating with each of the second recesses; each of the second conductive wires is formed by a metal paste filled in each of the third recesses, and each of the second conductive wires is electrically connected to each of the first conductive wires and to each of the conductive pillars; the external protective layer is disposed on the third intermediate layer, the external protective layer has a plurality of openings, at least one of the openings is located around the chip area on the second surface of the bare die, each of the second conductive wires is exposed to the outside through each of the openings, and a solder pad is formed within each of the openings; each of the bare dies is electrically connected to each of the antennas by each of the first conductive wirings and each of the conductive pillars in order; the bare die is electrically connected to the outside by the chip pads, the first conductive wires, the second conductive wires, and the solder pads around the chip area located on the second surface of the bare die, thereby forming a FOWLP unit; The method for manufacturing the FOWLP unit includes the following steps: Step S1: Prepare a carrier substrate; Step S2: placing a first intermediate layer on the carrier substrate, and forming a plurality of first recesses on the first intermediate layer; Step S3: forming an antenna in each of the first recesses; Step S4: placing a plurality of bare dies separated from at least one wafer on the first via layer and each of the antennas at intervals, each of the bare dies having a first surface and a second surface opposite to the first surface, the first surface of each of the bare dies being placed on the first via layer and each of the antennas, each of the bare dies having a plurality of chip pads on the second surface, and a chip area in the vertical direction on the second surface being defined as a chip area; Step S5: Forming a plurality of first conductive wires on the second surface of each of the bare dies using a technique of filling metal paste into recesses and then polishing it to form conductive wires, first laying a second intermediate layer on the first intermediate layer, each of the antennas, and each of the bare dies, then horizontally forming a plurality of second recesses and a plurality of through holes on the second intermediate layer, so that each chip pad of each of the bare dies is exposed to the outside through each of the second recesses, and each antenna is exposed to the outside through each of the through holes, first forming conductive pillars in each through hole, then filling each of the second recesses with metal paste, and the thickness of the metal paste is higher than the surface of the second intermediate layer, and finally polishing the metal paste higher than the surface of the second intermediate layer to flatten the surface of the metal paste and the surface of the second intermediate layer, thereby forming a plurality of first conductive wires; Step S6: Using a technique of first filling metal paste into recesses and then polishing to form conductive wiring, a plurality of second conductive wirings are formed on the second intermediate layer and each of the first conductive wirings; first laying a third intermediate layer on the second intermediate layer and each of the first conductive wirings; then forming a plurality of third recesses horizontally on the third intermediate layer, so that each of the first conductive wirings is exposed to the outside from each of the third recesses; then filling each of the third recesses with metal paste, and the thickness of the metal paste is higher than the surface of the third intermediate layer; finally, polishing the metal paste higher than the surface of the third intermediate layer to flatten the surface of the metal paste and the surface of the third intermediate layer, thereby forming a plurality of second conductive wirings; Step S7: laying an outer protective layer on the third intermediate layer; Step S8: forming a plurality of openings in the outer protective layer, whereby at least one opening is formed around the chip area on the second surface of the bare die, so that each of the second conductive wires is exposed to the outside through each of the openings, and a solder pad is formed within each of the openings; Step S9: Perform division operation to form multiple FOWLP units, FOWLP unit.

2. The FOWLP unit of claim 1 , wherein the carrier substrate comprises a silicon (Si) carrier substrate, a glass carrier substrate, or a ceramic carrier substrate.

3. The FOWLP unit according to claim 1 , wherein the metal paste constituting each of the first conductive wires includes silver paste, nano-silver paste, copper paste, or nano-copper paste.

4. The FOWLP unit according to claim 1 , wherein the metal paste constituting each of the second conductive wires includes silver paste, nano-silver paste, copper paste, or nano-copper paste.

5. The FOWLP unit of claim 1 , wherein the first surface of each of the bare dies is further attached to the first interposer layer and each of the antennas using a die attach film (DAF).

6. 2. The FOWLP unit of claim 1, further comprising a solder ball disposed on each of the openings, each of the solder balls electrically connecting with a respective one of the solder pads in each of the openings.

7. The FOWLP unit according to claim 6 , wherein the fan-out wafer level package unit is mounted on a printed circuit board (PCB) so as to be electrically connected using each of the solder balls.

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