Display device

Abstract

To solve various technical problems in a display panel.SOLUTION: According to an exemplary embodiment of the present specification, a display device includes a substrate including a display area including a plurality of pixels and a transmissive area between adjacent pixels and a non-display area around the display area, a thin film transistor disposed on the substrate, a first protective layer on the thin film transistor, a connection electrode electrically connected to the thin film transistor on the first protective layer, a second protective layer on the connection electrode, a light emitting part on the second protective layer, and a first microlens on the light emitting part, wherein the first microlens is disposed in the transmissive area.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present specification relates to a display device. [Background technology]

[0002] With the development of an information society, various demands for display devices for displaying images are increasing, and various types of display devices such as liquid crystal display devices (LCDs) and organic light emitting diode display devices (OLEDs) are being used.

[0003] Among display devices, organic light-emitting display devices are self-emitting devices that offer superior viewing angles and contrast ratios compared to liquid crystal displays (LCDs), and do not require a separate backlight, making them lightweight and thin, with advantages in terms of power consumption. Organic light-emitting display devices also have the advantages of being able to be driven at a low voltage, having a fast response speed, and low manufacturing costs.

[0004] The organic light emitting display device can also be applied to a display device mounted in an automobile. Among the display devices mounted in an automobile, the display device disposed in front of the driver's seat and the passenger seat needs to limit the viewing angle for the driver depending on the driving situation of the driver. The display device needs to limit the viewing angle according to the user's request to protect privacy and information. Summary of the Invention [Problem to be solved by the invention]

[0005] The problem to be solved by this specification is to provide a display device with an improved aesthetic design.

[0006] Another problem to be solved by this specification is to provide a display device in which the position of the light receiving sensor can be freely arranged within the display panel.

[0007] Another problem to be solved by the present disclosure is to provide a display device that does not require a separate through-hole for light transmission within a display panel.

[0008] Another problem that the present specification aims to solve is to provide a display device in which no through holes for light transmission are formed in the display panel and no changes are required to the arrangement and shape of the circuit components of the display panel.

[0009] Another problem to be solved by the present specification is to provide a display device in which the amount of light passing through a display panel can be increased even if no through-holes for light transmission are formed in the display panel.

[0010] The problems to be solved in this specification are not limited to those described above, and other technical problems can be inferred from the following embodiments. [Means for solving the problem]

[0011] A display device according to one embodiment of the present specification includes a substrate including a display area including a plurality of pixels and transmissive areas between adjacent pixels, and a non-display area around the display area, a thin-film transistor arranged on the substrate, a first protective layer on the thin-film transistor, a connection electrode electrically connected to the thin-film transistor on the first protective layer, a second protective layer on the connection electrode, a light-emitting portion on the second protective layer, and a first microlens on the light-emitting portion, wherein the first microlens is arranged in the transmissive area.

[0012] A display device according to another embodiment of the present specification includes a substrate including a display area including a plurality of pixels and transmissive areas between adjacent pixels, and a non-display area around the display area, a thin-film transistor arranged on the substrate, a first protective layer on the thin-film transistor, a light-emitting section on the first protective layer, a first microlens on the light-emitting section, and a plurality of light-receiving sensors arranged below the substrate, wherein the first microlens is arranged in the transmissive area, and at least a portion of the light-receiving sensor overlaps with the transmissive area.

[0013] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0014] According to the embodiments of the present specification, a display device with improved aesthetics can be provided.

[0015] According to the embodiments of the present specification, it is possible to provide a device in which the position of the light receiving sensor can be freely arranged within the display panel.

[0016] According to the embodiments of the present specification, it is possible to provide a device that does not require a separate through-hole for light transmission in a display panel.

[0017] According to the embodiments of the present specification, it is possible to provide a device in which no through-holes for light transmission are formed in the display panel, and which does not require changes to the arrangement and shape of circuit components and the like of the display panel.

[0018] According to the embodiments of the present specification, it is possible to provide a device in which the amount of light passing through a display panel can be increased even if no through-hole for light transmission is formed in the display panel.

[0019] According to the embodiments of the present specification, since the display panel does not require a through-hole for light transmission, the arrangement and shape of the circuit components of the display panel can be maintained, the display device manufacturing process can be carried out more efficiently, and production energy can be reduced.

[0020] However, the effects obtained in this specification are not limited to the above effects, and other effects not mentioned will be clearly understood by those having ordinary skill in the art to which this specification pertains from the following description.

[0021] Other systems, methods, features, and advantages will be, or will become, apparent to one with skill in the art upon examination of the following figures and detailed description. All such additional systems, methods, features, and advantages are intended to be included within this specification, be within the scope of this disclosure, and be protected by the following claims. Nothing in this section should be construed as limiting the scope of those claims. Further aspects and advantages are described below in connection with embodiments of the disclosure.

[0022] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the inventive concepts as claimed.

[0023] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. [Brief explanation of the drawings]

[0024] [Figure 1] FIG. 1 is a plan view of a display device according to an embodiment. [Figure 2] FIG. 2 is an enlarged view of the Q1 region in FIG. [Figure 3] FIG. 3 is a diagram showing only the display panel in the drawing of FIG. 2. [Figure 4] FIG. 2 is a plan view showing a pixel arrangement of a display panel according to an embodiment. [Figure 5] FIG. 5 is a cross-sectional view taken along the line DD' in FIG. [Figure 6] FIG. 5 is a cross-sectional view taken along line EE' in FIG. [Figure 7] FIG. 6 is a cross-sectional view of the touch part taken at an angle different from that of FIG. 5. [Figure 8] FIG. 6 is a cross-sectional view showing a schematic diagram illustrating how a microlens collects external light. [Figure 9] FIG. 2 is a cross-sectional view taken along line AA' in FIG. [Figure 10] FIG. 4 is a cross-sectional view taken along line BB' in FIG. [Figure 11] FIG. 4 is a cross-sectional view taken along the line CC' in FIG. [Figure 12] FIG. 10 is an enlarged plan view of the periphery of a pixel of a display device according to another embodiment. [Figure 13] FIG. 13 is a cross-sectional view taken along line FF' in FIG. [Figure 14] FIG. 10 is an enlarged plan view of the periphery of a pixel of a display device according to another embodiment. [Figure 15] FIG. 15 is a cross-sectional view taken along line FF' in FIG. [Figure 16] FIG. 10 is an enlarged plan view of the periphery of a pixel of a display device according to another embodiment. [Figure 17] FIG. 17 is a cross-sectional view taken along line HH' in FIG. [Figure 18] FIG. 10 is a plan view of a display device according to another embodiment. [Figure 19] FIG. 19 is an enlarged view of a region Q2 in FIG. [Figure 20] FIG. 20 is a cross-sectional view taken along the line KK' in FIG. [Figure 21] FIG. 10 is a plan view showing a pixel arrangement of a display device according to another embodiment.

[0025] Throughout the drawings and detailed description, the same drawing reference numerals should be understood to refer to the same elements, features, and structures unless otherwise stated. The relative size and depiction of these elements may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION OF THE INVENTION

[0026] Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. In the following description, if a detailed description of well-known functions or configurations related to this specification is deemed to unnecessarily obscure the gist of the inventive concept, such detailed description will be omitted or briefly described. The described process steps and / or operational progressions are exemplary, but the order of steps and / or operations is not limited to those described herein and may be varied as known in the art, except where the steps and / or operations necessarily occur in a specific order. Like reference numerals refer to like elements throughout. The names of elements used in the following description have been selected for convenience of description and may differ from those used in the actual product.

[0027] The advantages and features of the present disclosure, as well as methods for implementing the same, will become apparent through the following exemplary embodiments, which are described with reference to the accompanying drawings. However, the present disclosure may be embodied in different forms and should not be construed as being limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that the disclosure may be sufficiently thorough and complete to assist those skilled in the art in fully understanding the scope of the present disclosure. Furthermore, the present disclosure is defined solely by the claims.

[0028] The shapes, sizes, ratios, angles, and numbers disclosed in the drawings to illustrate embodiments of the present disclosure may be merely exemplary. Therefore, the present disclosure is not limited to the details shown. Like reference numerals refer to like elements throughout. In the following description, if a detailed description of relevant known functions or configurations is deemed to unnecessarily obscure the important points of the present disclosure, the detailed description of such known functions or configurations may be omitted. When "comprises," "has," and "includes" are used herein, other parts may be added unless "only" is used. Elements described in the singular are intended to include plural elements, and vice versa, unless the context to the contrary clearly dictates otherwise.

[0029] Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0030] In addition, when dimensions, relative sizes, etc. are mentioned, even if no related description is specified, it should be considered that the numerical values ​​of elements or features or corresponding information (e.g., levels, ranges, etc.) include tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). Furthermore, the term "obtain" fully encompasses all meanings of the term "can."

[0031] In describing temporal relationships, when the temporal order is described as, for example, "after," "succeeding," "next," and "before," non-consecutive cases may be included unless a more restrictive term, such as "just," "immediately," or "directly," is used.

[0032] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, "at least one of a first element, a second element, and a third element" means combinations of all three listed elements, combinations of any two of the three elements, and each individual element, first element, second element, or third element.

[0033] Hereinafter, embodiments will be described with reference to the drawings. In this specification, when a component (or a region, layer, portion, etc.) is referred to as being "on," "connected," or "coupled" to another component, this means that the component may be directly connected / coupled to the other component, or that a third component may be disposed therebetween.

[0034] The same reference numerals refer to the same elements. In the drawings, the thickness, proportions, and dimensions of the elements are exaggerated for the purpose of effectively explaining the technical contents. "And / or" includes all one or more combinations that can define the related configuration.

[0035] Terms such as "first," "second," etc. may be used to describe various components, but the components are not limited by these terms. These terms are used only to distinguish one component from another. For example, a first component may be referred to as a "second component," and similarly, a second component may be referred to as a "first component," without departing from the scope of the present embodiment. A singular expression includes a plural expression unless the context clearly dictates otherwise.

[0036] Terms such as "under," "below," "on," and "above" are used to describe the relative relationships of features shown in the drawings. These terms are relative concepts and are described with reference to the directions shown in the drawings.

[0037] Terms such as "comprise" or "have" are intended to specify the presence of features, numbers, steps, operations, components, parts, or combinations thereof stated in the specification, but are to be understood as not precluding the possible presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0038] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments belong. Furthermore, it will be understood that terms as defined in commonly used dictionaries should be interpreted as illustratively having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein. For example, the terms "part" or "unit" may apply to, for example, a separate circuit or structure, an integrated circuit, a computational block of a circuit device, or any structure configured to perform a described function as would be understood by one of ordinary skill in the art.

[0039] Rather, these embodiments are provided so that this disclosure may be thorough and complete, to aid those skilled in the art in fully appreciating the scope of the disclosure, which is further defined solely by the claims.

[0040] The features of various embodiments of the present disclosure may be partially or wholly combined or combined with each other, and may interoperate and be technically driven by each other in various ways, as will be readily understood by those skilled in the art. The embodiments of the present disclosure may be implemented independently of each other or may be implemented together in a codependent relationship.

[0041] Fig. 1 is a plan view of a display device according to an embodiment, Fig. 2 is an enlarged view of a region Q1 in Fig. 1, and Fig. 3 is a view showing only the display panel in Fig. 2.

[0042] Fig. 3 is a diagram in which the flexible film COF, main substrate MB, and driving IC DIC, excluding the display panel 100, are omitted from the diagram in Fig. 2. For ease of explanation, the proportions between the components are adjusted in Fig. 3.

[0043] 1 to 3, the display device 1 is a device including both a display function for displaying images and a touch sensing function for sensing a user's touch, but is not limited thereto. For example, the display device 1 may include only one of the display function for displaying images and the touch sensing function for sensing a user's touch.

[0044] The display device 1 may be an electroluminescent display device or a micro light emitting diode (Micro Light Emitting Diode) display device including a touch sensor. The electroluminescent display device including a touch sensor may be an organic light emitting diode (OLED) display device, a quantum dot light emitting diode (Quantum Dot Light Emitting Diode) display device, or an inorganic light emitting diode (Inorganic Light Emitting Diode) display device.

[0045] The display device 1 according to the present embodiment may be, but is not limited to, a vehicle display device. For example, the description of the display device 1 can be applied to any device that includes a display function, regardless of the type of device.

[0046] When the display device 1 according to this embodiment is a vehicle display device, the display device 1 may include a function for operating at least some of the various functions of the vehicle, a function for displaying various information related to the vehicle, and the like.

[0047] When the display device 1 according to the present embodiment is a display device for a vehicle, the display device 1 may be disposed on the dashboard of the vehicle. The display device 1 may be disposed across the driver's seat and the passenger seat, which are disposed in the front seats of the vehicle, but is not limited to this. Both the driver (DRIVER) seated in the driver's seat and the passenger (PASSENGER) seated in the passenger seat can use the display device 1.

[0048] The display device 1 may include a display panel 100. The display panel 100 may include a display area DA and a non-display area NDA.

[0049] The display area DA may be an area where light is emitted to the outside and a screen is displayed. The display area DA may further include a function for sensing a user's touch. In this case, the display area DA may correspond to, but is not limited to, a touch-sensing area.

[0050] The display area DA may correspond to the shape of the display panel 100, but is not limited to this.

[0051] A plurality of pixels PX may be arranged within the display area DA. The plurality of pixels PX may be repeatedly arranged along the first direction DR1 and the second direction DR2.

[0052] The non-display area NDA may be an area where light is not emitted to the outside and where no screen is displayed. The non-display area NDA may be present around the display area DA. The non-display area NDA may surround the display area DA, but the embodiment of the present specification is not limited thereto. The non-display area NDA may define a bezel area of ​​the display device 1, but the embodiment of the present specification is not limited thereto. The display panel 100 may be, but is not limited to, a rigid display panel. The display panel 100 may also be a flexible display panel that can be deformed into a different shape, such as a foldable, bendable, rollable, or stretchable display panel.

[0053] The display panel 100 may include a first long side LE1, a second long side LE2, a first short side SE1, and a second short side SE2 that form edges of the display panel 100.

[0054] The first long side LE1 and the second long side LE2 may extend in a first direction DR1, and the first short side SE1 and the second short side SE2 may extend in a direction between the first direction DR1 and the second direction DR2. The first long side LE1 and the second long side LE2 may be connected to each other at both ends via the first short side SE1 and the second short side SE2.

[0055] The first long side LE1 may be disposed on one side of the second long side LE2 in the second direction DR2, and the first long side LE1 and the second long side LE2 may extend parallel to each other, but are not limited thereto.

[0056] The length of the first long side LE1 may be shorter than the length of the second long side LE2, so that the first short side SE1 and the second short side SE2 may extend in directions intersecting each other, but this is not limiting.

[0057] The first direction DR1 and the second direction DR2 may be directions that intersect each other. The first direction DR1 and the second direction DR2 may be perpendicular to each other, but are not limited to this. The first direction DR1 and the second direction DR2 are used for clarity of the description of the invention, and the first direction DR1 and the second direction DR2 are relative, and the embodiments of the present specification are not limited to this.

[0058] In a plan view, the first long side LE1 may be disposed in the upper part of the display area DA, and the second long side LE2 may be disposed in the lower part of the display area DA1.

[0059] In a plan view, the first short side SE1 may be located on the right side of the display area DA, and the second short side SE2 may be located on the left side of the display area DA1.

[0060] The display panel 100 may include a curved notch portion NCP. The notch portion NCP may be formed on the second long side LE2, but is not limited to this. In other words, the second long side LE2 may extend generally along the first direction DR1 but include a notch portion NCP that curves toward the first long side LE1.

[0061] By arranging the notch portion NCP, it is possible to maximize the display area DA while arranging components such as the driver's seat handle in that area, thereby improving user convenience and aesthetic appeal.

[0062] The non-display area NDA may include a first non-display area NDA1 arranged along the first long side LE1, the first short side SE1, and the second short side SE2, and a second non-display area NDA2 arranged along the second long side LE2. The second non-display area NDA2 may be arranged along the second long side LE2 including a curved notch portion NCP.

[0063] The first non-display areas NDA1 may be arranged on one side and the other side of the display area DA in the first direction DR1, and may also be arranged on one side of the display area DA in the second direction DR2.

[0064] The second non-display area NDA2 may include a notch non-display area N_NDA arranged around the notch portion NCP, and an extended non-display area E_NDA arranged around the notch non-display area N_NDA. The extended non-display area E_NDA may extend from the notch non-display area N_NDA along the first direction DR1. The extended non-display area E_NDA may be disposed between the notch non-display area N_NDA and the first non-display area NDA1. The extended non-display area E_NDA may connect the notch non-display area N_NDA and the first non-display area NDA1.

[0065] The display device 1 may further include a light-receiving sensor 200. The light-receiving sensor 200 may be disposed below the display panel 100. A plurality of light-receiving sensors 200 may be provided, but this is not limiting, and one light-receiving sensor 200 may also be provided. The light-receiving sensor 200 may be disposed so as to overlap at least a portion of the light-receiving sensor 200 with the transmissive region TA (see FIGS. 6 and 8).

[0066] When the display panel 100 is viewed from above, the light receiving sensor 200 may be hidden by the display panel 100 and may not be visible. However, in FIG. 1, the light receiving sensor 200 is shown in order to explain the size, position, number, etc. at which the light receiving sensor 200 may be disposed.

[0067] The light receiving sensor 200 may be disposed within the display area DA of the display panel 100. However, without being limited to this, the light receiving sensor 200 may be disposed in the non-display area NDA, or may be disposed across the display area DA and the non-display area NDA.

[0068] The light receiving sensor 200 may be arranged at various positions within the display area DA. For example, the light receiving sensor 200 may be arranged along the periphery of the non-display area NDA within the display area DA. However, the light receiving sensor 200 is not limited to this, and may be arranged inside the display area DA away from the non-display area NDA, or may be arranged at various positions depending on the design and purpose.

[0069] The light receiving sensor 200 can sense light incident from the outside through the display panel 100. The light receiving sensor 200 can sense light that is incident on the display device 1 from the outside and reaches the light receiving sensor 200 through the display panel 100.

[0070] The light receiving sensor 200 can perform various operations by detecting external light that has penetrated the display panel 100 and reached the light receiving sensor 200. For example, the light receiving sensor 200 can perform functions such as adjusting the illuminance of the display panel 100 by detecting external light, recognizing the driver and passengers by detecting infrared (IR) light from the external light, or recognizing the eyes of the driver or passengers by detecting infrared (IR) light from the external light.

[0071] However, the functions that the light receiving sensor 200 can perform are not limited to these, and other functions that can be performed by sensing light incident from the outside can also be performed.

[0072] The display device 1 may further include a pad area PA, a gate driver GIP, a main substrate MB, a flexible film COF, a driving IC DIC, gate lines GL, gate control lines GCL, data lines DL, a low potential voltage line VSSL, and a high potential voltage line VDDL.

[0073] The pad area PA may overlap the flexible film COF. The flexible film COF may be attached to the pad area PA. In other words, the flexible film COF may be attached to the display panel 100 via the pad area PA.

[0074] The pad area PA may be arranged in the non-display area NDA. The pad area PA may be arranged in the non-display area NDA. The pad area PA may be arranged in the second non-display area NDA2. The pad area PA may be arranged in each of the notch non-display area N_NDA and the extended non-display area E_NDA.

[0075] The pad area PA may include a plurality of pads. The pad area PA may include a low-potential voltage pad VSSP, a high-potential voltage pad VDDP, a first data pad DP1, and a second data pad PD2. The low-potential voltage pad VSSP, the high-potential voltage pad VDDP, the first data pad DP1, and the second data pad PD2 may be arranged in the pad area PA.

[0076] However, without being limited thereto, the pad area PA arranged in the area overlapping the flexible film COF arranged at both ends of the flexible film COF arranged along the non-display area NDA may further include a gate control pad (not shown).

[0077] The gate driver GIP may be disposed in the non-display area NDA. The gate driver GIP may be disposed on at least one side of the display area DA in the first direction DR1, but is not limited to this. In plan view, the gate driver GIP may be disposed on the left side or the other side of the display area DA.

[0078] The gate driver GIP may include a plurality of transistors. The transistors arranged in the gate driver GIP may be connected to the pixels PX via gate lines GL. The gate driver GIP can apply gate signals to each pixel PX via the gate lines GL.

[0079] The gate driver GIP receives a gate control signal from the driver IC DIC via a gate control line GCL, and generates a scan signal and an emission signal (or an emission control signal) based on the gate control signal.

[0080] The gate driver GIP may include a scan driver and an emission signal driver. The scan driver may generate scan signals in a row sequential manner and supply them to at least one scan line connected to each pixel PX row. The emission signal driver may generate emission signals in a row sequential manner and supply them to at least one emission signal line connected to each pixel PX row.

[0081] The main substrate MB may be connected to the display panel 100 via a flexible film COF. The main substrate MB may be electrically connected to the pixels PX in the display area DA via the flexible film COF. The main substrate MB may be electrically connected to the flexible film COF. The main substrate MB and the flexible film COF may be electrically connected to each other via a plurality of pads VSSP, VDDP, and DP.

[0082] The main substrate MB may have various components arranged thereon to supply various signals, such as gate control signals, drive signals, and data signals, to the driver IC DIC. The main substrate MB may be, but is not limited to, a printed circuit board.

[0083] The main substrate MB may be connected to the display panel 100 via a flexible film COF in the second non-display area NDA2. A plurality of main substrates MB may be provided along the second non-display area NDA2, but is not limited to this. The number of main substrates MB may vary depending on the design.

[0084] At least one of the main substrates MB may be disposed around the notch portion NCP and connected to the display panel 100 in the notch non-display area N_NDA via a flexible film COF.

[0085] The flexible film COF may be connected to the display panel 100 and the main substrate MB. The flexible film COF may be attached to each of the display panel 100 and the main substrate MB, or may be electrically connected to each of the display panel 100 and the main substrate MB. In other words, the display panel 100 and the main substrate MB may be electrically connected via the flexible film COF. A plurality of flexible film COFs may be provided, but this is not limited to this.

[0086] The flexible film COF may be attached to the display panel 100 in the second non-display area NDA2. The flexible film COF may be repeatedly arranged along the second non-display area NDA2. The flexible film COF may be attached to the display panel 100 across the notch non-display area N_NDA and the extended non-display area E_NDA.

[0087] One main substrate MB may be electrically connected to the display panel 100 via at least one flexible film COF. For example, among the multiple main substrates MB arranged along the second non-display area NDA2, the main substrates MB arranged at both ends may be electrically connected to the display panel 100 via one flexible film COF, and the remaining main substrates MB may each be electrically connected to the display panel 100 via two flexible film COFs.

[0088] The flexible film COF may be electrically connected to the pad area PA, so that the flexible film COF can supply gate control signals, driving signals, power supply voltages, data voltages, etc. to the pixels PX and gate drivers GIP arranged in the display area DA.

[0089] The flexible film COF may be a flexible insulating film, and may include, but is not limited to, polycarbonate, polyethylene terephthalate, polyimide, polyamide, polyester, polyacrylate, polymethyl methacrylate, and the like.

[0090] The driving IC DIC may be mounted on a flexible film COF. Depending on the mounting method, the driving IC DIC may be arranged in a chip-on-glass, chip-on-film, tape carrier package, or other manner. Although the present invention has been described as a chip-on-film type in which the driving IC DIC is mounted on a flexible film COF, the present invention is not limited to this.

[0091] The driving IC DIC can drive the display device 1. The driving IC DIC can process data signals for displaying images and various driving signals for processing the data signals. The driving IC DIC may include a gate driver IC, a data driver IC, etc.

[0092] The gate lines GL may extend from the gate driver GIP and connect to the pixels PX. The gate lines GL can electrically connect the gate driver GIP and the pixels PX. The gate lines GL can apply gate signals from the gate driver GIP to each pixel PX.

[0093] The gate control line GCL may be disposed in the non-display area NDA, and may extend from the pad area PA to the gate driver GIP and be electrically connected to the gate driver GIP.

[0094] The gate control line GCL can apply a gate control signal to the gate driver GIP. The gate control signal can be received from the main substrate MB or the driver IC DIC. The gate control line GCL can electrically connect the gate driver GIP to the main substrate MB or the driver IC DIC.

[0095] The gate control line GCL may be electrically connected to flexible film COFs arranged at both ends of a plurality of flexible film COFs connected to the display panel 100 along the second non-display area NDA2. The gate control line GCL may be arranged at the outermost of a plurality of lines connected to one flexible film COF, but is not limited to this.

[0096] The data lines DL may extend from the pad area PA and be connected to the pixels PX in the display area DA. The data lines DL can apply data signals to each pixel PX. The data signals may be applied from the main substrate MB or the driving IC DIC. The data lines DL can electrically connect the pixels PX to the main substrate MB or the driving IC DIC.

[0097] The data line DL may include a first data line DL1 and a second data line DL2. The data line DL may be connected to data pads DP1 and DP2. The first data line DL1 may be in contact with and electrically connected to the first data pad DP1 through a first data contact hole CNT1. The second data line DL2 may be in contact with and electrically connected to the second data pad DP2 through a second data contact hole CNT2.

[0098] The low potential voltage line VSSL may be arranged in the non-display area NDA so as to surround the display area DA. The low potential voltage line VSSL may be arranged in the non-display area NDA so as to sandwich the display area DA and the gate driver GIP. In other words, the gate driver GIP may be arranged between the display area DA and the low potential voltage line VSSL.

[0099] The low potential voltage line VSSL can apply a low potential voltage to the pixel PX. The low potential voltage line VSSL is electrically connected to the cathode electrode (see 153 in FIG. 5) of the pixel PX and can apply a low potential voltage.

[0100] The low-potential voltage line VSSL may be connected to the pad area PA. The low-potential voltage line VSSL may be physically connected to the low-potential voltage pad VSSP and electrically connected to the low-potential voltage pad VSSP. The low-potential voltage line VSSL and the low-potential voltage pad VSSP may be integrally formed, but are not limited to this.

[0101] The high-potential voltage line VDDL may be disposed between the display area DA and the low-potential voltage line VSSL. The high-potential voltage line VDDL can apply a high-potential voltage to the pixel PX. The high-potential voltage line VDDL is electrically connected to the anode electrode (see 151 in FIG. 5) of the pixel PX and can apply a high-potential voltage.

[0102] The high-potential voltage line VDDL may be connected to the pad area PA. The high-potential voltage line VDDL may be physically connected to the high-potential voltage pad VDDP and electrically connected to the high-potential voltage pad VDDP. The high-potential voltage line VDDL and the high-potential voltage pad VDDP can be in contact with each other through a high-potential contact hole S_CNT.

[0103] However, the present invention is not limited thereto, and the high potential voltage line VDDL and the high potential voltage pad VDDP may be integrally formed. For example, the high potential voltage line VDDL may include the same material as the high potential voltage pad VDDP, may be made of the same conductive layer, and may be formed using the same mask process.

[0104] The display device 1 may further include a dam portion DMP. The dam portion DMP may be arranged in the non-display area NDA. The dam portion DMP may be arranged to surround the display area DA, but is not limited to this. The dam portion DMP may be arranged to at least partially overlap the low potential voltage line VSSL. The dam portion DMP may be arranged between the display area DA and the pad area PA in the second non-display area NDA2.

[0105] 4 is a plan view showing the pixel arrangement of a display panel according to one embodiment, which shows an enlarged view of a part of the display area DA in which the sub-pixels SP are arranged.

[0106] 1 and 4, a display panel 100 includes a plurality of pixels PX, which may be arranged in a display area DA.

[0107] Each of the pixels PX may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may emit light of different colors. For example, but not limited to, the first sub-pixel SP1 may emit red light, the second sub-pixel SP2 may emit green light, and the third sub-pixel SP3 may emit blue light.

[0108] In each pixel PX, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be arranged in order along the second direction DR2. The pixels PX may be arranged repeatedly along the first direction DR1 and the second direction DR2.

[0109] Each of the plurality of pixels PX may include a light-emitting area EA and a non-light-emitting area NEA arranged around the light-emitting area EA. The light-emitting area EA emits light, while the non-light-emitting area NEA does not emit light. The light-emitting area EA and the non-light-emitting area NEA may be defined by a bank 154 (see FIG. 5).

[0110] The light-emitting region EA may include a first light-emitting region EA1 from which light is substantially emitted in the first sub-pixel SP1, a second light-emitting region EA2 from which light is substantially emitted in the second sub-pixel SP2, and a third light-emitting region EA3 from which light is substantially emitted in the third sub-pixel SP3.

[0111] The shape of the luminescent area EA in a planar view may be longer in the first direction DR1 than in the second direction DR2, but is not limited to this, and the shape of the luminescent area EA in a planar view can vary depending on the design.

[0112] The non-light-emitting area NEA may include a first non-light-emitting area NEA1 arranged around the first light-emitting area EA1, a second non-light-emitting area NEA2 arranged around the second light-emitting area EA2, and a third non-light-emitting area NEA3 arranged around the third light-emitting area EA3.

[0113] In plan view, each of the non-light emitting areas NEA: NEA1, NEA2, NEA3 may surround each of the light emitting areas EA: EA1, EA2, EA3, but is not limited to this.

[0114] The first sub-pixel SP1 may include a first light-emitting area EA1 and a first non-light-emitting area NEA1, the second sub-pixel SP2 may include a second light-emitting area EA2 and a second non-light-emitting area NEA2, and the third sub-pixel SP3 may include a third light-emitting area EA3 and a third non-light-emitting area NEA3.

[0115] The display panel 100 may further include a transmissive region TA disposed between the pixels PX. The transmissive region TA may be disposed between the non-emissive regions NEA of the adjacent pixels PX.

[0116] The transmissive area TA is disposed within the display area DA and may be disposed over the entire display area DA, but is not limited to this. For example, a portion of the transmissive area TA may be disposed in the non-display area NDA.

[0117] The light transmittance of the transmissive region TA may be higher than that of the region in which the pixels PX are arranged. In other words, the light transmittance of the transmissive region TA may be higher than that of the emissive region EA and higher than that of the non-emissive region NEA.

[0118] The transmissive regions TA may be disposed between the pixels PX along the first direction DR1 and the second direction DR2. The transmissive regions TA may extend in the second direction DR2 between the pixels PX adjacent to each other in the first direction DR1, and may extend in the first direction DR1 between the pixels PX adjacent to each other in the second direction DR2.

[0119] The thin film transistor 120 and the bank 154 (see FIG. 5) may not be arranged in the transmissive region TA. The drive transistor and the switching transistor for driving the pixel PX may not be arranged in the transmissive region TA. In other words, not only the thin film transistor 120, which is the drive transistor, but also the switching transistor (not shown) may not be arranged in the transmissive region TA.

[0120] By arranging the transmissive area TA over the entire display area DA, a path is secured by the transmissive area TA to reach the light receiving sensor 200, and it may become unnecessary to physically remove through holes in each laminated member to allow light incident from the outside to reach the light receiving sensor 200.

[0121] Even if a through-hole is not provided, the light-receiving sensor 200 can be freely arranged within the display area DA by providing the transmissive area TA. Furthermore, the size and shape of the light-receiving sensor 200 can be freely designed. This allows the light-receiving sensor 200 to have various shapes, sizes, and arrangements depending on the design or need.

[0122] Furthermore, since there is no need to change the arrangement and shape of the circuit components of the display panel to arrange the through holes, the path of light incident on the light receiving sensor 200 is secured, and the process can be carried out more efficiently, thereby reducing production energy.

[0123] A first microlens ML1 may be disposed in the transmissive region TA. The first microlens ML1 condenses external light L (see FIG. 8) directed toward the display panel 100, allowing a larger amount of light L (see FIG. 8) to penetrate the display panel 100.

[0124] The first microlens ML1 may have a cross section that is round in at least a portion of its area (see FIG. 6). For example, the cross section of the first microlens ML1 may have a semicircular or semi-elliptical shape. However, the cross section of the first microlens ML1 may vary depending on the design.

[0125] The first microlens ML1 may extend along the extension direction of the transmissive region TA. For example, in a transmissive region TA extending in a first direction DR1, the first microlens ML1 may extend in the first direction DR1, and in a transmissive region TA extending in a second direction DR2, the first microlens ML1 may extend in the second direction DR2.

[0126] The first microlens ML1 may be formed integrally over the entire transmissive area TA, but is not limited to this.

[0127] The first microlens ML1 may be arranged within the transmissive area TA, but is not limited to this, and the first microlens ML1 may be arranged in the transmissive area TA and up to a portion of the non-light-emitting area NEA around the transmissive area TA.

[0128] By arranging the first microlens ML1 in the transmissive region TA, the first microlens ML1 can collect light L (see FIG. 8) incident from outside in the transmissive region TA, and the amount of light L (see FIG. 8) that penetrates the display panel 100 can be increased. Furthermore, more light L (see FIG. 8) is incident on the light receiving sensor 200 arranged in the transmissive region TA, and the light receiving sensor 200 can sense the light L (see FIG. 8) more smoothly.

[0129] A second microlens ML2 may be disposed in each of the sub-pixels SP1, SP2, and SP3. The second microlens ML2 may be disposed for each of the sub-pixels SP1, SP2, and SP3.

[0130] The second microlenses ML2 can control the direction of light emitted from the light-emitting area EA, so that when the display panel 100 is applied to a vehicle display device, the screens displayed to the driver and passengers can be individually controlled.

[0131] Furthermore, by disposing the second microlens ML2 in the light-emitting area EA, it is possible to improve brightness while maintaining a wide viewing angle characteristic, and to prevent or reduce light leakage by blocking leakage light and reflected light.

[0132] The second microlens ML2 may be disposed in each of the light-emitting areas EA1, EA2, and EA3. The second microlens ML2 may cover each of the light-emitting areas EA1, EA2, and EA3 and may extend to each of the light-emitting areas EA1, EA2, and EA3 and a portion of the non-light-emitting areas NEA1, NEA2, and NEA3 surrounding each of the light-emitting areas EA1, EA2, and EA3. However, the present invention is not limited to this, and the second microlens ML2 may be disposed only within each of the light-emitting areas EA1, EA2, and EA3.

[0133] The second microlens ML2 may have a cross section that is round in at least a portion of its area (see FIG. 6). For example, the cross section of the second microlens ML2 may have a semicircular or semi-elliptical shape. However, the cross section of the second microlens ML2 may vary depending on the design.

[0134] The surface of the second microlens ML2 may have a rounded shape, for example, but not limited to, a dome shape.

[0135] Although one second microlens ML2 is arranged for each of the subpixels SP1, SP2, and SP3 in the illustrated embodiment, this is not limiting. For example, two or more second microlenses ML2 may be provided for each of the subpixels SP1, SP2, and SP3 depending on the design of each of the subpixels SP1, SP2, and SP3. If multiple openings (light-emitting areas EA) are formed in one of the subpixels SP1, SP2, and SP3, a second microlens ML2 may be arranged for each opening, or multiple second microlenses ML2 may be arranged in one opening.

[0136] Hereinafter, the cross-sectional structure of the display area DA of the display panel 100 including the pixels PX will be described with reference to FIGS.

[0137] Fig. 5 is a cross-sectional view taken along line DD' in Fig. 4. Fig. 6 is a cross-sectional view taken along line EE' in Fig. 4. Fig. 7 is a cross-sectional view of the touch portion taken at an angle different from that in Fig. 5. Fig. 8 is a schematic diagram showing how the microlenses collect external light in the cross-sectional view of Fig. 6.

[0138] 6, if the light-receiving sensor 200 is disposed, the light-receiving sensor 200 may be disposed so as to overlap at least a portion of the transmissive area TA. This allows light incident from the outside to pass through the transmissive area TA of the display panel 100 and reach the light-receiving sensor 200.

[0139] 4 to 8 , the display panel 100 may include a substrate 101, a thin film transistor 120, a storage electrode 140, a light-emitting unit 150, an encapsulation unit 170, and a touch unit 180. The display panel 100 may further include a buffer layer 102, a first insulating layer 103, a second insulating layer 104, a third insulating layer 105, a fourth insulating layer 106, a first protective layer 111, a second protective layer 112, and a bank 154, which are disposed on the substrate 101 and between the respective components. However, the embodiments herein are not limited thereto.

[0140] The area where each pixel PX is arranged (light-emitting area EA and non-light-emitting area NEA) and the transmissive area TA may have different layered structures.

[0141] In the area where each pixel PX is arranged (light-emitting area EA and non-light-emitting area NEA), a substrate 101, a thin film transistor 120, a storage electrode 140, a light-emitting section 150, a sealing section 170, and a touch section 180 are arranged, and a buffer layer 102, a first insulating layer 103, a second insulating layer 104, a third insulating layer 105, a fourth insulating layer 106, a first protective layer 111, a second protective layer 112, and a bank 154 may further be arranged between each component.

[0142] The transmissive region TA may be provided with only high-transmittance components, and may not include low-transmittance components. For example, the transmissive region TA may include the substrate 101, a portion of the light-emitting unit 150 (cathode electrode 153), the sealing unit 170, and the touch unit 180, and may further include the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first protective layer 111, the second protective layer 112, and the bank 154, which are disposed between the respective components. The transmissive region TA may not include the thin-film transistor 120, the storage electrode 140, the bank 154, and the remaining portion of the light-emitting unit 150 (anode electrode 151 and organic layer 152).

[0143] By disposing only components with high transmittance in the transmissive region TA, the light transmittance of the transmissive region TA can be improved.

[0144] The substrate 101 may have a space on top where many components can be arranged. The substrate 101 may correspond to the planar shape of the display panel 100 in FIG. 1. In other words, the substrate 101 may include a notch portion NCP. The substrate 101 may include the display area DA and the non-display area NDA of the display panel 100 in substantially the same area.

[0145] The substrate 101 may include one or more plastic materials, but is not limited to such, and may also include a glass material.

[0146] The substrate 101 may be a multi-substrate including a first substrate 101a, a second substrate 101b, and a third substrate 101c, each of which includes a plastic material such as polyimide, but the embodiments of the present specification are not limited thereto. For example, the substrate 101 may be a single substrate consisting of one layer.

[0147] The substrate 101 may include a rigid substrate, but is not limited thereto, and may also include a flexible substrate.

[0148] A buffer layer 102 may be disposed on the substrate 101. The buffer layer 102 may minimize or delay the diffusion of moisture or oxygen that penetrates the substrate 101. The buffer layer 102 may be formed by alternately stacking at least one layer of silicon nitride (SiNx) and silicon oxide (SiOx), although embodiments herein are not limited thereto.

[0149] Although the specification shows that the buffer layer 102 is formed as a multilayer film consisting of three layers, the number of layers constituting the buffer layer 102 is not limited to this, and the buffer layer 102 may be formed as a single film.

[0150] A light-shielding layer 126 may be disposed on the buffer layer 102. The light-shielding layer 126 can prevent or reduce light from passing through the semiconductor layer 123 of the thin-film transistor 120. For example, the semiconductor layer 123 may be disposed to overlap the light-shielding layer 126. The light-shielding layer 126 may be a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof, but embodiments of the present specification are not limited thereto.

[0151] The light-shielding layer 126 may be in contact with the source electrode 121 of the thin film transistor 120 through a contact hole.

[0152] A first insulating layer 103 may be disposed on the light-shielding layer 126. The first insulating layer 103 may prevent or reduce a short circuit between the thin film transistor 120 and the light-shielding layer 126. The first insulating layer 103 may be made of the same material as the buffer layer 102, although embodiments of the present specification are not limited thereto. For example, the first insulating layer 103 may be made of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx), although embodiments of the present specification are not limited thereto.

[0153] A thin film transistor 120 may be disposed on the first insulating layer 103. The thin film transistor 120 may include a source electrode 121, a gate electrode 122, a semiconductor layer 123, and a drain electrode .

[0154] The thin film transistor 120 is disposed in the area where the pixel PX is disposed (the light emitting area EA and the non-light emitting area NEA), and does not necessarily have to be disposed in the transmissive area TA.

[0155] The semiconductor layer 123 may be disposed on the first insulating layer 103. The semiconductor layer 123 may include a metal oxide semiconductor such as indium-gallium-zinc oxide (IGZO), or a silicon-based semiconductor material such as amorphous silicon or polycrystalline silicon, but the embodiments herein are not limited thereto. The semiconductor layer 123 may include a source region, a drain region, and a channel region between the source region and the drain region.

[0156] A polycrystalline semiconductor layer has higher mobility than an amorphous semiconductor layer and an oxide semiconductor layer, and therefore has low power consumption and excellent reliability. Therefore, the driving transistor may be configured with a polycrystalline semiconductor layer, but the embodiments of this specification are not limited thereto.

[0157] A second insulating layer 104 may be disposed on the semiconductor layer 123. The second insulating layer 104 may be made of the same material as the first insulating layer 103, although embodiments herein are not limited thereto. The second insulating layer 104 may prevent or reduce short circuits between the semiconductor layer 123 and other components of the thin film transistor 120.

[0158] A gate electrode 122 may be disposed on the second insulating layer 104. The gate electrode 122 may be disposed on the second insulating layer 104 so as to overlap a channel region of the semiconductor layer 123. The gate electrode 122 may be composed of a single layer or multiple layers including molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or a compound thereof, although embodiments herein are not limited thereto. The gate electrode 122 may be disposed together with a gate line, although embodiments herein are not limited thereto.

[0159] A third insulating layer 105 may be disposed on the gate electrode 122. The third insulating layer 105 may be made of the same material as the first insulating layer 103 or the second insulating layer 104, although embodiments herein are not limited thereto.

[0160] The storage electrode 140 may be disposed to be spaced apart from the thin film transistor 120. The storage electrode 140 may include a first storage electrode 141 and a second storage electrode 142.

[0161] The storage electrode 140 is disposed in the area where the pixels PX are disposed (the light-emitting area EA and the non-light-emitting area NEA), and may not be disposed in the transmissive area TA.

[0162] The first storage electrode 141 may be disposed in the same layer as the gate electrode 122 and made of the same material, although embodiments herein are not limited thereto.

[0163] A second storage electrode 142 may be disposed on the first storage electrode 141. The second storage electrode 142 may be disposed on the third insulating layer 105, and a capacitance may be formed between the first storage electrode 141 and the second storage electrode 142 using the third insulating layer 105 as a dielectric. The second storage electrode 142 may be made of the same material as the first storage electrode 141, but the embodiment of the present specification is not limited thereto.

[0164] A fourth insulating layer 106 may be disposed on the second storage electrode 142. The fourth insulating layer 106 may be made of the same material as the first insulating layer 103, the second insulating layer 104, or the third insulating layer 105, although embodiments herein are not limited thereto.

[0165] A source electrode 121 and a drain electrode 124 may be disposed on the fourth insulating layer 106 .

[0166] The source electrode 121 and the drain electrode 124 may be electrically connected to the semiconductor layer 123 through contact holes. At least one of the source electrode 121 and the drain electrode 124 may be in contact with the light-shielding layer 126 through a contact hole. For example, the source electrode 121 may be in contact with the light-shielding layer 126 through a contact hole.

[0167] The source electrode 121 and the drain electrode 124 may be formed of a metal material. For example, the source electrode 121 and the drain electrode 124 may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but the embodiment of the present specification is not limited thereto.

[0168] The source electrode 121 and the drain electrode 124 may be disposed together with the data line. For example, the data line may be formed in the same layer as the source electrode 121 and the drain electrode 124 from the same material, although embodiments herein are not limited thereto.

[0169] The thin film transistor 120 may be a driving transistor, and although not shown, the display panel 100 may further include a switching transistor, although embodiments herein are not limited thereto.

[0170] A first protective layer 111 may be disposed on the source electrode 121 and the drain electrode 124 .

[0171] The first protective layer 111 can planarize the top of the thin film transistor 120 and protect the thin film transistor 120. The first protective layer 111 may be made of an organic material. For example, the first protective layer 111 may be made of an organic material including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin, but the embodiments of the present specification are not limited thereto.

[0172] A second protective layer 112 may be disposed on the first protective layer 111. The second protective layer 112 may be formed from the same material as the first protective layer 111, although embodiments herein are not limited thereto.

[0173] A connection electrode 145 may be disposed between the first protective layer 111 and the second protective layer 112.

[0174] The connection electrodes 145 are arranged in the areas where the pixels PX are arranged (the light-emitting areas EA and the non-light-emitting areas NEA), and may not be arranged in the transmissive areas TA.

[0175] The connection electrode 145 can electrically connect the thin film transistor 120 and the light emitting unit 150. The connection electrode 145 may be made of the same material as the source electrode 121 and the drain electrode 124, but the embodiment of the present specification is not limited thereto.

[0176] The connection electrode 145 may be in contact with the drain electrode 124 through a contact hole formed in the first protective layer 111, and may be electrically connected to each other.

[0177] The connection electrode 145 may be a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof, although embodiments herein are not limited thereto.

[0178] The light-emitting unit 150 may be disposed on the second protective layer 112. The light-emitting unit 150 may include an anode electrode 151, an organic layer 152, and a cathode electrode 153.

[0179] The anode electrode 151 and the organic layer 152 are disposed in the region where the pixels PX are disposed (the luminescent region EA and the non-luminescent region NEA), and may not be disposed in the transmissive region TA. The cathode electrode 153 may be disposed across the region where the pixels PX are disposed (the luminescent region EA and the non-luminescent region NEA) and the transmissive region TA. The cathode electrode 153 may be disposed across the entire display region DA.

[0180] An anode electrode 151 may be disposed on the second protective layer 112. The anode electrode 151 may be electrically connected to the thin film transistor 120 via contact holes formed in the first protective layer 111 and the second protective layer 112.

[0181] The anode electrode 151 may be a reflective electrode that reflects light, but the embodiment of the present specification is not limited thereto. The anode electrode 151 may include a metal material with high reflectivity, such as a laminated structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a laminated structure of aluminum (Al) and ITO (ITO / Al / ITO), or an APC alloy, and may be configured as a single layer or multiple layers, but the embodiment of the present specification is not limited thereto.

[0182] An organic layer 152 may be disposed on the anode electrode 151. The organic layer 152 may include one or more light-emitting structures (or light-emitting elements or devices) stacked on the anode electrode 151 in this order or the reverse order of a hole transport layer and an electron transport layer. For example, the hole transport layer may include a hole transport layer, a hole injection layer, an electron blocking layer, a P-type charge generation layer, or the like, but the embodiments herein are not limited thereto. For example, the electron transport layer may include an electron transport layer, an electron injection layer, a hole blocking layer, or an N-type charge generation layer, but the embodiments herein are not limited thereto.

[0183] The organic layer 152 may be an organic light-emitting layer, an inorganic light-emitting layer, a quantum dot light-emitting layer, a micro light-emitting diode, or a micro mini light-emitting diode, but the embodiment of the present specification is not limited thereto. For example, the organic layer 152 of the display panel 100 according to an embodiment of the present specification may include an organic light-emitting layer. The organic layer 152 may include a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer, but the embodiment of the present specification is not limited thereto. The organic layer 152 may further include a white light-emitting layer, but the embodiment of the present specification is not limited thereto.

[0184] A cathode electrode 153 may be disposed on the organic layer 152. The cathode electrode 153 may be a transparent electrode that transmits light, but the embodiment of the present specification is not limited thereto. For example, the cathode electrode 153 may include a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or a metal that transmits visible light, but the embodiment of the present specification is not limited thereto.

[0185] A capping layer 156 may be further disposed on the cathode electrode 153. The capping layer 156 may minimize or reduce damage from an external light source to the cathode electrode 153 of the light-emitting element (EL) and the organic layer 152 below the cathode electrode 153. The capping layer 156 may be formed of an organic or inorganic film.

[0186] The capping layer 156 may be formed using a material such as LiF as an inorganic film, or may further include an organic film, but the embodiment of the present specification is not limited thereto. For example, the capping layer 156 may be formed of a laminated structure of an organic film and an inorganic film, and the thickness of the organic film and the thickness of the inorganic film may be different. In this case, the thickness of the organic film may be greater than the thickness of the inorganic film. As another example, the capping layer 156 may be formed of two or more layers by laminating materials with different refractive indices. This may improve the light efficiency of the display panel 100.

[0187] The banks 154 may be arranged to expose the anode electrodes 151. The banks 154 may be arranged to define openings (or light-emitting areas EA) of the subpixels SP1, SP2, and SP3 and to cover the edges of the anode electrodes 151. The banks 154 may be arranged at the boundaries between the adjacent subpixels SP1, SP2, and SP3.

[0188] The organic layer 152 may be disposed within the opening of the subpixel SP. In other words, the organic layer 152 may be disposed on the anode electrode 151 exposed by the bank 154.

[0189] The bank 154 may be made of a material containing a black pigment or an organic material such as a benzocyclobutene resin, a polyimide resin, an acrylic resin, or a photosensitive polymer, but the embodiments of the present specification are not limited thereto. When the bank 154 is made of a material containing a black pigment or a black dye, it may be a black bank. When the bank 154 is made of a material containing a black pigment or a black dye, it can block external light or light reflected from the outside, thereby further improving the brightness of the display device.

[0190] The bank 154 is disposed in the area where the pixels PX are disposed (the luminous area EA and the non-luminous area NEA), and does not necessarily have to be disposed in the transmissive area TA.

[0191] Spacers (not shown) may be further disposed on the banks 154. The spacers (not shown) may be made of the same material as the banks 154, but the embodiment of the present specification is not limited thereto. The spacers (not shown) may prevent or reduce sagging of the mask during the mask process, thereby suppressing or preventing defects such as dents and scratches on the display panel 100.

[0192] An encapsulating unit 170 may be disposed on the bank 154 or the light-emitting unit 150. The encapsulating unit 170 may include one or more insulating layers. For example, the encapsulating unit 170 may include a first inorganic encapsulating layer 171, an organic encapsulating layer 172 on the first inorganic encapsulating layer 171, and a second inorganic encapsulating layer 173 on the organic encapsulating layer 172. The encapsulating unit 170 may include one or more inorganic material layers and one or more organic material layers. For example, the first inorganic encapsulating layer 171 and the second inorganic encapsulating layer 173 may include an inorganic material, and the organic encapsulating layer 172 may include an organic material, although embodiments herein are not limited thereto.

[0193] Even if the first inorganic sealing layer 171 and the second inorganic sealing layer 173 are arranged to extend to the edge of the non-display area NDA, the organic sealing layer 172 may be terminated inside the dam portion DMP. In other words, the organic sealing layer 172 may be arranged inside the area surrounded by the dam portion DMP without extending beyond the dam portion DMP.

[0194] A touch unit 180 may be disposed on the encapsulation unit 170. The touch unit 180 may include a touch buffer layer 181, a first touch electrode 182, a first touch insulation layer 183, a black matrix BM, a second touch insulation layer 184, a second touch electrode 185, and a third touch insulation layer 186.

[0195] A touch buffer layer 181 may be disposed on the encapsulation portion 170. For example, the touch buffer layer 181 may be disposed on the second inorganic encapsulation layer 173. The touch buffer layer 181 may be made of the same material as the buffer layer 102, although embodiments herein are not limited thereto.

[0196] On the touch buffer layer 181, a first touch electrode 182 may be disposed.

[0197] A first touch insulating layer 183 may be disposed on the first touch electrode 182. The first touch insulating layer 183 may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof, but embodiments herein are not limited thereto.

[0198] A black matrix BM may be disposed on the first touch insulating layer 183. The black matrix BM may include a material capable of absorbing light. The black matrix BM may include, but is not limited to, a black pigment or dye. The black matrix BM may prevent or reduce light leakage defects that may occur between the sub-pixels SP.

[0199] A second touch insulating layer 184 may be disposed on the black matrix BM. The second touch insulating layer 184 may include an organic insulating material. For example, the second touch insulating layer 184 may be made of, but is not limited to, photo acryl, benzocyclobutene (BCB), polyimide (PI), or polyamide (PA).

[0200] A second touch electrode 185 may be disposed on the second touch insulating layer 184. The second touch electrode 185 may include a 1a touch electrode 185a extending in a first direction DR1 and a 1b touch electrode 185b extending in a second direction DR2 different from the first direction.

[0201] The first touch electrode 182 may be electrically connected to the second touch electrode 185a through a contact hole formed in the second touch insulating layer 184. For example, the second touch electrode 185a and the first touch electrode 182 may extend in a first direction DR1.

[0202] The first touch electrode 182 and the second touch electrode 185 may include a metal material. For example, the first touch electrode 182 and the second touch electrode 185 may be made of titanium (Ti), nickel (Ni), aluminum (Al), or an alloy thereof, or may be made of three layers such as titanium (Ti) / aluminum (Al) / titanium (Ti), but the embodiments herein are not limited thereto.

[0203] One of the first touch electrode 182 and the second touch electrode 185 may have a touch sensing function, and the other may have a touch driving function, but is not limited thereto.

[0204] A third touch insulating layer 186 may be disposed on the second touch electrode 185. The third touch insulating layer 186 may include the same material as the first touch insulating layer 183, but is not limited to this.

[0205] Microlenses ML1 and ML2 may be disposed on the third touch insulating layer 186. The first microlens ML1 may be disposed in the transmissive region TA, and the second microlens ML2 may be disposed for each of the sub-pixels SP1, SP2, and SP3. The first microlens ML1 and the second microlens ML2 may be disposed on the same layer, but are not limited to this.

[0206] By arranging the first microlens ML1 in the transmissive region TA, the first microlens ML1 can collect the light L incident from outside in the transmissive region TA, thereby increasing the amount of light L that penetrates the display panel 100. Furthermore, more light L can be incident on the light receiving sensor 200 arranged in the transmissive region TA, allowing the light receiving sensor 200 to sense the light L more smoothly.

[0207] A lens protection film 190 may be disposed on the microlenses ML1 and ML2. The lens protection film 190 may include, but is not limited to, an organic insulating material. The lens protection film 190 can protect the microlenses ML1 and ML2 by covering the microlenses ML1 and ML2. The refractive index of the lens protection film 190 may be smaller than the refractive index of the microlenses ML1 and ML2. This makes it possible to prevent or reduce reflection of light that has passed through the microlenses ML1 and ML2 toward the substrate 101 due to the difference in refractive index between the microlenses ML1 and ML2 and the lens protection film 190.

[0208] The following describes the cross-sectional structure of the non-display area NDA of the display device 1. Contents that are the same as those described in the cross-sectional structure of the display area DA will be explained briefly or omitted.

[0209] Fig. 9 is a cross-sectional view taken along line A-A' in Fig. 1. Fig. 10 is a cross-sectional view taken along line B-B' in Fig. 3. Fig. 11 is a cross-sectional view taken along line CC' in Fig. 3.

[0210] Fig. 9 shows the cross-sectional structure of the first non-display area NDA1. Fig. 10 and Fig. 11 show the cross-sectional structure of the second non-display area NDA2. Fig. 10 and Fig. 11 show the cross-section of the notched non-display area N_NDA of the second non-display area NDA2, but the description thereof can be applied substantially identically to the extended non-display area E_NDA.

[0211] 1, 3, 5, and 9 to 11, the display panel 100 may further include a gate control transistor G120 arranged in the non-display area NDA, a low potential voltage line VSSL, a dam portion DMP, a plurality of pads VSSP, VDDP, DP arranged in the pad area PA, data lines DL: DL1, DL2, and a crack reduction pattern CSP.

[0212] The gate control transistor G120 has substantially the same configuration as the thin film transistor 120 of the sub-pixel SP, and may be formed together with the thin film transistor 120 of the sub-pixel SP in the same process, but is not limited to this.

[0213] The gate-controlled transistor G120 may include a control source electrode G121, a control gate electrode G122, a control semiconductor layer G123, and a control drain electrode G124.

[0214] A light-shielding layer (not shown) may be further disposed under the gate-controlled transistor G120. Either the control source electrode G121 or the control drain electrode G124 may be in contact with the light-shielding layer (not shown) and electrically connected thereto, but is not limited to this.

[0215] The low potential voltage line VSSL may be disposed on the fourth insulating layer 106. The low potential voltage line VSSL may be formed from the same metal layer as the source electrode 121 and the drain electrode 124 of the thin film transistor 120, but is not limited to this.

[0216] The display panel 100 may further include a low potential connecting electrode CE, which can connect the low potential voltage line VSSL and the cathode electrode 153.

[0217] The low potential connecting electrode CE may be disposed on the second protective layer 112. A bank 154 may be disposed on the low potential connecting electrode CE. The low potential connecting electrode CE may be disposed in the same layer as the anode electrode 151, may contain the same material, and may be formed together with the anode electrode 151 using one mask in the same process, but is not limited to this.

[0218] The display panel 100 may further include an exposed portion OP. The exposed portion OP may expose at least a portion of the low potential voltage line VSSL by recessing the first protective layer 111 and the second protective layer 112.

[0219] The exposed portion OP can be defined by the first protective layer 111 and the second protective layer 112. The exposed portion OP can be defined by the side surface of the first protective layer 111, the side surface of the second protective layer 112, and the side surface of the second dam DM2.

[0220] The low potential connection electrode CE may be in contact with the low potential voltage line VSSL exposed at the exposed portion OP, and may be electrically connected to each other. At least a portion of the low potential connection electrode CE may be disposed on the second protective layer 112, and may thereby extend toward the low potential voltage line VSSL.

[0221] The low potential connection electrode CE may be further disposed on the side surfaces of the first protective layer 111 and the second protective layer 112 that define the exposed portion OP, and may also be further disposed on the fourth insulating layer 106 and the low potential voltage line VSSL exposed by the exposed portion OP, thereby allowing the low potential connection electrode CE to come into contact with the low potential voltage line VSSL.

[0222] The low potential connection electrode CE may be electrically connected to the cathode electrode 153. The low potential connection electrode CE and the cathode electrode 153 may be in contact with each other and electrically connected to each other through a low potential contact hole C_CNT in the overlapping region. The low potential contact hole C_CNT is defined through the bank 154 in the overlapping region of the low potential connection electrode CE and the cathode electrode 153, and can expose the low potential connection electrode CE.

[0223] The dam portion DMP may include a first dam DM1 and a second dam DM2. The first dam DM1 and the second dam DM2 may overlap the first low-potential voltage line VSSL1 or the second low-potential voltage line VSSL2.

[0224] In the second non-display area NDA2, the first dam DM1 and the second dam DM2 may overlap the first low potential voltage line VSSL1. In the first non-display area NDA1, the first dam DM1 and the second dam DM2 may overlap the second low potential voltage line VSSL2.

[0225] The first dam DM1 may be disposed outside the second dam DM2, but is not limited to this.

[0226] The first dam DM1 may have a multi-layer structure, and each layer of the first dam DM1 may contain the same material as the second protective layer 112 and the bank 154, and may be formed together using one mask in the same process, but is not limited to this.

[0227] The second dam DM2 may have a multi-layer structure, and each layer of the second dam DM2 may contain the same material as the bank 154 and the spacer (not shown) and may be formed together using one mask in the same process, but is not limited to this.

[0228] The crack reduction pattern CSP may be disposed on the outermost side of the non-display area NDA. The crack reduction pattern CSP can be defined by recessing at least one of the inorganic films disposed on the substrate 101.

[0229] For example, but not limited to, the crack reduction pattern CSP can be defined by recessing the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, and the fourth insulating layer .

[0230] A crack dummy pattern DUP may be further disposed on the crack reduction pattern CSP. The crack dummy pattern DUP can fill the recessed crack reduction pattern CSP. The crack dummy pattern DUP may be composed of multiple layers. For example, the crack dummy pattern DUP may be composed of three layers. Each layer of the crack dummy pattern DUP may contain the same material as the first protective layer 111, the second protective layer 112, and the bank 154.

[0231] The high-potential voltage line VDDL may be disposed on the buffer layer 102 and covered by the first insulating layer 103. The high-potential voltage line VDDL may include the same material as the light-shielding layer 126 and may be formed together with the light-shielding layer 126 using one mask in the same process, but is not limited to this.

[0232] Although not shown, the high potential voltage pad VDDP may be disposed in the same layer as the source electrode 121 and the drain electrode 124, may contain the same material, and may be formed together with one mask in the same process, but is not limited to this.

[0233] In this case, the high potential voltage pad VDDP may be in contact with the high potential voltage line VDDL via a high potential contact hole S_CNT that exposes the high potential voltage line VDDL, and may be electrically connected to each other.

[0234] However, without being limited thereto, the high potential voltage line VDDL may be disposed in the same layer as the source electrode 121 and the drain electrode 124, may contain the same material, and may be formed together with one mask in the same process.

[0235] The first data pad DP1 and the second data pad DP2 may be disposed on the fourth insulating layer 106. The first data pad DP1 and the second data pad DP2 may be disposed in the same layer as the source electrode 121 and the drain electrode 124, may include the same material, and may be formed together using one mask in the same process, but is not limited to this.

[0236] The first data line DL1 may be disposed on the second insulating layer 104 and covered by the third insulating layer 105. The first data line DL1 may include the same material as the gate electrode 122 and may be formed together with the gate electrode 122 using one mask in the same process, but is not limited to this.

[0237] The second data line DL2 may be disposed on the third insulating layer 105 and covered by the fourth insulating layer 106. The second data line DL2 may include the same material as the second storage electrode 142 and may be formed together with the second storage electrode 142 using one mask in the same process, but is not limited to this.

[0238] The first data line DL1 may contact the first data pad DP1 through the first data contact hole CNT1 and be electrically connected to each other, and the second data line DL2 may contact the second data pad DP2 through the second data contact hole CNT2 and be electrically connected to each other.

[0239] The crack reduction pattern CSP may be arranged outside the pad area PA. The crack reduction pattern CSP may be arranged between the pad area PA and the end of the second non-display area NDA2.

[0240] However, the pads VSSP, VDDP, and DP do not have to be covered by the inorganic films. The pads VSSP, VDDP, and DP may be exposed from the inorganic films disposed on the fourth insulating layer 106. The inorganic films disposed on the fourth insulating layer 106 do not have to be disposed in the pad area PA.

[0241] As a result, the flexible film COF may be attached to the display panel 100 so as to overlap at least a portion of the pad area PA, and the flexible film COF may be in contact with and electrically connected to the multiple pads VSSP, VDDP, and DP in the pad area PA.

[0242] Other embodiments of the present specification will be described below. Among the configurations included in the other embodiments, the same reference numerals will be used to designate the substantially same components as those described with reference to Figures 1 to 11, and the overlapping components may be omitted or simplified.

[0243] Fig. 12 is an enlarged plan view of the periphery of a pixel of a display device according to another embodiment, and Fig. 13 is a cross-sectional view taken along line FF' in Fig. 12.

[0244] 12 and 13, the display panel 100_1 of the display device according to this embodiment includes the first microlens ML1, but may not include the second microlens ML2 (see FIG. 4).

[0245] In the display panel 100_1 according to this embodiment, the first microlens ML1 is arranged in the transmission region TA, but the second microlens ML2 (see FIG. 4) does not have to be arranged in each of the sub-pixels SP1, SP2, and SP3 of each pixel PX.

[0246] The first microlenses ML1 of the display panel 100_1 according to this embodiment may be arranged to extend along the transmissive region TA.

[0247] Even in this case, by arranging the first microlenses ML1 in the transmission regions TA, light incident on the display panel 100_1 from the outside can be collected in the transmission regions TA, and the amount of light passing through the display panel 100_1 can be increased.

[0248] By disposing the transmissive region TA in the display region DA, the light transmittance of the transmissive region TA can be improved, and the shape, size, and arrangement of the light-receiving sensor 200 (see FIG. 1) can be designed in a variety of ways. Furthermore, the process can be performed more efficiently while ensuring the path of light incident on the light-receiving sensor 200, thereby reducing production energy.

[0249] Furthermore, since the second microlens ML2 is omitted, the costs required for the process can be reduced and the process can be further simplified, thereby improving the process efficiency.

[0250] Fig. 14 is an enlarged plan view of the periphery of a pixel of a display device according to another embodiment, and Fig. 15 is a cross-sectional view taken along line FF' in Fig. 14.

[0251] 14 and 15, a display panel 100_2 of the display device according to this embodiment includes a first microlens ML1_2 and a second microlens ML2, and a plurality of first microlenses ML1_2 may be provided.

[0252] The display panel 100_2 may include a plurality of first microlenses ML1_2. The plurality of first microlenses ML1_2 may be repeatedly arranged along the extension direction of the transmissive region TA. For example, when the transmissive region TA extends between the pixels PX in the first direction DR1 and the second direction DR2, the plurality of first microlenses ML1_2 may be arranged in the transmissive region TA and repeatedly arranged along the first direction DR1 and the second direction DR2.

[0253] Each of the first microlenses ML1_2 may have a rounded surface. For example, the surface of the first microlens ML1_2 may have a dome shape, but is not limited to this. The first microlens ML1_2 may have a round shape in cross section. For example, the first microlens ML1_2 may have a semi-spherical or semi-elliptical shape, etc., in cross section, but is not limited to this.

[0254] Even in this case, by arranging the first microlenses ML1_2 in the transmission regions TA, light incident on the display panel 100_2 from the outside can be collected in the transmission regions TA, and the amount of light passing through the display panel 100_2 can be increased.

[0255] Furthermore, by forming each of the plurality of first microlenses ML1_2 in a dome shape, light incident on the display panel 100_2 from various directions can be collected more smoothly, and the amount of light penetrating the display panel 100_2 can be further increased.

[0256] By disposing the transmissive region TA in the display region DA, the light transmittance of the transmissive region TA can be improved, and the shape, size, and arrangement of the light-receiving sensor 200 (see FIG. 1) can be designed in a variety of ways. Furthermore, the process can be performed more efficiently while ensuring the path of light incident on the light-receiving sensor 200, thereby reducing production energy.

[0257] Fig. 16 is an enlarged plan view of the periphery of a pixel of a display device according to another embodiment, and Fig. 17 is a cross-sectional view taken along line HH' in Fig. 16.

[0258] 16 and 17, the display panel 100_3 of the display device according to this embodiment includes a first microlens ML1 and a second microlens ML2, and the centers EC1 and EC2 of the light-emitting area EA and the centers LC1 and LC2 of the second microlens ML2 may be misaligned with each other, and each pixel PX1 and PX2 may emit light L1 and L2 in different directions.

[0259] The display panel 100_3 may include a first pixel PX1 and a second pixel PX2 in the display area DA.

[0260] The first pixels PX1 and the second pixels PX2 may be repeatedly arranged along the first direction DR1, and the first pixels PX1 and the second pixels PX2 may be repeatedly arranged alternately along the second direction DR2.

[0261] The subpixels SP may include a 1_1 subpixel SP1_1, a 1_2 subpixel SP1_2, a 1_3 subpixel SP1_3, a 1_4 subpixel SP1_4, a 2_1 subpixel SP2_1, a 2_2 subpixel SP2_2, and a 2_3 subpixel SP2_3.

[0262] The first pixel PX1 may include a 1_1 subpixel SP1_1, a 1_2 subpixel SP1_2, a 1_3 subpixel SP1_3, and a 1_4 subpixel SP1_4. The 1_1 subpixel SP1_1, the 1_2 subpixel SP1_2, the 1_3 subpixel SP1_3, and the 1_4 subpixel SP1_4 may be arranged side by side along the first direction.

[0263] The 1_1 sub-pixel SP1_1 may emit red light, the 1_2 sub-pixel SP1_2 may emit green light, the 1_3 sub-pixel SP1_3 may emit blue light, and the 1_4 sub-pixel SP1_4 may emit red light.

[0264] Each of the 1_1 subpixel SP1_1, the 1_2 subpixel SP1_2, the 1_3 subpixel SP1_3, and the 1_4 subpixel SP1_4 may include an emitting region EA1_1, EA1_2, EA1_3, EA1_4, and a non-emitting region NEA1_1, NEA1_2, NEA1_3, NEA1_4 arranged around the emitting regions EA1_1, EA1_2, EA1_3, EA1_4.

[0265] The 1_1 sub-pixel SP1_1 may include a 1_1 light-emitting region EA1_1 and a 1_1 non-light-emitting region NEA1_1 disposed around the 1_1 light-emitting region EA1_1.

[0266] The 1_2 sub-pixel SP1_2 may include a 1_2 light-emitting region EA1_2 and a 1_2 non-light-emitting region NEA1_2 arranged around the 1_2 light-emitting region EA1_2.

[0267] The 1_3 sub-pixel SP1_3 may include a 1_3 light-emitting region EA1_3 and a 1_3 non-light-emitting region NEA1_3 arranged around the 1_3 light-emitting region EA1_3.

[0268] The 1_4th sub-pixel SP1_4 may include a 1_4th light-emitting region EA1_4 and a 1_4th non-light-emitting region NEA1_4 arranged around the 1_4th light-emitting region EA1_4.

[0269] The second pixel PX2 may include a 2_1 sub-pixel SP2_1, a 2_2 sub-pixel SP2_2, and a 2_3 sub-pixel SP2_3. The 2_1 sub-pixel SP2_1, the 2_2 sub-pixel SP2_2, and the 2_3 sub-pixel SP2_3 may be arranged side by side along the second direction.

[0270] The 2_1 sub-pixel SP2_1 may emit blue light, the 2_2 sub-pixel SP2_2 may emit red light, and the 2_3 sub-pixel SP2_3 may emit green light.

[0271] The 2_1 subpixel SP2_1, the 2_2 subpixel SP2_2, and the 2_3 subpixel SP2_3 may each include light-emitting regions EA2_1, EA2_2, and EA2_3, and non-light-emitting regions NEA2_1, NEA2_2, and NEA2_3 arranged around the light-emitting regions EA2_1, EA2_2, and EA2_3.

[0272] The 2_1 sub-pixel SP2_1 may include a 2_1 light-emitting region EA2_1 and a 2_1 non-light-emitting region NEA2_1 disposed around the 2_1 light-emitting region EA2_1.

[0273] The 2_2 sub-pixel SP2_2 may include a 2_2 light-emitting region EA2_2 and a 2_2 non-light-emitting region NEA2_2 arranged around the 2_2 light-emitting region EA2_2.

[0274] The 2_3 sub-pixel SP2_3 may include a 2_3 light-emitting region EA2_3 and a 2_3 non-light-emitting region NEA2_3 disposed around the 2_3 light-emitting region EA2_3.

[0275] In plan view, no sub-pixel may be arranged below the 1_1 sub-pixel SP1_1 (the other side in the second direction DR2), and this may be a non-light-emitting area NEA. However, this is not limitative, and a sub-pixel may be arranged therein.

[0276] In plan view, the 2_1 sub-pixel SP2_1 may be arranged below the 1_2 sub-pixel SP1_2 (on the other side in the second direction DR2).

[0277] In plan view, the 2_2 sub-pixel SP2_2 may be arranged below the 1_3 sub-pixel SP1_3 (on the other side in the second direction DR2).

[0278] In plan view, the 2_3 sub-pixel SP2_3 may be arranged below the 1_4 sub-pixel SP1_4 (on the other side in the second direction DR2).

[0279] A transmissive region TA may be disposed between the adjacent pixels PX1 and PX2. The transmissive region TA may be disposed between the non-light-emitting regions NEA of the adjacent pixels PX1 and PX2.

[0280] The light transmittance of the transmissive region TA may be higher than the light transmittance of the region in which the pixels PX1 and PX2 are arranged.

[0281] A first microlens ML1 may be disposed in the transmissive region TA. The first microlens ML1 can collect light entering from the outside toward the display panel 100_3, and can increase the amount of light passing through the display panel 100_3.

[0282] A second microlens ML2 may be disposed above each of the pixels PX1 and PX2. The second microlens ML2 may be disposed for each of the sub-pixels SP: SP1_1, SP1_2, SP1_3, SP1_4, SP2_1, SP2_2, and SP2_3.

[0283] Although the second microlens ML2 is illustrated as being arranged for each subpixel SP, this is not limiting. For example, depending on the design of each subpixel SP, two or more second microlenses ML2 may be provided for each subpixel SP.

[0284] The centers LC1 and LC2 of the second microlenses ML2 may be misaligned with the centers EC1 and EC2 of the corresponding light-emitting areas EA. Nevertheless, some components of the light-emitting unit 150 may be tilted, so that light emitted from the light-emitting areas EA of each subpixel SP can be directed toward the second microlenses ML2.

[0285] The second protective layer 112 may be formed so that a partial region of the upper surface has an inclined surface. The inclined surface of the second protective layer 112 may be inclined in the thickness direction (third direction DR3) of the display panel 100_3.

[0286] At least a portion of the light-emitting unit 150 may be disposed on the inclined surface of the second protective layer 112. As a result, at least a portion of the anode electrode 151 and the organic layer 152 may be inclined (or tilted). At least a portion of the anode electrode 151 and the organic layer 152 may be tilted toward the second microlens ML2 in each pixel PX1, PX2.

[0287] Specifically, each of the anode electrode 151 and the organic layer 152 may be disposed on the second protective layer 112 having at least a partial area that is inclined. Each of the anode electrode 151 and the organic layer 152 may be disposed on the second protective layer 112 having the entire area that is inclined, but is not limited to this.

[0288] The anode electrode 151 and the organic layer 152 disposed on the inclined second protective layer 112 may be disposed so as to be inclined (tilted) in accordance with the inclined second protective layer 112. As a result, a partial region of the cathode electrode 153 disposed on the organic layer 152 may be disposed so as to be inclined.

[0289] For example, the anode electrode 151 and the organic layer 152 may be arranged in the first_1 light-emitting region EA1_1 and the second_1 light-emitting region EA2_1 and their peripheries so as to be inclined in the thickness direction (third direction DR3) of the display panel 100_3. That is, the directions in which the upper surfaces of the anode electrode 151 and the organic layer 152 face may be inclined with respect to the thickness direction (third direction DR3) of the display panel 100_3.

[0290] As a result, the light emitted from each sub-pixel SP may be inclined with respect to the thickness direction (third direction DR3) of the display panel 100_3.

[0291] The directions of the inclined anode electrodes 151 and organic layers 152 in the first_1 light emitting region EA1_1 and the second_1 light emitting region EA2_1 and their peripheries may be different from each other.

[0292] In Figure 17, the anode electrode 151 and organic layer 152 around the 1_1 light-emitting area EA1_1 of the 1_1 sub-pixel SP1_1 and the 2_1 light-emitting area EA2_1 of the 2_1 sub-pixel SP2_1 are described, but this description can be applied to all sub-pixels SP.

[0293] The center EC1 of the 1_1 light-emitting region EA1_1 of the 1_1 sub-pixel SP1_1 may be misaligned with the center LC1 of the second microlens ML2 disposed on the 1_1 sub-pixel SP1_1. In plan view, the center LC1 of the second microlens ML2 may be misaligned to the other side (left side in plan view) in the first direction DR1 from the center EC1 of the 1_1 light-emitting region EA1_1.

[0294] The description of the misalignment of the 1_1 subpixel SP1_1 can be substantially applied to the remaining subpixels SP1_2, SP1_3, and SP1_4 of the first pixel PX1, except that the degree of misalignment between the second microlens ML2 and the light-emitting area EA may differ among the subpixels SP1_1, SP1_2, SP1_3, and SP1_4 of the first pixel PX1.

[0295] However, the present invention is not limited to this, and the direction in which the center LC1 of the second microlens ML2 and the center EC1 of the first_1 light-emitting area EA1_1 are misaligned may vary depending on the design.

[0296] The center EC2 of the 2_1 light-emitting region EA2_1 of the 2_1 subpixel SP2_1 may be misaligned with the center LC2 of the second microlens ML2 disposed on the 2_1 subpixel SP2_1. In plan view, the center LC2 of the second microlens ML2 may be misaligned to one side (right side in plan view) in the first direction DR1 from the center EC2 of the 2_1 light-emitting region EA2_1.

[0297] The description of the misalignment of the 2_1 subpixel SP2_1 can be substantially applied to the remaining subpixels SP2_2 and SP2_3 of the second pixel PX2. However, the degree of misalignment between the second microlens ML2 and the light-emitting area EA may differ between the subpixels SP2_1, SP2_2, and SP2_3 of the second pixel PX2.

[0298] However, the present invention is not limited to this, and the direction in which the center LC2 of the second microlens ML2 and the center EC2 of the 2_1 light-emitting area EA2_1 are misaligned may vary depending on the design.

[0299] The opening (or light-emitting area EA) of the sub-pixel SP and the light-emitting section 150 arranged around it may be arranged at an angle with respect to the thickness direction (third direction DR3), and the light L1, L2 emitted from the light-emitting section 150 may be directed in a direction at an angle with respect to the thickness direction (third direction DR3).

[0300] By misaligning the second microlens ML2 and the light emitting area EA, even if the light L1 and L2 emitted from the light emitting section 150 travels at an angle in the thickness direction (third direction DR3), each light L1 and L2 can travel toward the second microlens ML2.

[0301] The sub-pixels SP1_1, SP1_2, SP1_3, and SP1_4 arranged in the first pixel PX1 can emit light L1 to the left side in a plan view (the other side in the first direction DR1), and the sub-pixels SP2_1, SP2_2, and SP2_3 arranged in the second pixel PX2 can emit light L2 to the right side in a plan view (one side in the first direction DR1).

[0302] In other words, the light L1 emitted from the sub-pixels SP1_1, SP1_2, SP1_3, and SP1_4 of the first pixel PX1 may travel at an angle inclined toward the other side of the first direction DR1 with respect to the thickness direction (third direction DR3). The light L2 emitted from the sub-pixels SP2_1, SP2_2, and SP2_3 of the second pixel PX2 may travel at an angle inclined toward one side of the first direction DR1 with respect to the thickness direction (third direction DR3).

[0303] The direction and degree of misalignment between the second microlens ML2 and the light emitting area EA can vary depending on the traveling direction of the light emitted from the sub-pixels SP of each of the pixels PX1 and PX2.

[0304] In a plan view, the sub-pixels SP1_1, SP1_2, SP1_3, and SP1_4 arranged in the first pixel PX1 and the sub-pixels SP2_1, SP2_2, and SP2_3 arranged in the second pixel PX2 may emit light in different directions, thereby making it possible to distinguish between the screen displayed to the driver (DRIVER) sitting in the driver's seat and the screen displayed to the passenger (PASSENGER) sitting in the passenger seat and control each separately, thereby making it possible to display different screens to the driver (DRIVER) and the passenger (PASSENGER).

[0305] In this case as well, by arranging the first microlenses ML1 in the transmission regions TA, light incident on the display panel 100_3 from the outside can be collected in the transmission regions TA, and the amount of light passing through the display panel 100_3 can be increased.

[0306] By disposing the transmissive region TA in the display region DA, the light transmittance of the transmissive region TA can be improved, and the shape, size, and arrangement of the light-receiving sensor 200 (see FIG. 1) can be designed in a variety of ways. Furthermore, the process can be performed more efficiently while ensuring the path of light incident on the light-receiving sensor 200, thereby reducing production energy.

[0307] Fig. 18 is a plan view of a display device according to another embodiment. Fig. 19 is an enlarged view of region Q2 in Fig. 18. Fig. 20 is a cross-sectional view taken along line K-K' in Fig. 19. Fig. 21 is a plan view showing a pixel arrangement of a display device according to another embodiment.

[0308] FIG. 19 is a diagram of the Q2 region of a display device 1_4 according to another embodiment, in which the flexible film COF, the main substrate MB, and the driving IC DIC are omitted.

[0309] Referring to Figures 18 to 21, in the display device 1_4 of this embodiment, a separate gate driver GIP (see Figure 1) may not be arranged in the non-display area NDA, and the pixel gate driver GIA may be arranged in the display area DA.

[0310] A plurality of pixel gate drivers GIA may be provided, and each pixel gate driver GIA may be connected to a respective one of the plurality of pixels PX. The pixel gate drivers GIA may be arranged around the pixels PX. The pixel gate drivers GIA may be arranged between adjacent pixels PX.

[0311] For example, the pixel gate driver GIA may be disposed between adjacent pixels PX in the first direction DR1. The pixels PX and the pixel gate driver GIA may be disposed alternately and repeatedly along the first direction DR1. The pixels PX may be disposed consecutively and repeatedly along the second direction DR2. The pixel gate driver GIA may be disposed consecutively and repeatedly along the second direction DR2.

[0312] The pixel gate driver GIA can perform substantially the same function as the gate driver GIP (see FIG. 1). The pixel gate driver GIA may include at least one transistor.

[0313] The pixel gate driver GIA may be electrically connected to the adjacent pixels PX.

[0314] The pixel gate driver GIA receives a gate control signal from the driver IC DIC via the gate control line GCL_4. The pixel gate driver GIA generates a scan signal and an emission signal (or an emission control signal) based on the gate control signal, thereby controlling the driving of the adjacent pixel PX.

[0315] By disposing the pixel gate driver GIA in the display area DA, the non-display area NDA or bezel area can be minimized or reduced, providing users with an improved aesthetic experience.

[0316] The display device 1_4 may further include a gate control line GCL_4 and a gate control pad GCP.

[0317] The gate control line GCL_4 may be disposed in the non-display area NDA. The gate control line GCL_4 may be disposed in the second non-display area NDA2, but is not limited to this. The gate control line GCL_4 may be disposed along the extension direction of the second non-display area NDA2.

[0318] The gate control line GCL_4 may be electrically connected to a plurality of pixel gate drivers GIA arranged in the display area DA.

[0319] The gate control pad GCP may be arranged in the pad area PA. In the pad area PA, the gate control pad GCP is shown to be arranged between the high potential voltage pad VDDP and the data pad DP, but is not limited to this, and the arrangement position of the gate control pad GCP may be changed depending on the design.

[0320] The gate control pad GCP may include, but is not limited to, the same material as the gate control line GCL_4, and the gate control pad GCP and the gate control line GCL_4 may be integrally formed, but is not limited to this.

[0321] The gate control pad GCP and the gate control line GCL_4 may be disposed on the fourth insulating layer 106. The gate control pad GCP and the gate control line GCL_4 may be disposed in the same layer as the source electrode 121 (see FIG. 5) and the drain electrode 124 (see FIG. 5), may include the same material, and may be formed together using one mask in the same process, but is not limited to this.

[0322] The pads VSSP, VDDP, DP, and GCP may not be covered by the inorganic films. The pads VSSP, VDDP, DP, and GCP may be exposed by the inorganic films disposed on the fourth insulating layer 106. The inorganic films disposed on the fourth insulating layer 106 may not be disposed in the pad area PA.

[0323] This exposes the pads VSSP, VDDP, DP, and GCP arranged on the fourth insulating layer 106, and the display panel 100 can be electrically connected to the flexible film COF by being attached to the flexible film COF.

[0324] The display panel 100 of the display device 1_4 according to this embodiment may also include a transmissive region TA, a first microlens ML1, and a second microlens ML2.

[0325] The display panel 100 may further include a pixel group PXG including a pixel PX and a pixel gate driver GIA adjacent to the pixel PX.

[0326] The transmissive regions TA may be disposed between adjacent pixel groups PXG. The light transmittance of the transmissive regions TA may be higher than the light transmittance of the regions in which the pixel groups PXG are disposed.

[0327] The arrangement of the transmissive region TA and the first microlens ML1 is not limited to this. For example, the transmissive region TA and the first microlens ML1 may be further arranged between the pixel PX and the pixel gate driver GIA of one pixel group PXG.

[0328] The first microlens ML1 may be disposed in the transmissive region TA, and the second microlens ML2 may be disposed for each of the sub-pixels SP1, SP2, and SP3.

[0329] In this case as well, by arranging the first microlenses ML1 in the transmission regions TA, light incident on the display panel 100_4 from the outside can be collected in the transmission regions TA, and the amount of light passing through the display panel 100_4 can be increased.

[0330] By disposing the transmissive region TA in the display region DA, the light transmittance of the transmissive region TA can be improved, and the shape, size, and arrangement of the light-receiving sensor 200 (see FIG. 1) can be designed in a variety of ways. Furthermore, the process can be performed more efficiently while ensuring the path of light incident on the light-receiving sensor 200, thereby reducing production energy.

[0331] In addition, since the pixel gate driver GIA is disposed within the display area DA, the bezel area may be reduced and the size of the display area DA may be increased.

[0332] The display device according to various embodiments herein can be described as follows.

[0333] A display device according to an embodiment of the present specification includes a substrate including a display area including a plurality of pixels and transmissive areas between adjacent pixels, and a non-display area around the display area, a thin-film transistor arranged on the substrate, a first protective layer on the thin-film transistor, a connection electrode electrically connected to the thin-film transistor on the first protective layer, a second protective layer on the connection electrode, a light-emitting portion on the second protective layer, and a first microlens on the light-emitting portion, wherein the first microlens is arranged in the transmissive area.

[0334] According to various embodiments herein, the light receiving sensor may be disposed below the substrate and overlap the transmissive region.

[0335] According to various embodiments herein, thin film transistors may not be disposed on the transmissive areas.

[0336] According to various embodiments herein, the light-emitting portion includes an anode electrode disposed for each pixel, an organic layer on the anode electrode, and a cathode electrode on the organic layer, and the anode electrode does not have to be disposed on the transmissive region.

[0337] According to various embodiments herein, each pixel includes a plurality of sub-pixels, and may further include a second microlens disposed on the light-emitting portion for each of the plurality of sub-pixels.

[0338] According to various embodiments herein, the first microlens and the second microlens may be disposed in the same layer.

[0339] According to various embodiments herein, the device may further include a bank between the anode electrode and the organic layer, and the bank may not be located on the transmissive region.

[0340] According to various embodiments herein, the banks may be located at the boundaries between adjacent sub-pixels.

[0341] According to various embodiments herein, the sub-pixel includes a light-emitting region and a non-light-emitting region surrounding the light-emitting region, and the center of the light-emitting region may be offset from the center of the second microlens.

[0342] According to various embodiments herein, the display device may further include a printed circuit film attached to the pad area of ​​the non-display area of ​​the substrate, and a plurality of printed circuit films may be provided.

[0343] According to various embodiments of the present specification, the display device may further include a low-potential voltage line, a high-potential voltage line, and a data line electrically connected to the pad area, and in a non-display area below the display area, the high-potential voltage line may be located between the low-potential voltage line and the display area.

[0344] According to various embodiments herein, the low potential voltage lines may surround the display area.

[0345] According to various embodiments herein, the non-display area on the left or right side of the display area may further include a gate driver between the low-potential voltage line and the display area.

[0346] According to various embodiments herein, the display device may further include a pixel gate driver located in the display area, and may further include a gate control line electrically connecting the pad area and the pixel gate driver.

[0347] According to various embodiments herein, the gate control line may be located between the low potential voltage line and the display area.

[0348] According to various embodiments of the present specification, the light-emitting device may further include an encapsulating portion disposed on the light-emitting portion, and the encapsulating portion may include a first inorganic encapsulating layer on the light-emitting portion, an organic encapsulating layer on the first inorganic encapsulating layer, and a second inorganic encapsulating layer on the organic encapsulating layer.

[0349] According to various embodiments herein, the display device may further include a dam portion disposed in the non-display area and overlapping the low-potential voltage line, and the organic sealing layer may terminate inside the dam portion.

[0350] According to various embodiments herein, the substrate may further include a crack reduction pattern disposed between the edge of the substrate and the dam portion.

[0351] A display device according to an embodiment of the present specification includes a substrate including a display area including a plurality of pixels and transmissive areas between adjacent pixels, and a non-display area around the display area, a thin-film transistor arranged on the substrate, a first protective layer on the thin-film transistor, a light-emitting section on the first protective layer, a first microlens on the light-emitting section, and a plurality of light-receiving sensors arranged below the substrate, wherein the first microlens is arranged in the transmissive area and at least a portion of the light-receiving sensor overlaps with the transmissive area.

[0352] According to various embodiments herein, the light-emitting section includes an anode electrode arranged for each pixel, an organic layer on the anode electrode, and a cathode electrode on the organic layer, the anode electrode being not arranged on the transmissive region, and each pixel includes a plurality of sub-pixels, and may further include a second microlens arranged for each of the plurality of sub-pixels on the light-emitting section.

[0353] Although the embodiments have been described above with reference to the accompanying drawings, it will be understood that those skilled in the art to which this specification pertains may implement the above-described technical configuration in other specific forms without changing the technical spirit or essential features. Therefore, the above-described embodiments should be understood to be illustrative in all respects and not limiting. The scope of the embodiments is defined by the claims below rather than the detailed description. Furthermore, all modifications and variations derived from the meaning and scope of the claims and their equivalents should be construed as being within the scope of the embodiments. [Explanation of symbols]

[0354] 1:Display device 100:Display device 200: Light receiving sensor 101: Circuit board 120: Thin film transistor 150: Light emitting part 180: Sealing part ML1: First microlens ML2: Second microlens NCP: Notch part DA:Display area NDA: Hidden area NDA1: 1st hidden area NDA2: 2nd hidden area N_NDA: Notch hidden area E_NDA: Extended hidden area PA: Pad area PX: pixel SP: Sub-pixel EA: Emitting area NEA: Non-Emitting Area TA: Transparent area

Claims

1. a substrate including a display area including a plurality of pixels and a transmissive area between adjacent pixels, and a non-display area around the display area; a thin film transistor disposed on the substrate; a first protective layer on the thin film transistor; a connection electrode electrically connected to the thin film transistor on the first protective layer; a second protective layer on the connection electrode; a light-emitting portion on the second protective layer; a first microlens on the light-emitting portion; The display device, wherein the first microlens is disposed in the transmissive region.

2. The display device according to claim 1 , further comprising a light-receiving sensor disposed below the substrate and overlapping the transmissive region.

3. The display device according to claim 1 , wherein the thin film transistor is not disposed on the transmissive region.

4. the light-emitting section includes an anode electrode disposed for each pixel, an organic layer on the anode electrode, and a cathode electrode on the organic layer; The display device according to claim 1 , wherein the anode electrode is not disposed on the transmissive area.

5. Each of the pixels includes a plurality of sub-pixels, The display device according to claim 4 , further comprising a second microlens disposed in each of the plurality of sub-pixels on the light-emitting portion.

6. The display device according to claim 5 , wherein the first microlens and the second microlens are disposed on the same layer.

7. further comprising a bank between the anode electrode and the organic layer; The display device according to claim 5 , wherein the banks are not disposed on the transmissive areas.

8. The display device according to claim 7 , wherein the bank is disposed at a boundary between adjacent sub-pixels.

9. The sub-pixel includes a light-emitting region and a non-light-emitting region around the light-emitting region, The display device according to claim 5 , wherein the center of the light-emitting region is offset from the center of the second microlens.

10. The display device according to claim 1 , further comprising a printed circuit film attached to a pad area of ​​the non-display area of ​​the substrate, wherein a plurality of printed circuit films are provided.

11. further comprising a low potential voltage line, a high potential voltage line, and a data line electrically connected to the pad region; The display device according to claim 10 , wherein the high-potential voltage line is located between the low-potential voltage line and the display area in a non-display area below the display area.

12. The display device according to claim 11 , wherein the low-potential voltage line surrounds the display area.

13. The display device of claim 12 , wherein the non-display area on the left or right side of the display area further includes a gate driver between the low-potential voltage line and the display area.

14. further comprising a pixel gate driver located within the display area; The display device of claim 12 , further comprising a gate control line electrically connecting the pad area and the pixel gate driver.

15. The display device according to claim 14 , wherein the gate control line is located between the low potential voltage line and the display area.

16. Further comprising a sealing portion disposed on the light emitting portion, The display device according to claim 11 , wherein the sealing portion includes a first inorganic sealing layer on the light-emitting portion, an organic sealing layer on the first inorganic sealing layer, and a second inorganic sealing layer on the organic sealing layer.

17. The display device of claim 16 , further comprising a dam portion disposed in the non-display area and overlapping the low-potential voltage line, wherein the organic sealing layer terminates inside the dam portion.

18. The display device of claim 17 , further comprising a crack reduction pattern disposed between the edge of the substrate and the dam portion.

19. a substrate including a display area including a plurality of pixels and a transmissive area between adjacent pixels, and a non-display area around the display area; a thin film transistor disposed on the substrate; a first protective layer on the thin film transistor; a light-emitting portion on the first protective layer; a first microlens on the light-emitting portion; a plurality of light receiving sensors disposed below the substrate; the first microlens is disposed in the transmissive region; The display device, wherein at least a portion of the light receiving sensor overlaps with the transmissive region.

20. the light-emitting section includes an anode electrode disposed for each pixel, an organic layer on the anode electrode, and a cathode electrode on the organic layer; the anode electrode is not disposed on the transmissive area; Each of the pixels includes a plurality of sub-pixels, The display device according to claim 19 , wherein the light-emitting section further includes a second microlens disposed in each of the plurality of sub-pixels on the light-emitting section.

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