Display device and electronic device

Abstract

To provide a display device capable of improving display quality by allowing respective pixels to output light at mutually different luminance levels.SOLUTION: The display device includes (1) a base layer including a display area in which a plurality of pixels are disposed and a non-display area disposed around the display area, (2) a conductive layer overlapping at least a portion of the plurality of pixels in a plan view, (3) a first power line electrically connected to the plurality of pixels, and (4) a second power line electrically connected to the plurality of pixels. The conductive layer includes (I) a first conductive layer overlapping a first pixel of the plurality of pixels when viewed in a plan view and (ii) a second conductive layer overlapping a second pixel of the plurality of pixels when viewed in a plan view and spaced apart from the first conductive layer. The first power line includes (a) a first first power line electrically connected to the first pixel through the first conductive layer and (b) a first second power line electrically connected to the second pixel through the second conductive layer.SELECTED DRAWING: Figure 7D

Description

[Technical Field]

[0001] The present invention relates to a display device, and more particularly to a display device with improved display quality in a display area. [Background technology]

[0002] Generally, electronic devices that provide images to users, such as smartphones, digital cameras, laptops, navigation systems, and smart televisions, include a display device for displaying the images. The display device generates an image and provides the generated image to the user through a display screen.

[0003] The display device includes a plurality of pixels for generating an image, a scan driving circuit for applying scan signals to the pixels, a data driving unit for applying data voltages to the pixels, and an emission driving unit for applying emission signals to the pixels. The pixels receive the data voltages in response to the scan signals, and display an image by emitting light of a brightness corresponding to the data voltages in response to the emission signals.

[0004] A pixel can display moving and still images. When a pixel displays moving images, it can receive continuously updated images. When a pixel displays a still image, it can maintain the image it was initially provided with and not receive any images thereafter. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. WO2012 / 052886 [Patent Document 2] Korean Patent Publication No. 2015-0075016 (KR10-2015-0075016A) Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a display device capable of improving display quality by allowing each pixel to output light at a different luminance level. [Means for solving the problem]

[0007] A display device according to one embodiment of the present invention includes: (1) a base layer including a display region in which a plurality of pixels are arranged and a non-display region arranged around the display region; (2) a conductive layer overlapping (overlapping) at least a portion of the plurality of pixels in a plane; (3) a first power supply line electrically connected to the plurality of pixels; and (4) a second power supply line electrically connected to the plurality of pixels. The conductive layer includes: (i) a first conductive layer overlapping (overlapping) a first pixel of the plurality of pixels in a plane; and (ii) a second conductive layer overlapping (overlapping) a second pixel of the plurality of pixels in a plane and spaced apart from the first conductive layer. The first power supply line may include: (a) a 1-1 power supply line electrically connected to the first pixel through the first conductive layer; and (b) a 1-2 power supply line electrically connected to the second pixel through the second conductive layer.

[0008] Each of the plurality of pixels may include a pixel driving unit disposed on the base layer and including a transistor, and a light emitting element disposed on the transistor and including a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer, wherein the first power line is electrically connected to the first electrode, and the second power line is electrically connected to the transistor.

[0009] The first electrodes may include a 1-1 electrode electrically connected to the 1-1 power line and a 1-2 electrode electrically connected to the 1-2 power line, and the 1-1 electrode and the 1-2 electrode may be electrically insulated from each other.

[0010] The 1-1 electrode may be disposed on a layer different from the first conductive layer and electrically connected to the first conductive layer through a first contact hole, and the 1-2 electrode may be disposed on a layer different from the second conductive layer and electrically connected to the second conductive layer through a second contact hole.

[0011] The 1-1 electrode may include a plurality of first sub-electrodes, and the first sub-electrodes may be spaced apart from each other on a plane.

[0012] The first conductive layer may overlap a portion of each of the first sub-electrodes in a plane.

[0013] The first conductive layer may include a plurality of first sub-conductive layers, and the first sub-conductive layers may have shapes corresponding to the shapes of the first sub-electrodes.

[0014] The first conductive layer may further include a connection pattern that connects the first sub-conductive layers to each other.

[0015] The 1-1 power supply line may include a horizontal line extending in a first direction and a vertical line extending in a second direction intersecting the first direction, and the horizontal line may be disposed on the same layer as the first conductive layer and may extend from the first conductive layer.

[0016] The vertical line may extend from the horizontal line and not overlap the first electrode in a plane.

[0017] The vertical lines may be disposed on a different layer from the horizontal lines and may be electrically connected to the horizontal lines through contact holes.

[0018] The area of ​​the first conductive layer may be larger than the area of ​​the 1-1 electrode, and the area of ​​the second conductive layer may be larger than the area of ​​the 1-2 electrode.

[0019] The first conductive layer and the second conductive layer may have different shapes in plan view.

[0020] The first-1 power line may apply a first voltage to the first pixel, and the first-2 power line may apply a second voltage, different from the first voltage, to the second pixel.

[0021] The first-1 power supply line may be disposed on a layer different from the first conductive layer, and the first-1 power supply line may be electrically connected to the first conductive layer through a contact hole.

[0022] The first-1 power supply line may overlap the pixel.

[0023] The display device according to an embodiment of the present invention may further include a pad section disposed in the non-display area, and the pad section may include a first voltage pad electrically connected to the first power line and a second voltage pad electrically connected to the second power line.

[0024] The first voltage pad may include a 1-1 voltage pad electrically connected to the 1-1 power line and a 1-2 voltage pad electrically connected to the 1-2 power line.

[0025] The pad section may include a first pad section and a second pad section spaced apart from each other with the display area interposed therebetween.

[0026] The first pixel includes a plurality of first sub-pixels, and the first sub-pixels may overlap the first conductive layer in a plane.

[0027] Each of the plurality of pixels includes (1) a pixel driving unit disposed on the base layer and including a transistor; and (2) a light-emitting element disposed on the transistor and including a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer. A display device according to one embodiment of the present invention may further include a connecting electrode electrically connecting the transistor and the second electrode to each other.

[0028] A display device according to one embodiment of the present invention may further include a pixel defining film in which an opening exposing at least a portion of the first electrode is defined, and a separator disposed on the pixel defining film, and the lower surface of the second electrode may contact the upper surface of the connecting electrode in a contact region adjacent to the separator.

[0029] The connecting electrode may have a ring shape surrounding the opening.

[0030] A display device according to an embodiment of the present invention includes: a base layer including a display area divided into a plurality of regions and a non-display area disposed around the display area; a driving element layer disposed on the base layer and including a pixel driving unit; a plurality of light emitting elements disposed on the driving element layer, each including a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; a first power line electrically connected to the first electrode included in each of the light emitting elements; and a second power line electrically connected to the second electrode included in each of the light emitting elements. The first electrode may include a first-1 electrode disposed in a first region among the plurality of regions and receiving a first voltage via a first-1 power line of the first power line, and a first-2 electrode disposed in a second region among the plurality of regions and receiving a second voltage different from the first voltage via a first-2 power line of the first power line.

[0031] The 1-1 electrode may include a plurality of first sub-electrodes and a connection pattern that electrically connects the first sub-electrodes to each other.

[0032] The first power supply line may be disposed on a different layer from the first sub-electrode, and the first power supply line may be electrically connected to the first sub-electrode through a contact hole.

[0033] A display device according to an embodiment of the present invention may further include a first conductive layer disposed on a layer different from the 1-1 electrode and overlapping the 1-1 electrode, and a second conductive layer disposed on a layer different from the 1-2 electrode and overlapping the 1-2 electrode.

[0034] The 1-1 electrode may be electrically connected to the first conductive layer through a first contact hole, and the 1-2 electrode may be electrically connected to the second conductive layer through a second contact hole.

[0035] The 1-1 power supply line may include a horizontal line extending in a first direction and a vertical line extending in a second direction intersecting the first direction, and the horizontal line may be disposed on the same layer as the first conductive layer and may extend from the first conductive layer.

[0036] The vertical line may extend from the horizontal line and may not overlap the first electrode in a plane.

[0037] The vertical lines may be disposed on a different layer from the horizontal lines and may be electrically connected to the horizontal lines through contact holes.

[0038] The first-1 power supply line may be disposed on a layer different from the first conductive layer, and the first-1 power supply line may be electrically connected to the first conductive layer through a contact hole.

[0039] An electronic device according to one embodiment of the present invention includes a display device, an electronic module overlapping the display device, and a housing accommodating the display device. The display device includes: (1) a base layer including a display area in which a plurality of pixels are arranged and a non-display area arranged around the display area; (2) a conductive layer overlapping at least a portion of the plurality of pixels in a planar view; (3) a first power line electrically connected to the plurality of pixels; and (4) a second power line electrically connected to the plurality of pixels. The conductive layer includes a first conductive layer overlapping a first pixel among the plurality of pixels in a planar view and a second conductive layer overlapping a second pixel among the plurality of pixels in a planar view and spaced apart from the first conductive layer. The first power line may include a 1-1 power line electrically connected to the first pixel through the first conductive layer and a 1-2 power line electrically connected to the second pixel through the second conductive layer. [Effects of the Invention]

[0040] The first voltage applied to the first pixel and the second voltage applied to the second pixel arranged in the display area are different from each other, so that the pixels arranged in different areas of the display area emit light of different luminances, thereby providing a display panel with improved display quality.

[0041] In addition, by directly applying the first voltage to the first pixel through the 1-1 power line and directly applying the second voltage to the second pixel through the 1-2 power line, it is possible to prevent a voltage drop caused by a longer current path, and thus to prevent a deterioration in the display quality of the display device. [Brief explanation of the drawings]

[0042] [Figure 1] 1 is a perspective view of an electronic device according to one embodiment of the present invention; [Figure 2A] 2 is a cross-sectional view of a display device included in the electronic device of FIG. 1. [Figure 2B] FIG. 2B is a cross-sectional view of the display panel shown in FIG. 2A. [Figure 3] 1 is a block diagram of a display device according to an embodiment of the present invention; [Figure 4A] 1 is an equivalent circuit diagram (1) of a pixel according to one embodiment of the present invention. [Figure 4B] FIG. 2 is an equivalent circuit diagram (2) of a pixel according to one embodiment of the present invention. [Figure 4C] FIG. 3 is an equivalent circuit diagram (3) of a pixel according to one embodiment of the present invention. [Figure 5A] 1 is a simplified plan view (1) of a display panel according to an embodiment of the present invention. [Figure 5B] FIG. 2 is a plan view (2) showing a simplified view of a display panel according to an embodiment of the present invention. [Figure 6] 2 is a plan view of a display panel and a driving circuit unit according to an embodiment of the present invention; [Figure 7A]1 is an enlarged plan view (1) of a partial area of ​​a display panel according to an embodiment of the present invention. [Figure 7B] FIG. 2 is an enlarged plan view (2) of a partial area of ​​a display panel according to an embodiment of the present invention. [Figure 7C] FIG. 3 is an enlarged plan view (3) of a partial area of ​​a display panel according to an embodiment of the present invention. [Figure 7D] FIG. 4 is an enlarged plan view (4) of a partial area of ​​a display panel according to an embodiment of the present invention. [Figure 8] 1 is a cross-sectional view of a display module according to an embodiment of the present invention; [Figure 9A] 1 is an enlarged cross-sectional view (1) showing a partial area of ​​a display panel according to an embodiment of the present invention. [Figure 9B] 2 is an enlarged cross-sectional view (2) showing a partial area of ​​a display panel according to an embodiment of the present invention. FIG. [Figure 10] FIG. 7E is an enlarged view of the CC′ region shown in FIG. 7D. [Figure 11A] 11 is a cross-sectional view of a display panel according to an embodiment of the present invention, taken along line II-II' in FIG. [Figure 11B] 11 is a cross-sectional view (1) of a display panel according to another embodiment of the present invention, taken along line II-II' in FIG. [Figure 11C] 11 is a cross-sectional view (2) of a display panel according to another embodiment of the present invention, taken along line II-II' in FIG. [Figure 11D] 11 is a cross-sectional view (3) of a display panel according to another embodiment of the present invention, taken along line II-II' in FIG. [Figure 12A] 1 is an enlarged plan view (1) of a partial area of ​​a display panel according to an embodiment of the present invention. [Figure 12B] FIG. 2 is an enlarged plan view (2) of a partial area of ​​a display panel according to an embodiment of the present invention. [Figure 12C] FIG. 3 is an enlarged plan view (3) of a partial area of ​​a display panel according to an embodiment of the present invention. [Figure 12D]FIG. 4 is an enlarged plan view (4) of a partial area of ​​a display panel according to an embodiment of the present invention. [Figure 12E] FIG. 5 is an enlarged plan view (5) of a partial area of ​​a display panel according to an embodiment of the present invention. [Figure 13] 1 is a plan view (1) of a display panel and a driving circuit unit according to an embodiment of the present invention. [Figure 14] FIG. 2 is a plan view (2) of a display panel and a driving circuit unit according to an embodiment of the present invention. [Figure 15] 1 is a perspective view of an electronic device according to an embodiment of the present invention. [Figure 16] 16 is a view showing a folded state of the electronic device shown in FIG. 15; [Figure 17] FIG. 16 is an exploded perspective view of the electronic device shown in FIG. 15. [Figure 18] FIG. 16 is a block diagram of the electronic device shown in FIG. 15. [Figure 19] 1 is a perspective view of an electronic device according to one embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0043] Because the present invention can be modified in various ways and can have various forms, specific embodiments are shown by way of example in the drawings and described in detail herein, but it should be understood that this is not to limit the invention to the particular form disclosed, but rather to include all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention.

[0044] In this specification, when a certain component (or region, layer, portion, etc.) is described as being "on," "coupled," or "bonded" to another component, it means that it can be directly disposed / coupled / bonded to the other component, or that a third component can be disposed therebetween.

[0045] The same reference numerals refer to the same elements throughout the drawings, and the thickness, proportions, and dimensions of the elements are exaggerated for the purpose of explaining the technical content more clearly.

[0046] "And / or" includes all combinations of one or more that the associated constructs may define.

[0047] Terms such as "first," "second," etc. may be used to describe various components, but the components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, a first component may be referred to as a "second component," and similarly, a second component may be referred to as a "first component" without departing from the scope of the present invention. A singular expression includes a plural expression unless the context clearly dictates otherwise.

[0048] Furthermore, terms such as "under," "below," "on," and "above" are used to describe the relationship between components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant art, and unless interpreted as ideal or overly formal, they are expressly defined herein.

[0050] Terms such as "comprise" or "have" may be intended to specify the presence of any feature, number, step, operation, component, part, or combination thereof stated in the specification, and should be understood as not precluding the possible presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0051] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0052] Fig. 1 is a perspective view of an electronic device according to an embodiment of the present invention, Fig. 2A is a cross-sectional view of a display device included in the electronic device of Fig. 1, and Fig. 2B is a cross-sectional view of the display panel shown in Fig. 2A.

[0053] 1, the electronic device ED according to an embodiment of the present invention may have a rectangular shape having a short side extending in a first direction DR1 and a long side extending in a second direction DR2 intersecting the first direction DR1, but is not limited thereto, and the electronic device ED may have various shapes such as a circle and a polygon.

[0054] Hereinafter, a direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In addition, in this specification, "in a plan view" can be defined as a state viewed from the third direction DR3.

[0055] The top surface of the electronic device ED may be defined as a display surface DS, and the display surface DS may have a plane defined by a first direction DR1 and a second direction DR2. An image IM generated by the electronic device ED may be provided to a user through the display surface DS.

[0056] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may display an image, while the non-display area NDA may not display an image. The non-display area NDA may surround the display area DA and define a border of the electronic device ED that is printed in a predetermined color.

[0057] Although not shown, the electronic device ED may include a display device DD (see FIG. 2A), which will be described in more detail below.

[0058] 2A , the display device DD may include a display module DM, an anti-reflection layer RPL disposed on the display module DM, and a panel protection layer PPL disposed below the display module DM. The display module DM may include a display panel DP and a sensing layer ISL disposed on the display panel DP. The display panel DP may be a flexible panel. For example, the display panel DP may include a flexible substrate and a plurality of elements disposed on the flexible substrate.

[0059] The display panel DP according to an embodiment of the present invention is an emissive display panel and is not particularly limited. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of an inorganic light-emitting display panel may include quantum dots, quantum rods, etc. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0060] The sensing layer ISL may include a plurality of sensor units (not shown) for sensing an external input in a capacitive manner, and may be directly formed on the display panel DP without a separate adhesive layer during manufacturing of the display device DD.

[0061] The anti-reflection layer RPL may be disposed on the sensing layer ISL. The anti-reflection layer RPL may be formed directly on the sensing layer ISL during manufacturing of the display device DD. The anti-reflection layer RPL may be defined as an external light anti-reflection film. The anti-reflection layer RPL can reduce the reflectance of external light incident from above the electronic device ED toward the display panel DP.

[0062] For example, the sensing layer ISL may be formed directly on the display panel DP, and the anti-reflection layer RPL may be formed directly on the sensing layer ISL, but the embodiment of the present invention is not limited thereto. For example, the sensing layer ISL may be manufactured separately and attached to the display panel DP with an adhesive layer, and the anti-reflection layer RPL may be manufactured separately and attached to the sensing layer ISL with an adhesive layer.

[0063] The panel protection layer PPL may be disposed below the display panel DP. The panel protection layer PPL may protect the lower portion of the display panel DP. The panel protection layer PPL may include a flexible plastic material. For example, the panel protection layer PPL may include polyethylene terephthalate (PET).

[0064] Referring to FIG. 2B, the display panel DP may include a base layer BL, a circuit element layer DP-CL arranged on the base layer BL, a display element layer DP-ED arranged on the circuit element layer DP-CL, and an encapsulation layer ECL arranged on the display element layer DP-ED.

[0065] The base layer BL may include a display area DA and a non-display area NDA surrounding the display area DA. The base layer BL may include glass or a flexible plastic material such as polyimide (PI). The display element layers DP-ED may be disposed on the display area DA.

[0066] A plurality of pixels may be arranged on the circuit element layer DP-CL and the display element layer DP-ED, and each pixel may include a transistor arranged on the circuit element layer DP-CL and a light emitting element arranged on the display element layer DP-ED and coupled to the transistor.

[0067] The encapsulation layer ECL can be disposed on the circuit element layer DP-CL so as to cover the display element layer DP-ED. The encapsulation layer ECL can protect the pixels from moisture, oxygen, and external foreign substances.

[0068] FIG. 3 is a block diagram of a display device according to an embodiment of the present invention.

[0069] 3, the display device DD may include a display panel DP, a panel driver SDC, an EDC, a DDC, a power supply PWS, and a timing controller TC. The panel driver SDC, an EDC, and a DDC may include a scan driver SDC, a light emission driver EDC, and a data driver DDC.

[0070] The display panel DP may include scan lines GWL1-GWLn, GCL1-GCLn, GIL1-GILn, GBL1-GBLn, GRL1-GRLn, light emitting lines ESL1-ESLn, and data lines DL1-DLm. The display panel DP may include a plurality of pixels connected to the scan lines GWL1-GWLn, GCL1-GCLn, GIL1-GILn, GBL1-GBLn, GRL1-GRLn, light emitting lines ESL1-ESLn, and data lines DL1-DLm (where m and n are integers greater than 1).

[0071] For example, a pixel PXij (where i and j are integers greater than 1) located on the ith horizontal line (or the ith pixel row) and the jth vertical line (or the jth pixel column) may be connected to the ith first scan line GWLi (or the write scan line), the ith second scan line GCLi (or the compensation scan line), the ith third scan line GILi (or the first initialization scan line), the ith fourth scan line GBLi (or the second initialization scan line), the ith fifth scan line GRLi (or the reset scan line), the jth data line DLj, and the ith emission line ESLi.

[0072] The pixel PXij may include a plurality of light emitting elements, a plurality of transistors, and a plurality of capacitors. The pixel PXij may receive first power supply voltages VDD1 to VDDx, a second power supply voltage VSS, a third power supply voltage (or a reference voltage VREF), a fourth power supply voltage (or a first initialization voltage VINT1), a fifth power supply voltage (or a second initialization voltage VINT2), and a sixth power supply voltage (or a compensation voltage VCOMP) through a power supply unit PWS. The first power supply voltages VDD1 to VDDx may include a first voltage VDD1 to an x-th voltage VDDx. This will be described in detail later.

[0073] The first power supply voltages VDD1 to VDDx and the second power supply voltage VSS are set to have voltage values ​​such that a current flows through the light emitting element to cause it to emit light. For example, each of the first power supply voltages VDD1 to VDDx can be set to a voltage higher than the second power supply voltage SS.

[0074] The third power supply voltage VREF may be a voltage for initializing the gate of the driving transistor included in the pixel PXij. The third power supply voltage VREF may be used to implement a predetermined gray level by using a voltage difference with the data signal. To this end, the third power supply voltage VREF may be set to a predetermined voltage within the voltage range of the data signal.

[0075] The fourth power supply voltage VINT1 may be a voltage for initializing a capacitor included in the pixel PXij. The fourth power supply voltage VINT1 may be set to a voltage lower than the third power supply voltage VREF. For example, the fourth power supply voltage VINT1 may be set to a voltage lower than the difference between the third power supply voltage VREF and the threshold voltage of the driving transistor. However, the present invention is not limited thereto.

[0076] The fifth power supply voltage VINT2 may be a voltage for initializing the cathode (or second electrode) of the light emitting element included in the pixel PXij. The fifth power supply voltage VINT2 may be set to a voltage lower than the first power supply voltages VDD1 to VDDx and the fourth power supply voltage VINT1, or may be set to a voltage similar to or the same as the third power supply voltage VREF, but is not limited thereto, and the fifth power supply voltage VINT2 may be set to a voltage similar to or the same as the first power supply voltages VDD1 to VDDx.

[0077] The sixth power supply voltage VCOMP can supply a predetermined current to the driving transistor when compensating for the threshold voltage of the driving transistor.

[0078] 3 shows that the first to sixth power supply voltages VDD1 to VDDx, VSS, VREF, VINT1, VINT2, and VCOMP are all supplied from the power supply unit PWS, but the present invention is not limited to this. For example, the first power supply voltages VDD1 to VDDx and the second power supply voltage VSS are all supplied regardless of the structure of the pixel PXij, and at least one voltage among the third power supply voltage VREF, fourth power supply voltage VINT1, fifth power supply voltage VINT2, and sixth power supply voltage VCOMP may not be supplied depending on the structure of the pixel PXij.

[0079] In the embodiment of the present invention, the signal lines connected to the pixels PXij can be variously set in accordance with the circuit structure of the pixels PXij.

[0080] The scan driver SDC receives a first control signal SCS from the timing controller TC, and can supply scan signals to each of the first scan lines GWL1 to GWLn, the second scan lines GCL1 to GCLn, the third scan lines GIL1 to GILn, the fourth scan lines GBL1 to GBLn, and the fifth scan lines GRL1 to GRLn based on the first control signal SCS.

[0081] The scan signal may be set to a voltage that turns on the transistor to which the scan signal is supplied. For example, the scan signal supplied to a P-type transistor may be set to a logic low level, and the scan signal supplied to an N-type transistor may be set to a logic high level. Hereinafter, the term "scan signal is supplied" may be understood to mean that the scan signal is supplied at a logic level that turns on the transistor controlled thereby.

[0082] 3, for the sake of simplicity, the scan driver SDC is illustrated as a single component, but the present invention is not limited thereto. Depending on the embodiment, a plurality of scan drivers may be included to supply scan signals to the first scan lines GWL1 to GWLn, the second scan lines GCL1 to GCLn, the third scan lines GIL1 to GILn, the fourth scan lines GBL1 to GBLn, and the fifth scan lines GRL1 to GRLn, respectively.

[0083] The light emitting driver EDC may supply light emitting signals to the light emitting lines ESL1 to ESLn based on the second control signal ECS. For example, the light emitting signals may be sequentially supplied to the light emitting lines ESL1 to ESLn.

[0084] The transistors connected to the light emitting lines ESL1 to ESLn of the present invention may be N-type transistors. In this case, the light emitting signals supplied to the light emitting lines ESL1 to ESLn may be set as gate-off voltages. The transistors receiving the light emitting signals may be turned off when the light emitting signals are supplied, and may be turned on otherwise.

[0085] The second control signal ECS includes a light emission start signal and a clock signal, and the light emission driver EDC can be implemented as a shift register that sequentially shifts the pulse-type light emission start signal using the clock signal to sequentially generate and output pulse-type light emission signals.

[0086] The data driver DDC can receive a third control signal DCS and image data RGB from the timing controller TC. The data driver DDC can convert the digital image data RGB into an analog data signal (i.e., data signal). The data driver DDC can supply data signals to the data lines DL1 to DLm in response to the third control signal DCS.

[0087] The third control signal DCS may include a data enable signal instructing output of a valid data signal, a horizontal start signal, a data clock signal, etc. For example, the data driver DDC may include a shift register that generates a sampling signal by shifting the horizontal start signal in synchronization with the data clock signal, a latch that latches (holds) image data RGB in response to the sampling signal, a digital-to-analog converter (or decoder) that converts the latched image data (e.g., digital data) into an analog data signal, and a buffer (or amplifier) ​​that outputs the data signal to the data lines DL1 to DLm.

[0088] The power supply unit PWS can supply the first power supply voltages VDD1 to VDDx, the second power supply voltage VSS, and the third power supply voltage VREF to the display panel DP for driving the pixels PXij. The power supply unit PWS can also supply at least one voltage from the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP to the display panel DP.

[0089] For example, the power supply unit PWS may supply the first power supply voltages VDD1 to VDDx, the second power supply voltage VSS, the third power supply voltage VREF, the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP to the display panel DP via a first power supply line VDL (see FIG. 4A), a second power supply line VSL (see FIG. 4A), a third power supply line (or a reference voltage line VRL, see FIG. 4A), a fourth power supply line (or a first initialization voltage line VIL1, see FIG. 4A), a fifth power supply line (or a second initialization voltage line VIL2, see FIG. 4A), and a sixth power supply line (or a compensation voltage line VCL, see FIG. 4A), which are not shown. The power supply unit PWS may be embodied as, but is not limited to, a power management integrated circuit.

[0090] The timing controller TC may generate a first control signal SCS, a second control signal ECS, a third control signal DCS, and a fourth control signal PCS based on input image data IRGB, a synchronization signal Sync (e.g., a vertical synchronization signal, a horizontal synchronization signal, etc.), a data enable signal DE, a clock signal, etc. The first control signal SCS may be supplied to the scan driver SDC, the second control signal ECS may be supplied to the emission driver EDC, the third control signal DCS may be supplied to the data driver DDC, and the fourth control signal PCS may be supplied to the power supply PWS. The timing controller TC may rearrange the input image data IRGB in accordance with the arrangement of the pixels PXij in the display panel DP to generate image data RGB (or frame data).

[0091] Meanwhile, the scan driver SDC, emission driver EDC, data driver DDC, power supply PWS, and / or timing controller TC may be formed directly on the display panel DP or may be provided in the form of separate driver chips and connected to the display panel DP. Also, at least two of the scan driver SDC, emission driver EDC, data driver DDC, power supply PWS, and timing controller TC may be provided on a single driver chip. For example, the data driver DDC and timing controller TC may be provided on a single driver chip.

[0092] Although the display device DD according to an embodiment has been described above with reference to FIG. 3, the display device of the present invention is not limited thereto. Signal lines may be added or omitted depending on the pixel configuration. Furthermore, the connection relationship between a pixel and a signal line may be changed. When one of the signal lines is omitted, another signal line may replace the omitted signal line.

[0093] 4A, 4B, and 4C are equivalent circuit diagrams of pixels PXij, PXij-1, and PXij-2 connected to an i-th first scan line GWLi (hereinafter, the first scan line) and a j-th data line DLj (hereinafter, the data line) according to an embodiment of the present invention.

[0094] 4A, the pixel PXij includes a light emitting element LD and a pixel driving circuit PDC, and the light emitting element LD is connected to a first power line VDL and the pixel driving circuit PDC.

[0095] The pixel driver PDC may be connected to a plurality of scan lines GWLi, GCLi, GILi, GBLi, GRLi, data lines DLj, light emitting lines ESLi, and a plurality of power supply voltage lines VDL, VSL, VIL1, VIL2, VRL, and VCL. The pixel driver PDC may include first to eighth transistors T1, T2, T3, T4, T5, T6, T7, and T8, a first capacitor C1, and a second capacitor C2. Hereinafter, a case will be described in which the first to eighth transistors T1, T2, T3, T4, T5, T6, T7, and T8 are all N-type transistors. However, the present invention is not limited thereto. Some of the first to eighth transistors T1 to T8 may be N-type transistors and the rest may be P-type transistors, or each of the first to eighth transistors T1 to T8 may be P-type transistors. Therefore, the present invention is not limited to any one embodiment.

[0096] The gate of the first transistor T1 may be connected to a first node N1. The first electrode of the first transistor T1 may be connected to a second node N2, and the second electrode may be connected to a third node N3. The first transistor T1 may be a driving transistor. The first transistor T1 may control a driving current ILD flowing from a first power line VDL through the light emitting device LD to a second power line VSL in response to the voltage of the first node N1. The first power voltage VDD may be set to a voltage having a higher potential than the second power voltage VSS. Here, the first power voltage VDD may be one of the first voltage VDD1 to the xth voltage VDDx described with reference to FIG. 3. A plurality of first power lines VDL may be provided, and each of the plurality of first power lines VDL may provide one of the first voltages VDD1 to VDDx to the light emitting device LD. The driving current ILD may be variable depending on the voltage levels of the first voltages VDD1 to VDDx.

[0097] In this specification, "electrically connected between a transistor and a signal line or between transistors" means "the source, drain, and gate of the transistor are integral with the signal line or are connected through a connecting electrode."

[0098] The second transistor T2 may include a gate connected to the write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 may supply a data signal DATA to the first node N1 in response to a write scan signal GW transmitted through the write scan line GWLi. When the write scan signal GW is supplied to the write scan line GWLi, the second transistor T2 may be turned on to electrically connect the data line DLj to the first node N1.

[0099] The third transistor T3 may be connected between the first node N1 and the reference voltage line VRL. A first electrode of the third transistor T3 may receive the reference voltage VREF through the reference voltage line VRL, and a second electrode of the third transistor T3 may be connected to the first node N1. In this embodiment, a gate of the third transistor T3 may receive a reset scan signal GR through an i-th fifth scan line GRLi (hereinafter, a reset scan line). When the reset scan signal GR is supplied to the reset scan line GRLi, the third transistor T3 is turned on to provide the reference voltage VREF to the first node N1.

[0100] The fourth transistor T4 may be connected between the third node N3 and the first initialization voltage line VIL1. A first electrode of the fourth transistor T4 may be connected to the third node N3, and a second electrode of the fourth transistor T4 may be connected to the first initialization voltage line VIL1 that provides the first initialization voltage VINT1. The fourth transistor T4 may be referred to as a first initialization transistor. A gate of the fourth transistor T4 may receive a first initialization scan signal GI through an i-th third scan line GILi (hereinafter, referred to as the first initialization scan line). When the first initialization scan signal GI is provided to the first initialization scan line GILi, the fourth transistor T4 may be turned on to provide the first initialization voltage VINT1 to the third node N3.

[0101] The fifth transistor T5 may be connected between the compensation voltage line VCL and the second node N2. A first electrode of the fifth transistor T5 receives the compensation voltage VCOMP through the compensation voltage line VCL, and a second electrode of the fifth transistor T5 may be connected to the second node N2 and electrically connected to the first electrode of the first transistor T1. A gate of the fifth transistor T5 may receive a compensation scan signal GC through an i-th second scan line GCLi (hereinafter, a compensation scan line). When the compensation scan signal GC is supplied to the compensation scan line GCLi, the fifth transistor T5 may be turned on to provide the compensation voltage VCOMP to the second node N2, thereby compensating the threshold voltage of the first transistor T1 during the compensation period.

[0102] The sixth transistor T6 may be connected between the first transistor T1 and the light emitting element LD. Specifically, the gate of the sixth transistor T6 may receive an emission signal EM through an i-th emission line ESLi (hereinafter, referred to as an emission line). A first electrode of the sixth transistor T6 may be connected to the cathode of the light emitting element LD through a fourth node N4, and a second electrode of the sixth transistor T6 may be connected to the first electrode of the first transistor T1 through a second node N2. The sixth transistor T6 may be referred to as a first emission control transistor. When an emission signal EM is supplied to the emission line ESLi, the sixth transistor T6 may be turned on to electrically connect the light emitting element LD and the first transistor T1.

[0103] The seventh transistor T7 may be connected between the second power line VSL and the third node N3. A first electrode of the seventh transistor T7 may be connected to the second electrode of the first transistor T1 through the third node N3, and a second electrode of the seventh transistor T7 may receive the second power voltage VSS through the second power line VSL. A gate of the seventh transistor T7 may be electrically connected to the light emitting line ESLi. The seventh transistor T7 may be referred to as a second light emitting control transistor. When an light emitting signal EM is supplied to the light emitting line ESLi, the seventh transistor T7 is turned on to electrically connect the second electrode of the first transistor T1 to the second power line VSL.

[0104] Meanwhile, in the present embodiment, the sixth transistor T6 and the seventh transistor T7 are illustrated as being connected to the same emission line ESLi and turned on by the same emission signal EM, but this is merely an example, and the sixth transistor T6 and the seventh transistor T7 may be turned on independently by different signals that are distinct from each other. Also, in the pixel driver PDC according to an embodiment of the present invention, either the sixth transistor T6 or the seventh transistor T7 may be omitted.

[0105] The eighth transistor T8 may be connected between the second initialization voltage line VIL2 and the fourth node N4. That is, the eighth transistor T8 may include a gate connected to the i-th fourth scan line GBLi (hereinafter, the second initialization scan line), a first electrode connected to the second initialization voltage line VIL2, and a second electrode connected to the fourth node N4. The eighth transistor T8 may be referred to as a second initialization transistor. The eighth transistor T8 may supply a second initialization voltage VINT2 to the fourth node N4 corresponding to the cathode of the light emitting element LD in response to a second initialization scan signal GB transmitted through the second initialization scan line GBLi. The cathode of the light emitting element LD may be initialized by the second initialization voltage VINT2.

[0106] Meanwhile, in this embodiment, some of the second to eighth transistors T2, T3, T4, T5, T6, T7, and T8 may be turned on simultaneously by the same scan signal. For example, the eighth transistor T8 and the fifth transistor T5 may be turned on simultaneously by the same scan signal. For example, the eighth transistor T8 and the fifth transistor T5 may be operated by the same compensation scan signal GC. The eighth transistor T8 and the fifth transistor T5 may be turned on / off simultaneously by the same compensation scan signal GC. In this case, the compensation scan line GCLi and the second initialization scan line GBLi may be provided as a substantially single scan line. Therefore, the cathode initialization of the light emitting element LD and the compensation of the threshold voltage of the first transistor T1 may be performed at the same timing. However, this is merely an example and is not limited to any one embodiment.

[0107] Furthermore, according to the present invention, the cathode initialization of the light emitting element LD and the compensation of the threshold voltage of the first transistor T1 may be performed by applying the same power supply voltage. For example, the compensation voltage line VCL and the second initialization voltage line VIL2 may be provided as a substantially single power supply voltage line. In this case, the cathode initialization operation and the compensation operation of the driving transistor are performed using a single power supply voltage, which may simplify the design of the driver. However, this is merely an example, and the present invention is not limited to any particular embodiment.

[0108] The first capacitor C1 may be disposed between the first node N1 and the third node N3. The first capacitor C1 may store a differential voltage between the first node N1 and the third node N3. The first capacitor C1 may be referred to as a storage capacitor.

[0109] The second capacitor C2 may be disposed between the third node N3 and the second power line VSL. That is, one electrode of the second capacitor C2 may be coupled to the second power line VSL, which receives the second power voltage VSS, and the other electrode of the second capacitor C2 may be coupled to the third node N3. The second capacitor C2 may store a charge corresponding to the voltage difference between the second power voltage VSS and the third node N3. The second capacitor C2 may be referred to as a hold capacitor. The second capacitor C2 may have a higher storage capacitance than the first capacitor C1. Therefore, the second capacitor C2 may minimize a voltage change at the third node N3 in response to a voltage change at the first node N1.

[0110] In this embodiment, the light emitting element LD may be connected to the pixel driver PDC through a fourth node N4. The light emitting element LD may include an anode (or a first electrode) connected to the first power line VDL and a cathode facing the anode. In this embodiment, the light emitting element LD may be connected to the pixel driver PDC through the cathode. That is, in the pixel PXij according to the present invention, the connection node between the light emitting element LD and the pixel driver PDC is the fourth node N4, which may correspond to the connection node between the first electrode of the sixth transistor T6 and the cathode of the light emitting element LD. Therefore, the potential of the fourth node N4 may substantially correspond to the cathode potential of the light emitting element LD.

[0111] Specifically, the anode of the light emitting element LD is connected to the first power line VDL and receives the first power voltage VDD, which is a constant voltage, and the cathode is connected to the first transistor T1 through the sixth transistor T6. That is, in this embodiment, the first to eighth transistors T1 to T8 are N-type transistors, and the potential of the third node N3 corresponding to the source of the first transistor T1, which is the driving transistor, may not be directly affected by the characteristics of the light emitting element LD. Therefore, even if degradation of the light emitting element LD occurs, the influence on the transistors constituting the pixel driver PDC, particularly the gate-source voltage Vgs of the driving transistor, may be reduced. That is, since the amount of change in driving current due to degradation of the light emitting element LD is reduced, the problem of image retention in the display panel that occurs over time may be reduced and the lifespan may be improved.

[0112] As shown in FIG. 4B, pixel PXij-1 may include a pixel driver PDC-1 including two transistors T1 and T2 and a first capacitor C1. The pixel driver PDC-1 may be connected to the light emitting element LD, the write scan line GWLi, the data line DLj, and the second power line VSL. The pixel driver PDC-1 shown in FIG. 4B may correspond to the pixel driver PDC shown in FIG. 4A with the third to eighth transistors T3 to T8 and the second capacitor C2 omitted.

[0113] Each of the first and second transistors T1 and T2 may be an N-type or a P-type transistor, and in this embodiment, a case where each of the first and second transistors T1 and T2 is an N-type transistor will be described as an example.

[0114] The first transistor T1 may include a gate connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The second node N2 may be a node connected to a first power line VDL, and the third node N3 may be a node connected to a second power line VSL. The first transistor T1 is connected to the light emitting element LD through the second node N2 and to the second power line VSL through the third node N3. The first transistor T1 may be a driving transistor.

[0115] The second transistor T2 may include a gate receiving a write scan signal GW through a write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to a first node N1, and may supply a data signal DATA to the first node N1 in response to the write scan signal GW transmitted through the write scan line GWLi.

[0116] The first capacitor C1 may include an electrode coupled to the first node N1 and an electrode coupled to the third node N3, and may store a data signal DATA transmitted to the first node N1.

[0117] The light emitting element LD may include an anode and a cathode. In this embodiment, the anode of the light emitting element LD is connected to the first power line VDL, and the cathode is connected to the pixel driving unit PDC-1 through a second node N2. In this embodiment, the cathode of the light emitting element LD may be connected to the first transistor T1. The light emitting element LD may emit light in response to the amount of current flowing through the first transistor T1 of the pixel driving unit PDC-1.

[0118] In this embodiment, the first and second transistors T1 and T2 are N-type transistors, and the second node N2, to which the cathode of the light emitting device LD and the pixel driver PDC-1 are connected, may correspond to the drain of the first transistor T1. That is, the change in the gate-source voltage Vgs of the first transistor T1 due to the light emitting device LD can be prevented. Therefore, the amount of change in driving current due to deterioration of the light emitting device LD is reduced, thereby reducing image retention in the display panel as the use time increases and improving the lifespan.

[0119] As shown in FIG. 4C, pixel PXij-2 may include a pixel driver PDC-2 that includes six transistors T1, T2, T3, T4a, T5a, and T6a and two capacitors C1 and C2.

[0120] The pixel driving unit PDC-2 may be connected to the light emitting element LD, the write scan line GWLi, the reset scan line GRLi, the compensation scan line GCLi, the i-th first light emitting line ESL1i (hereinafter referred to as the first light emitting line), the i-th second light emitting line ESL2i (hereinafter referred to as the second light emitting line), the data line DLj, the first power supply line VDL, the second power supply line VSL, the third power supply line VRL, and the initialization voltage line VIL.

[0121] The pixel driver PDC-2 shown in Figure 4C may have a structure similar to that of the pixel driver PDC shown in Figure 4A, except that the fourth transistor T4 and the fifth transistor T5 are omitted. Because the area of ​​the pixel driver PDC-2 shown in Figure 4C is smaller than the area of ​​the pixel driver PDC shown in Figure 4A, it may be easier to implement high resolution.

[0122] Each of the first to sixth transistors T1, T2, T3, T4a, T5a, and T6a may be an N-type or P-type transistor. In this embodiment, a case where each of the first to sixth transistors T1, T2, T3, T4a, T5a, and T6a is an N-type transistor will be described as an example.

[0123] The first transistor T1 may include a gate connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The second node N2 may be a node connected to a first power line VDL, and the third node N3 may be a node connected to a second power line VSL. The first transistor T1 is connected to the light emitting element LD through the second node N2 and to the second power line VSL through the third node N3. The first transistor T1 may be a driving transistor.

[0124] The second transistor T2 may include a gate receiving a write scan signal GW through a write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1, and may provide a data signal DATA to the first node N1 in response to the write scan signal GW transmitted through the write scan line GWLi.

[0125] The third transistor T3 may be connected between the first node N1 and a reference voltage line VRL. A first electrode of the third transistor T3 may receive the reference voltage VREF through the reference voltage line VRL, and a second electrode of the third transistor T3 may be connected to the first node N1. In this embodiment, a gate of the third transistor T3 may receive a reset scan signal GR through a reset scan line GRLi. When the reset scan signal GR is supplied to the reset scan line GRLi, the third transistor T3 is turned on to provide the reference voltage VREF to the first node N1.

[0126] The fourth transistor T4a may be connected between the first transistor T1 and the light emitting element LD. Specifically, the gate of the fourth transistor T4a may receive a first light emitting signal EM1 through a first light emitting line ESL1i. A first electrode of the fourth transistor T4a may be connected to the cathode of the light emitting element LD through a fourth node N4, and a second electrode of the fourth transistor T4a may be connected to the first electrode of the first transistor T1 through a second node N2. The fourth transistor T4a may be referred to as a first light emitting control transistor. When the first light emitting signal EM1 is supplied to the first light emitting line ESL1i, the fourth transistor T4a may be turned on to electrically connect the light emitting element LD and the first transistor T1.

[0127] The fifth transistor T5a may be connected between the second power line VSL and the third node N3. A first electrode of the fifth transistor T5a may be connected to the second electrode of the first transistor T1 through the third node N3, and a second electrode of the fifth transistor T5a may receive the second power voltage VSS through the second power line VSL. A gate of the fifth transistor T5a may be electrically connected to the second light-emitting line ESL2i. The fifth transistor T5a may be referred to as a second light-emitting control transistor. When a second light-emitting signal EM2 is provided to the second light-emitting line ESL2i, the fifth transistor T5a is turned on to electrically connect the second electrode of the first transistor T1 to the second power line VSL.

[0128] Meanwhile, in this embodiment, the fourth transistor T4a and the fifth transistor T5a are connected to first and second light-emitting lines ESL1i and ESL2i, respectively, and may be turned on by first and second light-emitting signals EM1 and EM2, respectively. That is, the fourth transistor T4a and the fifth transistor T5a may be turned on independently. However, this is merely an example and is not limiting. For example, in an embodiment of the present invention, the fourth transistor T4a and the fifth transistor T5a may be connected to the same light-emitting line and controlled by the same light-emitting signal. Also, in the pixel driver PDC-2 according to an embodiment of the present invention, either the fourth transistor T4a or the fifth transistor T5a may be omitted.

[0129] The sixth transistor T6a may be connected between the initialization voltage line VIL and the fourth node N4. That is, the sixth transistor T6a may include a gate connected to the compensation scan line GCLi, a first electrode connected to the initialization voltage line VIL, and a second electrode connected to the fourth node N4. The sixth transistor T6a may be referred to as an initialization transistor. The sixth transistor T6a may supply the initialization voltage VINT to the fourth node N4 corresponding to the cathode of the light emitting element LD in response to the compensation scan signal GC transmitted through the compensation scan line GCLi. The cathode of the light emitting element LD may be initialized by the initialization voltage VINT.

[0130] The first capacitor C1 may be disposed between the first node N1 and the third node N3. The first capacitor C1 may store a differential voltage between the first node N1 and the third node N3. The first capacitor C1 may be referred to as a storage capacitor.

[0131] The second capacitor C2 may be disposed between the third node N3 and the second power line VSL. That is, one electrode of the second capacitor C2 may be coupled to the second power line VSL, which receives the second power voltage VSS, and the other electrode of the second capacitor C2 may be coupled to the third node N3. The second capacitor C2 may store a charge corresponding to the voltage difference between the second power voltage VSS and the third node N3. The second capacitor C2 may be referred to as a hold capacitor.

[0132] The light emitting device LD may include an anode and a cathode. In this embodiment, the anode of the light emitting device LD is connected to the first power line VDL, and the cathode is connected to the pixel driving unit PDC-2 through a fourth node N4. In this embodiment, the cathode of the light emitting device LD may be connected to the first transistor T1 through a fourth transistor T4a. The light emitting device LD may emit light in response to the amount of current flowing through the first transistor T1 of the pixel driving unit PDC-1.

[0133] In this embodiment, the first to sixth transistors T1, T2, T3, T4a, T5a, and T6a are N-type transistors, and the potential of the third node N3 corresponding to the source of the first transistor T1, which is a driving transistor, is not directly affected by the characteristics of the light emitting device LD. Therefore, even if degradation of the light emitting device LD occurs, the influence on the transistors constituting the pixel driver PDC-2, particularly the gate-source voltage Vgs of the driving transistor, can be reduced. In other words, since the amount of change in driving current due to degradation of the light emitting device LD is reduced, image retention defects of the display panel that occur over time can be reduced and the lifespan can be improved.

[0134] Meanwhile, Figures 4A, 4B, and 4C show circuits for pixel drivers PDC, PDC-1, and PDC-2 according to an embodiment of the present invention, and the display panel according to an embodiment of the present invention may be designed in various ways with respect to the number and arrangement of transistors and the number and arrangement of capacitors as long as the circuit is connected to the cathode of the light emitting element LD, and is not limited to any one embodiment.

[0135] 5A and 5B are simplified plan views illustrating a display panel according to an embodiment of the present invention. Some components are omitted in each of FIGS. 5A and 5B. Hereinafter, the present invention will be described with reference to FIGS. 5A and 5B.

[0136] Referring to FIG. 5A, the display panel DP may be divided into a display area DA and a non-display area (or peripheral area NDA). The display area DA may include a plurality of light-emitting portions EP. These light-emitting portions EP may be areas that are respectively illuminated by pixels PXij (see FIG. 3). Specifically, each of the light-emitting portions EP may correspond to a light-emitting opening OP-PDL (see FIG. 8), which will be described later.

[0137] The non-display area NDA may be disposed adjacent to the display area DA. In the present embodiment, the non-display area NDA is illustrated as surrounding the edge of the display area DA. However, this is merely an example, and the non-display area NDA may be disposed on one side of the display area DA or may be omitted, and is not limited to any one embodiment.

[0138] In one embodiment, the data driver DDC may be provided in the form of a separate driver chip independent of the display panel DP and connected to the display panel DP, but this is merely an example, and the data driver DDC may be formed in the same process as the scan driver SDC to form the display panel DP, and is not limited to any one embodiment.

[0139] The display panel DP may have a length in the first direction DR1 that is longer than a length in the second direction DR2. A plurality of pixels PX11 to PXnm are exemplarily illustrated as being arranged in n rows and m columns in the display area DA. In this embodiment, the display panel DP may include a plurality of scan drivers SDC1 and SDC2. The scan drivers SDC1 and SDC2 are exemplarily illustrated as including a first scan driver SDC1 and a second scan driver SDC2 that are spaced apart from each other in the first direction DR1.

[0140] The first scan driver SDC1 may be connected to some of the scan lines GL1 to GLn, and the second scan driver SDC2 may be connected to other parts of the scan lines GL1 to GLn. For example, the first scan driver SDC1 may be connected to odd-numbered scan lines among the scan lines GL1 to GLn, and the second scan driver SDC2 may be connected to even-numbered scan lines among the scan lines GL1 to GLn.

[0141] 5A illustrates pads PD of the data lines DL1 to DLm for ease of explanation. The pads PD may be defined at the ends of the data lines DL1 to DLm. The data lines DL1 to DLm may be connected to the data driver DDC (see FIG. 3) through the pads PD.

[0142] 5A, the pads PD may be divided and arranged in the non-display area NDA at positions spaced apart from each other across the display area DA. For example, some of the pads PD may be arranged on the upper side, i.e., adjacent to the first scan line GL1 among the scan lines GL1 to GLn, and other pads PD may be arranged on the lower side, i.e., adjacent to the last scan line GLn among the scan lines GL1 to GLn. In this embodiment, the pads PD connected to odd-numbered data lines among the data lines DL1 to DLm may be arranged on the upper side, and the pads PD connected to even-numbered data lines among the data lines DL1 to DLm may be arranged on the lower side.

[0143] Although not shown, the display panel DP may include a plurality of lower data drivers connected to the pads PD arranged below it, but this is merely an example, and the display panel DP may include only one lower data driver connected to the pad PD arranged below it.

[0144] In FIG. 5A, the scan drivers SDC1 and SDC2 of the display panel DP may be arranged in the display area DA, and accordingly, some of the light emitting units EP arranged in the display area DA may overlap the scan drivers SDC1 and SDC2 on a plane.

[0145] 5B, the scan driver SDC and the data driver DDC may be implemented on a display panel DP. In one embodiment, the scan driver SDC may be disposed in the display area DA, and the data driver DDC may be disposed in the non-display area NDA. The scan driver SDC may overlap at least some of the plurality of light emitting units EP disposed in the display area DA in a planar manner. Since the scan driver SDC is disposed in the display area DA, the area of ​​the non-display area NDA may be reduced compared to a conventional display panel in which the scan driver is disposed in the non-display area, making it easier to implement a display device with a thin bezel.

[0146] Meanwhile, unlike the configuration shown in Fig. 5B, the scan driver SDC may be provided in two separate parts as shown in Fig. 5A. The two scan drivers SDC may be spaced apart on the left and right sides of the center of the display area DA. Alternatively, the number of scan drivers SDC may be greater than two, and the present invention is not limited to any one embodiment.

[0147] 5B shows an example of a display panel DP, and the data driver DDC may be disposed in the display area DA, where a portion of the light emitting unit EP disposed in the display area DA may overlap the data driver DDC in a plane.

[0148] FIG. 6 is a plan view of a display panel and a driving circuit unit according to an embodiment of the present invention.

[0149] 6, an electronic device ED according to an embodiment of the present invention may include a display panel DP and a driving circuit unit DC. The driving circuit unit DC may be electrically connected to the display panel DP. The driving circuit unit DC may include a main circuit board MB and flexible films CF1, CF2, and CF3.

[0150] A series of pixels PXij (see FIG. 3) may be arranged in a display area DA of a display panel DP. The pixels PXij may be arranged in a first direction DR1 and a second direction DR2. FIG. 6 illustrates some pixels PX1 and PX2 among the pixels PXij. The pixels PX1 and PX2 may include a first pixel PX1 and a second pixel PX2. Each of the first pixel PX1 and the second pixel PX2 may be one pixel among the series of pixels PXij. The first pixel PX1 and the second pixel PX2 may have substantially the same configuration.

[0151] The flexible films CF1, CF2, and CF3 are electrically connected to the display panel DP. The flexible films CF1, CF2, and CF3 may be connected to a pad portion PDP of the display panel DP disposed in the non-display area NDA. The flexible film CF provides electrical signals to the display panel DP for driving the display panel DP. The electrical signals may be generated by the flexible films CF1, CF2, and CF3 or may be generated by the main circuit board MB. The flexible films CF1, CF2, and CF3 may include a first flexible film CF1, a second flexible film CF2, and a third flexible film CF3 arranged along the first direction DR1. Unlike the configuration shown in FIG. 6, the flexible films CF1, CF2, and CF3 may be provided as a single flexible film or as a plurality of four or more flexible films.

[0152] The main circuit board MB may include various drive circuits for driving the display module DM, connectors for power supply, etc. In Fig. 6, only the power supply unit PWS disposed on the main circuit board MB is illustrated as an example.

[0153] The pad part PDP may include a first pad PD1 and a second pad PD2. The pad part PDP may be a portion to which the flexible films CF1, CF2, and CF3 are connected. The pad part PDP may include various pads such as a data pad (not shown) or an input pad (not shown), but in the present invention, only the first pad PD1 and the second pad PD2 associated with the voltages provided to the pixels PX1 and PX2 are shown.

[0154] The pad part PDP may overlap the non-display area NDA. The pad part PDP may be disposed adjacent to the lower end of the display panel DP. However, the arrangement of the pad part PDP is not limited thereto and may be disposed in various positions.

[0155] The first pad PD1 is disposed in the non-display area NDA and can receive first and second voltages VDD1 and VDD2. The first pad PD1 is electrically connected to the pixels PX1 and PX2 and can provide the first and second voltages VDD1 and VDD2 to the pixels PX1 and PX2. The first pad PD1 can include a first-1 pad PD1-1 that receives the first voltage VDD1 and a first-2 pad PD1-2 that receives the second voltage VDD2. The first-1 pad PD1-1 can be electrically connected to the first pixel PX1 and can provide the first voltage VDD1 to the first-1 electrode EL1_1 (see FIG. 7D) of the first pixel PX1, and the first-2 pad PD1-2 can be electrically connected to the second pixel PX2 and can provide the second voltage VDD2 to the first-2 electrode EL1_2 (see FIG. 7D) of the second pixel PX2. The second pad PD2 is disposed in the non-display area NDA and can receive the second power supply voltage VSS. The second pad PD2 may be electrically connected to the pixels PX1 and PX2 to provide the second power supply voltage VSS to the second electrodes EL2 (see FIG. 7A) of the pixels PX1 and PX2.

[0156] The display panel DP may include a first power line PL1 and a second power line PL2. The first power line PL1 may include a first power line PL1-1 and a second power line PL1-2. The first power line PL1-1 and the first power line PL1-2 may overlap the display area DA. The first power line PL1-1 and the first power line PL1-2 may extend along the second direction DR2. In FIG. 6, the first power line PL1 is illustrated as including two power lines, a first power line PL1-1 and a second power line PL1-2, but is not limited thereto and may further include a power line electrically connected to each pixel arranged in the display area DA.

[0157] The first-1 power line PL1-1 may be electrically connected to the first pixel PX1. The first-1 power line PL1-1 may be electrically connected to the first-1 electrode EL1_1 (see FIG. 7D) of the first pixel PX1 and may supply the first voltage VDD1 applied from the first-1 pad PD1-1. The first-2 power line PL1-2 may be electrically connected to the first-2 electrode EL1_2 (see FIG. 7D) of the second pixel PX2 and may supply the second voltage VDD2 applied from the first-2 pad PD1-2.

[0158] The second power lines PL2 may overlap the display area DA and extend along the first direction DR1 or the second direction DR2. The second power lines PL2 may cross the display area DA in the first direction DR1 or the second direction DR2. A plurality of second power lines PL2 may be provided. The second power lines PL2 may extend along the second direction DR2 and be arranged along the first direction DR1, and may extend along the first direction DR1 and be arranged along the second direction DR2. One second power line PL2 may be arranged for each pixel column extended in the second direction DR2, and one second power line PL2 may be arranged for each pixel row extended in the first direction DR1.

[0159] The second power supply line PL2 may be electrically connected to the second pad PD2. Each of the first power supply lines PL1 may be electrically connected to a series of pixels PXij (see FIG. 3). The second power supply line PL2 may be electrically connected to the series of pixels PXij and may supply a second power supply voltage VSS applied from the second pad PD2.

[0160] The power supply unit PWS may be disposed on the main circuit board MB. The power supply unit PWS may generate first power supply voltages VDD1 to VDDx and a second power supply voltage VSS. The pad unit PDP may be electrically connected to the power supply unit PWS. The power supply unit PWS may be electrically connected to the first power line PL1 and the second power line PL2 through the pad unit PDP. The power supply unit PWS may apply a first voltage VDD1 to the 1-1 pad PD1-1, a second voltage VDD2 to the 1-2 pad PD1-2, and a second power supply voltage VSS to the 2nd pad PD2. As a result, the power supply unit PWS may apply the first voltage VDD1 to the 1st pixel PX1 and the second voltage VDD2 to the 2nd pixel PX2. Although not shown, the power supply unit PWS may apply third voltages VDD3 to xth voltages VDDx to the 1-3 pad to the 1-xth pad, respectively.

[0161] 7A to 7D are enlarged plan views of a display panel according to an embodiment of the present invention, specifically, FIG. 7A is an enlarged view of an area AA′ shown in FIG.

[0162] 7A illustrates two rows and two columns of light emitting units UT11, UT12, UT21, and UT22. Referring to FIG. 7A, the light emitting unit in the first row Rk includes light emitting units constituting the light emitting unit UT11 in the first row and the first column and the light emitting unit UT12 in the first row and the second column, and the light emitting unit in the second row Rk+1 includes light emitting units constituting the light emitting unit UT21 in the second row and the first column and the light emitting unit UT22 in the second row and the second column. In this embodiment, the light emitting unit UT11 in the first row and the first column is included in the first pixel PX1 shown in FIG. 6, and the light emitting unit UT21 in the second row and the first column is included in the second pixel PX2 shown in FIG. 6. The rows may correspond to a first direction DR1, and the columns may correspond to a second direction DR2.

[0163] Each of the light-emitting portions EP1, EP2, and EP3 may correspond to a light-emitting opening OP-PDL (see FIG. 8) described below. That is, each of the light-emitting portions EP1, EP2, and EP3 may be an area from which light is emitted by the light-emitting element described above. The light-emitting portions EP1, EP2, and EP3 may correspond to a unit that configures an image displayed on the display panel DP (see FIG. 2A). More specifically, each of the light-emitting portions EP1, EP2, and EP3 may correspond to an area defined by a light-emitting opening OP-PDL described below, in particular an area defined by the bottom surface of the light-emitting opening OP-PDL.

[0164] The light-emitting units EP1, EP2, and EP3 may include a first light-emitting unit EP1, a second light-emitting unit EP2, and a third light-emitting unit EP3. That is, the first pixel PX1 (see FIG. 6) and the second pixel PX2 (see FIG. 6) may include a first light-emitting unit EP1, a second light-emitting unit EP2, and a third light-emitting unit EP3, respectively. The first pixel PX1 and the second pixel PX2 may each include three sub-pixels. The three sub-pixels may correspond to the first light-emitting unit EP1, the second light-emitting unit EP2, and the third light-emitting unit EP3, respectively.

[0165] The first, second, and third light-emitting units EP1, EP2, and EP3 may emit light of different colors. For example, the first light-emitting unit EP1 may emit red light, the second light-emitting unit EP2 may emit green light, and the third light-emitting unit EP3 may emit blue light, but the color combinations are not limited to these. Furthermore, at least two of the first, second, and third light-emitting units EP1, EP2, and EP3 may emit light of the same color. For example, all of the first, second, and third light-emitting units EP1, EP2, and EP3 may emit blue light or white light.

[0166] The third light emitting unit EP3, which displays light emitted by a third light emitting element among the first to third light emitting units EP1, EP2, and EP3, may include two sub-light emitting units EP31 and EP32 spaced apart from each other in the second direction DR2. However, this is merely an example, and the third light emitting unit EP3 may be provided in a single pattern having an integrated shape like the first and second light emitting units EP1 and EP2, or at least one of the first and second light emitting units EP1 and EP2 may include sub-light emitting units spaced apart from each other, and is not limited to any one embodiment.

[0167] The light-emitting section in the first row Rk includes first to third light-emitting sections EP1, EP2, EP3 that constitute the light-emitting unit UT11 in the first row and first column, and first to third light-emitting sections EP1, EP2, EP3a that constitute the light-emitting unit UT12 in the first row and second column, and the light-emitting section in the second row Rk+1 includes first to third light-emitting sections EP1, EP2, EP3a that constitute the light-emitting unit UT21 in the second row and first column, and first to third light-emitting sections EP1, EP2, EP3 that constitute the light-emitting unit UT22 in the second row and second column.

[0168] In one embodiment of the present invention, the shape of the light emitting portion of the light emitting unit UT11 in the first row and first column may be substantially the same as that of the light emitting portion of the light emitting unit UT22 in the second row and second column. Also, the shape of the light emitting portion of the light emitting unit UT12 in the first row and second column may be substantially the same as that of the light emitting portion of the light emitting unit UT21 in the second row and first column. The shape of the light emitting portion of the light emitting unit UT11 in the first row and first column may be different from the shape of the light emitting portion of the light emitting unit UT12 in the first row and second column. For example, a portion of the light emitting portion in the first row Rk and a portion of the light emitting portion in the second row Rk+1 may have symmetrical shapes.

[0169] In one embodiment of the present invention, the third light-emitting part EP3a of the light-emitting unit UT21 in the second row and first column and the third light-emitting part EP3 of the light-emitting unit UT11 in the first row and first column may have a shape and arrangement that is line-symmetrical with respect to an axis along the first direction DR1, and the third light-emitting part EP3 of the light-emitting unit UT22 in the second row and second column and the third light-emitting part EP3a of the light-emitting unit UT12 in the first row and second column may have a shape and arrangement that is line-symmetrical with respect to the axis along the first direction DR1, but this is merely an example and is not limiting.

[0170] 7B illustrates light-emitting portions arranged in a row. For ease of explanation, FIG. 7B also illustrates a plurality of second electrodes EL2_1, EL2_2, and EL2_3 (also referred to as cathodes), a plurality of pixel P driving circuits PDC1, PDC2, and PDC3, first to third connecting electrodes CNE1, CNE2, and CNE3, and a separator SPR. 7C illustrates a separator SPR within the display panel, a plurality of light-emitting portions EP1, EP2, and EP3, and a plurality of connecting electrodes CNE1, CNE2, and CNE3 arranged within an area defined by the separator SPR.

[0171] 7B and 7C, the first to third cathodes EL2_1, EL2_2, and EL2_3 may be electrically isolated from each other by separators SPR. The first to third cathodes EL2_1, EL2_2, and EL2_3 may also be referred to as second sub-electrodes in the present invention. In this embodiment, one light-emitting unit UT11 may include three light-emitting portions EP1, EP2, and EP3. Therefore, the light-emitting unit UT11 may include three light-emitting portions EP1, EP2, and EP3, three pixel driving portions PDC1, PDC2, and PDC3, and three connecting electrodes CNE1, CNE2, and CNE3. However, this is merely an example, and the number and arrangement of the light-emitting portions included in the light-emitting unit UT11 may be variously designed and is not limited to any one embodiment.

[0172] The first to third pixel driving units PDC1, PDC2, and PDC3 are electrically connected to the first to third light emitting elements LD1, LD2, and LD3, respectively, including the first to third light emitting units EP1, EP2, and EP3. In this specification, "connected" refers to being connected in direct physical contact as well as being electrically connected.

[0173] Also, as shown in FIG. 7B, each area in which the first to third pixel driving units PDC1, PDC2, and PDC3 are partitioned (defined) on a plane may correspond to a unit in which transistors and capacitor elements constituting the pixel driving unit PDC (see FIG. 4A) for driving the light emitting element of the pixel are repeatedly arranged.

[0174] The first to third pixel driving units PDC1, PDC2, and PDC3 may be sequentially arranged along the first direction DR1. Meanwhile, the arrangement positions of the first to third pixel driving units PDC1, PDC2, and PDC3 may be designed independently, regardless of the positions and shapes of the first to third light emitting units EP1, EP2, and EP3.

[0175] For example, the first to third pixel driving units PDC1, PDC2, and PDC3 may be arranged at positions different from the positions of the regions defined by the separators SPR, i.e., the first to third cathodes EL2_1, EL2_2, and EL2_3, or may be designed to have shapes and areas different from the shapes of the first to third cathodes EL2_1, EL2_2, and EL2_3. Alternatively, the first to third pixel driving units PDC1, PDC2, and PDC3 may be arranged to overlap the positions of the first to third light emitting units EP1, EP2, and EP3, respectively, and may be designed to have shapes having areas similar to the regions defined by the separators SPR, e.g., the first to third cathodes EL2_1, EL2_2, and EL2_3.

[0176] In this embodiment, the first to third pixel driving units PDC1, PDC2, and PDC3 are each illustrated as a rectangle, the first to third light emitting units EP1, EP2, and EP3 are each arranged to have a smaller area and a different shape than the corresponding pixel driving units, and the first to third cathodes EL2_1, EL2_2, and EL2_3 are illustrated as having an irregular shape and are arranged at positions overlapping the first to third light emitting units EP1, EP2, and EP3.

[0177] 7B, the first pixel driver PDC1 may be disposed at a position where it partially overlaps with the first light emitter EP1, the second light emitter EP2, and other adjacent light emitting units. The second pixel driver PDC2 may be disposed at a position where it overlaps with the first light emitter EP1, the second light emitter EP2, and the third cathode EL2_3. The third pixel driver PDC3 may be disposed at a position where it overlaps with the third light emitter EP3. However, this is merely an example, and the positions and arrangements of the first to third pixel drivers PDC1, PDC2, and PDC3 may be designed in various shapes and arrangements independent of the first to third light emitters EP1, EP2, and EP3, and are not limited to any one embodiment.

[0178] The light emitting unit UT11 may include first to third connecting electrodes CNE1, CNE2, and CNE3. The first connecting electrode CNE1 electrically connects the first light emitting element LD1 forming the first light emitting portion EP1 (or the first light emitting portion EP1 is defined) to the first pixel driving circuit PDC1, the second connecting electrode CNE2 electrically connects the second light emitting element LD2 forming the second light emitting portion EP2 to the second pixel driving circuit PDC2, and the third connecting electrode CNE3 electrically connects the third light emitting element LD3 forming the third light emitting portion EP3 to the third pixel driving circuit PDC3. Each of the first to third light emitting elements LD1, LD2, and LD3 may include a first electrode EL1, an intermediate layer IML disposed on the first electrode EL1, and a second electrode EL2 disposed on the intermediate layer.

[0179] Specifically, the first to third connecting electrodes CNE1, CNE2, and CNE3 may electrically connect the first to third cathodes EL2_1, EL2_2, and EL2_3 to the first to third pixel driving parts PDC1, PDC2, and PDC3 in a one-to-one correspondence, respectively. For example, the first connecting electrode CNE1 may be electrically connected to the first pixel driving part PDC1 and the first cathode EL2_1, the second connecting electrode CNE2 may be electrically connected to the second pixel driving part PDC2 and the second cathode EL2_2, and the third connecting electrode CNE3 may be electrically connected to the third pixel driving part PDC3 and the third cathode EL2_3.

[0180] Each of the first to third connecting electrodes CNE1, CNE2, and CNE3 may be disposed on a pixel definition layer PDL (see FIG. 8 ), which will be described later. The first to third connecting electrodes CNE1, CNE2, and CNE3 may have a ring shape surrounding the corresponding first to third light emitting portions EP1, EP2, and EP3. In one embodiment of the present invention, each of the first to third connecting electrodes CNE1, CNE2, and CNE3 has a closed line ring shape, but this is not limiting. For example, at least some of the first to third connecting electrodes CNE1, CNE2, and CNE3 may have an open ring shape with a broken portion.

[0181] Because the first to third connecting electrodes CNE1, CNE2, and CNE3 have a ring shape, the degree of freedom in the positions at which the first to third connecting electrodes CNE1, CNE2, and CNE3 are connected to the first to third pixel driving parts PDC1, PDC2, and PDC3 may be improved. For example, the first connecting electrode CNE1 may be connected to the first pixel driving part PDC1 through the first connecting part CE1, the second connecting electrode CNE2 may be connected to the second pixel driving part PDC2 through the second connecting part CE2, and the third connecting electrode CNE3 may be connected to the third pixel driving part PDC3 through the connecting wire CN3. That is, additional connecting wires connected to the first and second connecting electrodes CNE1 and CNE2 may be omitted.

[0182] One connection line CN3 may electrically connect the third pixel driver PDC3 and the third light emitting element LD3 constituting the third light emitting unit EP3. Specifically, the connection line CN3 may correspond to a node (see the fourth node N4 in FIG. 4A, the second node N2 in FIG. 4B, or the fourth node N4 in FIG. 4C) at which the light emitting element LD (see FIG. 4A) is connected to the pixel driver (PDC in FIG. 4A, PDC-1 in FIG. 4B, or PDC-2 in FIG. 4C).

[0183] The connecting wire CN3 may include a third connecting part CE3 and a driving connecting part CD3, The third connecting part CE3 may be provided on one side of the connecting wire CN3, and the driving connecting part CD3 may be provided on the other side of the connecting wire CN3.

[0184] The driving connection part CD3 may be a part of the connecting line CN3 that is connected to the pixel driver PDC3. In this embodiment, the driving connection part CD3 may be connected to one electrode of a transistor constituting the pixel driver PDC3. Specifically, the driving connection part CD3 may be connected to the drain of the sixth transistor T6 shown in FIG. 4A, the drain of the first transistor T1 shown in FIG. 4B, or the drain of the fourth transistor T4a shown in FIG. 4C. Therefore, the position of the driving connection part CD3 may correspond to the position of a transistor physically connected to the connecting line CN3 in the pixel driver. The third connection part CE3 may be a part of the connecting line CN3 that is connected to the third light emitting element LD3. In this embodiment, the third connection part CE3 may be connected to the third connecting electrode CNE3.

[0185] The first linking electrode CNE1 may include a first edge EG11 surrounding at least a portion of the first light-emitting portion EP1 and a second edge EG12 surrounding the first edge EG11. The second linking electrode CNE2 may include a first edge EG21 surrounding at least a portion of the second light-emitting portion EP2 and a second edge EG22 surrounding the first edge EG21. The third linking electrode CNE3 may include a first edge EG31 surrounding at least a portion of the third light-emitting portion EP3 and a second edge EG32 surrounding the first edge EG31.

[0186] The first to third connecting electrodes CNE1, CNE2, and CNE3 may be arranged spaced apart from one another. For example, gaps GP1, GP2, and GP3 between adjacent connecting electrodes among the first to third connecting electrodes CNE1, CNE2, and CNE3 may overlap with separators SPR. For example, first edges EG11, EG21, and EG31 of the first to third connecting electrodes CNE1, CNE2, and CNE3 may not be covered with separators SPR, and second edges EG12, EG22, and EG32 of the first to third connecting electrodes CNE1, CNE2, and CNE3 may overlap with separators SPR. Alternatively, the second edges EG12, EG22, and EG32 of the first to third connecting electrodes CNE1, CNE2, and CNE3 may be covered with separators SPR.

[0187] In an embodiment of the present invention, the first to third connection parts CE1, CE2, and CE3 may be arranged at positions that do not overlap the first to third light emitting parts EP1, EP2, and EP3 in a plan view. For example, a light emitting opening OP-PDL (see FIG. 8) and a through hole OP-P (see FIG. 8) spaced apart from the light emitting opening OP-PDL may be defined in the pixel defining (defining) layer PDL.

[0188] The through holes OP-P may include a first through hole OP-P1, a second through hole OP-P2, and a third through hole OP-P3. The first to third connection portions CE1, CE2, and CE3 may be arranged corresponding to the first to third through holes OP-P1, OP-P2, and OP-P3, respectively. The light-emitting opening OP-PDL may include a first light-emitting opening OP-PDL1, a second light-emitting opening OP-PDL2, and a third light-emitting opening OP-PDL3. The first to third light-emitting portions EP1, EP2, and EP3 may be defined corresponding to the first to third light-emitting openings OP-PDL1, OP-PDL2, and OP-PDL3, respectively. Therefore, the first to third connection portions CE1, CE2, and CE3 may be arranged at positions spaced apart from the first to third light-emitting portions EP1, EP2, and EP3.

[0189] The first to third connecting electrodes CNE1, CNE2, and CNE3 may be disposed on the pixel definition film PDL (see FIG. 8). In a plan view, the first connecting electrode CNE1 may surround the first light-emitting opening OP-PDL1, the second connecting electrode CNE2 may surround the second light-emitting opening OP-PDL2, and the third connecting electrode CNE3 may surround the third light-emitting opening OP-PDL3.

[0190] The first to third cathodes EL2_1, EL2_2, and EL2_3 may be connected to the first to third connecting electrodes CNE1, CNE2, and CNE3. For example, the bottom surfaces of the first to third cathodes EL2_1, EL2_2, and EL2_3 may be connected to (or in contact with) the top surfaces of the first to third connecting electrodes CNE1, CNE2, and CNE3, respectively. Therefore, the contact reliability (or connection stability) between the first to third cathodes EL2_1, EL2_2, and EL2_3 and the first to third connecting electrodes CNE1, CNE2, and CNE3 may be further improved.

[0191] In addition, connection regions where the first to third cathodes EL2_1, EL2_2, and EL2_3 and the first to third connecting electrodes CNE1, CNE2, and CNE3 are connected may surround at least a portion of the first to third light-emitting openings OP-PDL1, OP-PDL2, and OP-PDL3, respectively. The first to third cathodes EL2_1, EL2_2, and EL2_R and the first to third connecting electrodes CNE1, CNE2, and CNE3 may be connected in regions adjacent to the separators SPR, and each of the connection regions may be defined adjacent to the separators SPR. That is, the first to third cathodes EL2_1, EL2_2, and EL2_R and the first to third connecting electrodes CNE1, CNE2, and CNE3 may be connected over a relatively wide area, for example, an area similar in shape to the first to third connecting electrodes CNE1, CNE2, and CNE3, rather than at a specific point, which increases the area of ​​the connection region and allows for stable connection.

[0192] FIG. 7D illustrates the separator SPR, the light emitting portions EP1, EP2, and EP3, the first electrode EL1, the conductive layer MCL, and the first power supply line PL1.

[0193] 7D, the first electrode EL1 may include a first-first electrode EL1_1 disposed in the first light-emitting unit (or the light-emitting unit in the first row and first column) UT11 and a first-second electrode EL1_2 disposed in the second light-emitting unit (or the light-emitting unit in the second row and first column) UT21. The first-first electrode EL1_1 may include first to third anodes AE1, AE2, and AE3, and the first-second electrode EL1_2 may include first to third anodes AE1a, AE2a, and AE3a. The third anode AE3 may be separated into two and spaced apart from each other in the second direction DR2. However, this is merely an example, and the third anode AE3 may be provided in a single pattern having an integral shape like the first and second anodes AE1 and AE2. The descriptions of the first to third anodes AE1, AE2, and AE3 and the first to third anodes AE1a, AE2a, and AE3a may be the same. In the present invention, the first to third anodes AE1, AE2, and AE3 and the first to third anodes AE1a, AE2a, and AE3a may each be referred to as a first sub-electrode.

[0194] The first to third anodes AE1, AE2, and AE3 may be formed as independent conductive patterns spaced apart from one another. That is, the first to third anodes AE1, AE2, and AE3 may be electrically isolated by separators SPR. The first to third anodes AE1, AE2, and AE3 may be disposed so as to overlap the first to third light-emitting portions EP1, EP2, and EP3. The first anode AE1 may have a shape corresponding to the first light-emitting portion EP1, the second anode AE2 may have a shape corresponding to the second light-emitting portion EP2, and the third anode AE3 may have a shape corresponding to the third light-emitting portion EP3. The area of ​​each of the first to third anodes AE1, AE2, and AE3 may be larger than the area of ​​each of the first to third light-emitting portions EP1, EP2, and EP3.

[0195] The conductive layer MCL may include a first conductive layer MCL1 disposed in the first light-emitting unit UT11 and a second conductive layer MCL2 disposed in the second light-emitting unit UT21. The first conductive layer MCL1 and the second conductive layer MCL2 may be spaced apart from each other in the second direction DR2. The first conductive layer MCL1 and the second conductive layer MCL2 may be electrically disconnected from each other. Although not shown, the conductive layer MCL may further include a third conductive layer disposed in the third light-emitting unit (or the light-emitting unit in the first row and second column) UT12 and a fourth conductive layer disposed in the fourth light-emitting unit (or the light-emitting unit in the second row and second column) UT22. The descriptions of the third conductive layer and the fourth conductive layer may be similarly applied to the descriptions of the first conductive layer MCL1 and the second conductive layer MCL2.

[0196] The first conductive layer MCL1 and the second conductive layer MCL2 may each include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO). Alternatively, the transparent conductive layer may include a conductive polymer such as PEDOT (Poly3,4-Ethylene Dioxythiophene), a metal nanowire, graphene, or the like.

[0197] The first conductive layer MCL1 and the second conductive layer MCL2 may each include a multilayer metal layer. The metal layer may have a three-layer structure of, for example, titanium (Ti) / aluminum (Al) / titanium (Ti). Alternatively, the multilayer metal layer may include at least one metal layer and at least one transparent conductive layer.

[0198] The first conductive layer MCL1 may overlap the 1-1 electrode EL1_1 in a planar manner. Specifically, the first conductive layer MCL1 may overlap each of the first to third anodes AE1, AE2, and AE3 in a planar manner. The first conductive layer MCL1 may be disposed on a different layer from the first to third anodes AE1, AE2, and AE3. The first conductive layer MCL1 may be electrically connected to each of the first to third anodes AE1, AE2, and AE3 through the first contact holes CNT1.

[0199] The second conductive layer MCL2 may overlap the first to third electrode EL1_2 in a plane. Specifically, the second conductive layer MCL2 may overlap each of the first to third anodes AE1a, AE2a, and AE3a in a plane. The second conductive layer MCL2 may be disposed on a different layer from the first to third anodes AE1a, AE2a, and AE3a. The second conductive layer MCL2 may be electrically connected to each of the first to third anodes AE1a, AE2a, and AE3a through second contact holes CNT2.

[0200] The first contact hole CNT1 may be formed at a position overlapping each of the first to third anodes AE1, AE2, and AE3 in a plan view, and the second contact hole CNT2 may be formed at a position overlapping each of the first to third anodes AE1a, AE2a, and AE3a in a plan view. The position at which the first contact hole CNT1 is formed is not limited to that shown in the drawing and may be formed at a position overlapping each of the first to third anodes AE1, AE2, and AE3, and the position at which the second contact hole CNT2 is formed is not limited to that shown in the drawing and may be formed at a position overlapping each of the first to third anodes AE1a, AE2a, and AE3a.

[0201] The first power line PL1 may include a first-1 power line PL1-1 and a first-2 power line PL1-2. The first-1 power line PL1-1 may be electrically connected to the first conductive layer MCL1. For example, the first-1 power line PL1-1 may be extended from the first conductive layer MCL1. The first-1 power line PL1-1 may be electrically connected to the first-1 electrode EL1_1 through the first conductive layer MCL1. The first-1 power line PL1-1 may apply a first voltage VDD1 (see FIG. 6) to the first-1 electrode EL1_1 through the first conductive layer MCL1. Specifically, the first-1 power line PL1-1 may apply the first voltage VDD1 commonly to each of the first to third anodes AE1, AE2, and AE3 through the first conductive layer MCL1.

[0202] The first-second power supply line PL1-2 may be electrically connected to the second conductive layer MCL2. For example, the first-second power supply line PL1-2 may be formed by extending from the second conductive layer MCL2. The first-second power supply line PL1-2 may be electrically connected to the first-second electrode EL1_2 through the second conductive layer MCL2. The first-second power supply line PL1-2 may apply a second voltage VDD2 (see FIG. 6) to the first-second electrode EL1_2 through the second conductive layer MCL2. Specifically, the first-second power supply line PL1-2 may apply the second voltage VDD2 in common to each of the first to third anodes AE1a, AE2a, and AE3a through the second conductive layer MCL2.

[0203] The first-1 power line PL1-1 and the first-2 power line PL1-2 may not overlap each other in a plane. The first-1 power line PL1-1 may be arranged to overlap the separator SPR in a plane. The first-1 power line PL1-1 and the first-2 power line PL1-2 may apply different voltages (e.g., the first voltage VDD1 and the second voltage VDD2 shown in FIG. 6) to respective pixels (e.g., the first pixel PX1 and the second pixel PX2 shown in FIG. 6). Although not shown, the first power line PL1 may further include a first-3 power line, etc., that applies a third voltage to a third pixel.

[0204] 4A, 6, and 7D, the light emitting element LD included in the first pixel PX1 receives a driving current ILD corresponding to the first voltage VDD1 and emits light having a luminance corresponding to the driving current ILD, and the light emitting element LD included in the second pixel PX2 receives a driving current ILD corresponding to the second voltage VDD2 and emits light having a luminance corresponding to the driving current ILD. That is, the first pixel PX1 and the second pixel PX2, which are different from each other and arranged in the display area DA, can independently emit light having different luminances. As a result, pixels arranged in different regions of the display area DA can emit light having different luminances, thereby providing a display panel DP with improved display quality.

[0205] In addition, by directly applying the first voltage VDD1 to the first pixel PX1 through the first-1 power line PL1-1 and directly applying the second voltage VDD2 to the second pixel PX2 through the first-2 power line PL1-2, it is possible to prevent voltage drop (IR-DROP phenomenon) caused by a longer current path, and to prevent a deterioration in the display quality of the display device DD (see Figure 2A).

[0206] FIG. 8 is a cross-sectional view of a display module according to an embodiment of the present invention. FIGS. 9A and 9B are cross-sectional views showing enlarged portions of a display panel according to an embodiment of the present invention. FIG. 8 is a cross-sectional view showing a portion corresponding to line I-I' in FIG. 7A. FIG. 9A is a cross-sectional view showing an enlarged portion BB' in FIG. 8. FIG. 9B is a cross-sectional view showing an enlarged portion DD' in FIG. 8. In describing FIGS. 8 to 9B, the same reference numerals are used to refer to the same components as those previously described, and descriptions thereof will be omitted, with differences being mainly described.

[0207] 8, a display module DM according to an embodiment of the present invention may include a base layer BL, a circuit element layer DP-CL, connecting wires CN, connecting electrodes CNE, display element layers DP-ED, an encapsulation layer ECL, and a sensing layer ISL. However, this is merely an example, and in an embodiment of the present invention, the display module DM may not include the sensing layer ISL.

[0208] The circuit element layer DP-CL may include a plurality of insulating layers 10, 20, 30, 40, 50, and 60 disposed on the base layer BL, and a plurality of conductive patterns and semiconductor patterns disposed between the insulating layers 10, 20, 30, 40, 50, and 60. The conductive patterns and semiconductor patterns may be disposed between the insulating layers 10, 20, 30, 40, 50, and 60 to form a pixel driving unit PDC. For ease of explanation, FIG. 8 exemplarily illustrates a cross section of one region among regions where one light emitting unit is disposed.

[0209] The base layer BL may be a member that provides a base surface on which the pixel driving units PDC are disposed. The base layer BL may be a rigid substrate or a flexible substrate that allows bending, folding, rolling, etc. The base layer BL may be a glass substrate, a metal substrate, a polymer substrate, etc. However, embodiments of the present invention are not limited thereto, and the base layer BL may be formed of an inorganic layer, an organic layer, or a composite material layer of inorganic and organic layers, etc.

[0210] The base layer BL may have a multi-layer structure. The base layer BL may include a first polymer resin layer, a silicon oxide (SiOx) layer disposed on the first polymer resin layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second polymer resin layer disposed on the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer may be referred to as a base barrier layer.

[0211] The polymer resin layer may include a polyimide-based resin. The polymer resin layer may also include at least one of an acrylate-based resin, a methacrylate-based resin, a polyisoprene-based resin, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. In this specification, a "-based" resin means that the resin contains a functional group of "-based."

[0212] Each of the insulating layer, conductive layer, and semiconductor layer disposed on the base layer BL may be formed by coating, deposition, etc. Then, the insulating layer, semiconductor layer, and conductive layer may be selectively patterned through multiple photolithography processes to form holes in the insulating layer, or semiconductor patterns, conductive patterns, signal lines, etc.

[0213] The circuit element layer DP-CL may include first to sixth insulating layers 10, 20, 30, 40, 50, and 60 and a pixel driver PDC, which are sequentially stacked on a base layer BL. Figure 8 exemplarily illustrates the pixel driver PDC shown in Figure 4A, and the pixel driver PDC includes one transistor TR and two capacitors C1 and C2. The transistor TR may be one of multiple transistors included in the pixel driver PDC.

[0214] The transistor TR of the pixel driver PDC corresponds to a transistor connected to the light emitting device LD through the connecting line CN and the connecting electrode CNE, i.e., a connection transistor connected to a node corresponding to the cathode of the light emitting device LD (the fourth node N4 in FIG. 4A, the second node N2 in FIG. 4B, or the fourth node N4 in FIG. 4C), and may specifically correspond to the sixth transistor T6 in FIG. 4A, the first transistor T1 in FIG. 4B, or the fourth transistor T4a in FIG. 4C. The transistor TR of the pixel driver PDC may be referred to as a connection transistor.

[0215] Meanwhile, although not shown, other transistors constituting the pixel driver PDC may have the same structure as the transistor TR shown in Fig. 8. However, this is merely an example, and other transistors constituting the pixel driver PDC may have a structure different from that of the transistor TR shown in Fig. 8, and are not limited to any one embodiment.

[0216] A first insulating layer 10 may be disposed on the base layer BL. The first insulating layer 10 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer 10 is illustrated as a single-layer silicon oxide layer. Meanwhile, insulating layers, which will be described later, may be inorganic layers and / or organic layers and may have a single-layer or multi-layer structure. The inorganic layer may include at least one of the above-mentioned materials, but is not limited thereto.

[0217] Meanwhile, the first insulating layer 10 may cover the lower conductive layer BCL. That is, the display panel DP may further include a lower conductive layer BCL disposed to overlap the transistor TR. The lower conductive layer BCL may block the transistor TR from being affected by an electric potential due to polarization of the base layer BL. The lower conductive layer BCL may also block light incident on the transistor TR from below. At least one of an inorganic barrier layer and a buffer layer may be further disposed between the lower conductive layer BCL and the base layer BL.

[0218] The lower conductive layer BCL may include a reflective metal, such as titanium (Ti), molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), and copper (Cu).

[0219] The lower conductive layer BCL may be connected to the source of the transistor TR through a source electrode pattern S1, and in this case, the lower conductive layer BCL may be synchronized with the source of the transistor TR.

[0220] A transistor TR of the pixel driver PDC may be disposed on the first insulating layer 10. The transistor TR of the pixel driver PDC may include a semiconductor pattern SP and a gate electrode GE. The semiconductor pattern SP may be disposed on the first insulating layer 10. The semiconductor pattern SP may include an oxide semiconductor. For example, the oxide semiconductor may include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3). However, without being limited thereto, the semiconductor pattern SP may include amorphous silicon, low-temperature polycrystalline silicon, or polycrystalline silicon.

[0221] Each of the semiconductor patterns SP may include a source region, a drain region, and a channel region, which are differentiated according to the degree of conductivity. For example, the semiconductor pattern SP may include a source region SR, a drain region DR, and a channel region CR. The source region SR and the drain region DR may be separated by the channel region CR. The channel region CR may overlap with the gate electrode GE in a plan view.

[0222] When the semiconductor pattern SP is an oxide semiconductor, each of the source region SR and the drain region DR may be a reduced region, i.e., the source region SR and the drain region DR have a relatively higher reduced metal content than the channel region CR, or when the semiconductor pattern SP is polycrystalline silicon, each of the source region SR and the drain region DR may be a highly doped region.

[0223] The source region SR and the drain region DR may have a relatively high conductivity compared to the channel region CR. The source region SR may correspond to a source electrode of the transistor TR, and the drain region DR may correspond to a drain electrode of the transistor TR. As shown in FIG. 8, a separate source electrode pattern S1 and a drain electrode pattern D1 may be further provided, connected to the source region SR and the drain region DR, respectively. Specifically, the separate source electrode pattern S1 and the drain electrode pattern D1 may each be integrally formed with one of the lines constituting the pixel driving unit PDC, and are not limited to any one embodiment.

[0224] The second insulating layer 20 may overlap a plurality of pixels and cover the semiconductor pattern SP. The second insulating layer 20 may be an inorganic and / or organic layer and may have a single-layer or multi-layer structure. The second insulating layer 20 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the second insulating layer 20 may be a single silicon oxide layer.

[0225] The gate electrodes GE may be disposed on the second insulating layer 20. The gate electrodes GE may correspond to the gates of the transistors TR of the pixel driving unit PDC. The gate electrodes GE may be disposed above the semiconductor patterns SP. However, this is merely an example, and each of the gate electrodes GE may be disposed below the semiconductor patterns SP, and is not limited to any one embodiment.

[0226] The gate electrode GE may include, but is not limited to, titanium (Ti), silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), or alloys thereof.

[0227] A third insulating layer 30 may be disposed on the gate electrode GE. The third insulating layer 30 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The third insulating layer 30 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0228] Among the conductive patterns S1, D1, CPE1, CPE2, and CPE3, the first capacitor electrode CPE1 and the second capacitor electrode CPE2 constitute a first capacitor C1. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 may be separated by a first insulating layer 10 and a second insulating layer 20.

[0229] In one embodiment of the present invention, the first capacitor electrode CPE1 and the lower conductive layer BCL may have an integral shape. Also, the second capacitor electrode CPE2 and the gate electrode GE may have an integral shape and be connected to each other. However, this is merely an example and the present invention is not particularly limited thereto. For example, the first capacitor electrode CPE1 and the lower conductive layer BCL may be disposed on the same layer but spaced apart from each other. The second capacitor electrode CPE2 and the gate electrode GE may be disposed on the same layer but spaced apart from each other.

[0230] A third capacitor electrode CPE3 may be disposed on the third insulating layer 30. The third capacitor electrode CPE3 may be spaced apart from the second capacitor electrode CPE2 via the third insulating layer 30 and may overlap on a plane. The third capacitor electrode CPE3 may form a second capacitor C2 together with the second capacitor electrode CPE2.

[0231] A fourth insulating layer 40 may be disposed on the third insulating layer 30 and / or the third capacitor electrode CPE3. The fourth insulating layer 40 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0232] A source electrode pattern S1 and a drain electrode pattern D1 connected to the semiconductor pattern SP may be disposed on the fourth insulating layer 40.

[0233] The source electrode pattern S1 may be connected to the source region SR of the transistor TR through the first contact hole CNT1a, and the source electrode pattern S1 and the source region SR of the semiconductor pattern SP may function as the source of the transistor TR. The drain electrode pattern D1 may be connected to the drain region DR of the transistor TR through the second contact hole CNT2a, and the drain electrode pattern D1 and the drain region DR of the semiconductor pattern SP may function as the drain of the transistor TR.

[0234] The fifth insulating layer 50 may be disposed on the source electrode pattern S1 and the drain electrode pattern D1.

[0235] A connecting wire CN may be disposed on the fifth insulating layer 50. The connecting wire CN may electrically connect the pixel driving part PDC and the light emitting element LD. That is, the connecting wire CN may electrically connect the transistor TR and the light emitting element LD. The connecting wire CN may be a connection node connecting the pixel driving part PDC and the light emitting element LD. For example, the connecting wire CN may correspond to the fourth node N4 shown in FIG. 4A.

[0236] A first conductive layer MCL1 and a first power line PL1-1 may be disposed on the fifth insulating layer 50. The first conductive layer MCL1 may be electrically connected to the light emitting device LD. The first power line PL1-1 may extend from the first conductive layer MCL1. The first conductive layer MCL1 and the first power line PL1-1 may be formed in the same process as the connecting line CN.

[0237] A sixth insulating layer 60 may be disposed on the connecting wire CN. The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 to cover at least a portion of the connecting wire CN. Each of the fifth insulating layer 50 and the sixth insulating layer 60 may be an organic layer. For example, each of the fifth insulating layer 50 and the sixth insulating layer 60 may include a general-purpose polymer such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), PMMA (Polymethylmethacrylate), or PS (Polystyrene), a polymer derivative having a phenol-based group, an acrylic-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a blend thereof.

[0238] The sixth insulating layer 60 may have a through-hole OP-60 exposing at least a portion of the connecting wire CN. The connecting wire CN may be connected to the connecting electrode CNE through a portion exposed from the sixth insulating layer 60, and thus may be electrically connected to the light emitting element LD. That is, the connecting wire CN, together with the connecting electrode CNE, may electrically connect the transistor TR and the light emitting element LD. Meanwhile, in a display panel DP according to an embodiment of the present invention, the sixth insulating layer 60 may be omitted or a plurality of sixth insulating layers 60 may be provided, and is not limited to any one embodiment. If the sixth insulating layer 60 is omitted, the connecting wire CN may also be omitted.

[0239] The connecting wire CN may include a first layer L1, a second layer L2, and a third layer L3 sequentially stacked along a third direction DR3. The second layer L2 may include a different material from the first layer L1. Also, the second layer L2 may include a different material from the third layer L3. The second layer L2 may have a relatively thicker thickness than the first layer L1. Also, the second layer L2 may have a relatively thicker thickness than the third layer L3. The second layer L2 may include a highly conductive material. In one embodiment, the second layer L2 may include aluminum (Al).

[0240] The first conductive layer MCL1 and the first-1 power supply line PL1-1 may have the same configuration as the connecting line CN. For example, the first conductive layer MCL1 and the first-1 power supply line PL1-1 may include a first layer L1a, a second layer L2a, and a third layer L3a stacked sequentially along the third direction DR3. However, the present invention is not limited thereto, and the first conductive layer MCL1 and the first-1 power supply line PL1-1 may be formed in a process separate from the connecting line CN and may have a different structure from the connecting line CN.

[0241] The first conductive layer MCL1 may be electrically connected to the light emitting element LD through the first contact hole CNT1. That is, the first-1 power supply line PL1-1 may apply a first voltage VDD1 (see FIG. 6) to the first electrode EL1 of the light emitting element LD through the first conductive layer MCL1. The first electrode EL1 may correspond to the first-1 electrode EL1_1 shown in FIG. 6 of the present invention.

[0242] A connecting electrode CNE may be disposed on the pixel definition layer PDL. The connecting electrode CNE may electrically connect the pixel driver PDC and the light emitting device LD. That is, the pixel driver PDC may be electrically connected to the light emitting device LD via the connecting line CN and the connecting electrode CNE. The connecting electrode CNE may correspond to the third connecting electrode CNE3 shown in FIG. 7A. The second connecting electrode CNE2 (see FIG. 7A) and the third connecting electrode CNE3 (see FIG. 7A) may also have a structure similar to that of the connecting electrode CNE.

[0243] The connecting electrode CNE may include a first edge EG1c adjacent to the light-emitting opening OP-PDL and a second edge EG2c surrounding the first edge EG1c. The second electrode EL2 of the light-emitting element LD may be in contact with the connecting electrode CNE in a region adjacent to the second edge EG2c.

[0244] The connecting electrode CNE may include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3), but the material constituting the connecting electrode CNE is not limited to these examples.

[0245] A display element layer DP-ED may be disposed on the circuit element layer DP-CL. The display element layer DP-ED may include a pixel defining layer PDL, a light emitting element LD, and a separator SPR.

[0246] A through hole OP-P may be defined in the pixel definition layer PDL. A plurality of through holes OP-P may be provided and disposed corresponding to each light emitting element. The size of the through hole OP-P defined in the pixel definition layer PDL may be larger than the size of the through hole OP-60 defined in the sixth insulating layer 60. The connection electrode CNE may be disposed in the through hole OP-P and the through hole OP-60 and connected to the connection wire CN.

[0247] The pixel defining layer PDL may define a light emitting opening OP-PDL spaced apart from the through hole OP-P. A plurality of light emitting openings OP-PDL may be provided and disposed corresponding to each light emitting element. A portion of the light emitting element LD (e.g., the light emitting layer EML) may be disposed within the light emitting opening OP-PDL.

[0248] The light emitting element LD may include a first electrode EL1, an intermediate layer IML, and a second electrode EL2. The intermediate layer IML may include an emitting layer EML and a functional layer FNL.

[0249] The first electrode EL1 may be a semi-transparent, transparent, or reflective electrode. According to one embodiment of the present invention, the first electrode EL1 may include a reflective layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a combination thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), and aluminum-doped zinc oxide (AZO). For example, the first electrode EL1 may include an ITO / Ag / ITO stacked structure.

[0250] In this embodiment, the first electrode EL1 may be an anode of the light emitting element LD disposed on the sixth insulating layer 60. That is, the first electrode EL1 may be electrically connected to the first conductive layer MCL1 through a first contact hole CNT1 formed through the sixth insulating layer 60. The 1-1 power supply line PL1-1 may apply a first voltage VDD1 (see FIG. 6) to the first electrode EL1 of the light emitting element LD through the first conductive layer MCL1. That is, a first voltage corresponding to each of the plurality of light emitting elements may be applied to each of the plurality of light emitting elements.

[0251] The functional layer FNL may include a first intermediary functional layer FNLa disposed between the first electrode EL1 and the emitting layer EML, and a second intermediary functional layer FNLb disposed between the second electrode EL2 and the emitting layer EML. In one embodiment of the present invention, one of the first intermediary functional layer FNLa and the second intermediary functional layer FNLb may be omitted. In this embodiment, the emitting layer EML is illustrated as being inserted within the functional layer FNL. That is, it can be understood that the emitting layer EML is disposed between the first intermediary functional layer FNLa and the second intermediary functional layer FNLb.

[0252] The functional layer FNL can control charge transfer between the first electrode EL1 and the second electrode EL2. For example, the first intermediate functional layer FNLa can include a hole injection / transport material and / or an electron injection / transport material. The second intermediate functional layer FNLb can include at least one of an electron blocking layer, a hole transport layer, a hole injection layer, a hole blocking layer, an electron transport layer, an electron injection layer, and a charge generation layer.

[0253] 8 and 9A, the separator SPR may be disposed on the pixel defining layer PDL, and may also be disposed on the gap GP between the connecting electrode CNE disposed on the pixel defining layer PDL and the connecting electrode CNEn adjacent to the connecting electrode CNE.

[0254] In one embodiment, the second electrode EL2 and the intermediate layer IML may be formed by common deposition in a plurality of pixels through an open mask. In this case, the second electrode EL2 and the intermediate layer IML may be divided by a separator SPR. As described above, the separator SPR may have a closed line shape for each light-emitting portion, and accordingly, the second electrode EL2 and the intermediate layer IML may have a divided shape for each light-emitting portion. That is, the second electrode EL2 and the intermediate layer IML may be electrically independent for each adjacent pixel. However, this is merely an example, and the functional layer FNL of the intermediate layer IML may be formed through an open mask, and the light-emitting layer EML may be formed through a fine metal mask. Therefore, the present invention is not limited to any one embodiment.

[0255] 9A, the separator SPR may have a double-tapered shape. That is, the taper angle formed by the first side TP1 of the separator SPR with respect to the upper surface of the pixel-defining (defining) layer PDL may be different from the taper angle formed by the second side TP2 of the separator SPR with respect to the upper surface of the pixel-defining (defining) layer PDL. The taper angle may be an obtuse angle. For example, referring to FIG. 9A, the taper angle formed by the first side TP1 with respect to the upper surface of the pixel-defining (defining) layer PDL may be smaller than the taper angle formed by the second side TP2 with respect to the upper surface of the pixel-defining (defining) layer PDL.

[0256] In one embodiment of the present invention, the connecting region BDA between the first side surface TP1 and the second side surface TP2 may have a curved cross section, i.e., the connecting region BDA between the first side surface TP1 and the second side surface TP2 having different taper angles may have a rounded shape with a gradually changing slope.

[0257] In an embodiment of the present invention, the second side surface TP2 may have a larger taper angle than the first side surface TP1, thereby defining a predetermined space between the second side surface TP2 of the separator SPR and the connecting electrode CNEn. The second electrode EL2n may have a shape extending toward the predetermined space.

[0258] 9A is merely an example, and the tapered angle may be set in various ways as long as the separator SPR can electrically disconnect the second electrode EL2 for each pixel. Also, the separator SPR may have a tip-like structure, and is not limited to any one embodiment.

[0259] In one embodiment, the separator SPR may include an insulating material, particularly an organic insulating material. The separator SPR may also include an inorganic insulating material, or may be configured with multiple layers of organic and inorganic insulating materials. Depending on the embodiment, the separator SPR may also include a conductive material. That is, as long as the second electrode EL2 can be electrically disconnected for each pixel, the separator SPR is not particularly limited in terms of the type of material.

[0260] A dummy layer UP may be disposed on top of the separator SPR. The dummy layer UP may include a first dummy layer UP1 disposed on the separator SPR and a second dummy layer UP2 disposed on the first dummy layer UP1. The first dummy layer UP1 may be formed in the same process as the intermediate layer IML and may include the same material. The first dummy layer UP1 may include a 1-1 dummy layer UP1a and a 1-2 dummy layer UP1b. The 1-1 dummy layer UP1a may be formed in the same process as the first intermediate functional layer FNLa and may include the same material. The 1-2 dummy layer UP1b may be formed in the same process as the second intermediate functional layer FNLb and may include the same material. The second dummy layer UP2 may be formed in the same process as the second electrode EL2 and may include the same material. That is, the first dummy layer UP1 and the second dummy layer UP2 may be formed simultaneously during the formation of the functional layer FNL and the second electrode EL2. In another embodiment, the display panel DP does not need to include the dummy layer UP.

[0261] 8 and 9B, the intermediate layer IML may include a first region AR1 and a second region AR2. For example, the first region AR1 may be a region including only layers formed using an open mask among the layers constituting the intermediate layer IML, and the second region AR2 may be a region including all layers formed using an open mask and layers formed using a fine metal mask among the layers constituting the intermediate layer IML.

[0262] For example, the first region AR1 may include a first intermediate functional layer FNLa and a second intermediate functional layer FMLb. The second region AR2 may include a first intermediate functional layer FNLa, a second intermediate functional layer FMLb, and an emitting layer EML. Therefore, the first thickness TK1 of the first region AR1 of the intermediate layer IML may be smaller than the second thickness TK2 of the second region AR2 of the intermediate layer IML. A portion of the boundary between the first region AR1 and the second region AR2 may not overlap with the connecting electrode CNE and may be separated from the first edge EG1c of the connecting electrode CNE. Therefore, the edge EG of the emitting layer EML included only in the second region AR2 may be separated from the first edge EG1c.

[0263] 9A, the first region AR1 of the intermediate layer IML is illustrated on the right side of the separator SPR, and the second region AR2n of the adjacent intermediate layer IML is illustrated on the left side. Comparing the left and right sides of the separator SPR, it can be seen that the area of ​​the region where the connecting electrode CNE is exposed adjacent to the first region AR1 is larger than the area of ​​the region where the connecting electrode CNEn is exposed adjacent to the second region AR2n.

[0264] The second electrode EL2 may be in contact with the connecting electrode CNE through the connection region CA. The second electrode EL2n may be in contact with the connecting electrode CNEn through the connection region CAn. That is, by forming a layer formed using a fine metal mask, for example, an emission layer EML, so as not to overlap a portion of the connecting electrode CNE, an exposed region of a portion of the connecting electrode CNE may be stably secured, thereby improving the contact reliability between the connecting electrode CNE and the second electrode EL2. Therefore, contamination defects caused by contact defects may be reduced or eliminated. As a result, the image quality or manufacturing yield of the display panel DP and a display device DD including the same (see FIG. 2A) may be improved.

[0265] According to an embodiment of the present invention, the connecting electrode CNE has a shape that surrounds at least a portion of the light-emitting portion EP1 (see FIG. 4A ) defined in the light-emitting element LD. Therefore, the degree of freedom in the position at which the connecting electrode CNE is connected to the light-emitting element LD and the degree of freedom in the position at which the connecting electrode CNE is connected to the pixel driving circuit PDC can be improved. Furthermore, the upper surface CNE-us of the connecting electrode CNE can be in contact with the lower surface EL2-bs of the second electrode EL2 of the light-emitting element LD. In this case, the contact reliability between the connecting electrode CNE and the second electrode EL2 can be improved. Furthermore, since the lower surface of the connecting electrode CNE is in contact with the upper surface of the connecting line CN, the contact reliability can be improved. Therefore, the size of the through-holes OP-P and OP-60 for connecting the connecting electrode CNE and the connecting line CN can be reduced or minimized. Therefore, the area or resolution of the light-emitting portion of the display panel DP can be easily increased.

[0266] An encapsulating layer ECL may be disposed on the display element layers DP-ED. The encapsulating layer ECL may cover the light emitting element LD and the separator SPR. The encapsulating layer ECL may include a first inorganic layer IL1, an organic layer OL, and a second inorganic layer IL2 stacked in sequence. However, without being limited thereto, the encapsulating layer ECL may further include a plurality of inorganic layers and organic layers. The encapsulating layer ECL may also be a glass substrate.

[0267] The first and second inorganic layers IL1 and IL2 protect the light emitting device LD from moisture and oxygen outside the display panel DP, and the organic layer OL protects the light emitting device LD from foreign substances such as particles remaining during the formation of the first inorganic layer IL1. The first and second inorganic layers IL1 and IL2 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, or the like. The organic layer OL may include an acrylic organic layer, and the type of material is not limited to any one of them.

[0268] The sensing layer ISL can sense an external input. In this embodiment, the sensing layer ISL can be formed on the encapsulation layer ECL through a continuous process. In this case, the sensing layer ISL can be expressed as being directly disposed on the encapsulation layer ECL. "Directly disposed" can mean that no other components are disposed between the sensing layer ISL and the encapsulation layer ECL. That is, a separate adhesive member does not need to be disposed between the sensing layer ISL and the encapsulation layer ECL. However, this is merely an example, and in the display panel DP according to an embodiment of the present invention, the sensing layer ISL can also be formed separately and then coupled to the display panel DP through an adhesive member, and the present invention is not limited to any one embodiment.

[0269] The sensing layer ISL may include a plurality of conductive layers and a plurality of insulating layers. The plurality of conductive layers may include a first sensing conductive layer MTL1 and a second sensing conductive layer MTL2, and the plurality of insulating layers may include first to third sensing insulating layers 71, 72, and 73. However, this is merely an example, and the number of conductive layers and insulating layers is not limited to any one embodiment.

[0270] Each of the first to third sensing insulating layers 71, 72, and 73 may have a single-layer structure or a multi-layer structure stacked along the third direction DR3. The first to third sensing insulating layers 71, 72, and 73 may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first to third sensing insulating layers 71, 72, and 73 may include an organic film. The organic film may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0271] The first sensing conductive layer MTL1 may be disposed between the first sensing insulating layer 71 and the second sensing insulating layer 72, and the second sensing conductive layer MTL2 may be disposed between the second sensing insulating layer 72 and the third sensing insulating layer 73. A portion of the second sensing conductive layer MTL2 may be connected to the first sensing conductive layer MTL1 through a contact hole CNT formed in the second sensing insulating layer 72. Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may have a single-layer structure or a multi-layer structure stacked along the third direction DR3.

[0272] The single-layer sensing conductive layer may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO). Alternatively, the transparent conductive layer may include a conductive polymer such as PEDOT, a metal nanowire, graphene, or the like.

[0273] The multi-layered sensing conductive layer can include a metal layer, such as a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), or can include at least one metal layer and at least one transparent conductive layer.

[0274] The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may constitute a sensor that senses an external input in the sensing layer ISL. The sensor may be driven in a capacitive manner, and may be driven by either a mutual capacitance (mutual-cap) manner or a magnetic capacitance (self-cap) manner. However, this is merely an example, and the sensor may be driven by a resistive, ultrasonic, or infrared manner in addition to the capacitive manner, and is not limited to any one embodiment.

[0275] Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may include a transparent conductive oxide or may have a metal mesh shape formed of an opaque conductive material. The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may have various materials and shapes as long as the visibility of the image displayed by the display panel DP is not reduced, and are not limited to any one embodiment.

[0276] Figure 10 is an enlarged view of region CC' shown in Figure 7D. Figure 11A is a cross-sectional view of a display panel according to an embodiment of the present invention, taken along line II-II' in Figure 10. Figures 11B to 11D are cross-sectional views of display panels according to other embodiments of the present invention, taken along line II-II' in Figure 10. Figures 11A to 11D show only a portion of the configuration of a display panel DP.

[0277] 10 and 11A, the first-1 power line PL1-1 may include a horizontal line HL extending in a first direction DR1 and a vertical line VL extending in a second direction DR2. The horizontal line HL may be disposed on the same layer as the first conductive layer MCL1 and may extend from the first conductive layer MCL1. The vertical line VL may be disposed on the same layer as the horizontal line HL and may extend from the horizontal line HL. That is, the first conductive layer MCL1, the horizontal line HL, and the vertical line VL may be disposed on the fifth insulating layer 50. The vertical line VL may overlap the separator SPR in a plane. Although not shown, the first-2 power line PL1-2 (see FIG. 7D) may also include a horizontal line extending in the first direction DR1 and a vertical line extending in the second direction DR2.

[0278] 10 and 11B, the first-1 power supply line PL1-1a may be disposed on a different layer from the first conductive layer MCL1. For example, the first-1 power supply line PL1-1a may be disposed on the fourth insulating layer 40. The first-1 power supply line PL1-1a may be disposed on the same layer as the source electrode pattern S1 and the drain electrode pattern D1 shown in FIG. 8 and may be formed in the same process. The first-1 power supply line PL1-1a may be electrically connected to the first conductive layer MCL1 through a contact hole CNTa formed in the fifth insulating layer 50. The first-1 power supply line PL1-1a may partially overlap the first conductive layer MCL1 in plan view. The contact hole CNTa formed in the fifth insulating layer 50 may be formed in a region overlapping the first-1 power supply line PL1-1a and the first conductive layer MCL1 in plan view.

[0279] The first-1 power supply line PL1-1a may include a horizontal line HLa extending in a first direction DR1 and a vertical line VLa extending in a second direction DR2. The vertical line VLa may be disposed on the same layer as the horizontal line HLa and may extend from the horizontal line HL.

[0280] 10 and 11C, the first-1 power supply line PL1-1b may include a horizontal line HLb extending in a first direction DR1 and a vertical line VLb extending in a second direction DR2. According to an embodiment of the present invention, the vertical line VLb may be disposed on a different layer from the horizontal line HLb. For example, the horizontal line HLb may be disposed on the fourth insulating layer 40, and the vertical line VLb may be disposed on the third insulating layer 30. The vertical line VLb may be disposed on the same layer as the third capacitor electrode CPE3 shown in FIG. 8 and may be formed using the same process.

[0281] The vertical line VLb may be electrically connected to the horizontal line HLb through a contact hole CNTb formed in the fourth insulating layer 40. The vertical line VLb may partially overlap the horizontal line HLb in a plan view. The contact hole CNTb formed in the fourth insulating layer 40 may be formed in a region overlapping the horizontal line HLb and the vertical line VLb in a plan view.

[0282] 10 and 11D, the first-1 power supply line PL1-1 may include a horizontal line HL extending in a first direction DR1 and a vertical line VLa extending in a second direction DR2. According to an embodiment of the present invention, the vertical line VLa may be disposed on a different layer from the horizontal line HL. The horizontal line HL may be disposed on the same layer as the first conductive layer MCL1 and may extend from the first conductive layer MCL1. The vertical line VLa may be disposed on the fourth insulating layer 40. The vertical line VLa may be disposed on the same layer as the source electrode pattern S1 and the drain electrode pattern D1 shown in FIG. 8 and may be formed using the same process.

[0283] The vertical line VLa may be electrically connected to the horizontal line HL through a contact hole CNTa formed in the fifth insulating layer 50. The vertical line VLa may partially overlap the horizontal line HL in a plan view. The contact hole CNTa formed in the fifth insulating layer 50 may be formed in an area overlapping the horizontal line HL and the vertical line VLa in a plan view. Figures 12A to 12E are enlarged plan views of a portion of a display panel according to an embodiment of the present invention. Hereinafter, the same reference numerals will be used to refer to the same components as those previously described, and descriptions thereof will be omitted, with differences being mainly described.

[0284] 12A , the conductive layer MCLa may include a first conductive layer MCL1a disposed in the first light-emitting unit UT11 and a second conductive layer MCL2a disposed in the second light-emitting unit UT21. The first conductive layer MCL1a and the second conductive layer MCL2a may be spaced apart from each other in the second direction DR2. The first conductive layer MCL1a and the second conductive layer MCL2a may be electrically disconnected from each other. Although not shown, the conductive layer MCLa may further include a third conductive layer disposed in the third light-emitting unit (or the light-emitting unit in the first row and second column) UT12 and a fourth conductive layer disposed in the fourth light-emitting unit (or the light-emitting unit in the second row and second column) UT22. The descriptions of the third and fourth conductive layers may be similarly applied to the descriptions of the first and second conductive layers MCL1a and MCL2a.

[0285] According to an embodiment of the present invention, the first conductive layer MCL1a may overlap a portion of each of the first to third anodes (or first sub-electrodes) AE1, AE2, and AE3 in a plan view. The first to third anodes AE1, AE2, and AE3 may be electrically connected to the first conductive layer MCL1a through the first contact hole CNT1. The first to third anodes AE1, AE2, and AE3 may each commonly receive a first voltage VDD1 (see FIG. 6) through the first conductive layer MCL1a. The first contact hole CNT1 may be formed at a position overlapping the first to third anodes AE1, AE2, and AE3 and the first conductive layer MCL1a in a plan view.

[0286] According to an embodiment of the present invention, the second conductive layer MCL2a may overlap a portion of each of the first to third anodes (or first sub-electrodes) AE1a, AE2a, and AE3a in a plan view. The first to third anodes AE1a, AE2a, and AE3a may be electrically connected to the second conductive layer MCL2a through the second contact hole CNT2a. The first to third anodes AE1a, AE2a, and AE3a may each commonly receive the second voltage VDD2 (see FIG. 6) through the second conductive layer MCL2a. The second contact hole CNT2a may be formed at a position overlapping the first to third anodes AE1a, AE2a, and AE3a and the second conductive layer MCL2a in a plan view.

[0287] 12B, the conductive layer MCLb may include a first conductive layer MCL1b disposed in the first light-emitting unit UT11 and a second conductive layer MCL2b disposed in the second light-emitting unit UT21. The first conductive layer MCL1b and the second conductive layer MCL2b may be spaced apart from each other in the second direction DR2. The first conductive layer MCL1b and the second conductive layer MCL2b may each have a mesh shape.

[0288] According to an embodiment of the present invention, the first conductive layer MCL1b may include first to third sub-conductive layers SMCL1, SMCL2, and SMCL3 and a first connecting pattern CP1 electrically connecting the first to third sub-conductive layers SMCL1, SMCL2, and SMCL3 to each other. The first to third sub-conductive layers SMCL1, SMCL2, and SMCL3 may have shapes corresponding to the shapes of the first to third anodes AE1, AE2, and AE3, respectively. However, the present invention is not limited thereto, and the first to third sub-conductive layers SMCL1, SMCL2, and SMCL3 may have shapes different from the first to third anodes AE1, AE2, and AE3. A first opening OP1 defined by the first to third sub-conductive layers SMCL1, SMCL2, and SMCL3 and the first connecting pattern CP1 may be defined in the first conductive layer MCL1b. However, according to one embodiment, the first opening OP1 does not have to be formed in the first conductive layer MCL1b.

[0289] According to an embodiment of the present invention, the second conductive layer MCL2b may include fourth to sixth sub-conductive layers SMCL4, SMCL5, and SMCL6 and a second connecting pattern CP2 electrically connecting the fourth to sixth sub-conductive layers SMCL4, SMCL5, and SMCL6 to each other. The fourth to sixth sub-conductive layers SMCL4, SMCL5, and SMCL6 may have shapes corresponding to the shapes of the first to third anodes AE1a, AE2a, and AE3a, respectively. However, the present invention is not limited thereto, and the fourth to sixth sub-conductive layers SMCL4, SMCL5, and SMCL6 may have shapes different from the first to third anodes AE1a, AE2a, and AE3a. A second opening OP2 defined by the fourth to sixth sub-conductive layers SMCL4, SMCL5, and SMCL6 and the second connecting pattern CP2 may be defined in the second conductive layer MCL2b. However, according to one embodiment, the second opening OP2 does not have to be formed in the second conductive layer MCL2b.

[0290] 12C, the conductive layer MCLc may include a first conductive layer MCL1 disposed in the first light-emitting unit UT11 and a second conductive layer MCL2b disposed in the second light-emitting unit UT21. According to an embodiment of the present invention, the shape of the first conductive layer MCL1 and the shape of the second conductive layer MCL2b may be different from each other. For example, the shape of the first conductive layer MCL1 may be the same as the shape of the first conductive layer MCL1 shown in FIG. 7D, and the shape of the second conductive layer MCL2b may be the same as the shape of the second conductive layer MCL2b shown in FIG. 12B. In the present invention, the shapes of the conductive layers MCL1 and MCL2b are not limited to those shown in the drawings. That is, the shapes of the conductive layers disposed in each light-emitting unit may be different from each other.

[0291] 12D, the first electrode EL1a may include a 1-1 electrode EL1_1a disposed in the first light-emitting unit UT11 and a 1-2 electrode EL1_2a disposed in the second light-emitting unit UT21. The 1-1 electrode EL1_1a and the 1-2 electrode EL1_2a may be spaced apart from each other in the second direction DR2 via a separator SPR. The 1-1 electrode EL1_1a and the 1-2 electrode EL1_2a may each have a mesh shape.

[0292] The 1-1 electrode EL1_1a may be provided in common to the first to third light emitting units EP1, EP2, and EP3. The 1-1 electrode EL1_1a may be formed as a single, integrated layer and may be disposed overlapping the separator SPR. An opening may be defined in the 1-1 electrode EL1_1a according to this embodiment, and the opening may penetrate the 1-1 electrode EL1_1a. The opening may not overlap the light emitting units EP1, EP2, and EP3.

[0293] The first-second electrode EL1_2a may be provided in common to the first to third light emitting units EP1a, EP2a, and EP3a. The first-second electrode EL1_2a may be formed as a single, integrated layer and may be disposed overlapping the separator SPR. An opening may be defined in the first-second electrode EL1_2a according to this embodiment, and the opening may penetrate the first-second electrode EL1_2a. The opening may not overlap with the light emitting units EP1a, EP2a, and EP3a.

[0294] The first power line PL1a may include a first power line PL1-1c and a first-2 power line PL1-2a. The first power line PL1-1c may be electrically connected to the first electrode EL1_1a. For example, the first power line PL1-1c may be extended from the first electrode EL1_1a. According to an embodiment of the present invention, the first power line PL1-1c may be disposed on a different layer from the first electrode EL1_1a. The first power line PL1-1c may be electrically connected to the first electrode EL1_1a through a first contact hole CNT1b. The first power line PL1-1c may directly apply a first voltage VDD1 (see FIG. 6) to the first electrode EL1_1a.

[0295] The first-second power supply line PL1-2a may be electrically connected to the first-second electrode EL1_2a. For example, the first-second power supply line PL1-2a may be extended from the first-second electrode EL1_2a. According to an embodiment of the present invention, the first-second power supply line PL1-2a may be disposed on a different layer from the first-second electrode EL1_2a. The first-second power supply line PL1-2a may be electrically connected to the first-second electrode EL1_2a through the second contact hole CNT2b. The first-second power supply line PL1-2a may directly apply the second voltage VDD2 (see FIG. 6) to the first-second electrode EL1_2a.

[0296] 12E, the first power line PL1b may include a first-1 power line PL1-1 and a first-2 power line PL1-2b. According to an embodiment of the present invention, a portion of the first-1 power line PL1-1 and a portion of the first-2 power line PL1-2b may overlap each other in a plane. Specifically, a portion of the first-1 power line PL1-1 extending in the second direction DR2 (e.g., a first vertical line) and a portion of the first-2 power line PL1-2b extending in the second direction DR2 (e.g., a second vertical line) may overlap each other in a plane. The first vertical line and the second vertical line may overlap with the separator SPR in a plane.

[0297] Since the first and second vertical lines are arranged to overlap each other on a plane, the first and second vertical lines may be arranged on different layers. For example, the first vertical line may be arranged on the fourth insulating layer 40 (see FIG. 8), and the second vertical line may be arranged on the third insulating layer 30 (see FIG. 8). Figures 13 and 14 are plan views of a display panel and a driving circuit unit according to an embodiment of the present invention. The same reference numerals are used to refer to the same components as those previously described, and descriptions thereof will be omitted, with differences being mainly described.

[0298] 13, the display area DA may include multiple areas. For example, the display area DA may include a first area AA1 and a second area AA2. While the display area DA is illustrated as including only the first area AA1 and the second area AA2, the present invention is not limited thereto. That is, the display area DA may further include a third area spaced apart from the first area AA1 and the second area AA2. The sizes of the first area AA1 and the second area AA2 may differ from each other and are not limited to those illustrated.

[0299] The pixel PXa may include a first pixel PX1a and a second pixel PX2a. The first pixel PX1a may be arranged in the first area AA1, and the second pixel PX2a may be arranged in the second area AA2. The first and second pixels PX1a and PX2a may have substantially the same configuration. The number of first and second pixels PX1a and PX2a may vary depending on the sizes of the first area AA1 and the second area AA2.

[0300] The first power line PL1 may include a 1-1 power line PL1-1 and a 1-2 power line PL1-2. The 1-1 power line PL1-1 may be electrically connected to the first pixel PX1a arranged in the first area AA1, and the 1-2 power line PL1-2 may be electrically connected to the second pixel PX2a arranged in the second area AA2. That is, the 1-1 power line PL1-1 is electrically connected to the first pixel PX1a and can commonly supply the first voltage VDD1 applied from the 1-1 pad PD1-1 to the first pixel PX1a, and the 1-2 power line PL1-2 is electrically connected to the second pixel PX2a and can commonly supply the second voltage VDD2 applied from the 1-2 pad PD1-2 to the second pixel PX2a.

[0301] The first-1 power line PL1-1 and the first-2 power line PL1-2 may overlap the display area DA. The first-1 power line PL1-1 and the first-2 power line PL1-2 may extend along the second direction DR2. In FIG. 13, the first power line PL1 includes two power lines, the first-1 power line PL1-1 and the first-2 power line PL1-2, but is not limited thereto and may further include a third power line electrically connected to a third pixel arranged in a third region of the display area DA.

[0302] Since images can be displayed at different luminance levels in the first and second areas AA1 and AA2 of the display area DA, a display panel DP with improved display quality can be provided. Also, since it is only necessary to adjust the voltage level of the first voltage VDD1 to increase the luminance of the first area AA1 or the voltage level of the second voltage VDD2 to increase the luminance of the second area AA2, the pixels PX1a and PX2a are provided with required voltage levels, thereby reducing power consumption.

[0303] 14, the drive circuit unit DC may include a first drive circuit unit DC1 and a second drive circuit unit DC2 spaced apart in the second direction DR2. The first drive circuit unit DC1 may be disposed below the display panel DP, and the second drive circuit unit DC2 may be disposed above the display panel DP. The first drive circuit unit DC1 may include a first main circuit board MB1 and flexible films CF1, CF2, and CF3. The second drive circuit unit DC2 may include a second main circuit board MB2 and flexible films CF4, CF5, and CF6.

[0304] The pad part PDP may include a first pad part PDP1 disposed below the display panel DP and a second pad part PDP2 disposed above the display panel DP. The first pad part PDP1 and the second pad part PDP2 may be disposed in the non-display area NDA. Flexible films CF1, CF2, and CF3 may be connected to the first pad part PDP1, and flexible films CF4, CF5, and CF6 may be connected to the second pad part PDP2.

[0305] The first pad unit PDP1 includes a first-1 pad PD1-1a that receives a first voltage VDD1, and the second pad unit PDP2 includes a first-2 pad PD1-2a that receives a second voltage VDD2. The first-1 pad PD1-1a provides the first voltage VDD1 to the first pixel PX1b arranged in the first area AA1a, and the first-2 pad PD1-2a provides the second voltage VDD2 to the second pixel PX2b arranged in the second area AA2a.

[0306] Fig. 15 is a perspective view of an electronic device according to an embodiment of the present invention, and Fig. 16 is a view showing a folded state of the electronic device shown in Fig. 15.

[0307] 15, the electronic device ED according to an embodiment of the present invention may have a rectangular shape having a short side extending in a first direction DR1 and a long side extending in a second direction DR2 intersecting the first direction DR1. However, the electronic device ED is not limited thereto and may have various shapes such as a circle and a polygon. The electronic device ED may be flexible.

[0308] The electronic device ED may include a folding area FA and a plurality of non-folding areas NFA1, NFA2. The non-folding areas NFA1, NFA2 may include a first non-folding area NFA1 and a second non-folding area NFA2. The folding area FA may be disposed between the first non-folding area NFA1 and the second non-folding area NFA2. The folding area FA, the first non-folding area NFA1, and the second non-folding area NFA2 may be arranged in a first direction DR1.

[0309] Although one folding area FA and two non-folding areas NFA1 and NFA2 are illustrated by way of example, the number of folding areas FA and non-folding areas NFA1 and NFA2 is not limited thereto. For example, the electronic device ED may include more than two non-folding areas and multiple folding areas disposed between the non-folding areas.

[0310] The top surface of the electronic device ED may be defined as a display surface DS, and the display surface DS may have a plane defined by a first direction DR1 and a second direction DR2. An image IM generated by the electronic device ED may be provided to a user through the display surface DS.

[0311] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may display an image, while the non-display area NDA may not display an image. The non-display area NDA may surround the display area DA and define a border of the electronic device ED that is printed in a predetermined color.

[0312] Referring to FIG. 16 , the electronic device ED may be a foldable electronic device ED that can be folded or unfolded. For example, the folding area FA may be folded about a folding axis FX parallel to the second direction DR2 to fold the electronic device ED. The folding axis FX may be defined as a major axis parallel to a long side of the electronic device ED. When folding the electronic device ED, the first non-folding area NFA1 and the second non-folding area NFA2 face each other, and the electronic device ED may be in-folded so that the display surface DS is not exposed to the outside. However, embodiments of the present invention are not limited thereto. For example, although not shown, the electronic device ED may be out-folded about the folding axis FX to expose the display surface DS to the outside. Also, although not shown, the electronic device ED may be capable of both in-folding and out-folding.

[0313] FIG. 17 is an exploded perspective view of the electronic device shown in FIG.

[0314] 17, the electronic device ED may include a display device DD, an electronic module EM, a power supply module PSM, and a hinge module EDC. Although not shown, the electronic device ED may further include a fixture structure (e.g., a hinge) for controlling the folding operation of the display device DD.

[0315] The display device DD can generate an image and sense an external input. The display device DD can include a window module WM and a display module DM. The window module WM can provide a front surface of the electronic device ED. The window module WM is disposed on the display module DM to protect the display module DM. The window module WM can transmit light generated by the display module DM to provide it to a user.

[0316] The display module DM may include a display panel DP. Although only the display panel DP is illustrated in Fig. 17 among the laminated structure of the display module DM, the display module DM may actually further include a plurality of components disposed above and below the display panel DP. The display panel DP may include a display area DA and a non-display area NDA, which correspond to the display area DA and non-display area NDA of the electronic device ED in Fig. 15.

[0317] The display module DM may include a data driver DDC disposed on the non-display area NDA of the display panel DP. The data driver DDC may be directly manufactured in the form of a circuit chip and mounted on the non-display area NDA. However, without being limited thereto, the data driver DDC may be mounted on a flexible circuit board connected to the display panel DP.

[0318] The electronic module EM and the power module PSM may be disposed within the hinge module EDC. For example, FIG. 17 illustrates a state in which the electronic module EM and the power module PSM are exposed to the outside from the hinge module EDC. Although not shown, the electronic module EM and the power module PSM may be connected to each other via a separate flexible circuit board. The electronic module EM may control the operation of the display device DD. The power module PSM may supply power to the electronic module EM.

[0319] The hinge module EDC can accommodate the display device DD, the electronic module EM, and the power module PSM. The hinge module EDC can include two housings, first and second housings HS1 and HS2, for folding the display device DD. The first and second housings HS1 and HS2 can extend in a second direction DR2 and be arranged in the first direction DR1.

[0320] The hinge module EDC may include a housing assembly HS. The housing assembly HS may include a first housing HS1 and a second housing HS2 spaced apart in a first direction DR1, and a hinge housing HGH disposed between the first housing HS1 and the second housing HS2. The hinge module EDC may further include hinges HG1 and HG2 for connecting the first and second housings HS1 and HS2, a plurality of main plates, and a plurality of moving plates.

[0321] FIG. 18 is a block diagram of the electronic device shown in FIG.

[0322] 18, the electronic device ED may include an electronic module EM, a power supply module PSM, and a display device DD. The electronic module EM may include a control module 10, a wireless communication module 20, an image input module 30, an audio input module 40, an audio output module 50, a memory 60, and an external interface module 70. The modules may be mounted on a circuit board or electrically connected via a flexible circuit board. The electronic module EM may be electrically connected to the power supply module PSM.

[0323] The control module 10 can control the overall operation of the electronic device ED. For example, the control module 10 can activate or deactivate the display device DD in response to a user input. The control module 10 can control the image input module 30, the audio input module 40, and the audio output module 50 in response to a user input. The control module 10 can include at least one microprocessor.

[0324] The wireless communication module 20 can transmit / receive wireless signals to / from other terminals using a Bluetooth® or WIFI line. The wireless communication module 20 can transmit / receive audio signals using a general communication line. The wireless communication module 20 can include a transmitting circuit 22 that modulates and transmits a signal to be transmitted, and a receiving circuit 24 that demodulates a received signal.

[0325] The image input module 30 processes image signals and converts them into image data that can be displayed on the display device DD. The audio input module 40 receives external audio signals using a microphone in a recording mode or a voice recognition mode and converts them into electrical audio data. The audio output module 50 converts audio data received from the wireless communication module 20 or audio data stored in the memory 60 and outputs the converted data to the outside.

[0326] The external interface module 70 can act as an interface connected to an external charger, a wired / wireless data port, a card socket (for example, a memory card, a SIM / UIM card), and the like.

[0327] The power supply module PSM is capable of supplying the power necessary for the overall operation of the electronic device ED. The power supply module PSM can include a conventional battery device.

[0328] 19, the electronic device ED of Fig. 19 may be applied to a smart watch 2000 including a display unit 2100 and a strap unit 2200. The smart watch 2000 may have a structure in which the strap unit 2200 is worn on a user's wrist. In this case, the electronic device ED may be applied to the display unit 2100, and image data including time information may be provided to the user.

[0329] Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood that those skilled in the art or those with ordinary knowledge in the art can make various modifications and changes to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

[0330] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

[0331] According to a preferred specific embodiment, it is as follows:

[0332] The background and issues of this case are as follows (i) to (ix).

[0333] (i) When using smartphones, smartwatches, tablet PCs, etc. outdoors on sunny days, they are sometimes switched to High Brightness Mode (HBM) so that the characters and figures on the screen can be read.

[0334] (ii) However, since the high brightness mode (HBM) has problems such as increased power consumption and heat generation, it is possible to designate only specific areas as high brightness mode (HBM) areas where the high brightness mode (HBM) is possible.

[0335] (iii) On the other hand, it is also possible to display a still image in some areas and update it as needed, while displaying a moving image in other areas. In this case, the display area for the still image may be set as a high brightness mode (HBM) area.

[0336] (vi) Patent Document 1 (WO2012052886) discloses that in a display panel in which light-emitting display elements (OLEDs) are arranged, a first brightness control region (50, 50') and a second brightness control region (51, 51') are set in the display region, and the drive current and brightness in the first brightness control region (50, 50') are made larger than those in the second brightness control region (51, 51'). This addresses the problem of brightness reduction due to attenuation of the drive voltage when the display panel becomes larger and the drive voltage line length becomes longer (Figure 2 in Patent Document 1).

[0337] (v) On the other hand, organic light-emitting devices (OLEDs) have the problem of being easily deteriorated by oxygen, moisture, etc. To prevent such deterioration, organic light-emitting devices with an inverted structure (inverted OLEDs) are also widely used. "Development of Air-Stable Inverted Organic EL Devices," NHK STRL R&D, May 2014, Report 02 https: / / www.nhk.or.jp / strl / publica / rd / 145 / 6.html For example, Figure 9b of Patent Document 2 (KR10-2015-0075016A)

[0338] (vi) In the case of an organic light-emitting element with an inverted structure (inverted OLED), the pixel electrode (particularly the cathode; the first electrode EL1 in this application, FIG. 7D in this application) for each subpixel is disposed on the upper side (the side farther from the pixel circuit) during stack formation.

[0339] (vii) Furthermore, a common electrode (particularly an anode; second electrode EL2 in this application, FIG. 7B in this application) to which a common voltage is supplied is disposed on the lower side (the side closer to the pixel circuit) when the layers are formed.

[0340] (viii) In general, these common electrodes are connected to each other or to a common power supply voltage line, and a common power supply voltage (VDD (first voltage) in FIGS. 4A to 4C of the present application) is supplied to them.

[0341] (ix) In such an inverted OLED, a wiring structure suitable for realizing a high brightness mode (HBM) is required.

[0342] In a specific embodiment of the present application, the following A1 to A4 or A1 to A5 may be used in particular.

[0343] A1 A "power supply unit PWS" provided on the "main circuit board MB" or the like supplies mutually different "common voltages" or counter voltages (particularly voltages to the "second electrode EL2" of the present application, which is the anode) to adjacent pixels (PX1, PX2) or to pixel groups in adjacent regions via respective power supply lines (PL1-1, PL1-2) (Fig. 6 of the present application).

[0344] A2: A voltage for realizing the high brightness mode (HBM) is supplied to a pixel or pixel group capable of the high brightness mode (HBM) through the power supply lines (PL1-2) for this purpose during the high brightness mode realization period (FIG. 7D of the present application). In other words, the supply voltage (second voltage ELVSS2) to the common electrode (first electrode EL1) of a pixel (PX1) capable of high brightness mode (HBM) can be set so that the difference with the voltage level of the pixel electrode (first electrode EL1) is greater than the supply voltage to the common electrode (first electrode CE1) of a pixel (PX2) that is not in high brightness mode.

[0345] A3 The power supply lines (PL1-1, PL1-2) for the counter electrodes of high brightness mode (HBM) enabled pixels or non-high brightness mode pixels extend into the display area (DA), for example, in the data line direction (see, for example, Figure 7D of the present application).

[0346] A4 In each pixel (PX1, PX2), a counter electrode (first to third anodes AE1, AE2, AE3) is provided for each light-emitting portion (EP1, EP2, EP31, EP32; Figure 7A) that constitutes a subpixel, and these are commonly connected to a single conductive pattern (conductive layer MCL) provided in the lower layer. The conductive pattern (conductive layer MCL) for each pixel (PX1, PX2) is then connected to the tip of the power supply line (PL1-1, PL1-2) for the counter electrode (Figures 7D, 8, 10, 11A, and 11B of the present application).

[0347] A4-1 The conductive pattern (conductive layer MCL) for each pixel (PX1, PX2) can be formed in a rectangular shape, for example, over almost the entire sub-pixel region (Figure 7D of the present application) or in the central portion of the sub-pixel region (Figure 12A of the present application).

[0348] A4-2 The conductive pattern (conductive layer MCL) for each pixel (PX1, PX2) can be formed in the same layer at the same time as the "connecting wiring CN" for drawing upward from the driving terminal of the pixel circuit (for example, node N4 in FIG. 4A) to the pixel electrode (second electrode EL2) (FIG. 8 of the present application).

[0349] A4-3 The conductive pattern (conductive layer MCL) for each pixel (PX1, PX2) is located at the upper end of the backplane (circuit element layer DP-CL) including the pixel circuit, and can be formed on the first planarization layer (the fifth insulating layer 50 as an organic layer) and covered by the second planarization layer (the sixth insulating layer 60 as an organic layer).

[0350] A4-4 On the second planarization layer (sixth insulating layer 60), a counter electrode (first electrode EL1) and a pixel defining film (PDL) are formed.

[0351] A5 The pixel electrode (particularly the cathode; the first electrode EL1 in this application) is separated by a partition wall (separator SPR) so as to be surrounded by each sub-pixel.

[0352] A5-1: Power supply lines (PL1-1, PL1-2) for the counter electrodes are arranged along the partition wall (separator SPR), particularly so as to overlap the partition wall (separator SPR) (Figs. 7D and 10 of the present application).

[0353] A5-2 The partition (separator SPR) is formed on the pixel defining layer (PDL) that forms the pixel aperture (light-emitting aperture OP-PDL), and both side surfaces are inverted tapered or overhanging (Fig. 8 of the present application).

[0354] A5-3 When the functional layer (FNL) for the organic light-emitting element and the electrode layer of the pixel electrode (EL2) that covers it are formed by isotropic film formation such as vapor deposition, discontinuities occur at the lower end of the reverse-tapered side surface.

[0355] A5-4 Below the overhanging side of the partition wall (separator SPR), the electrode layer of the pixel electrode (EL2) is directly overlapped and connected to the "connecting electrode (CNE)". The "connecting electrode (CNE)" is connected to the driving end of the pixel circuit (for example, node N4 in Figure 4A) via the "connecting wiring CN".

[0356] A5-5 The "connecting electrode (CNE)" is connected to the "connecting wiring CN" at a portion that covers the inner surface of the opening (OP-P) that exposes a portion of the upper surface of the "connecting wiring CN."

[0357] A5-6 The angle (taper angle θ) formed between the lower end of the side surface (SPR_W) of the partition (separator SPR) and the bottom surface of the partition (separator SPR) (the flat upper surface of the pixel defining layer (PDL)) is at least 90°, 100°, or 110°, and may be, for example, less than 150°, less than 140°, or less than 130°. [Explanation of symbols]

[0358] DD display device DP display panel DA display area NDA Hidden Area PX1 1st pixel PX2 2nd pixel BL Base Layer MCL conductive layer PL1 First power line PL2 Second power line MCL1 1st conductive layer MCL2 2nd conductive layer PL1-1 No. 1-1 power line PL1-2 1st and 2nd power supply lines

Claims

1. a base layer including a display area in which a plurality of pixels are arranged and a non-display area arranged around the display area; a conductive layer overlapping with at least a portion of the plurality of pixels in a plane; a first power line electrically connected to the plurality of pixels; a second power line electrically connected to the plurality of pixels; The conductive layer is a first conductive layer overlapping a first pixel of the plurality of pixels in a plane; a second conductive layer overlapping a second pixel of the plurality of pixels in a plane and spaced apart from the first conductive layer; The first power supply line is a first power line electrically connected to the first pixel through the first conductive layer; a first and second power supply line electrically connected to the second pixel through the second conductive layer.

2. Each of the plurality of pixels is a pixel driving unit disposed on the base layer and including a transistor; a light-emitting element disposed on the transistor, the light-emitting element including a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; the first power line is electrically connected to the first electrode; The display device of claim 1 , wherein the second power line is electrically connected to the transistor.

3. The first electrode is a first electrode electrically connected to the first power line; a first-second electrode electrically connected to the first-second power line; 3. The display device according to claim 2, wherein the first-1 electrode and the first-2 electrode are electrically insulated from each other.

4. the first-1 electrode is disposed on a layer different from the first conductive layer and is electrically connected to the first conductive layer through a first contact hole; 4. The display device of claim 3, wherein the first and second electrodes are disposed on a layer different from the second conductive layer and are electrically connected to the second conductive layer through a second contact hole.

5. 5. The display device of claim 4, wherein the first-1 electrode includes a plurality of first sub-electrodes, and the first sub-electrodes are arranged spaced apart from each other on a plane.

6. The display device according to claim 5 , wherein the first conductive layer overlaps a portion of each of the first sub-electrodes in a plane.

7. the first conductive layer includes a plurality of first sub-conductive layers; The display device according to claim 5 , wherein the first sub-conductive layer has a shape corresponding to the shape of each of the first sub-electrodes.

8. The display device of claim 7 , wherein the first conductive layer further comprises a connection pattern that connects the first sub-conductive layers to each other.

9. The first-1 power supply line is a horizontal line extending in a first direction; a vertical line extending in a second direction intersecting the first direction, The display device of claim 2 , wherein the horizontal lines are disposed on the same layer as the first conductive layer and extend from the first conductive layer.

10. The display device of claim 8 , wherein the vertical lines extend from the horizontal lines and do not overlap the first electrodes in a plane.

11. 10. The display device of claim 9, wherein the vertical lines are disposed on a different layer from the horizontal lines and are electrically connected to the horizontal lines through contact holes.

12. the area of ​​the first conductive layer is larger than the area of ​​the 1-1 electrode; the area of ​​the second conductive layer is larger than the area of ​​the first-second electrode; The display device according to claim 3 , wherein the first conductive layer and the second conductive layer have mutually different shapes in plan view.

13. the first-1 power supply line is disposed on a layer different from the first conductive layer; The first-1 power supply line is electrically connected to the first conductive layer through a contact hole, 2. The display device according to claim 1, wherein the first-1 power supply line overlaps with the pixel.

14. further comprising a pad portion disposed in the non-display area, The pad portion is a first voltage pad electrically connected to the first power line; The display device of claim 1 , further comprising: a second voltage pad electrically connected to the second power line.

15. The first voltage pad is a first-1 voltage pad electrically connected to the first-1 power line; 15. The display device of claim 14, further comprising: a first-second voltage pad electrically connected to the first-second power line.

16. The display device of claim 14 , wherein the pad section includes a first pad section and a second pad section spaced apart from each other across the display area.

17. Each of the plurality of pixels is a pixel driving unit disposed on the base layer and including a transistor; a light-emitting element disposed on the transistor, the light-emitting element including a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; The display device of claim 1 , further comprising a connection electrode electrically connecting the transistor and the second electrode to each other.

18. a pixel defining film in which an opening exposing at least a portion of the first electrode is defined; a separator disposed on the pixel defining membrane, a lower surface of the second electrode contacts an upper surface of the connecting electrode in a contact region adjacent to the separator; The display device according to claim 17 , wherein the connecting electrode has a ring shape surrounding the opening.

19. a base layer including a display area divided into a plurality of areas and a non-display area arranged around the display area; a driving element layer disposed on the base layer and including a pixel driving unit; a plurality of light-emitting elements disposed on the driving element layer, each including a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; a first power line electrically connected to the first electrode included in each of the light emitting elements; a second power line electrically connected to the second electrode included in each of the light emitting elements; The first electrode is a first-1 electrode disposed in a first region among the plurality of regions, to which a first voltage is applied via a first-1 power line of the first power line; a first-second electrode disposed in a second region among the plurality of regions, the first-second electrode receiving a second voltage different from the first voltage through a first-second power line of the first power line.

20. a display device; an electronic module overlying the display device; a housing that houses the display device; The display device includes: a base layer including a display area in which a plurality of pixels are arranged and a non-display area arranged around the display area; a conductive layer overlapping with at least a portion of the plurality of pixels in a plane; a first power line electrically connected to the plurality of pixels; a second power line electrically connected to the plurality of pixels; The conductive layer is a first conductive layer overlapping a first pixel of the plurality of pixels in a plane; a second conductive layer overlapping a second pixel of the plurality of pixels in a plane and spaced apart from the first conductive layer; The first power supply line is a first power line electrically connected to the first pixel through the first conductive layer; a first and second power supply line electrically connected to the second pixel through the second conductive layer.

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