Three dimensional memory device with split drain select gate line and method for forming three dimensional memory device

Abstract

To provide a memory device and a method for forming the memory device.SOLUTION: A memory device comprises a stack structure over a substrate, a channel structure extending in the stack structure, and a dielectric layer over the channel structure. The dielectric layer includes a first material. The memory device may also include a drain select gate (DSG) cut structure extending through the dielectric layer. The DSG cleavage structure includes a second material different from the first material.SELECTED DRAWING: Figure 1B

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to memory devices and methods for forming memory devices. [Background technology]

[0002] Planar memory cells are being scaled to smaller and smaller dimensions through improvements in processing techniques, circuit designs, programming algorithms, and manufacturing processes. However, as the minimum feature size of memory cells approaches its lower limit, planar processing and manufacturing techniques become more difficult and costly. As a result, the storage density of planar memory cells approaches its upper limit.

[0003] Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells. 3D memory architectures include a memory array and peripheral circuitry to facilitate operation of the memory array. Summary of the Invention [Means for solving the problem]

[0004] In one aspect, a memory device is disclosed. The memory device includes a stack structure over a substrate, a channel structure extending in the stack structure, and a dielectric layer over the channel structure. The dielectric layer includes a first material. The memory device may also include a DSG cut structure extending through the dielectric layer. The DSG cut structure includes a second material different from the first material.

[0005] In another aspect, a memory system is disclosed. The memory system includes a memory device configured to store data. The memory device includes a stack structure over a substrate, a channel structure extending in the stack structure, a dielectric layer over the channel structure, the dielectric layer including a first material, and a DSG cut structure extending through the dielectric layer. The DSG cut structure includes a second material different from the first material. The memory system also includes a memory controller coupled to the memory device and configured to control operation of the channel structure.

[0006] In yet another aspect, a method for forming a memory device is disclosed. The method includes forming a stack structure over a substrate, forming a channel structure extending in the stack structure, depositing a first material to form a dielectric layer over the channel structure, and patterning the dielectric layer and the stack structure to form an opening, the opening penetrating the dielectric layer and contacting a conductive layer in an upper portion of the stack structure. The method may also include depositing a second material in the opening to form a DSG disconnection structure. The second material is different from the first material. The method may further include forming a contact in the dielectric layer that contacts the channel structure.

[0007] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the disclosure and to enable one skilled in the art to make and use the disclosure. [Brief explanation of the drawings]

[0008] [Figure 1A] 1 is a top view of an example 3D memory device according to some aspects of the present disclosure. [Figure 1B] 1 is a cross-sectional view of an example 3D memory device according to some aspects of the present disclosure. [Figure 1C]1A and 1B are diagrams of example DSG cutting structures in a 3D memory device according to some aspects of the present disclosure. [Figure 1D] 1A and 1B are diagrams of example DSG cutting structures in a 3D memory device according to some aspects of the present disclosure. [Figure 1E] 1A and 1B are diagrams of example DSG cutting structures in a 3D memory device according to some aspects of the present disclosure. [Figure 2A] 1A-1D are cross-sectional views of an exemplary 3D memory device at different stages of a manufacturing process in accordance with some embodiments of the present disclosure. [Figure 2B] 1A-1D are cross-sectional views of an exemplary 3D memory device at different stages of a manufacturing process in accordance with some embodiments of the present disclosure. [Figure 2C] 1A-1D are cross-sectional views of an exemplary 3D memory device at different stages of a manufacturing process in accordance with some embodiments of the present disclosure. [Figure 2D] 1A-1D are cross-sectional views of an exemplary 3D memory device at different stages of a manufacturing process in accordance with some embodiments of the present disclosure. [Figure 2E] 1A-1D are cross-sectional views of an exemplary 3D memory device at different stages of a manufacturing process in accordance with some embodiments of the present disclosure. [Figure 2F] 1A-1D are cross-sectional views of an exemplary 3D memory device at different stages of a manufacturing process in accordance with some embodiments of the present disclosure. [Figure 2G] 1A-1D are cross-sectional views of an exemplary 3D memory device at different stages of a manufacturing process in accordance with some embodiments of the present disclosure. [Figure 2H] 1A-1D are cross-sectional views of an exemplary 3D memory device at different stages of a manufacturing process in accordance with some embodiments of the present disclosure. [Figure 3] 1 is a flow diagram of an example method for forming a 3D memory device according to some aspects of the present disclosure. [Figure 4] FIG. 1 is a block diagram of an example system having a memory device in accordance with some aspects of the present disclosure. [Figure 5A] 1 is a diagram of an example memory card having a memory device in accordance with some aspects of the present disclosure. [Figure 5B] FIG. 1 is a diagram of an example solid-state drive (SSD) having a memory device in accordance with some aspects of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] The present disclosure will be described with reference to the accompanying drawings.

[0010] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. The present disclosure can also be used in a variety of other applications. The functional and structural features as described in this disclosure can be combined, arranged, and modified in ways not expressly depicted in the drawings, such that the combinations, arrangements, and modifications are within the scope of the present disclosure.

[0011] Generally, terms can be understood, at least in part, from their use in context. For example, the term "one or more," as used herein, may be used to describe a feature, structure, or characteristic in the singular sense, or may be used to describe a combination of features, structures, or characteristics in the plural sense, depending at least in part on the context. Similarly, terms such as "one" or "the" may be utilized to convey singular use or to convey plural use, depending at least in part on the context. Also, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, but instead may allow for the presence of additional factors not necessarily explicitly recited, depending at least in part on the context.

[0012] It should be readily understood that the meanings of "on," "above," and "across" in this disclosure should be interpreted in the broadest manner so that "on" does not only mean "directly on" something, but can also mean "on" something with an intermediate feature or layer between them, and so that "above" and "across" can not only mean "above" and "across" something, but can also mean "above" and "across" something without an intermediate feature or layer between them (i.e., directly on top of something).

[0013] Additionally, spatially relative terms such as "below," "below," "lower," "above," and "above" may be used herein for ease of description to describe the relationship of one element or feature to other elements or features, as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or rotated to other orientations), and the spatially relative descriptions used herein may be similarly interpreted accordingly.

[0014] As used herein, the term "layer" refers to a portion of material that includes a region with a thickness. A layer can extend throughout an underlying or overlying structure, or can have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer can be a homogeneous or non-homogeneous region of a continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be positioned between any pair of horizontal surfaces, between the upper and lower surfaces of a continuous structure, or at the upper and lower surfaces. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers, and / or can have one or more layers on, above, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor layers and contact layers (in which interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0015] As used herein, the term "substrate" refers to a material onto which subsequent layers of material are added. The substrate itself may be patterned. Materials added on top of the substrate may be patterned or left unpatterned. Additionally, the substrate may include a wide array of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made from a non-conductive material such as glass, plastic, or a sapphire wafer.

[0016] As used herein, "3D memory device" refers to a semiconductor device with vertically oriented strings of memory cell transistors (such as NAND memory strings, referred to herein as "memory strings") in a laterally oriented substrate such that the memory strings extend vertically relative to the substrate. As used herein, the term "vertical" means nominally perpendicular to the lateral surface of the substrate.

[0017] In some 3D memory devices, such as 3D NAND memory devices, memory cells are formed with functional channel structures that extend in a stack structure of interleaved stacked conductive layers and stacked guide layers. Due to the ever-increasing demand for higher capacity, channel structures now have more compact lateral arrangements to increase the number / density of memory cells and, ultimately, the capacity of 3D memory devices. One way to increase capacity is to allocate more functional channel structures to a memory block of a 3D memory device. For example, instead of nine columns, 12 or 16 columns of functional channel structures may be arranged in a memory block. Another method is to additionally or alternatively reduce the number of dummy channel structures in order to form more functional channel structures in a memory block. Often, memory cells are not formed in dummy channel structures.

[0018] To operate a 3D memory device, memory cells are divided into memory blocks, and the memory blocks are further divided into strings. For example, drain select gate (DSG) disconnect structures are often formed between adjacent strings in a memory block to disconnect the DSGs in different strings. Therefore, strings can be selected through their respective DSGs in various operations. DSG disconnect structures are often formed above dummy channel structures. To reduce the number of dummy channel structures, dummy channel structures are not formed, and DSG disconnect structures are formed between strings but above functional channel structures. The DSG disconnect structures contact columns of functional channel structures and one or more DSGs of strings so that the DSGs of adjacent strings are disconnected. Vertically, the DSG disconnect structures partially overlap channel structures, such as the drains of the channel structures.

[0019] After the DSG cut structure is formed in the stack structure, a contact, such as a channel contact, is formed above and in contact with the functional channel structure. The contact allows a drain voltage to be applied to the functional channel structure during operation. The contact is often formed in a dielectric layer over the functional channel structure. The dielectric layer and the DSG cut structure in contact with the functional channel structure often have the same dielectric material, such as silicon oxide. To form the contact, an opening is first formed in the dielectric layer to expose the drain below the functional channel structure, and a conductive material is deposited in the opening. In the vertical direction, the opening often partially overlaps the DSG cut structure. Because the dielectric layer and the DSG cut structure have the same structure, the etchant used to form the opening often overetches the DSG cut structure, resulting in undesired etched areas in the functional channel structure. As a result, conductive material may be deposited in the undesired etched areas, causing problems such as shorts and / or leakage.

[0020] The present disclosure provides 3D memory devices and fabrication processes with DSG cut structures that include an etch-stop material for forming the DSG cut structure. The etch-stop material is a different material from the dielectric layer overlying the channel structure. For example, the dielectric layer includes silicon oxide and the etch-stop material includes silicon nitride. In some implementations, the etch-stop material is made of silicon nitride. In some implementations, the etch-stop material includes silicon nitride, silicon oxide, and / or voids. During the formation of the opening in which the contact is formed, the etch rate of the etch-stop material is desirably less than the etch rate of the dielectric layer. Thus, the bottom of the opening can stop at the DSG cut structure instead of extending into the channel structure. Therefore, the channel structure in contact with the DSG cut structure is less susceptible to over-etching during the formation of the contact. Therefore, shorts and / or leakage are less likely to occur in the 3D memory devices disclosed herein.

[0021] FIG. 1A illustrates a top view of an example 3D memory device 100 according to some embodiments of the present disclosure. FIG. 1B illustrates a cross-sectional view of the 3D memory device 100 along the A-A′ direction according to some embodiments of the present disclosure. For illustrative purposes, only a portion of the 3D memory device is depicted in FIG. 1B. FIG. 1A and FIG. 1B will be described together.

[0022] The 3D memory device 100 may include a substrate 110, which may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. In some implementations, the substrate 110 is a thinned substrate (e.g., a semiconductor layer) thinned by grinding, etching, chemical-mechanical polishing (CMP), or any combination thereof. It is noted that x-, y-, and z-axes are included in FIGS. 1A and 1B to further illustrate the spatial relationships of components in the 3D memory device 100. The substrate 110 of the 3D memory device 100 includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x- and y-directions (i.e., lateral directions). As used herein, whether one component (e.g., a layer or device) is "on," "above," or "below" another component (e.g., a layer or device) of a 3D memory device (e.g., 3D memory device 100) is determined relative to the substrate (e.g., substrate 110) of the 3D memory device in the z-direction (i.e., vertical direction) when the substrate is positioned in a plane below the 3D memory device in the y-direction. The same concepts of describing spatial relationships are applied throughout this disclosure.

[0023] 3D memory device 100 may be a counterpart to a monolithic 3D memory device. The term "monolithic" means that the components of the 3D memory device (e.g., peripheral devices and memory array) are formed on a single substrate. For monolithic 3D memory devices, fabrication faces additional constraints due to the convolution of peripheral device processing and memory array device processing. For example, fabrication of memory array devices (e.g., NAND memory strings) is constrained by thermal budgets associated with peripheral devices formed on or in the same substrate.

[0024] Alternatively, 3D memory device 100 may be part of a non-monolithic 3D memory device in which components (e.g., peripheral devices and memory array devices) may be formed separately on different substrates and then bonded, such as in a face-to-face manner. In some implementations, the substrate of the memory array device (e.g., substrate 110) remains as the substrate of the bonded non-monolithic 3D memory device, and the peripheral devices (e.g., including any suitable digital, analog, and / or mixed-signal peripheral circuitry used to facilitate operation of 3D memory device 100, such as page buffers, decoders, and latches, not shown) are flipped over and face down toward the memory array devices (e.g., NAND memory strings) for hybrid bonding. It is understood that in some implementations, the memory array device substrate (e.g., substrate 110) is flipped over and faces down toward the peripheral devices (not shown) for hybrid bonding, such that in the bonded non-monolithic 3D memory device, the memory array devices are above the peripheral devices. The memory array device substrate (e.g., substrate 110) can be a thinned substrate (not a substrate of a bonded non-monolithic 3D memory device), and the back end of line (BEOL) of the interconnects of the non-monolithic 3D memory device can be formed on the back side of the thinned memory array device substrate.

[0025] In some implementations, the 3D memory device 100 is a NAND flash memory device in which memory cells are provided in the form of an array of NAND memory strings, such as channel structures, each extending vertically above a substrate 110. FIG. 1A shows a plan view of a portion of a memory block 101 in the 3D memory device 100 in accordance with some embodiments of the present disclosure. The memory block 101 may include a plurality of memory cells (not shown) disposed between pairs of slit structures 102. The memory cells arranged in the array are formed by a plurality of channel structures 108 between the slit structures 102. The 3D memory device 100 may also include one or more DSG cut structures 106 between pairs of adjacent strings 104, respectively.

[0026] 1B , the 3D memory device 100 may include a stack structure 130 and a plurality of channel structures 108 extending vertically through the stack structure 130 in the z-direction. The stack structure 130 may include stack conductive layers and stack inducing layers 118 interleaved above a substrate 110. The stack conductive layers may include one or more DSG lines 116, such as in an upper portion of the stack structure 130, and a plurality of control gate lines (e.g., word lines) 120. For example, the DSG lines 116 may be upper stack conductive layers, and the number of DSG lines may be 1, 2, 3, 4, etc. The number of stack conductive layers may be any suitable positive number, such as 16, 432, 64, 96, 128, 256, etc. The stack conductive layers (DSG lines 116 and word lines 120) may have a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. The stack inductive layer 118 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0027] Intersections of control gate lines 120 and channel structures 108 form memory cells. The 3D memory device 100 can include multiple channel structures 108, such as an array, positioned between slit structures 102 in the y-direction. In some implementations, the channel structures 108 can be arranged in columns, each extending in the x-direction, with multiple columns arranged in the y-direction. In some implementations, a memory block 101 includes 4×M columns of channel structures 108 arranged in the y-direction, where M is a positive integer. For example, the memory block 101 can include 8 columns, 12 columns, 16 columns, etc. In some implementations, as shown in FIG. 1A , the memory block 101 includes 16 columns of channel structures 108.

[0028] The channel structure 108 may include a channel hole filled with a semiconductor material (e.g., as a semiconductor channel) and a dielectric material (e.g., as a memory film). In some implementations, the semiconductor channel includes silicon, such as amorphous silicon, polysilicon, or single-crystal silicon. In some implementations, the memory film is a composite layer including a tunnel layer, a storage layer (also known as a "charge trapping layer"), and a blocking layer. In some implementations, the remaining space of the channel structure 108 can be partially or completely filled with a fill layer including a dielectric material such as silicon oxide. The channel structure 108 may have a cylindrical shape (e.g., a pillar shape). According to some implementations, the fill layer, semiconductor channel, tunnel layer, storage layer, and blocking layer are radially arranged from the center of the pillar to the outer surface in this order. The tunnel layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon oxide, silicon oxynitride, or any combination thereof. The blocking layer may include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film may include a silicon oxide / silicon oxynitride (or silicon nitride) / silicon oxide (ONO) composite layer.

[0029] In some implementations, the channel structure 108 may further comprise a semiconductor plug at a lower portion (e.g., bottom end) of the channel structure 108. As used herein, when the substrate 110 is positioned in the lowermost plane of the 3D memory device 100, the “top end” of a component (e.g., the channel structure 108) is the end farthest from the substrate 110 in the z-direction, and the “bottom end” of the component (e.g., the channel structure 108) is the end closest to the substrate 110 in the z-direction. The semiconductor plug may comprise a semiconductor material such as silicon that may be epitaxially grown from or deposited over the substrate 110 in any suitable direction. It is understood that in some implementations, the semiconductor plug comprises monocrystalline silicon of the same material as the substrate 110. Stated differently, the semiconductor plug may comprise an epitaxially grown semiconductor layer that is the same material as the substrate 110. In some implementations, a portion of the semiconductor plug is above the top surface of the substrate 110 and in contact with the semiconductor channel. The semiconductor plug can function as a channel controlled by the source select gate of the channel structure 108. It is understood that in some implementations, the 3D memory device 100 does not include a semiconductor plug as shown in FIG. 1B.

[0030] In some implementations, the channel structure 108 may further comprise a channel plug at an upper portion (e.g., top end) of the channel structure 108. The channel plug may be in contact with the top end of the semiconductor channel. The channel plug may include a semiconductor material (e.g., polysilicon). By covering the top end of the channel structure 108 during fabrication of the 3D memory device 100, the channel plug can function as an etch stop layer to prevent etching of dielectrics filled in the channel structure 108, such as silicon oxide and silicon nitride. In some implementations, the channel plug also functions as a drain for the channel structure 108.

[0031] The slit structure 102 may extend vertically (e.g., in the z-direction) and laterally (e.g., in the x-direction) in the stack structure 130. The slit structure 102 may also be referred to as a gate line slit. In some implementations, a source contact structure may be formed as part of an array common source (ACS) that applies a source voltage to the channel structure 108. The slit structure 102 may be in contact with the substrate 110. In some implementations, the source contact structure in the slit structure 102 may each include a dielectric spacer and a source contact in the dielectric spacer. The source contact may be conductively connected to the substrate 110. The source contact may include a conductive material, including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. The dielectric spacer may include a dielectric material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0032] The 3D memory device 100 may further include a dielectric layer 114 in contact with the channel structure 108 over the channel structure 108 (e.g., a channel plug of the channel structure 108) and a contact 112 in the dielectric layer 114. The contact 112 may be in contact with the channel structure 108 (e.g., a channel plug / drain of the channel structure 108). The dielectric layer 114 may include a single layer or multiple layers and may include one or more dielectric materials. In some implementations, the dielectric layer 114 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. For example, the dielectric layer 114 may include a silicon nitride layer sandwiched by a pair of silicon oxide layers. In some implementations, the channel plug (e.g., drain) of the channel structure 108 is in contact with the silicon oxide layer. In some implementations, the contact 112 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. The contact 112 may apply a drain voltage to the channel structure 108 during operation.

[0033] One or more DSG disconnect structures 106 may extend vertically (e.g., in the z-direction) and laterally (e.g., in the x-direction) in the stack structure 130. The DSG disconnect structures 106 may each be positioned between adjacent strings 104 of a memory block 101. For example, a memory block 101 may include 16 columns of channel structures 108 divided into four strings 104 by three DSG disconnect structures 106. As shown in FIGS. 1A and 1B , a DSG disconnect structure 106 may contact multiple channel structures 108 in the first column of each string 104. The channel structures 108 in contact with the DSG disconnect structure 106 may be functional channel structures in which memory cells are formed. The DSG disconnect structure 106 may contact one or more stack conductive layers in one of the adjacent strings 104 such that these stack conductive layers are unconnected / isolated from one string 104 to the other string 104. The stacked conductive layer in contact with the DSG disconnect structure 106 may be referred to as a DSG line 116. A portion of the DSG line 116 in each string 104 may form the DSG of the respective string 104, and a gate select voltage may be applied to the DSG to select the respective string 104 during operation. In some implementations, depending on the design, the number of DSG lines 116 may be 1, 2, 3, 4, or any other suitable positive number. In some implementations, the DSG in each string 104 may be positioned in the upper portion of the stack structure 130 and may be referred to as a top select gate (TSG). In some implementations, as shown in FIG. 1A , the DSG disconnect structure 106 contacts two adjacent columns of channel structures 108. For ease of illustration, in this disclosure, the DSG disconnect structure is depicted in contact with one channel structure in FIGS. 1B-1E and 2A-2H by way of example.

[0034] The DSG cutting structures 106 may comprise a different material than the dielectric layer 114. In some implementations, the DSG cutting structures 106 may comprise a dielectric material that can function as an etch stop layer in the form of the contacts 112. In some implementations, the etchant used to form the openings in which the contacts 112 are located has a higher etch rate in the dielectric layer 114 than in the DSG cutting structures 106. For example, the etch selectivity of the dielectric layer 114 relative to the DSG cutting structures 106 may be greater than 1. In some implementations, the dielectric layer 114 comprises silicon oxide and the DSG cutting structures 106 comprise silicon nitride.

[0035] 1C-1E each illustrate the structure of a DSG cutting structure 106 according to some embodiments of the present disclosure. In one example, as shown in FIG. 1C, the DSG cutting structure 106 can include silicon nitride. In some implementations, the DSG cutting structure 106 is comprised of an etch stop layer such as a silicon nitride layer. In another example, as shown in FIG. 1D, the DSG cutting structure 106 can include a liner layer 106-1 and an etch stop layer 106-2 surrounded by and in contact with the liner layer 106-1. The liner layer 106-1 can be in contact with the channel structure 108 and the DSG line 116. The top surface of the etch stop layer 106-2 can be coplanar with the top surface of the dielectric layer 114. In some implementations, the liner layer 106-1 includes silicon oxide, and the etch stop layer 106-2 includes silicon nitride. In a further example, as shown in FIG. 1E, the DSG cutting structure 106 may include a liner layer 106-1, an etch-stop layer 106-2 surrounded by and in contact with the liner layer 106-1, and a filler layer 106-3 surrounded by and in contact with (e.g., within) the etch-stop layer 106-2. The material of the filler layer 106-3 may be different from the material of the etch-stop layer 106-2. For example, the filler layer 106-3 may include silicon oxide, silicon oxynitride, or voids. In some implementations, the filler layer 106-3 includes voids. In the example shown in FIGS. 1D and 1E, the thickness of the liner layer 106-1 may range between 2 nm and 8 nm (e.g., 2 nm, 3 nm, 5 nm, 7 nm, 8 nm). For example, the thickness of the liner layer 106-1 may be approximately 5 nm.

[0036] 2A-2H illustrate cross-sectional views of a 3D memory device 200 at different stages of a fabrication process according to some embodiments of the present disclosure. FIG. 3 illustrates a flow diagram of an example method 300 for forming a 3D memory device 200 according to some embodiments of the present disclosure. The 3D memory device 200 may be an example of a 3D memory device 100. For illustrative purposes, FIGS. 2A-2H and the method 300 are considered together. It is understood that the operations shown in the method 300 are not inclusive and that other operations may be performed before, after, or between any of the illustrated operations. Furthermore, some of the operations may be performed simultaneously or in a different order than shown in FIGS. 2A-2H and 3.

[0037] The method 300 begins at operation 302, where a stack structure is formed over a substrate and a channel structure is formed in the stack structure. Figure 2A shows the corresponding structure.

[0038] 2A, a stack structure 230 may be formed over a substrate (not shown), and a vertically extending channel structure 208 may be formed in the stack structure 230. The stack structure 230 may include multiple stack conductive layers (e.g., DSG lines 216 and control gate lines 220) interleaved with multiple stack dielectric layers 218.

[0039] To form the stack structure 230, multiple layers of a first material and multiple layers of a second material are deposited on the substrate in a stacked manner above the substrate. In a “gate-last” process, a dielectric stack (not shown) having multiple alternating stack inductive layers and stack sacrificial layers can be formed above the substrate. The stack inductive layers and stack sacrificial layers can form multiple stack dielectric / sacrificial layer pairs across the substrate. A gate replacement process can be performed later to form stack conductive layers in the stack structure 230. In some implementations, the substrate can include a silicon substrate. The stack inductive layers and stack sacrificial layers can include different materials. In some implementations, each stack inductive layer can include a layer of silicon oxide, and each stack sacrificial layer can include a layer of silicon nitride. The dielectric stack can be formed by one or more thin film deposition processes, including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In some implementations, a pad oxide layer (not shown) is formed between the substrate and the dielectric stack by depositing a dielectric material, such as silicon oxide, on the substrate.

[0040] In a "gate-first" process, a stack of interleaved stack conductive layers and stack inductor layers can be formed across a substrate without requiring a gate replacement process. The stack conductive layers can each include a layer of polysilicon, and the stack inductor layers can each include a layer of silicon oxide. The stack can be formed by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some implementations, the interleaved layers of first and second materials can undergo a trimming process, in which the layers of first and second materials are repeatedly patterned to form a staircase structure on one or more sides of the stack structure 230. The trimming process can include photolithography and etching processes (e.g., wet and / or dry etching).

[0041] A channel structure 208 may be formed that extends through the stack structure 230 (e.g., a dielectric stack) in the z-direction. The channel structure 208 may include a channel plug 215 (e.g., a drain of the channel structure 208) in an upper portion of the channel structure 208 (or stack structure 230). The channel plug 215 may include polysilicon and / or metal and may subsequently be conductively connected to a contact that applies a drain voltage to the channel structure 208. In some implementations, an etching process may be performed to form multiple channel holes that extend vertically through the interleaved stack dielectric layer / sacrificial layer pairs. In some implementations, the fabrication process for forming the channel holes may include wet etching and / or dry etching, such as deep reactive ion etching (DRIE). In some implementations, the channel holes may extend further into an upper portion of the substrate. After the formation of the channel holes, in some implementations, an epitaxial operation, such as a selective epitaxial growth operation, may be performed to form semiconductor plugs at the bottom of the channel holes. A memory film including a tunnel layer, a storage layer, a blocking layer, and a semiconductor channel may be formed in the channel hole. Optionally, a fill layer may be formed in the channel hole. In some implementations, the channel structure 208 may not include a semiconductor plug. The deposition of the memory film, the semiconductor channel, and the fill layer may include any suitable thin film deposition process, such as CVD, PVD, ALD, or any combination thereof. The deposition of the channel plug 215 may include CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof.

[0042] A plurality of gate line slits (not shown) may be formed extending through the stack structure 230 in the z-direction. The gate line slits in which the source contact structures are formed may extend laterally in the x-direction, referring back to FIG. 1A . The gate line slits may contact or extend into an upper portion of the substrate. In some implementations, the fabrication process for forming the gate line slits may include wet etching and / or dry etching, such as deep reactive ion etching (DRIE).

[0043] In the gate-last process, an anisotropic etching process may be performed to remove the stack sacrificial layer and form the multiple lateral recesses. One or more thin film deposition processes, such as CVD, PVD, and / or ALD, may be performed to form the multiple stack conductive layers in the lateral recesses. In some implementations, the stack conductive layers include W.

[0044] Next, a source contact structure (e.g., referring back to source contact structure 102) may be formed in each gate line slit. The source contact structure may comprise a dielectric spacer (e.g., silicon oxide) and a source contact (e.g., W) in the dielectric spacer. Formation of the dielectric spacer may include one or more thin film deposition processes, such as CVD, PVD, and / or ALD. Formation of the source contact may include CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof.

[0045] The method 300 proceeds to operation 304 where a first material is deposited to form a dielectric layer over the channel structure. Figure 2A shows the corresponding structure.

[0046] As shown in FIG. 2A , after the stack structure 230 and the channel structure 208 are formed, a dielectric layer 214 is formed over and in contact with the channel structure 208. The formation of the dielectric layer 214 may include deposition of a first material, such as silicon oxide. In some implementations, the dielectric layer 214, having a single layer or multiple layers, includes silicon oxide, silicon nitride, and / or silicon oxynitride. In some implementations, the dielectric layer 214 includes a silicon nitride layer sandwiched by a pair of silicon oxide layers. In some implementations, the channel structure 208 (e.g., the drain of the channel structure 208) is in contact with a layer of silicon oxide that is part of the dielectric layer 214. The formation of the dielectric layer 214 may include one or more thin film deposition processes, such as CVD, PVD, and / or ALD.

[0047] The method 300 proceeds to operation 306, where the dielectric layer and stack structure are patterned to form openings through the dielectric layer and in contact with one or more conductive layers in an upper portion of the stack structure. Figure 2B shows a corresponding structure.

[0048] As shown in FIG. 2B , after the formation of the dielectric layer 214, an opening 222 is formed through the dielectric layer 214 and into the stack structure 230. The opening 222 may contact the upper portion of the channel structure 208 and one or more stack conductive layers in the upper portion of the stack structure 230. For example, in the xy plane, the opening 222 may partially overlap the channel structure 208 and one or more stack conductive layers. The opening 222 can disconnect one or more stack conductive layers from the channel structure 208. At least a portion of the channel plug 215 is left intact for subsequent conductive connection to a contact. In some implementations, the opening 222 is positioned between the channel structure 208 and one or more stack conductive layers, and the bottom surface of the opening 222 can be below the bottom structure of one or more stack conductive layers. The number of stack conductive layers disconnected by the opening 222 can be one, two, three, four, etc. The unconnected stacked conductive layers can form DSG line 216, and the stacked conductive layers below DSG line 216 can include control gate line 220. In some implementations, forming opening 222 can include photolithography and etching steps (e.g., wet etching and / or dry etching).

[0049] The method 300 proceeds to operation 308, where a second material is deposited into the opening to form a DSG cut structure. Figures 2C-2E show corresponding structures.

[0050] After the formation of the openings 222, a second material may be deposited into the openings 222 to form the DSG cut structures. The second material may include silicon nitride, which can function as an etch stop material in etching the structures in the dielectric layer 214. In some implementations, the second material also includes other non-conductive materials, such as other dielectric materials and / or air gaps. In some implementations, the second material is comprised of silicon nitride, and the deposition of the second material may include one or more thin film deposition processes, such as CVD, PVD, and / or ALD. A planarization process, such as chemical mechanical polishing (CMP) and / or recess etching, is performed after deposition to remove excess deposited material over the dielectric layer 214.

[0051] As an example, FIGS. 2C-2E show a structure in which the second material includes silicon nitride and silicon oxide. As shown in FIG. 2C, a liner material layer 224 of a suitable material, such as silicon oxide, can be deposited into the opening 222. In some implementations, the liner material layer 224 has a thickness of 2 nm to 8 nm, such as 5 nm, and can be deposited using ALD. The liner material layer 224 can cover the bottom and side surfaces of the opening 222. As shown in FIG. 2D, an etch-stop material layer 226 can be deposited over the liner material layer 224 to fill the opening 222. Deposition of the etch-stop material layer 226 can include one or more thin film deposition processes, such as CVD, PVD, and / or ALD. In some implementations, a void (not shown) is formed in the etch-stop material layer 226. Formation of the void can include any suitable manufacturing process, such as rapid thermal sealing. The void can be enclosed, such as sealed, by the etch-stop material layer 226.

[0052] 2E, a planarization process, such as CMP and / or recess etching, is performed after deposition of etch-stop material layer 226 to remove excess deposition material over dielectric layer 214. DSG cutting structure 206 may be formed having liner layer 225 (e.g., silicon oxide) and etch-stop layer 228 (e.g., silicon nitride). Liner layer 225 may surround etch-stop layer 228 on the bottom and sides of etch-stop layer 228. In some implementations, the top surface of DSG cutting structure 206 may be flush with dielectric layer 214.

[0053] The method 300 continues with operation 310, where a contact is formed in the dielectric layer, the contact contacting the channel structure. Figures 2F-2H show corresponding structures.

[0054] 2F, after formation of the DSG cut structure 206, a cap layer 240 may be formed over the dielectric layer 214 and the DSG cut structure 206. The cap layer 240 may cover at least the DSG cut structure 206 and the channel structure 208. In some implementations, the cap layer 240 comprises a dielectric material, such as silicon oxide, and may be deposited using one or more thin film deposition processes, such as CVD, PVD, and / or ALD.

[0055] As shown in FIG. 2G , an opening 232 may be formed in the cap layer 240 and the dielectric layer 214. The opening 232 may extend through the dielectric layer 214 and contact the channel structure 208 (e.g., the channel plug 215). In some implementations, the opening 232 may be in contact with the DSG cut structure 206, such as being partially in the DSG cut structure 206, as shown in FIG. 2G . At least the top surface of the etch stop layer 228 may be exposed to etching to form the opening 232. The portion of the liner layer 225 in contact with the opening 232 may or may not be partially removed by the etching process that forms the opening 232. In some implementations, the liner layer 225 may be fully or partially retained in the etch stop layer 228 at the opening 232. For example, when the liner layer 225 is fully or partially removed at the opening 232, the side etch stop layer 228 may be exposed at the opening 232. In another example, when the liner layer 225 is fully retained, the sides of the etch stop layer 228 are covered by the liner layer 225 in the opening 232. In some implementations, the thickness of the liner layer 225 is desirably thin so that the etch stop layer 228 still prevents etching of the channel structure 208. Thus, the channel structure 208 is less susceptible to damage during the formation of the opening 232. In some implementations, the formation of the opening 232 may include photolithography and etching steps (e.g., dry etching and / or wet etching).

[0056] As shown in FIG. 2H, a conductive material is deposited to fill the opening 232, forming the contact 212. The contact 212 may extend through the dielectric layer 214 in the cap layer 240 and into contact with the channel plug 215 of the channel structure 208. In some implementations, if the liner layer 225 is partially or completely removed in the opening 232, the contact 212 contacts the sides and top of the etch stop layer 228. In some implementations, if the liner layer 225 is completely retained on the sides of the etch stop layer 228, the contact 212 contacts the etch stop layer 228 on the top surface but not on the sides. In some implementations, the conductive material includes tungsten (W), and the deposition includes CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. In some implementations, an adhesion layer, such as titanium nitride (TiN), is deposited on the sides of the opening 232 before the deposition of tungsten. In some implementations, deposition of the adhesion layer includes CVD, PVD, ALD, or any combination thereof.

[0057] FIG. 4 shows a block diagram of an example system 400 having a memory device according to some aspects of the present disclosure. The system 400 may be a mobile phone, a desktop computer, a laptop computer, a tablet, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device. As shown in FIG. 4 , the system 400 may include a host 408 and a memory system 402 having one or more memory devices 404 and a memory controller 406. The host 408 may be an electronic device such as a central processing unit (CPU) or a processing unit of a system-on-chip (SoC) such as an application processor (AP). The host 408 may be configured to transmit data to or receive data from the memory device 404.

[0058] The memory device 404 may be any memory device disclosed in this disclosure. As disclosed in detail above, the memory device 404, such as a NAND flash memory device, may have one or more DSG cut structures with an etch-stop material. The memory controller 406 is coupled to the memory device 404 and a host 408 and, according to some implementations, is configured to control the memory device 404. The memory controller 406 may manage data stored in the memory device 404 and may communicate with the host 408. For example, the memory controller 406 may be coupled to a memory device 404, such as the 3D memory device 100 described above, and the memory controller 406 may be configured to control operation of the channel structure 108 of the 3D memory device 100 through the DSG lines 116.

[0059] In some implementations, the memory controller 406 is designed to operate in low duty-cycle environments, such as a Secure Digital (SD) card, a CompactFlash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, and mobile phones. In some implementations, the memory controller 406 is designed to operate in high duty-cycle environments, such as an SSD or embedded multimedia card (eMMC) used as a data storage device in portable devices such as smartphones, tablets, and laptop computers, and for enterprise storage arrays. The memory controller 406 may be configured to control operations of the memory device 404, such as read, erase, and program operations. The memory controller 406 may also be configured to manage various functions with respect to data stored or to be stored on the memory device 404, including, but not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, and the like. In some implementations, memory controller 406 is further configured to process error correction codes (ECC) on data read from or written to memory device 404. Any other suitable functions, such as formatting memory device 404, may also be performed by memory controller 406. Memory controller 406 can communicate with external devices (e.g., host 408) according to a particular communication protocol.For example, the memory controller 406 may communicate with external devices through at least one of a variety of interface protocols, such as a USB protocol, an MMC protocol, a PCI (Peripheral Component Interconnect) protocol, a PCI-Express (PCI-E) protocol, an ATA (Advanced Technology Attachment) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

[0060] The memory controller 406 and one or more memory devices 404 can be incorporated into various types of storage devices and can be included in the same package, such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the memory system 402 can be implemented and packaged into different types of end electronic products. In one example, as shown in FIG. 5A , the memory controller 406 and a single memory device 404 can be incorporated into a memory card 502. The memory card 502 can be a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a SmartMedia (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS card, or the like. The memory card 502 can further include a memory card connector 504 that couples the memory card 502 to a host (e.g., host 408 in FIG. 4 ). 5B, the memory controller 406 and the plurality of memory devices 404 can be combined into an SSD 506. The SSD 506 can further include an SSD connector 508 that couples the SSD 506 to a host (e.g., host 408 in FIG. 4). In some implementations, the storage capacity and / or operating speed of the SSD 506 is greater than the storage capacity and / or operating speed of the memory card 502.

[0061] According to one aspect of the present disclosure, a memory device includes a stack structure over a substrate, a channel structure extending in the stack structure, and a dielectric layer over the channel structure. The dielectric layer includes a first material. The memory device may also include a DSG cut structure extending through the dielectric layer. The DSG cut structure includes a second material different from the first material.

[0062] In some implementations, the DSG disconnection structure contacts the channel structure and the DSG in multiple conductive layers.

[0063] In some implementations, the etch selectivity of the first material relative to the second material is greater than one.

[0064] In some implementations, the first material and the second material each include a respective dielectric material.

[0065] In some implementations, the first material comprises silicon oxide and the second material comprises silicon nitride.

[0066] In some implementations, the DSG cleavage structure does not include silicon oxide.

[0067] In some implementations, the DSG cutting structure does not include silicon nitride.

[0068] In some implementations, the DSG cutting structure comprises a liner silicon oxide layer and a silicon nitride layer surrounded by the liner silicon oxide layer.

[0069] In some implementations, the thickness of the liner silicon oxide layer ranges from 2 nm to 8 nm.

[0070] In some implementations, the DSG cutting structure comprises a silicon nitride layer surrounded by a liner silicon oxide layer and a void surrounded by the silicon nitride layer.

[0071] In some implementations, the memory device further includes a pair of laterally extending source contact structures and a memory block between the pair of source contact structures. The memory block includes a plurality of memory cells in a plurality of channel structures between the source contact structures. The memory block includes a pair of adjacent strings. Each of the strings includes a plurality of columns of channel structures in the laterally extending direction. The DSG disconnection structure extends laterally between the pair of strings and contacts one of the columns of channel structures.

[0072] In some implementations, each of the strings comprises four rows of channel structures.

[0073] In some implementations, a memory block comprises four strings, each of which comprises four columns of channel structures extending laterally.

[0074] According to another aspect of the present disclosure, a memory system includes a memory device configured to store data. The memory device includes a stack structure over a substrate, a channel structure extending in the stack structure, a dielectric layer over the channel structure, the dielectric layer including a first material, and a DSG cut structure extending through the dielectric layer. The DSG cut structure includes a second material different from the first material. The memory system also includes a memory controller coupled to the memory device and configured to control operation of the channel structure.

[0075] According to another aspect of the present disclosure, a method for forming a memory device includes forming a stack structure over a substrate, forming a channel structure extending in the stack structure, depositing a first material to form a dielectric layer over the channel structure, and patterning the dielectric layer and the stack structure to form an opening, the opening extending through the dielectric layer and contacting a conductive layer in an upper portion of the stack structure. The method may also include depositing a second material in the opening to form a DSG disconnection structure. The second material is different from the first material. The method may further include forming a contact in the dielectric layer that contacts the channel structure.

[0076] In some implementations, the opening is in contact with the channel structure.

[0077] In some implementations, depositing the first material includes depositing silicon oxide.

[0078] In some implementations, depositing a second material to form a DSG cutting structure includes depositing silicon nitride.

[0079] In some implementations, depositing a second material to form the DSG cutting structure includes depositing silicon nitride to fill the opening.

[0080] In some implementations, the step of depositing a second material to form a DSG cutting structure includes the steps of depositing a liner oxide layer in the opening, the liner oxide layer contacting a surface of the opening, and depositing a silicon nitride layer to fill the opening.

[0081] In some implementations, the deposition of the liner oxide layer comprises ALD.

[0082] In some implementations, depositing a second material to form a DSG cutting structure includes depositing a liner oxide layer in the opening, the liner oxide layer contacting a surface of the opening. Depositing the second material may include depositing a silicon nitride layer over the liner oxide layer and forming voids in the silicon nitride layer during deposition of the silicon nitride layer.

[0083] In some implementations, forming contacts in the dielectric layer includes etching the dielectric layer to form other openings in contact with the channel structure and the DSG cut structure, and depositing a conductive material to fill the other openings.

[0084] In some implementations, the DSG cut structure is an etch stop for etching the dielectric layer.

[0085] In some implementations, the etch rate of the second material is less than the etch rate of the first material in etching the dielectric layer.

[0086] The foregoing description of specific implementations may be readily modified and / or adapted for various uses. As such, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

[0087] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.

[0088] The present invention may further include the following aspects. [Section 1] a stack structure across the substrate; a channel structure extending in the stack structure; a dielectric layer over the channel structure, the dielectric layer comprising a first material; a drain select gate (DSG) cut structure extending through the dielectric layer, the DSG cut structure comprising a second material different from the first material; A memory device comprising: [Section 2] Item 1, wherein the DSG cutting structure contacts the channel structure and DSG in multiple conductive layers. [Section 3] Item 3. The memory device according to item 1 or 2, wherein an etching selectivity of the first material to the second material is greater than 1. [Section 4] 4. The memory device of any one of claims 1 to 3, wherein the first material and the second material each comprise a respective dielectric material. [Section 5] 5. The memory device of any one of claims 1 to 4, wherein the first material comprises silicon oxide and the second material comprises silicon nitride. [Section 6] Item 6. The memory device of any one of items 1 to 5, wherein the DSG cut structure does not contain silicon oxide. [Section 7] Item 7. The memory device of item 6, wherein the DSG cut structure comprises silicon nitride. [Section 8] 6. The memory device of any one of claims 1 to 5, wherein the DSG cutting structure comprises a liner silicon oxide layer and a silicon nitride layer surrounded by the liner silicon oxide layer. [Section 9] Item 9. The memory device of item 8, wherein the thickness of the liner silicon oxide layer is in the range of 2 nm to 8 nm. [Section 10] 10. The memory device of claim 8 or 9, wherein the DSG cutting structure comprises a silicon nitride layer surrounded by the liner silicon oxide layer and a filler layer surrounded by the silicon nitride layer. [Section 11] Item 11. The memory device of item 10, wherein the filler layer comprises an air gap. [Section 12] the memory device further comprises a pair of laterally extending source contact structures and a memory block between the pair of source contact structures, the memory block comprising a plurality of memory cells in a plurality of channel structures between the source contact structures; the memory block comprises a pair of adjacent strings, each of the strings comprising a plurality of columns of channel structures in the lateral direction; 12. The memory device of any one of claims 1 to 11, wherein the DSG disconnection structure extends in the lateral direction, is between pairs of the strings, and is in contact with at least one of the columns of the channel structure. [Section 13] Item 13. The memory device of item 12, wherein each of the strings comprises four columns of channel structures. [Section 14] 14. The memory device of claim 12 or 13, wherein the memory block comprises four strings, each of the four strings comprising four columns of channel structures extending in the horizontal direction. [Section 15] 15. The memory device of any one of claims 1 to 14, further comprising a contact above the channel structure in contact with the channel structure, the contact extending through the dielectric layer and in contact with the second material. [Section 16] Item 16. The memory device of item 15, wherein the contact contacts at least a top or side surface of the second material. [Section 17] 1. A memory device configured to store data, comprising: Stack structure across the substrate, a channel structure extending in the stack structure; a dielectric layer over the channel structure, the dielectric layer comprising a first material; and a drain select gate (DSG) cut structure extending through the dielectric layer, the DSG cut structure comprising a second material different from the first material; a memory device comprising: a memory controller coupled to the memory device and configured to control operation of the channel structure; A memory system comprising: [Section 18] 1. A method for forming a memory device, comprising: forming a stack structure over a substrate; forming an extending channel structure in the stack structure; depositing a first material to form a dielectric layer over the channel structure; patterning the dielectric layer and the stack structure to form an opening through the dielectric layer and in contact with a conductive layer at an upper portion of the stack structure; depositing a second material in the opening to form a drain select gate (DSG) disconnect structure, the second material being different from the first material; forming a contact in the dielectric layer in contact with the channel structure; A method comprising: [Section 19] Item 19. The method of item 18, wherein the opening is in contact with the channel structure. [Section 20] 20. The method of claim 18 or 19, wherein the step of depositing the first material includes a step of depositing silicon oxide. [Section 21] 21. The method of any one of clauses 18 to 20, wherein depositing the second material to form the DSG cutting structure comprises depositing silicon nitride. [Section 22] 22. The method of claim 21, wherein depositing the second material to form the DSG cutting structure includes depositing the silicon nitride to fill the opening. [Section 23] depositing the second material to form the DSG cut structure comprises: depositing a liner oxide layer in the opening, the liner oxide layer contacting a surface of the opening; depositing a silicon nitride layer to fill the opening; Item 22. The method according to Item 21, comprising: [Section 24] 24. The method of claim 23, wherein the deposition of the liner oxide layer comprises atomic layer deposition (ALD). [Section 25] depositing the second material to form the DSG cut structure comprises: depositing a liner oxide layer in the opening, the liner oxide layer contacting a surface of the opening; depositing a silicon nitride layer over the liner oxide layer; forming voids in the silicon nitride layer during the deposition of the silicon nitride layer; Item 22. The method according to Item 21, comprising: [Section 26] forming the contact in the dielectric layer etching the dielectric layer to form another opening in contact with the channel structure and the DSG cut structure; depositing a conductive material to fill said other opening; 26. The method of any one of paragraphs 18 to 25, comprising: [Section 27] 27. The method of claim 26, wherein the DSG cut structure is an etch stop layer for the etching of the dielectric layer. [Section 28] 28. The method of claim 26 or 27, wherein the etching rate of the second material is less than the etching rate of the first material during the etching of the dielectric layer. [Explanation of symbols]

[0089] 100 3D memory devices 101 memory blocks 102 Slit structure, source contact structure 104 strings 106 DSG cutting structure 106-1 Liner layer 106-2 Etch stop layer 106-3 Filler layer 108 channel structure 110 Substrate 112 Contacts 114 Dielectric Layer 116 DSG line 118 stack induction layer 120 control gate line, word line 130 stack structure 200 3D memory devices 208 Channel Structure 212 Contacts 215 Channel Plug 216 DSG line 218 stack dielectric layers 220 control gate line 224 Liner material layer 225 Liner layer 228 Etch stop layer 230 stack structure 232 Aperture 240 cap layer 400 System 402 Memory System 404 Memory Devices 406 Memory Control Device 408 Host 502 memory card 504 memory card connector 506 SSD 508 SSD Connector

Claims

[Claim 1] a stack structure across the substrate; a channel structure extending in the stack structure; a dielectric layer over the channel structure, the dielectric layer comprising a first material; a drain select gate (DSG) cut structure extending through the dielectric layer, the DSG cut structure comprising a second material different from the first material; A memory device comprising:

Images