Semiconductor device module and assembly method
The stacked configuration of IGBT and freewheeling diode dies in semiconductor modules addresses size and thermal stress issues, improving reliability and thermal management in power semiconductor devices.
Patent Information
- Application Number
- JP2025183599
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2019-12-11
- Filing Date
- 2025-10-30
- Publication Date
- 2026-01-27
Smart Images
Figure 2026012912000001_ABST
Abstract
Description
[Technical Field]
[0001] FIELD Embodiments relate to the field of semiconductor devices, and in particular to packages for power semiconductor chips. [Background technology]
[0002] Currently, fast switching power semiconductor devices typically use fast switching diodes, such as freewheeling diodes, to protect them from inductive loads, including motor coils or relay windings. At each instance of switching, where the switching device is turned "on," the freewheeling diode changes from a conducting state to a blocking state, where it becomes reverse biased.
[0003] However, if the device is suddenly turned "off," the freewheeling diode becomes forward biased and current will flow through it, for example due to the collapse of energy stored in the coil. Without the protection of a freewheeling diode, high di / dt currents can occur, which in turn can cause high voltage spikes or transients that can damage the switching device.
[0004] Therefore, power semiconductor devices such as insulated gate bipolar transistors (IGBTs) are often arranged in a power semiconductor module on one or more substrates (e.g., two, four, or six similar substrates). Each substrate contains wiring and resistors and holds multiple pairs of IGBT dies (chips) and diode chips, where one or more IGBT chips may be paired with a diode chip. This arrangement provides a modular approach to switching a desired amount of current by selecting an appropriate number of chips. Because the IGBT chips and diode chips are arranged in a planar configuration on the substrate, the substrate must be sized to accommodate all the chips, including the wiring between them. As a result, a power semiconductor module may become excessively large to accommodate the required number of substrates and power semiconductor devices.
[0005] In consideration of the above, the present embodiment is provided. Summary of the Invention
[0006] In some embodiments, a semiconductor device module is provided. The semiconductor device module may include a first substrate and a semiconductor die assembly disposed on the first substrate. The semiconductor die assembly may include a first semiconductor die bonded to the first substrate, a second semiconductor die disposed on the first semiconductor die, and an electrical connector disposed between the first semiconductor die and the second semiconductor die, and the semiconductor die assembly includes an insulated gate bipolar transistor (IGBT) die and a freewheeling diode die.
[0007] In another embodiment, a method of forming a semiconductor device module may include providing a first substrate and attaching a semiconductor die assembly to the first substrate. The semiconductor die assembly may include a first semiconductor die bonded to the first substrate, a second semiconductor die disposed over the first semiconductor die, and an electrical connector disposed between the first and second semiconductor die, where the first semiconductor die assembly includes an insulated gate bipolar transistor (IGBT) die and a freewheeling diode die.
[0008] In a further embodiment, a semiconductor device module may include a first substrate and a semiconductor die assembly disposed on the first substrate, the semiconductor die assembly including a stack of a first insulated gate bipolar transistor (IGBT) die and a freewheeling diode die, and an electrical connector disposed between the IGBT die and the freewheeling diode semiconductor die, such that the IGBT die may be directly bonded to the first substrate, and the stack defines a first die area corresponding to the area of the IGBT die. [Brief explanation of the drawings]
[0009] [Figure 1A] 1 illustrates a side view of a semiconductor device module according to various embodiments of the present disclosure.
[0010] [Figure 1B] 1B shows a top view of the semiconductor device module of FIG. 1A.
[0011] [Figure 1C] 1 illustrates a circuit representation of a semiconductor device module according to an embodiment of the present disclosure.
[0012] [Figure 2A] 10 shows a top view of another semiconductor device module according to a further embodiment of the present disclosure.
[0013] [Figure 2B] FIG. 1 shows a top view of a reference semiconductor device module.
[0014] [Figure 3] 10 illustrates a side view of another semiconductor device module according to a further embodiment of the present disclosure.
[0015] [Figure 4] 10 shows the electrical behavior of the semiconductor device module according to the present embodiment when a pulse is generated.
[0016] [Figure 5A] FIG. 10 shows a side view of the wiring for a reference device having a coplanar structure of IGBT and diode dies.
[0017] [Figure 5B] 1 shows a side view of wiring for a device according to the present embodiment.
[0018] [Figure 6A] 5B shows the relatively low frequency motor signal and the resulting IGBT die temperature behavior for the reference device of FIG. 5A.
[0019] [Figure 6B]6B illustrates the relatively low frequency motor signal and the resulting temperature behavior of the die assembly for the device of FIG. 6A.
[0020] [Figure 6C] 6B illustrates the relatively high frequency motor signal and the resulting temperature behavior of the IGBT die assembly for the device of FIG. 6A.
[0021] [Figure 6D] 6C illustrates the relatively high frequency motor signal and the resulting temperature behavior of the die assembly for the device of FIG. 6B.
[0022] [Figure 7] 1 illustrates a process flow according to an embodiment of the present disclosure.
[0023] [Figure 8] 10 illustrates another process flow according to a further embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION
[0024] The present embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. These embodiments should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the drawings.
[0025] In the following description and / or claims, the terms "on," "overlying," "disposed on," and "over" may be used in the following description and claims. "On," "overlying," "disposed on," and "over" may be used to indicate that two or more elements are in direct physical contact with each other. The terms "on," "overlying," "disposed on," and "over" may also mean that two or more elements are not in direct contact with each other. For example, "over" may mean that one element is above another element but is not in contact with each other, and may have another element or elements between the two elements. Additionally, the term "and / or" can mean "and," can mean "or," can mean "exclusive-or," can mean "one," can mean "some, but not all," can mean "neither," and / or can mean "both," although the scope of claimed subject matter is not limited in this respect.
[0026] In various embodiments, semiconductor device modules and assembly techniques are provided for power semiconductor devices.
[0027] Referring to FIG. 1A, a side view of a semiconductor device module 100 according to various embodiments of the present disclosure is shown. FIG. 1B shows a top view of a variation of the semiconductor device module 100. FIG. 1C shows an electrical circuit representation of the semiconductor device module 100. The semiconductor device module 100 includes a first substrate 102 and a semiconductor die assembly 104 disposed on the first substrate 102. The first substrate 102 may be a known material stack, also known as DCB or DBC®, such as copper / aluminum oxide / copper, according to some embodiments. As such, the first substrate may include an insulator portion sandwiched between metal layers and may be referred to as an insulator substrate. The semiconductor die assembly 104 includes a first semiconductor die 106 attached to the first substrate 102, a second semiconductor die 110 disposed on the first semiconductor die 106, wire bonds 112, and an electrical connector 108 disposed between the first semiconductor die 106 and the second semiconductor die 110. In this and other embodiments of the present disclosure, the semiconductor die assembly 104 includes an insulated gate bipolar transistor (IGBT) die and a freewheeling diode die. Typically, the IGBT die may be disposed in contact with the first substrate 102. As in known power device modules, the IGBT die may be coupled with a diode die used to protect the IGBT die as a freewheeling diode. In other words, the first semiconductor die 106 may be an IGBT die, and the second semiconductor die 110 may be a freewheeling diode die. In various embodiments, an IGBT die, such as the first semiconductor die 106, is disposed in a first region on the first substrate 102 (in the plan view shown in FIG. 1B ) and occupies a first area, and the freewheeling diode die, such as the second semiconductor die 110, occupies a second area that is smaller than the first area. In some non-limiting embodiments, the second area may be approximately 50% (e.g., 40% to 60%) of the first area. Notably, as shown in the plan view of FIG. 1B, second semiconductor die 110 completely overlaps first semiconductor die 106.As such, semiconductor die assembly 104 is characterized by a stacked structure of the IGBT die and the freewheeling diode die, in comparison to known semiconductor power module structures, in which the IGBT die and the diode die are each disposed directly on a substrate in a coplanar configuration. Notably, various metal layers (not shown) may be used to bond semiconductor die assembly 104 to first substrate 102 and to solder or otherwise attach multiple components to one another within semiconductor die assembly 104.
[0028] Notably, as shown in FIG. 1C, the freewheeling diode die and the IGBT die may be electrically coupled, with the freewheeling diode die being electrically coupled to the IGBT die as a reverse freewheeling diode.
[0029] In various embodiments, the stacked structure of IGBT dies and freewheeling diode dies may be provided modularly on one or more substrates. Thus, in various embodiments, semiconductor die assembly 104 may represent only one of multiple semiconductor die assemblies in a given semiconductor device module. FIG. 2A illustrates a top view of another semiconductor device module according to further embodiments of the present disclosure. Semiconductor device module 200 includes four separate semiconductor die assemblies, each of which may be represented by semiconductor die assembly 104 described above. Thus, each additional semiconductor die assembly may be disposed on substrate 202 in a manner similar to the structure of semiconductor die assembly 104 shown in FIG. 1A, with each additional semiconductor die assembly including an insulated gate bipolar transistor (IGBT) die and a freewheeling diode die.
[0030] Although a given freewheeling diode die is located directly above a given IGBT die in semiconductor die assembly 104, the different semiconductor die assemblies do not overlap one another as shown in Figure 2A. Thus, a first semiconductor die assembly, shown as semiconductor die assembly 104A, is disposed on substrate 202 in a first region, and a second semiconductor die assembly, shown as semiconductor die assembly 104B, is disposed on substrate 202 in a second region, not overlapping the first region. In other words, the different semiconductor die assemblies in Figure 2A are disposed on one another in a coplanar manner.
[0031] To highlight the advantages of semiconductor device module 200, FIG. 2B illustrates a top view of a reference semiconductor device module, designated semiconductor device module 220. This reference semiconductor device module is generally arranged in accordance with known power semiconductor device components. In this configuration, two different semiconductor die assemblies are arranged on substrate 202. These semiconductor die assemblies are designated semiconductor die assembly 104C, and the first semiconductor die 106 and the second semiconductor die 110 of a given semiconductor die assembly 104C are arranged in a non-stacked, i.e., coplanar, configuration relative to one another, rather than the stacked configuration of semiconductor die assembly 104. As shown in FIG. 2A, substrate 202 is configured to accommodate semiconductor die assembly 104 in a stacked configuration within a first substrate area designated as A1. As shown in FIG. 2B, the same substrate is configured to accommodate semiconductor die assembly 104C in a second substrate area designated as A2, which includes the same semiconductor die as found in semiconductor die assembly 104, but arranged in a non-stacked configuration. According to various embodiments of the present disclosure, area A2 may be significantly larger than area A1, such as at least 50% larger, and in some instances, 100% larger. In other words, area A1 occupied by semiconductor die assembly 104 of the present embodiment may be 67% of area A2, and in some instances, may be only 50% of area A2. Thus, a semiconductor device module arranged within semiconductor die assembly 104 may have a much more compact area for a given number of IGBT dies compared to known semiconductor power device modules. For example, as shown in FIGS. 2A and 2B , individual IGBT dies, such as first semiconductor die 106, and individual freewheeling diode dies, such as second semiconductor die 110, may all be the same size, and substrate 202 may be the same size in FIGS. 2A and 2B . However, while substrate 202 in FIG. 2A can accommodate four IGBT dies in a stacked configuration, in the non-stacked arrangement of FIG. 2B , substrate 202 can accommodate only two IGBT dies.
[0032] While the above-described embodiments represent so-called single-sided cooled device modules, further embodiments provide double-sided cooled device modules. Figure 3 illustrates a side view of another semiconductor device module according to a further embodiment of the present disclosure. In this embodiment, the semiconductor device module 250 includes, in addition to the above-described components of the semiconductor device module 100, a spacer 252 disposed over the semiconductor die assembly 104 and a second substrate 254 bonded to the spacer 252, with the spacer 252 disposed between the semiconductor die assembly 104 and the second substrate 254. Thus, the first substrate 102 and the second substrate 254 can provide double-sided cooling for the semiconductor die assembly 104.
[0033] In various further embodiments, multiple semiconductor die assemblies 104 may be disposed between a first substrate 102 and a second substrate 254 that includes spacers 252 .
[0034] Another advantage of the stacked semiconductor die assembly structure provided by the present embodiment is improved thermal management due to the stacked structure of the diode and IGBT dies. FIG. 4 illustrates the electrical behavior of a semiconductor device module according to the present embodiment when pulsed. The illustrated example shows a series of regular power pulses as a function of time, and the change in module temperature as a function of time. As shown, a relatively rapid temperature increase occurs at the start of the pulse, which may subside over time depending on the duration of the pulse. After the pulse ends, a gradual temperature decrease may occur, which may also subside over time depending on the duration of the off-time between pulses. Therefore, the temperature swing between maximum and minimum temperatures may be characterized as a metric. According to the present embodiment, the freewheeling diodes are stacked directly above the IGBTs, so the overall temperature swing may be reduced for a given power switching level compared to non-stacked structures in known power modules, and the freewheeling diodes are located away from the IGBT dies.
[0035] To highlight the improved temperature swing provided by this embodiment, Figures 5A and 5B show a reference structure and a device implementation of this embodiment. Figure 5A shows a side view of the wiring of a reference device 500 having a coplanar structure of a first semiconductor die 106, which in one implementation is an IGBT device, and a second semiconductor die 110, such as a diode die. Wire bonds 122 are provided, connecting the IGBT device and the diode die in series to ground. The first substrate 102 may be laminated with a conductive layer 120, such as copper, coupled to an external voltage on the opposite side of the die from the wire bonds.
[0036] 5B shows a side view of the wiring of a device 550 according to this embodiment. In this example, a diode die (second semiconductor die 110) is stacked on top of an IGBT die (first semiconductor die 106). An electrical connector 108 located between the two dies is coupled to ground, while the top surface of the diode die and the bottom surface of the IGBT die (see conductive layer 120) are coupled to an external voltage.
[0037] As is known, in operation, IGBTs may be used as high-speed switches, providing the ability to generate various types of output signals, including motor currents or sinusoidal outputs, at frequencies much lower than the switching speed. A pair of IGBT switches may operate in pulse-width modulation (PWM) mode to generate a time-varying output based on pulse-width modulation. Current may be disconnected between Switch 1 / Diode 2 and Switch 2 / Diode 1 to generate a motor signal, such as a current signal that varies with time as a sinusoid. As the current varies with time, the degree of heating generated in the IGBT die may vary accordingly. FIG. 6A illustrates a relatively low-frequency motor signal, referred to herein as "low frequency," and the resulting IGBT die temperature behavior for the reference device of FIG. 5A. The top curve represents the "motor signal," i.e., current as a function of time, and the bottom curve represents the IGBT die temperature as a function of time. In this example, the IGBT die temperature may vary from a value T1 to a maximum temperature, represented by the dashed line. In the first half-cycle 602, the IGBT die heats up, and in the second half-cycle 604, the IGBT die cools down. As shown, a temperature swing equal to ΔT1 occurs.
[0038] FIG. 6B illustrates the low-frequency motor signal and the resulting die assembly temperature behavior of the device of FIG. 5B. In this example, the motor signal may be assumed to be the same as that seen in FIG. 6A. Due to the stacked die structure, the temperature of the die assembly of FIG. 5B tends to remain higher than the device of FIG. 5A, with a minimum temperature represented as T2. Notably, in the first half-cycle 602, the IGBT die (first semiconductor die 106) heats up, and in the second half-cycle 604, the IGBT die tends to cool. However, in the second half-cycle 604, the second semiconductor die 110, i.e., the diode die, is active. In other words, the second semiconductor die 110 is paired with another IGBT die (not shown), which accordingly generates more heat during the second half-cycle 604, keeping the IGBT die of device 550 warm and resulting in the second temperature peak shown in the second half-cycle 604. As a result, the overall temperature swing of the device assembly including the first semiconductor die 106 and the second semiconductor die 110 is smaller, as shown by ΔT2. This smaller temperature swing generates less thermal stress, which may correspondingly improve the reliability and lifetime of the device.
[0039] FIG. 6C illustrates a relatively high-frequency motor signal, referred to herein as a “high-frequency” signal, and the resulting temperature behavior of the IGBT die assembly of the reference device of FIG. 5A. In this example, a first half-cycle 612 and a second half-cycle 614 are shown. The frequency of the motor signal in this example is required to be much higher (e.g., twice as frequent) than in the example of FIG. 6A. Notably, the temperature behavior of the IGBT device is qualitatively similar to that of FIG. 6A, with a temperature swing of ΔT3 and an average temperature of approximately T3. Thus, the IGBT device heats up above the average temperature in the first half-cycle 612 and cools down below the average temperature in the second half-cycle 614.
[0040] Figure 6D shows the high frequency motor signal and the resulting temperature behavior of the die assembly for the device of Figure 5B. Again, as the second semiconductor die 110 becomes active during the second half-cycle 614, the temperature exhibits a second peak during this period, and the overall temperature swing decreases as shown by ΔT4.
[0041] Notably, at very low frequencies, the number of power cycles doubles in the stack structure of this embodiment. Generally, the PWM of the phase leg is sinusoidally modulated to form a sinusoidal motor current. Thus, in a configuration in which a first transistor / diode pair is coupled to a second transistor / diode pair, during one half-cycle (the “positive waveform”), current toggles between the second transistor die (T2) of the second transistor / diode stack and the first diode die (D1) of the first transistor / diode pair, while the second diode die (D2) of the second transistor / diode pair and the first transistor die (T1) of the first transistor / diode pair do not conduct current. During the second half-cycle (the “negative waveform”), T2 and D1 are turned off, and D2 and T1 are conducting. When the frequency of the motor current is very low (e.g., ∼10 Hz), the temperature of the conducting semiconductor tracks the current. At very low frequencies, non-conducting semiconductors have enough time to cool down to the heat sink temperature. Thus, during the "positive waveform" portion, T2 and D1 experience maximum temperature swings, causing D2 and T1 to drop to the heat sink temperature. During the "negative waveform" portion, T1 and D2 experience maximum temperature swings, causing D1 and T2 to drop to the heat sink temperature. In this embodiment, if D2 is stacked with T2, T2 heats the stack during the "positive waveform," and T2 is not conducting during the "negative waveform," but T2 is heated by D2 (whose die is conducting during the "negative waveform"). In this manner, the frequency of the temperature swings experienced by the transistor / diode stack is doubled, resulting in reduced stresses due to reduced dT in the frequency range where the thermal capacitance acts as a filter.
[0042] 7 illustrates a process flow 700 according to an embodiment of the present disclosure. At block 702, a substrate is provided. The main portion of the substrate may be a known material such as aluminum oxide, aluminum nitride, etc., according to various non-limiting embodiments, and may include a conductive layer such as the known "DCB / DBC" (direct copper bond / direct bond copper substrate).
[0043] A first side of the IGBT die is attached to a substrate at block 704. The IGBT may be bonded to the substrate using appropriate known metallurgy according to known techniques.
[0044] At block 706, electrical connectors or leads are attached to a second side of the IGBT die, opposite the first side. Specifically, a first connector lead may be connected to the "emitter" contact area of the IGBT die, and a second connector lead is attached to the gate contact of the IGBT.
[0045] At block 708, a reverse freewheeling diode die is mounted on an electrical connector, such as a first connector lead, with the reverse freewheeling diode die positioned directly above the IGBT die. In various embodiments, the reverse freewheeling diode die may have an area smaller than the area of the IGBT die, such that it completely overlaps the IGBT die. In various embodiments, the reverse freewheeling diode die may be positioned above and centered on the IGBT die.
[0046] According to variations of process flow 700, the process flow may be implemented using multiple IGBT dies and multiple reverse freewheeling diode dies, with a given IGBT die and a given reverse freewheeling diode die forming a given semiconductor die assembly, resulting in multiple freewheeling diode dies being assembled on a given insulator substrate.
[0047] 8 illustrates another process flow, designated as process flow 750, in accordance with a further embodiment of the present disclosure. Process flow 750 may generally proceed through blocks 702, 704, 706, and 708 as seen in process flow 700. After block 708, in block 760, a spacer is attached to the reverse freewheeling diode die. The spacer may be selected from known spacer materials for IGBT modules. The spacer thickness may be selected to provide adequate isolation.
[0048] Following block 760, a second substrate is attached to the spacer in block 762. The second substrate may be attached to the spacer on a second side of the spacer opposite the first side of the spacer that is used to bond the reverse freewheeling diode die. Depending on the exact design requirements, the second substrate may be the same as or different from the first substrate provided in block 702.
[0049] According to variations of process flow 750, this process flow may be implemented using multiple IGBT dies and multiple reverse freewheeling diode dies, with a given IGBT die and a given reverse freewheeling diode die forming a given semiconductor die assembly, resulting in multiple freewheeling diode dies assembled between two insulator substrates.
[0050] Although the present embodiments have been disclosed with reference to particular embodiments, numerous modifications, variations, and variations to the described embodiments are possible without departing from the sphere and scope of the present disclosure, as defined in the appended claims. Accordingly, the present embodiments are not limited to the described embodiments, but may have the full scope defined by the language of the following claims and their equivalents.
Claims
1. 1. A semiconductor device module, comprising: a first substrate; a stacked semiconductor die assembly disposed on the first substrate, the stacked semiconductor die assembly comprising: an insulated gate bipolar transistor (IGBT) die including an IGBT die first side and an IGBT die second side disposed opposite the IGBT die first side, the IGBT die being bonded to the first substrate using the IGBT die first side; a freewheeling diode die including a freewheeling diode die first side and a freewheeling diode die second side disposed opposite the freewheeling diode die first side; a planar electrical connector bonded to the IGBT die using the IGBT die second side and bonded to the freewheeling diode die using the freewheeling diode die first side, the planar electrical connector being disposed between the IGBT die and the freewheeling diode die; and a spacer having a spacer first surface and a spacer second surface disposed opposite the spacer first surface, the spacer being bonded to the freewheeling diode die second surface using the spacer first surface; a second substrate bonded to the spacer using a second surface of the spacer, the spacer being disposed between the freewheeling diode die and the second substrate; Equipped with the first and second substrates and the stacked semiconductor die assembly provide double-sided cooling to at least one of the IGBT die or the freewheeling diode die to maintain a predetermined operating temperature for a current received by the semiconductor device module.
2. The semiconductor device module of claim 1 , wherein the IGBT die is directly bonded to the first substrate.
3. 3. The semiconductor device module of claim 2, wherein the IGBT die has a first area and is disposed on the first substrate in a first region, and the freewheeling diode die has a second area smaller than the first area and is disposed in the first region.
4. The semiconductor device module of claim 1 , wherein the freewheeling diode die is electrically coupled to the IGBT die as a reverse diode.
5. the stacked semiconductor die assembly is a first stacked semiconductor die assembly, and the semiconductor device module further comprises: a second stacked semiconductor die assembly disposed on the first substrate, the second stacked semiconductor die assembly comprising: a second IGBT die including a second IGBT die first side and a second IGBT die second side disposed opposite the second IGBT die first side, wherein the second IGBT die is bonded to the first substrate using the second IGBT die first side; a second freewheeling diode die including a second freewheeling diode die first face and a second freewheeling diode die second face disposed opposite the second freewheeling diode die first face; a second planar electrical connector bonded to the second IGBT die using the second IGBT die second side and bonded to the second freewheeling diode die using the second freewheeling diode die first side, the second planar electrical connector being disposed between the second IGBT die and the second freewheeling diode die; The semiconductor device module of claim 1 , comprising:
6. 6. The semiconductor device module of claim 5, wherein the first substrate is an insulating substrate, the first stacked semiconductor die assembly is disposed on the insulating substrate in a first region, the second stacked semiconductor die assembly is disposed on the first substrate in a second region not overlapping the first region, and the first stacked semiconductor die assembly is disposed on the same plane as the second stacked semiconductor die assembly.
7. the semiconductor device module further comprising at least one additional stacked semiconductor die assembly disposed on the first substrate; the at least one additional stacked semiconductor die assembly has a stacked structure of another IGBT die and another freewheeling diode die; each additional stacked semiconductor die assembly of the at least one additional semiconductor die assembly has a stacked structure of an additional IGBT die and an additional freewheeling diode die; the first substrate is configured to accommodate the stacked semiconductor die assembly in a stacked configuration within a first substrate area, and is configured to accommodate the at least one additional stacked semiconductor die assembly within a second substrate area; The semiconductor device module according to claim 1 .
8. The semiconductor device module of claim 1 , wherein the stacked semiconductor die assembly is configured to reduce temperature swings upon application of a current pulse.
9. 1. A method of forming a semiconductor device module, the method comprising: providing a first substrate; bonding a stacked semiconductor die assembly to the first substrate, the stacked semiconductor die assembly comprising: an insulated gate bipolar transistor (IGBT) die including an IGBT die first side and an IGBT die second side disposed opposite the IGBT die first side, the IGBT die being bonded to the first substrate using the IGBT die first side; a freewheeling diode die including a freewheeling diode die first side and a freewheeling diode die second side disposed opposite the freewheeling diode die first side; a planar electrical connector bonded to the IGBT die using the IGBT die second side and bonded to the freewheeling diode die using the freewheeling diode die first side, the planar electrical connector being disposed between the IGBT die and the freewheeling diode die; bonding a spacer to the freewheeling diode die second surface using a spacer first surface, the spacer including a spacer first surface and a spacer second surface disposed opposite the spacer first surface; bonding a second substrate to the spacer using the spacer second surface, the spacer being disposed between the freewheeling diode die and the second substrate; Equipped with the first and second substrates and the stacked semiconductor die assembly provide double-sided cooling to at least one of the IGBT die or the freewheeling diode die to maintain a predetermined operating temperature for a current received by the semiconductor device module.
10. The method of claim 9 , wherein the IGBT die is directly bonded to the first substrate.
11. 11. The method of claim 10, wherein the IGBT die has a first area and is disposed on the first substrate in a first region, and the freewheeling diode die has a second area smaller than the first area and is disposed in the first region.
12. 12. The method of claim 9, wherein the freewheeling diode die is electrically coupled to the IGBT die as a reverse diode.
13. the stacked semiconductor die assembly is a first stacked semiconductor die assembly, and the method further comprises: bonding a second stacked semiconductor die assembly onto the first substrate, the second stacked semiconductor die assembly comprising: a second IGBT die having a second IGBT die first side and a second IGBT die second side disposed opposite the second IGBT die first side, the second IGBT die being bonded to the first substrate using the second IGBT die first side; a second freewheeling diode die having a second freewheeling diode die first face and a second freewheeling diode die second face disposed opposite the second freewheeling diode die first face; 13. The method of claim 9, comprising: a second planar electrical connector bonded to the second IGBT die using the second side of the second IGBT die and bonded to the second freewheeling diode die using the first side of the second freewheeling diode die, the second planar electrical connector being disposed between the second IGBT die and the second freewheeling diode die.
14. 14. The method of claim 13, wherein the first substrate is an insulating substrate, the first stacked semiconductor die assembly is disposed in a first region of the insulating substrate, the second stacked semiconductor die assembly is disposed on the first substrate in a second region not overlapping the first region, and the first stacked semiconductor die assembly is disposed coplanar with the second stacked semiconductor die assembly.
15. further comprising bonding at least one additional stacked semiconductor die assembly to the first substrate, the at least one additional stacked semiconductor die assembly having a stack structure of another IGBT die and another freewheeling diode die; each additional stacked semiconductor die assembly of the at least one additional semiconductor die assembly includes a stacked structure of an additional IGBT die and an additional freewheeling diode die; 15. The method of claim 9, wherein the first substrate is configured to accommodate the stacked semiconductor die assembly in a stacked configuration within a first substrate area and to accommodate the at least one additional stacked semiconductor die assembly within a second substrate area.
16. 16. The method of claim 9, wherein the stacked semiconductor die assembly is configured to reduce temperature swings upon application of a current pulse.