Power semiconductor device

Abstract

To provide a technique capable of suppressing unbalance of a current flowing through a semiconductor element.SOLUTION: The power semiconductor device includes a plurality of power modules. The packages of the plurality of power modules have the same outer shape. The plurality of power modules include a first half-bridge module including a first semiconductor, and at least one of a second half-bridge module including a second semiconductor, a second relay module including a second semiconductor, and a second diode module including a second semiconductor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to power semiconductor devices. [Background technology]

[0002] Various technologies have been proposed for power semiconductor devices. For example, Patent Document 1 proposes a power semiconductor device in which a semiconductor switching element made of silicon (Si) and a semiconductor switching element made of wide bandgap (WBG) semiconductor are connected in parallel within a single power module. Such a power semiconductor device can reduce power loss and costs. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-125806 Summary of the Invention [Problem to be solved by the invention]

[0004] However, with the configuration described in Patent Document 1, there is a problem in that the imbalance in the currents flowing through the semiconductor elements becomes relatively large due to differences in the materials of the semiconductor elements and differences in the current paths of the semiconductor elements. While this imbalance can be suppressed by adjusting the drive timing of each semiconductor element, making such adjustments creates another problem in that the design becomes complicated.

[0005] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and aims to provide a technique capable of suppressing imbalance in current flowing through a semiconductor element. [Means for solving the problem]

[0006] A power semiconductor device according to the present disclosure includes a plurality of power modules, each including a semiconductor element, a package that is rectangular in a plan view and covers the semiconductor element, and a power terminal electrically connected to the semiconductor element, wherein the packages of the plurality of power modules have the same outer shape, and the plurality of power modules include a first half-bridge module, the semiconductor element of which is a first semiconductor that is one of Si and a wide bandgap semiconductor, a second half-bridge module, the semiconductor element of which is a second semiconductor that is the other of Si and a wide bandgap semiconductor, and connected in parallel with the first half-bridge module, a second relay module, the second semiconductor, and the second relay module, the second relay module, and the and at least one of a first relay module and a second diode module electrically connected to the first half-bridge module, wherein in each of the first half-bridge module and the second half-bridge module, the semiconductor elements include two semiconductor switching elements connected in series, and the power terminals are provided on both short sides of the package; in the second relay module, the semiconductor elements include two semiconductor switching elements connected in anti-series, and the power terminals are provided on one or both short sides of the package; and in the second diode module, the semiconductor elements include two diodes connected in series, and the power terminals are provided on both short sides of the package. [Effects of the Invention]

[0007] According to the present disclosure, the packages of the power modules have the same outer shape, and this configuration can suppress imbalances in the currents flowing through the semiconductor elements. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a plan view showing a configuration of a power semiconductor device according to a first embodiment. [Figure 2] 1 is an equivalent circuit diagram showing a configuration of a power semiconductor device according to a first embodiment. [Figure 3] 1A and 1B are a plan view and a side view showing the appearance of a half-bridge module according to a first embodiment. [Figure 4] 3(a) and 3(b) are equivalent circuit diagrams showing the configuration of a half-bridge module according to the first embodiment. [Figure 5] FIG. 10 is a plan view showing the configuration of a power semiconductor device according to a second embodiment. [Figure 6] FIG. 10 is an equivalent circuit diagram showing a configuration of a power semiconductor device according to a second embodiment. [Figure 7] 10A and 10B are a plan view and a side view showing the appearance of a relay module according to a second embodiment. [Figure 8] 10(a) and 10(b) are equivalent circuit diagrams showing the configuration of a relay module according to a second embodiment. [Figure 9] FIG. 11 is a plan view showing a configuration of a power semiconductor device according to a third embodiment. [Figure 10] FIG. 10 is an equivalent circuit diagram showing a configuration of a power semiconductor device according to a third embodiment. [Figure 11] 11A and 11B are a plan view and a side view showing the appearance of a relay module according to a third embodiment. [Figure 12] 10(a) and 10(b) are equivalent circuit diagrams showing the configuration of a relay module according to a third embodiment. [Figure 13] FIG. 10 is a plan view showing the configuration of a power semiconductor device according to a fourth embodiment. [Figure 14] FIG. 10 is an equivalent circuit diagram showing a configuration of a power semiconductor device according to a fourth embodiment. [Figure 15] 10A and 10B are a plan view and a side view showing the appearance of a diode module according to a fourth embodiment. [Figure 16] 10(a) and 10(b) are equivalent circuit diagrams showing the configuration of a diode module according to a fourth embodiment. [Figure 17] FIG. 10 is a plan view showing the configuration of a power semiconductor device according to a fifth embodiment. [Figure 18] FIG. 10 is an equivalent circuit diagram showing a configuration of a power semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the accompanying drawings. Features described in each of the following embodiments are exemplary, and not all features are necessarily required. In addition, in the following description, similar components in multiple embodiments are denoted by the same or similar reference numerals, and different components will be mainly described. In addition, in the following description, specific positions and directions such as "upper," "lower," "left," "right," "front," or "back" may not necessarily correspond to positions and directions in actual implementation.

[0010] <First Embodiment> Fig. 1 is a plan view (top view) showing the configuration of a power semiconductor device according to the present embodiment 1, and Fig. 2 is an equivalent circuit diagram of the configuration of Fig. 1. The power semiconductor device according to the present embodiment 1 includes a plurality of power modules. The plurality of power modules according to the present embodiment 1 includes a first half-bridge module made up of a first semiconductor and a second half-bridge module made up of a second semiconductor.

[0011] In the following, a case where the first semiconductor and the second semiconductor are silicon carbide (SiC) and silicon (Si), respectively, will be described. A case where the SiC half-bridge modules 1a, 1b, and 1c of FIG. 1 are provided as the first half-bridge module, and the Si half-bridge modules 2a, 2b, and 2c of FIG. 1 are provided as the second half-bridge module will be described. However, the first semiconductor and the second semiconductor may be Si and SiC, respectively, as opposed to the above, or other wide bandgap semiconductors (e.g., gallium nitride (GaN), gallium oxide (Ga2O3), diamond, etc.) may be used instead of SiC. The above also applies to power modules other than half-bridge modules.

[0012] In the following description, the SiC half-bridge modules 1a, 1b, and 1c may be referred to as SiC half-bridge module 1 without distinction, and the Si half-bridge modules 2a, 2b, and 2c may be referred to as Si half-bridge module 2 without distinction. In the following description, the SiC half-bridge module 1 and the Si half-bridge module 2 may be referred to as half-bridge modules without distinction. In the following description, the number of SiC half-bridge modules 1 and Si half-bridge modules 2 is three, but this is not limited to three.

[0013] 3 is a plan view (top view) and a side view showing the appearance of the half-bridge module, and FIGS. 4(a) and 4(b) are equivalent circuit diagrams of the SiC half-bridge module 1 and the Si half-bridge module 2, respectively. The configurations of the SiC half-bridge module 1 and the Si half-bridge module 2 will be described below.

[0014] <SiCハーフブリッジモジュール1> 3 and 4(a), the SiC half-bridge module 1 includes MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) 11 and 12, which are semiconductor elements, a package 13, power terminals 14, 15, and 16, and a control terminal 17. The two sets of control terminals 17 in FIG. 3 correspond to the two control terminals 17 in FIG. 4(a), and the same applies to the other control terminals.

[0015] The MOSFETs 11 and 12 are two semiconductor switching elements connected in series. In the first embodiment, the two semiconductor switching elements of the SiC half-bridge module 1 are Nch MOSFETs, but may be, for example, Pch MOSFETs, IGBTs (Insulated Gate Bipolar Transistors), HEMTs (High Electron Mobility Transistors), or RC-IGBTs (Reverse Conducting IGBTs).

[0016] Package 13 in Fig. 3 is a resin package that covers MOSFETs 11 and 12 and has a rectangular shape in a plan view. Power terminals 14 and 16 are DC input terminals (P terminal and N terminal) provided on one short side of package 13, and power terminal 15 is an AC output terminal provided on the other short side of package 13. In Fig. 3, one of two sets of control terminals 17 is provided on one short side of package 13, and the other of the two sets of control terminals 17 is provided on the other short side of package 13. However, the positions and pin assignments of the two sets of control terminals 17 are not limited to those shown in Fig. 3.

[0017] As shown in FIG. 4(a), power terminal 14, which is a P terminal, is electrically connected to the drain of MOSFET 11. The source of MOSFET 11 and the drain of MOSFET 12 are electrically connected, and MOSFETs 11 and 12 are connected in series. Power terminal 15, which is an AC output terminal, is electrically connected to the source of MOSFET 11 and the drain of MOSFET 12. Power terminal 16, which is an N terminal, is electrically connected to the source of MOSFET 12. Two control terminals 17 are electrically connected to the gates of MOSFETs 11 and 12, respectively.

[0018] <Siハーフブリッジモジュール2> As shown in FIGS. 3 and 4(b), the Si half-bridge module 2 includes IGBTs 21 and 22 which are semiconductor elements, a package 23, power terminals 24, 25, and 26, a control terminal 27, and diodes 28 and 29.

[0019] The IGBTs 21 and 22 are two semiconductor switching elements connected in series. In the first embodiment, the two semiconductor switching elements of the Si half-bridge module 2 are IGBTs, but may be, for example, MOSFETs, HEMTs, or RC-IGBTs.

[0020] 3 is a resin package that covers the IGBTs 21 and 22 and has a rectangular shape in a plan view. The packages 13 of the SiC half-bridge modules 1a, 1b, and 1c and the packages 23 of the Si half-bridge modules 2a, 2b, and 2c have the same outer shape. The packages having the same outer shape include packages that differ by, for example, 5% or less.

[0021] The power terminals 24 and 26 are DC input terminals (P terminal and N terminal) provided on one short side of the package 23, and the power terminal 25 is an AC output terminal provided on the other short side of the package 23. In Fig. 3, one of the two sets of control terminals 27 is provided on one short side of the package 23, and the other of the two sets of control terminals 27 is provided on the other short side of the package 23. However, the positions and pin assignments of the two sets of control terminals 27 are not limited to those shown in Fig. 3.

[0022] As shown in FIG. 4(b), a power terminal 24, which is a P terminal, is electrically connected to the collector of the IGBT 21. The emitter of the IGBT 21 and the collector of the IGBT 22 are electrically connected, and the IGBTs 21 and 22 are connected in series. A power terminal 25, which is an AC output terminal, is electrically connected to the emitter of the IGBT 21 and the collector of the IGBT 22. A power terminal 26, which is an N terminal, is electrically connected to the emitter of the IGBT 22. Two control terminals 27 are electrically connected to the gates of the IGBTs 21 and 22, respectively. A diode 28 is connected in anti-parallel to the IGBT 21, and a diode 29 is connected in anti-parallel to the IGBT 22.

[0023] <Overall structure> The power semiconductor device shown in FIGS. 1 and 2 includes not only a half-bridge module but also a DC link capacitor 81, a P bus bar 86, AC bus bars 87a, 87b, 87c, and an N bus bar 88.

[0024] The power terminal 14, which is the P terminal of the SiC half-bridge modules 1a, 1b, and 1c, the power terminal 24, which is the P terminal of the Si half-bridge modules 2a, 2b, and 2c, and one end of the DC link capacitor 81 are electrically connected by a P bus bar 86.

[0025] The power terminal 16, which is the N terminal of the SiC half-bridge modules 1a, 1b, and 1c, the power terminal 26, which is the N terminal of the Si half-bridge modules 2a, 2b, and 2c, and the other end of the DC link capacitor 81 are electrically connected by an N bus bar 88.

[0026] Power terminals 15, which are AC output terminals of the SiC half-bridge modules 1a, 1b, and 1c, and power terminals 25, which are AC output terminals of the Si half-bridge modules 2a, 2b, and 2c, are electrically connected by AC bus bars 87a, 87b, and 87c, respectively.

[0027] As described above, in the first embodiment, the SiC half-bridge modules 1a, 1b, and 1c, the Si half-bridge modules 2a, 2b, and 2c, and the DC link capacitor 81 are connected in parallel, thereby realizing a three-phase inverter.

[0028] <Summary of the First Embodiment> The SiC half-bridge module 1 can reduce power loss in the small current range, but increases power loss in the large current range and is expensive. On the other hand, the Si half-bridge module 2 can reduce power loss in the large current range and is inexpensive, but increases power loss in the small current range. In contrast, the power semiconductor device according to the first embodiment includes the SiC half-bridge module 1 and the Si half-bridge module 2, and therefore can appropriately reduce power loss and costs.

[0029] Furthermore, in the first embodiment, the package 13 of the SiC half-bridge module 1 and the package 23 of the Si half-bridge module 2 have the same outer shape. This allows the inductances of the current paths of the SiC half-bridge module 1 and the Si half-bridge module 2 to be approximately equal, thereby suppressing imbalances in currents flowing through the semiconductor elements of the half-bridge modules connected in parallel.

[0030] Furthermore, by providing the power terminals 14 to 16 and 24 to 26 on the short sides of the packages 13 and 23, it is possible to shorten the bus bars connecting the half-bridge modules, which is expected to reduce the inductance between the half-bridge modules and make the power semiconductor device more compact.

[0031] Furthermore, because one package (one power module) realizes one function, a half-bridge, it is possible to perform optimal control for each power module. Furthermore, because power modules are easy to connect, it is easy to change the number of connected power modules depending on, for example, the power capacity.

[0032] <Embodiment 2> Fig. 5 is a plan view (top view) showing the configuration of a power semiconductor device according to the second embodiment, and Fig. 6 is an equivalent circuit diagram of the configuration of Fig. 5. The power semiconductor device according to the second embodiment includes a plurality of power modules. The plurality of power modules according to the second embodiment include a SiC half-bridge module 1, a Si half-bridge module 2, a SiC relay module 3 (3a, 3b) made of SiC, and a Si relay module 4 (4a, 4b) made of Si. In the following description, the SiC relay module 3 and the Si relay module 4 may be referred to as relay modules without distinction.

[0033] 7 is a plan view (top view) and a side view showing the appearance of the relay module, and Fig. 8(a) and Fig. 8(b) are equivalent circuit diagrams of the SiC relay module 3 and the Si relay module 4, respectively. The configurations of the SiC relay module 3 and the Si relay module 4 will be described below.

[0034] <SiCリレーモジュール3> As shown in FIGS. 7 and 8(a), the bidirectional SiC relay module 3 includes MOSFETs 31 and 32 which are semiconductor elements, a package 33, power terminals 34 and 36, and a control terminal 37.

[0035] The MOSFETs 31 and 32 are two semiconductor switching elements connected in anti-series. In the second embodiment, the two semiconductor switching elements of the SiC relay module 3 are Nch MOSFETs, but may be, for example, Pch MOSFETs, IGBTs, HEMTs, or RC-IGBTs.

[0036] 7 is a resin package that covers the MOSFETs 31 and 32 and has a rectangular shape in a plan view. The power terminals 34 and 36 are a T1 terminal and a T2 terminal provided on one short side of the package 33. In FIG. 7, one of the two sets of control terminals 37 is provided on one short side of the package 33, and the other of the two sets of control terminals 37 is provided on the other short side of the package 33, but the positions and pin assignments of the two sets of control terminals 37 are not limited to those shown in FIG. 7.

[0037] As shown in FIG. 8(a), a power terminal 34, which is a T1 terminal, is electrically connected to the drain of MOSFET 31. The sources of MOSFETs 31 and 32 are electrically connected to each other, and MOSFETs 31 and 32 are connected in anti-series. A power terminal 36, which is a T2 terminal, is electrically connected to the drain of MOSFET 32. Two control terminals 37 are electrically connected to the gates of MOSFETs 31 and 32, respectively. Note that, although the sources of MOSFETs 31 and 32 are electrically connected to each other in FIG. 8(a), the drains of MOSFETs 31 and 32 may be electrically connected to each other instead of the sources.

[0038] <Siリレーモジュール4> As shown in FIGS. 7 and 8(b), the bidirectional Si relay module 4 includes IGBTs 41 and 42 which are semiconductor elements, a package 43, power terminals 44 and 46, a control terminal 47, and diodes 48 and 49.

[0039] The IGBTs 41 and 42 are two semiconductor switching elements connected in anti-series. In the second embodiment, the two semiconductor switching elements of the Si relay module 4 are IGBTs, but may be, for example, MOSFETs, HEMTs, or RC-IGBTs.

[0040] 7 is a resin package having a rectangular shape in a plan view and covering the IGBTs 41 and 42. The package 13 of the SiC half-bridge module 1, the package 23 of the Si half-bridge module 2, the package 33 of the SiC relay modules 3a and 3b, and the package 43 of the Si relay modules 4a and 4b all have the same external shape.

[0041] The power terminals 44, 46 are a T1 terminal and a T2 terminal provided on one short side of the package 43. In Fig. 7, one of the two sets of control terminals 47 is provided on one short side of the package 43, and the other of the two sets of control terminals 47 is provided on the other short side of the package 43, but the positions and pin assignments of the two sets of control terminals 47 are not limited to those shown in Fig. 7.

[0042] As shown in FIG. 8(b), a power terminal 44, which is a T1 terminal, is electrically connected to the collector of the IGBT 41. The emitters of the IGBTs 41 and 42 are electrically connected to each other, and the IGBTs 41 and 42 are connected in anti-series. A power terminal 46, which is a T2 terminal, is electrically connected to the collector of the IGBT 42. Two control terminals 47 are electrically connected to the gates of the IGBTs 41 and 42, respectively. A diode 48 is connected in anti-parallel to the IGBT 41, and a diode 49 is connected in anti-parallel to the IGBT 42. Note that, although the emitters of the IGBTs 41 and 42 are electrically connected to each other in FIG. 8(b), the collectors of the IGBTs 41 and 42 may be electrically connected to each other instead of the emitters.

[0043] <Overall structure> The power semiconductor device shown in Figures 5 and 6 includes not only a half-bridge module and a relay module, but also a DC link capacitor 81, P bus bars 86a, 86b, an AC bus bar 87, N bus bars 88a, 88b, and a DC power supply 89 as a power source.

[0044] The power terminal 14 of the SiC half-bridge module 1, the power terminal 24 of the Si half-bridge module 2, the power terminal 36 of the SiC relay module 3a, the power terminal 46 of the Si relay module 4a, and one end of the DC link capacitor 81 are electrically connected by a P bus bar 86a. The power terminal 34 of the SiC relay module 3a, the power terminal 44 of the Si relay module 4a, and the positive pole of the DC power supply 89 are electrically connected by a P bus bar 86b. This makes it possible to switch between connection and disconnection between the P bus and the DC power supply 89 by the SiC relay module 3a and the Si relay module 4a.

[0045] The power terminal 16 of the SiC half-bridge module 1, the power terminal 26 of the Si half-bridge module 2, the power terminal 34 of the SiC relay module 3b, the power terminal 44 of the Si relay module 4b, and the other end of the DC link capacitor 81 are electrically connected by an N bus bar 88a. The power terminal 36 of the SiC relay module 3b, the power terminal 46 of the Si relay module 4b, and the negative pole of the DC power supply 89 are electrically connected by an N bus bar 88b. This makes it possible to switch between connection and disconnection between the N bus and the DC power supply 89 by the SiC relay module 3b and the Si relay module 4b.

[0046] The power terminals 15 of the SiC half-bridge module 1 and the power terminals 25 of the Si half-bridge module 2 are electrically connected by an AC bus bar 87 .

[0047] As described above, in the second embodiment, the SiC relay modules 3a and 3b and the Si relay modules 4a and 4b are electrically and selectively connected between the PN buses of the SiC half-bridge module 1 and the Si half-bridge module 2 and the DC power supply 89. This realizes an inverter having a function of switching between connection and disconnection with the DC power supply 89.

[0048] <Summary of the second embodiment> The power semiconductor device according to the second embodiment includes a SiC relay module 4 for a SiC half-bridge module 1, and a SiC relay module 3 for a Si half-bridge module 2, and therefore can appropriately reduce power loss and costs.

[0049] In addition, in the present embodiment 2, the package 13 of the SiC half-bridge module 1, the package 23 of the Si half-bridge module 2, the package 33 of the SiC relay modules 3a and 3b, and the package 43 of the Si relay modules 4a and 4b have the same external shape. Therefore, the inductance of the current path of the power module made of SiC and the current path of the power module made of Si can be made approximately equal, so that imbalance of the current flowing through the semiconductor elements of each power module can be suppressed.

[0050] Furthermore, in the second embodiment, the power terminals are provided on the short sides of the package, which allows the bus bars connecting the power modules to be shorter, which is expected to reduce the inductance between the power modules and make the power semiconductor device more compact.

[0051] <Modification> When the first half-bridge module is a SiC half-bridge module 1, the second half-bridge module is a Si half-bridge module 2, the second relay module is a Si relay module 4, and the third relay module is a SiC relay module 3. On the other hand, when the first half-bridge module is a Si half-bridge module 2, the second half-bridge module is a SiC half-bridge module 1, the second relay module is a SiC relay module 3, and the third relay module is a Si relay module 4.

[0052] The multiple power modules according to the second embodiment may be configured to include one or more first half-bridge modules and one or more second relay modules. At least one of one or more second half-bridge modules and one or more third relay modules may be added to this configuration as appropriate. In this specification, for example, "at least one of A, B, C, ..., and Z" means any one of all combinations of one or more types selected from the group A, B, C, ..., and Z.

[0053] <Third Embodiment> Fig. 9 is a plan view (top view) showing the configuration of a power semiconductor device according to the third embodiment, and Fig. 10 is an equivalent circuit diagram of the configuration of Fig. 9. The power semiconductor device according to the third embodiment includes a plurality of power modules. The plurality of power modules according to the third embodiment includes a SiC half-bridge module 1, a SiC relay module 3, and a Si relay module 4.

[0054] 11 is a plan view (top view) and a side view showing the appearance of the relay module, and FIGS. 12(a) and 12(b) are equivalent circuit diagrams of the SiC relay module 3 and the Si relay module 4, respectively. The SiC relay module 3 according to the third embodiment is similar to the SiC relay module 3 according to the second embodiment except that the power terminals 34 and 36 are the T1 terminal and the T2 terminal provided on the two short sides of the package 33, respectively. The Si relay module 4 according to the third embodiment is similar to the Si relay module 4 according to the second embodiment except that the power terminals 44 and 46 are the T1 terminal and the T2 terminal provided on the two short sides of the package 43, respectively.

[0055] <Overall structure> The power semiconductor device shown in Figures 9 and 10 includes not only a half-bridge module and a relay module, but also DC link capacitors 81a, 81b, a P bus bar 86, an AC bus bar 87, an N bus bar 88, a DC power supply 89, and a U bus bar 90.

[0056] The power terminal 14 of the SiC half-bridge module 1, one end of the DC link capacitor 81a, and the positive pole of the DC power supply 89 are electrically connected by a P bus bar 86. The power terminal 16 of the SiC half-bridge module 1, one end of the DC link capacitor 81b, and the negative pole of the DC power supply 89 are electrically connected by an N bus bar 88.

[0057] The power terminal 15 of the SiC half-bridge module 1, the power terminal 36 of the SiC relay module 3, and the power terminal 46 of the Si relay module 4 are electrically connected by an AC bus bar 87. The connection point between the other ends of the DC link capacitors 81a and 81b, which has the intermediate potential of the DC power supply 89, the power terminal 34 of the SiC relay module 3, and the power terminal 44 of the Si relay module 4 are electrically connected by a U bus bar 90.

[0058] As described above, in the third embodiment, the SiC relay module 3 and the Si relay module 4 are electrically connected between the power terminal 15, which is the output terminal of the SiC half-bridge module 1, and the intermediate potential of the DC power supply 89. This realizes a three-level inverter.

[0059] <Summary of the Third Embodiment> The power semiconductor device according to the third embodiment can appropriately reduce power loss and costs because it includes the Si relay module 4 for the SiC half-bridge module 1. As in the second embodiment, it is possible to suppress imbalance in current flowing through the semiconductor elements of each power module, and it is expected to reduce inductance between power modules and achieve miniaturization of the power semiconductor device.

[0060] <Modification> The power modules according to the third embodiment may include one or more first half-bridge modules and one or more second relay modules. At least one of one or more second half-bridge modules and one or more third relay modules may be added to this configuration as appropriate.

[0061] <Fourth Embodiment> Fig. 13 is a plan view (top view) showing the configuration of a power semiconductor device according to the fourth embodiment, and Fig. 14 is an equivalent circuit diagram of the configuration of Fig. 13. The power semiconductor device according to the fourth embodiment includes a plurality of power modules. The plurality of power modules according to the fourth embodiment include a SiC half-bridge module 1 (1a, 1b), a SiC diode module 5 made of SiC, and a Si diode module 6 made of Si. In the following description, the SiC diode module 5 and the Si diode module 6 may be referred to as diode modules without distinction.

[0062] Fig. 15 is a plan view (top view) and a side view showing the appearance of the diode module, and Fig. 16(a) and Fig. 16(b) are equivalent circuit diagrams of the SiC diode module 5 and the Si diode module 6, respectively. The configurations of the SiC diode module 5 and the Si diode module 6 will be described below.

[0063] <SiCダイオードモジュール5> As shown in FIGS. 15 and 16(a), the SiC diode module 5 includes SiC diodes 51 and 52 which are semiconductor elements, a package 53, and power terminals 54, 55, and 56.

[0064] SiC diodes 51 and 52 are two diodes connected in series. Package 53 in Fig. 15 is a resin package that covers SiC diodes 51 and 52 and has a rectangular shape in a plan view. Power terminals 54 and 56 are a P terminal and an N terminal provided on one short side of package 53, and power terminal 55 is an AC terminal provided on the other short side of package 53.

[0065] 16(a), a power terminal 54, which is a P terminal, is electrically connected to the cathode of the SiC diode 51. The anode of the SiC diode 51 and the cathode of the SiC diode 52 are electrically connected, and the SiC diodes 51 and 52 are connected in series. A power terminal 55, which is an AC terminal, is electrically connected to the anode of the SiC diode 51 and the cathode of the SiC diode 52. A power terminal 56, which is an N terminal, is electrically connected to the anode of the SiC diode 52.

[0066] <Siダイオードモジュール6> As shown in FIGS. 15 and 16(b), the Si diode module 6 includes Si diodes 61 and 62 which are semiconductor elements, a package 63, and power terminals 64, 65, and 66.

[0067] The Si diodes 61 and 62 are diodes connected in series. The package 63 in Fig. 15 is a resin package that covers the Si diodes 61 and 62 and has a rectangular shape in a plan view. The packages 13 of the SiC half-bridge modules 1a and 1b, the package 53 of the SiC diode module 5, and the package 63 of the Si diode module 6 have the same external shape. The power terminals 64 and 66 are a P terminal and an N terminal provided on one short side of the package 63, and the power terminal 65 is an AC terminal provided on the other short side of the package 63.

[0068] 16(b), a power terminal 64, which is a P terminal, is electrically connected to the cathode of the Si diode 61. The anode of the Si diode 61 and the cathode of the Si diode 62 are electrically connected, and the Si diodes 61 and 62 are connected in series. A power terminal 65, which is an AC terminal, is electrically connected to the anode of the Si diode 61 and the cathode of the Si diode 62. A power terminal 66, which is an N terminal, is electrically connected to the anode of the Si diode 62.

[0069] <Overall structure> The power semiconductor device shown in Figures 13 and 14 includes not only a half-bridge module and a diode module, but also DC link capacitors 81a, 81b, a P bus bar 86, an N bus bar 88, a DC power supply 89, a U bus bar 90, bus bars 91a, 91b, and an output bus bar 92.

[0070] The power terminal 14 of the SiC half-bridge module 1a, one end of the DC link capacitor 81a, and the positive pole of the DC power supply 89 are electrically connected by a P bus bar 86. The power terminal 16 of the SiC half-bridge module 1b, one end of the DC link capacitor 81b, and the negative pole of the DC power supply 89 are electrically connected by an N bus bar 88. The power terminal 16 of the SiC half-bridge module 1a and the power terminal 14 of the SiC half-bridge module 1b are electrically connected by an output bus bar 92.

[0071] The power terminal 54 of the SiC diode module 5, the power terminal 64 of the Si diode module 6, and the power terminal 15 of the SiC half-bridge module 1a are electrically connected by a bus bar 91a. The power terminal 56 of the SiC diode module 5, the power terminal 66 of the Si diode module 6, and the power terminal 15 of the SiC half-bridge module 1b are electrically connected by a bus bar 91b. The connection point between the other ends of the DC link capacitors 81a and 81b, which has the intermediate potential of the DC power supply 89, is electrically connected to the power terminal 55 of the SiC diode module 5 and the power terminal 65 of the Si diode module 6 by a U-bus bar 90.

[0072] As described above, in the fourth embodiment, the SiC diode module 5 and the Si diode module 6 are electrically and selectively connected between the connection point between the MOSFETs 11, 12 and the IGBTs 21, 22 included in the SiC half-bridge modules 1a, 1b and the intermediate potential of the DC power supply 89. This realizes an NPC type three-level inverter.

[0073] <Summary of the Fourth Embodiment> The power semiconductor device according to the fourth embodiment can appropriately reduce power loss and costs because it includes the Si diode module 6 for the SiC half-bridge module 1. As in the second embodiment, it is possible to suppress imbalance in current flowing through the semiconductor elements of each power module, and it is expected to reduce inductance between power modules and achieve miniaturization of the power semiconductor device.

[0074] <Modification> In the fourth embodiment, the first half-bridge module is a SiC half-bridge module 1, the second diode module is a Si diode module 6, and the third diode module is a SiC diode module 5, but the present invention is not limited to this.

[0075] The power modules according to the fourth embodiment may be configured to include one or more first half-bridge modules and one or more second diode modules. At least one of one or more second half-bridge modules and one or more third diode modules may be added to this configuration as appropriate.

[0076] Furthermore, by combining the first to fourth embodiments, the plurality of power modules may include at least one of one or more second half-bridge modules, one or more second relay modules, and one or more second diode modules, and one or more first half-bridge modules. At least one of one or more third relay modules and one or more third diode modules may be added to this configuration as appropriate.

[0077] <Fifth Embodiment> Fig. 17 is a plan view (top view) showing the configuration of the power semiconductor device according to the fifth embodiment, and Fig. 18 is an equivalent circuit diagram of the configuration of Fig. 17. Note that in Fig. 18, the front side portions of the packages 13 and 23 of the SiC half-bridge module 1 and the Si half-bridge module 2 are not shown.

[0078] In the SiC half-bridge module 1, a frame 71, part of which is used as a power terminal, is selectively connected to the MOSFETs 11 and 12 and a metal pattern 72 via bonding regions 73. Wires 74 are connected between the MOSFETs 11 and 12 and two sets of control terminals 17.

[0079] In the Si half-bridge module 2, a frame 75, part of which is used as a power terminal, is selectively connected to the IGBTs 21 and 22 and a metal pattern 76 via bonding regions 77. Wires 78 are connected between the IGBTs 21 and 22 and two sets of control terminals 27.

[0080] 17, notches 79 are selectively provided in the path portions of the main current in the plurality of power modules. In the example of Fig. 17, notches 79 are provided in the frame 71 and the metal pattern 72, which are the path portions of the main current in the SiC half-bridge module 1.

[0081] <Summary of the Fifth Embodiment> In the first to fourth embodiments, the current imbalance is suppressed by making the inductances of the current paths approximately equal, that is, by making L1=L5, L2=L6, L3=L7, and L4=L8 in Fig. 18. However, depending on the characteristics of the elements, simply making the inductances of the current paths approximately equal may not be enough to suppress the current imbalance.

[0082] In contrast to this, in the power semiconductor device according to the fifth embodiment, the inductance of the path portion of the main current can be adjusted by the notch 79. Therefore, it is possible to suppress the imbalance of the current when power modules made up of different elements are driven in parallel.

[0083] For example, consider a case where the switching speed of the SiC half-bridge module 1 is high and it switches earlier than the Si half-bridge module 2. In such a case, a notch may be provided in the main current path of the SiC half-bridge module 1 without providing a notch in the main current path of the Si half-bridge module 2. With this configuration, the inductance of the SiC half-bridge module 1 can be increased, thereby suppressing imbalances in the currents flowing through the semiconductor elements.

[0084] In this disclosure in English, 'a' and 'an' mean one or more. Therefore, 'a', 'an', 'one or more' and 'at least one' can be used interchangeably.

[0085] It should be noted that the embodiments and modifications may be freely combined, and the embodiments and modifications may be modified or omitted as appropriate.

[0086] Various aspects of the present disclosure are summarized below as appendices.

[0087] (Appendix 1) a plurality of power modules each including a semiconductor element, a package that is rectangular in plan view and covers the semiconductor element, and a power terminal electrically connected to the semiconductor element; The packages of the plurality of power modules have the same outer shape, The plurality of power modules include: a first half-bridge module including a first semiconductor element that is one of Si and a wide bandgap semiconductor; the semiconductor element is made of a second semiconductor which is the other of Si and a wide band gap semiconductor, and at least one of a second half-bridge module connected in parallel with the first half-bridge module, a second relay module made of the second semiconductor and electrically connected to the first half-bridge module, and a second diode module made of the second semiconductor and electrically connected to the first half-bridge module; Including, In each of the first half-bridge module and the second half-bridge module, the semiconductor device includes two semiconductor switching devices connected in series, and the power terminals are provided on both short sides of the package; In the second relay module, the semiconductor device includes two semiconductor switching devices connected in anti-series, and the power terminals are provided on one or both short sides of the package; In the second diode module, the semiconductor element includes two diodes connected in series, and the power terminals are provided on both short sides of the package.

[0088] (Appendix 2) 10. The power semiconductor device according to claim 1, The plurality of power modules includes the second half-bridge module.

[0089] (Appendix 3) 10. The power semiconductor device according to claim 1, The power semiconductor device, wherein the plurality of power modules includes the second relay module.

[0090] (Appendix 4) 4. The power semiconductor device according to claim 3, The second relay module is a power semiconductor device electrically connected between a P bus or an N bus of the first half-bridge module and a power source.

[0091] (Appendix 5) The power semiconductor device according to claim 3 or 4, The second relay module is electrically connected between the output terminal of the first half-bridge module and an intermediate potential of a power supply.

[0092] (Appendix 6) The power semiconductor device according to any one of Supplementary Note 3 to Supplementary Note 5, The plurality of power modules include: a third relay module including the first semiconductor and connected in parallel with the second relay module; In the third relay module, the semiconductor element includes two semiconductor switching elements connected in anti-series, and the power terminals are provided on one or both short sides of the package.

[0093] (Appendix 7) 10. The power semiconductor device according to claim 1, The power semiconductor device, wherein the plurality of power modules includes the second diode module.

[0094] (Appendix 8) 8. The power semiconductor device according to claim 7, The power semiconductor device wherein the second diode module is electrically connected between a connection point between the two semiconductor switching elements included in the first half-bridge module and an intermediate potential of a power supply, thereby realizing an NPC type three-level inverter.

[0095] (Appendix 9) The power semiconductor device according to claim 7 or 8, The plurality of power modules include: a third diode module made of the first semiconductor and connected in parallel with the second diode module; In the third diode module, the semiconductor element includes two diodes connected in series, and the power terminals are provided on both short sides of the package.

[0096] (Appendix 10) A power semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 9, A power semiconductor device, wherein a notch is selectively provided in a path portion of a main current in the plurality of power modules. [Explanation of symbols]

[0097] 1,1a,1b,1c SiC half-bridge module, 2,2a,2b,2c Si half-bridge module, 3,3a,3b SiC relay module, 4,4a,4b Si relay module, 5 SiC diode module, 6 Si diode module, 11,12,31,32 MOSFET, 13,23,33,43,53,63 Package, 14,15,16,24,25,26,34,36,44,46,54,55,56,64,65,66 Power terminal, 21,22,41,42 IGBT, 51,52 SiC diode, 61,62 Si diode, 79 Notch, 89 DC power supply.

Claims

1. a plurality of power modules each including a semiconductor element, a package that is rectangular in plan view and covers the semiconductor element, and a power terminal electrically connected to the semiconductor element; The packages of the plurality of power modules have the same outer shape, The plurality of power modules include: a first half-bridge module including a first semiconductor element that is one of Si and a wide bandgap semiconductor; the semiconductor element is made of a second semiconductor which is the other of Si and a wide band gap semiconductor, and at least one of a second half bridge module connected in parallel with the first half bridge module, a second relay module made of the second semiconductor and electrically connected to the first half bridge module, and a second diode module made of the second semiconductor and electrically connected to the first half bridge module; Including, In each of the first half-bridge module and the second half-bridge module, the semiconductor device includes two semiconductor switching devices connected in series, and the power terminals are provided on both short sides of the package; In the second relay module, the semiconductor device includes two semiconductor switching devices connected in anti-series, and the power terminals are provided on one or both short sides of the package; In the second diode module, the semiconductor element includes two diodes connected in series, and the power terminals are provided on both short sides of the package.

2. 2. The power semiconductor device according to claim 1, The power semiconductor device, wherein the plurality of power modules includes the second half-bridge module.

3. 2. The power semiconductor device according to claim 1, The power semiconductor device, wherein the plurality of power modules includes the second relay module.

4. 4. The power semiconductor device according to claim 3, The second relay module is electrically connected between a P bus or an N bus of the first half-bridge module and a power supply.

5. 4. The power semiconductor device according to claim 3, The second relay module is electrically connected between the output terminal of the first half-bridge module and an intermediate potential of a power supply.

6. 6. The power semiconductor device according to claim 3, The plurality of power modules include: a third relay module including the first semiconductor and connected in parallel with the second relay module; In the third relay module, the semiconductor element includes two semiconductor switching elements connected in anti-series, and the power terminals are provided on one or both short sides of the package.

7. 2. The power semiconductor device according to claim 1, The power semiconductor device, wherein the plurality of power modules includes the second diode module.

8. 8. The power semiconductor device according to claim 7, a power semiconductor device in which an NPC type three-level inverter is realized by electrically connecting the second diode module between a connection point between the two semiconductor switching elements included in the first half-bridge module and an intermediate potential of a power supply.

9. 9. The power semiconductor device according to claim 7, The plurality of power modules include: a third diode module made of the first semiconductor and connected in parallel with the second diode module; In the third diode module, the semiconductor element includes two diodes connected in series, and the power terminals are provided on both short sides of the package.

10. 2. The power semiconductor device according to claim 1, A power semiconductor device, wherein a notch is selectively provided in a path portion of a main current in the plurality of power modules.

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