RC-igbt

Abstract

To suppress deterioration in electrical characteristics of a semiconductor device.SOLUTION: The RC-IGBT includes a IGBT10 layer 20 including a first surface 20S, an IGBT region 21, a diode region 22, a boundary region 23, a base region 25B provided in the IGBT region 21, an anode region 25A provided in the diode region 22, an insulating layer 30 covering the IGBT region 21 on the first surface 20S while exposing both the diode region 22 and the boundary region 23, and a first terminal layer 40 including a first terminal portion 41 provided on the insulating layer 30 in the IGBT region 21, a second terminal portion 42 provided on the first surface 20S in the diode region 22, and a third terminal portion 43 provided on the first surface 20S in the boundary region 23. The boundary region 23 includes a boundary well region 25W. The boundary well region 25W is provided apart from both the base region 25B and the anode region 25A.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a reverse conducting-insulating gate bipolar transistor (RC-IGBT). [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including an RC-IGBT. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-120990

[0004] [overview] It is desirable to suppress the degradation of the electrical characteristics of RC-IGBTs.

[0005] A semiconductor device according to one aspect of the present disclosure includes a semiconductor layer including a first surface and a drift region of a first conductivity type; an IGBT region and a diode region spaced apart in a first direction in a plan view seen from a direction perpendicular to the first surface; a boundary region provided between the IGBT region and the diode region in the first direction; a first trench provided corresponding to the IGBT region; a second trench provided corresponding to the diode region; a first trench insulating layer provided in the first trench; a second trench insulating layer provided in the second trench; a first buried electrode embedded in the first trench insulating layer in the first trench; a second buried electrode disposed on the first surface, a base region of a second conductivity type disposed in the IGBT region, an anode region of the second conductivity type disposed in the diode region, an insulating layer disposed on the first surface to cover the IGBT region while exposing both the diode region and the boundary region, and an electrode layer including: a first electrode portion disposed on the insulating layer in the IGBT region, a second electrode portion disposed on the first surface in the diode region, and a third electrode portion disposed on the first surface in the boundary region, wherein the boundary region includes a boundary well region of the second conductivity type, and the boundary well region is disposed spaced apart from both the base region and the anode region in the first direction. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view of an exemplary semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an arrangement of an IGBT region and a diode region in the semiconductor device shown in FIG. [Figure 3] FIG. 3 is a schematic plan view showing an enlarged area F3 of FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view of the semiconductor device taken along line F4-F4 in FIG. [Figure 5] FIG. 5 is a schematic cross-sectional view of the semiconductor device taken along line F5-F5 in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view illustrating the manufacturing process of an exemplary method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 16] FIG. 16 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 18] FIG. 18 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 19] FIG. 19 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. [Figure 20] FIG. 20 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 21] FIG. 21 is a schematic cross-sectional view of a portion of a semiconductor device of a comparative example. [Figure 22]FIG. 22 is a schematic cross-sectional view of an exemplary semiconductor device according to the second embodiment. [Figure 23] FIG. 23 is a schematic cross-sectional view illustrating a manufacturing process of an exemplary method for manufacturing a semiconductor device according to the second embodiment. [Figure 24] FIG. 24 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. [Figure 25] FIG. 25 is a schematic cross-sectional view of a semiconductor device according to a modified example. [Figure 26] FIG. 26 is a schematic cross-sectional view of a semiconductor device according to a modified example. [Figure 27] FIG. 27 is a schematic cross-sectional view of a semiconductor device according to a modified example.

[0007] [Detailed explanation] Hereinafter, several embodiments of the RC-IGBT (Reverse Conducting Insulated Gate Bipolar Transistor) of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] Terms such as "first," "second," and "third" are used in this disclosure merely to label and are not necessarily intended to dictate any ordering of their objects. The phrase "at least one" used in this disclosure means "one or more" of the desired options. As an example, the phrase "at least one" used in this disclosure means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" used in this disclosure means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0010] As used in this disclosure, "the dimensions (width, length) of A are equal to the dimensions (width, length) of B" or "the dimensions (width, length) of A and the dimensions (width, length) of B are equal to each other" also includes a relationship in which the difference between the dimensions (width, length) of A and the dimensions (width, length) of B is, for example, within 10% of the dimensions (width, length) of A.

[0011] First Embodiment [Overall planar structure of RC-IGBT] The planar structure of the RC-IGBT 10 according to the first embodiment will be described with reference to Figures 1 and 2. Figure 1 schematically shows the planar structure of an exemplary RC-IGBT 10 according to the first embodiment. Figure 2 schematically shows the arrangement of an IGBT region 21 and a diode region 22 (described later) in the RC-IGBT 10 shown in Figure 1.

[0012] As shown in Fig. 1, the RC-IGBT10 has a flat plate shape with the Z direction as its thickness direction. The RC-IGBT10 has a rectangular shape when viewed from the Z direction. Here, the term "plan view" used in this specification refers to viewing the RC-IGBT10 from the Z direction, unless explicitly stated otherwise. Furthermore, two directions perpendicular to the Z direction that are perpendicular to each other are referred to as the "X direction" and the "Y direction."

[0013] The RC-IGBT 10 includes, in a plan view, a cell region 11 and an outer periphery region 12 surrounding the cell region 11. The cell region 11 has a rectangular shape in a plan view. The outer periphery region 12 has a rectangular ring shape in a plan view.

[0014] The cell region 11 includes an IGBT region 21 in which an IGBT 21A (see FIG. 4) is provided, and a diode region 22 in which a diode 22A (see FIG. 4) is provided. The diode 22A may be a freewheeling diode (FWD) connected in anti-parallel to the IGBT 21A. Both the IGBT 21A and the diode 22A are provided on the same chip.

[0015] The RC-IGBT 10 includes a semiconductor layer 20. The semiconductor layer 20 may include a semiconductor substrate and an epitaxial layer. Therefore, the semiconductor layer 20 may be referred to as, for example, a "chip" or a "semiconductor chip." The semiconductor layer 20 may be made of a material containing Si. Therefore, a Si substrate may be used as the semiconductor substrate in the semiconductor layer 20. In this case, the epitaxial layer may be a Si epitaxial layer epitaxially grown on the Si substrate. The semiconductor layer 20 includes a first surface 20S and a second surface 20R (see FIG. 4) opposite to the first surface 20S.

[0016] The RC-IGBT 10 includes an insulating layer 30 and a first electrode layer 40 provided on the first surface 20S. The first electrode layer 40 can be arranged so as to overlap at least both the IGBT region 21 and the diode region 22 in a plan view. Here, the first electrode layer 40 is an example of an "electrode layer."

[0017] The insulating layer 30 may include at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and aluminum oxide (Al2O3). The insulating layer 30 may be composed of a single insulating layer or may have a stacked structure of multiple different insulating layers.

[0018] The first electrode layer 40 may include at least one of aluminum (Al), copper (Cu), an aluminum alloy, a copper alloy, tungsten (W), molybdenum (Mo), nickel (Ni), titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The first electrode layer 40 may be composed of a single metal layer or may have a stacked structure of multiple different metal layers. In the first embodiment, the first electrode layer 40 is composed of a single metal layer. In the first embodiment, the first electrode layer 40 is composed of aluminum silicon copper (AlSiCu) as an aluminum alloy. In one example, the first electrode layer 40 may have a thickness of 3 μm or more and 6 μm or less.

[0019] The first electrode layer 40 includes a first pad electrode 40P and a gate pad electrode 40G. The first pad electrode 40P and the gate pad electrode 40G are arranged spaced apart from each other in a plan view.

[0020] The first pad electrode 40P is arranged to overlap both the IGBT region 21 and the diode region 22 in a plan view. In the example shown in Fig. 1 , the first pad electrode 40P is provided to overlap the entire IGBT region 21 and the entire diode region 22. The first pad electrode 40P is provided on most of the first surface 20S of the semiconductor layer 20.

[0021] The gate pad electrode 40G is arranged in a region different from both the IGBT region 21 and the diode region 22 in a plan view. The gate pad electrode 40G is arranged at a position spaced apart from the first pad electrode 40P in the Y direction.

[0022] The RC-IGBT 10 may further include a gate wiring 50 electrically connected to the gate pad electrode 40G. The gate wiring 50 is disposed above the semiconductor layer 20 and below the first pad electrode 40P. The gate wiring 50 may be insulated from both the semiconductor layer 20 and the first pad electrode 40P by the insulating layer 30. Therefore, the gate wiring 50 can be said to be embedded in the insulating layer 30. In one example, the gate wiring 50 may be made of conductive polysilicon. In another example, the gate wiring 50 may be made of another metal material.

[0023] The gate wiring 50 may include multiple gate fingers 51. In the example of FIG. 1, the gate wiring 50 includes five gate fingers 51. Each gate finger 51 may extend in the X direction. The number of gate fingers 51 may be set appropriately depending on the desired characteristics of the RC-IGBT 10.

[0024] As shown in FIG. 2, the RC-IGBT 10 may include multiple IGBT regions 21 and multiple diode regions 22. The multiple IGBT regions 21 and the multiple diode regions 22 may be arranged in an array without overlapping each other in a plan view. The multiple IGBT regions 21 may be arranged spaced apart from each other in the X direction and the Y direction. The multiple diode regions 22 may be arranged spaced apart from each other in the X direction and the Y direction. In the example shown in FIG. 2, both the IGBT regions 21 and the diode regions 22 are rectangular in a plan view. Here, in the present disclosure, the X direction corresponds to the "first direction."

[0025] Each IGBT region 21 may be arranged adjacent to some of the multiple diode regions 22. In one example, some of the multiple IGBT regions 21 may be arranged alternately with some of the multiple diode regions 22 in the X direction. In the example of FIG. 2, four IGBT regions 21 and three diode regions 22 are arranged alternately in the X direction. A subregion 20A including such alternately arranged IGBT regions 21 and diode regions 22 may be arranged adjacent to the gate finger 51 shown in FIG. 1. The RC-IGBT 10 may include multiple subregions 20A arranged spaced apart from one another. In the example shown in FIG. 2, the multiple subregions 20A are arranged spaced apart from one another in the Y direction. The multiple subregions 20A and multiple gate fingers 51 may be arranged alternately in the Y direction. The number of IGBT regions 21 and diode regions 22 included in a subregion 20A, and the number of subregions 20A, are set appropriately depending on the desired characteristics of the RC-IGBT 10.

[0026] 2, the area of ​​the IGBT region 21 in a plan view is larger than the area of ​​the diode region 22 in a plan view. The areas of the IGBT region 21 in a plan view and the diode region 22 in a plan view are set appropriately according to the desired characteristics of the RC-IGBT 10.

[0027] In the example shown in FIG. 1 , the rectangular cell region 11 is a region including five subregions 20A arranged in the Y direction. Therefore, it can be said that a portion of the gate finger 51 is provided in the cell region 11. The rectangular annular peripheral region 12 is a region that surrounds both the five subregions 20A and a portion of the gate finger 51 in a planar view. In other words, the peripheral region 12 is a region that is located outward of at least six subregions 20A of the semiconductor layer 20 in a planar view. Therefore, it can be said that the gate pad electrode 40G is provided in the peripheral region 12. In addition, in the example shown in FIG. 1 , the first pad electrode 40P is provided throughout the entire cell region 11.

[0028] 1 and 2 for simplification, a boundary region 23 can be provided between the adjacent IGBT region 21 and diode region 22. The boundary region 23 will be described later with reference to FIGS. 3 and 4.

[0029] [Detailed structure of part of the cell area] The detailed planar structure and cross-sectional structure of a portion of the RC-IGBT 10 will be described with reference to Figures 3 and 4. Figure 3 schematically shows the planar structure by enlarging region F3 in Figure 2. Figure 4 schematically shows the cross-sectional structure of the RC-IGBT 10 taken along line F4-F4 in Figure 3.

[0030] As shown in FIG. 3 , the RC-IGBT 10 may include multiple trench structures 70 provided in the semiconductor layer 20. In the example shown in FIG. 3 , each trench structure 70 extends in the Y direction in a plan view. The multiple trench structures 70 are arranged spaced apart from one another in the X direction across the IGBT region 21, the boundary region 23, and the diode region 22. In the example shown in FIG. 3 , the pitch PT of the multiple trench structures 70 in the X direction is constant. Note that the pitch PT of the multiple trench structures 70 can be changed as desired. In one example, the pitch PT of the multiple trench structures 70 may be different in the IGBT region 21, the boundary region 23, and the diode region 22.

[0031] As shown in FIG. 4, the RC-IGBT 10 includes a first region 20P containing n-type impurities and a second region 20Q containing p-type impurities. Therefore, the first region 20P is an n-type region, and the second region 20Q is a p-type region. The second region 20Q is provided on the first region 20P. The first region 20P includes a semiconductor substrate and a portion of the epitaxial layer of the semiconductor layer 20. The second region 20Q includes the epitaxial layer of the semiconductor layer 20. In this disclosure, the n-type is also referred to as the first conductivity type, and the p-type is also referred to as the second conductivity type. The n-type impurities may be, for example, phosphorus (P) or arsenic (As). The p-type impurities may be, for example, boron (B) or aluminum (Al).

[0032] (IGBT area) In the IGBT region 21, the semiconductor layer 20 may further include an n-type emitter region 24 adjacent to the second region 20Q. The emitter region 24 includes a part of the first surface 20S of the semiconductor layer 20. That is, in the IGBT region 21, the emitter region 24 is provided in a surface layer portion closer to the first surface 20S of the semiconductor layer 20. In one example, the n-type impurity concentration of the emitter region 24 is 1×10 19 cm -3 More than 1×10 20 cm -3 It can be as follows:

[0033] In the IGBT region 21, the second region 20Q may include a base region 25B. The base region 25B is adjacent to both the emitter region 24 and the first region 20P. That is, the base region 25B is sandwiched between the emitter region 24 and the first region 20P in the Z direction. In one example, the p-type impurity concentration of the base region 25B is 1×10 15 cm -3 More than 1×10 18 cm -3 It can be as follows:

[0034] In the IGBT region 21, the semiconductor layer 20 may further include a p-type collector region 26C adjacent to the first region 20P. The collector region 26C includes a part of the second surface 20R of the semiconductor layer 20. That is, in the IGBT region 21, the collector region 26C is provided in a surface layer portion closer to the second surface 20R of the semiconductor layer 20. In one example, the p-type impurity concentration of the collector region 26C is 1×10 15 cm -3 More than 1×10 18 cm -3 It can be as follows:

[0035] In the IGBT region 21, the first region 20P may include a buffer region 27 adjacent to the collector region 26C, a drift region 28 provided on the buffer region 27, and a carrier storage region 29 adjacent to the drift region 28. The carrier storage region 29 is sandwiched between the base region 25B and the drift region 28 in the Z direction. In one example, the n-type impurity concentration of the buffer region 27 is 1×10 15 cm -3 More than 1×10 17 cm -3 In one example, the n-type impurity concentration of the drift region 28 can be 1×10 13 cm -3 More than 1×10 15 cm -3 The drift region 28 has a lower n-type impurity concentration than the buffer region 27. The carrier storage region 29 has a higher n-type impurity concentration than the drift region 28. In one example, the n-type impurity concentration of the carrier storage region 29 is 1×10 15 cm -3 More than 1×10 17 cm -3 Preferably, the carrier storage region 29 has a lower n-type impurity concentration than the emitter region 24.

[0036] The provision of the carrier storage region 29 suppresses the discharge of carriers (holes) into the base region 25B, thereby promoting the accumulation of carriers (holes) in the region immediately below the trench structure 70 in the IGBT region 21. Therefore, the carrier storage region 29 can reduce the on-resistance and on-voltage of the IGBT 21A.

[0037] In the IGBT region 21, the multiple trench structures 70 may include multiple gate trench structures 70G and multiple emitter trench structures 70E. In one example, the gate trench structures 70G and the emitter trench structures 70E may be arranged alternately one by one in the X direction. Note that the number and arrangement of the gate trench structures 70G and the emitter trench structures 70E may be changed as appropriate depending on the desired characteristics of the IGBT 21A.

[0038] Each gate trench structure 70G includes a gate trench 71G, a gate insulating layer 72G, and a gate electrode 73G. Here, the gate trench 71G is an example of a "first trench." The gate insulating layer 72G is an example of a "first trench insulating layer." The gate electrode 73G is an example of a "first buried electrode."

[0039] The gate trench 71G has an opening in the first surface 20S of the semiconductor layer 20 and extends to penetrate the base region 25B. Therefore, the gate trench 71G also penetrates the emitter region 24. The gate trench 71G penetrates the carrier storage region 29 and reaches the drift region 28.

[0040] The multiple gate trenches 71G may be arranged at intervals of 1 μm to 10 μm in the X direction. Each gate trench 71G may have a width (dimension in the X direction) of 0.5 μm to 3 μm inclusive. Each gate trench 71G may have a depth (dimension in the Z direction) of 1 μm to 10 μm inclusive.

[0041] The gate trench 71G includes a sidewall and a bottom wall. The sidewall extends from the first surface 20S of the semiconductor layer 20 toward the bottom wall. The bottom wall forms an end of the gate trench 71G on the second surface 20R side of the semiconductor layer 20. In the example shown in FIG. 4, the sidewall extends along the Z direction. The bottom wall has a curved shape that convexly extends toward the second surface 20R of the semiconductor layer 20.

[0042] The sidewalls may be tapered such that the opening width (dimension in the X direction) narrows from the first surface 20S of the semiconductor layer 20 toward the bottom wall. The bottom wall may be a flat surface perpendicular to the Z direction. In this case, the corners between the bottom wall and the sidewalls may be curved and convex outward.

[0043] The gate insulating layer 72G is provided in the gate trench 71G. The gate insulating layer 72G may be formed by, for example, thermal oxidation. In this case, the gate insulating layer 72G may form the sidewalls and bottom wall of the gate trench 71G. In other words, the outer surface of the gate insulating layer 72G may form the sidewalls and bottom wall of the gate trench 71G. The gate insulating layer 72G may contain at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The gate insulating layer 72G is integrated with the insulating layer 30 provided on the first surface 20S of the semiconductor layer 20. Therefore, it can be said that the insulating layer 30 includes the gate insulating layer 72G.

[0044] The gate insulating layer 72G is provided in a layered manner on the sidewalls and bottom wall of the gate trench 71G. As a result, a recess space is formed in the gate trench 71G by the gate insulating layer 72G. A gate electrode 73G is buried in this recess space. Therefore, it can be said that the gate electrode 73G is buried in the gate insulating layer 72G within the gate trench 71G.

[0045] The gate electrode 73G is configured to receive a gate potential. That is, the gate electrode 73G may be electrically connected to the gate pad electrode 40G (see FIG. 1). In one example, although not shown, the gate electrode 73G is connected to a gate contact at one end of the gate trench 71G in the Y direction. The gate contact is connected to the gate finger 51 (see FIG. 1). As a result, the gate electrode 73G is electrically connected to the gate pad electrode 40G via the gate contact and the gate finger 51. The upper end surface of the gate electrode 73G may be located closer to the bottom wall of the gate trench 71G than the first surface 20S of the semiconductor layer 20. The gate electrode 73G is made of, for example, conductive polysilicon.

[0046] Each emitter trench structure 70E includes an emitter trench 71E, an emitter insulating layer 72E, and a field plate electrode 73E. Here, the emitter trench 71E is an example of a "first trench." The emitter insulating layer 72E is an example of a "first trench insulating layer." The field plate electrode 73E is an example of a "first buried electrode."

[0047] Like the gate trench 71G, the emitter trench 71E penetrates the emitter region 24, the base region 25B, and the carrier storage region 29 and reaches the drift region .

[0048] The multiple emitter trenches 71E may be arranged at intervals of 1 μm or more and 10 μm or less in the X direction. Each emitter trench 71E may have a width (dimension in the X direction) of 0.5 μm or more and 3 μm or less. Each emitter trench 71E may have a depth (dimension in the Z direction) of 1 μm or more and 10 μm or less. The shape of the emitter trench 71E shown in FIG. 4 may be the same as the shape of the gate trench 71G. In the first embodiment, the size and pitch of the emitter trench 71E may be the same as those of the gate trench 71G. In another example, the size and pitch of the emitter trench 71E may be different from those of the gate trench 71G.

[0049] The emitter insulating layer 72E is provided in the emitter trench 71E. When the emitter insulating layer 72E is formed by, for example, thermal oxidation, the emitter insulating layer 72E may form the sidewalls and bottom wall of the emitter trench 71E. The emitter insulating layer 72E may contain at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. In other words, the emitter insulating layer 72E may be made of the same material as the gate insulating layer 72G. The emitter insulating layer 72E is integrated with the insulating layer 30 provided on the first surface 20S of the semiconductor layer 20. Therefore, it can be said that the insulating layer 30 includes the emitter insulating layer 72E.

[0050] The emitter insulating layer 72E is provided in a layered form on the sidewalls and bottom wall of the emitter trench 71E. This forms a recess space within the emitter trench 71E due to the emitter insulating layer 72E. A field plate electrode 73E is embedded in this recess space. Therefore, it can be said that the field plate electrode 73E is embedded in the emitter insulating layer 72E within the emitter trench 71E.

[0051] The field plate electrode 73E is configured to be applied with an emitter potential. That is, the field plate electrode 73E may be electrically connected to the first pad electrode 40P (see FIG. 1). In one example, although not shown, the field plate electrode 73E is connected to an emitter contact at one end of the emitter trench 71E in the Y direction. The emitter contact is connected to the first pad electrode 40P. As a result, the field plate electrode 73E is electrically connected to the first pad electrode 40P via the emitter contact. The upper end surface of the field plate electrode 73E may be located closer to the bottom wall of the emitter trench 71E than the first surface 20S of the semiconductor layer 20. The field plate electrode 73E is made of, for example, conductive polysilicon. In this way, the field plate electrode 73E may be made of the same material as the gate electrode 73G.

[0052] The RC-IGBT 10 includes a plurality of contact structures 80 that electrically connect the first pad electrode 40P and the second region 20Q in the IGBT region 21. The contact structures 80 are arranged on both sides of the gate trench structure 70G in the X direction at intervals from the gate trench structure 70G in the X direction.

[0053] The contact structure 80 includes a contact hole 81 , an emitter contact 82 , and a base contact region 83 . The contact hole 81 has an opening in the first surface 20S of the semiconductor layer 20 and extends in the Z direction toward the second surface 20R. The contact hole 81 also penetrates the insulating layer 30 in the Z direction. The contact hole 81 includes a sidewall and a bottom wall. The sidewall extends from the upper surface 30S of the insulating layer 30 toward the bottom wall. The sidewall includes a first sidewall formed by the insulating layer 30 and a second sidewall formed by the semiconductor layer 20. In the example shown in FIG. 4, the sidewall has a tapered shape in which the opening width (dimension in the X direction) narrows from the upper surface 30S of the insulating layer 30 toward the bottom wall. The bottom wall has a curved shape that convexly curves toward the base region 25B.

[0054] The side walls may extend along the Z direction. The bottom wall may be a flat surface perpendicular to the Z direction. In this case, the corner between the bottom wall and the side walls may be curved and convex outward.

[0055] The emitter contact 82 is buried in the contact hole 81. The emitter contact 82 is in contact with the emitter region 24. The emitter contact 82 may have, for example, a stacked structure of a first conductive layer 82A and a second conductive layer 82B. The first conductive layer 82A may include at least one of titanium, titanium nitride, tantalum (Ta), and tantalum nitride (TaN). The second conductive layer 82B is provided on the first conductive layer 82A. The second conductive layer 82B may include at least one of tungsten (W), molybdenum, nickel, aluminum, copper, an aluminum alloy, and a copper alloy.

[0056] The base contact region 83 is provided in the base region 25B. The base contact region 83 is in contact with the bottom wall of the contact hole 81. In other words, the base contact region 83 is exposed at the bottom wall of the contact hole 81. Therefore, the emitter contact 82 is in contact with the base contact region 83 at the bottom wall of the contact hole 81. The p-type impurity concentration of the base contact region 83 is 1×10 19 cm -3 More than 1×10 20 cm -3 It can be as follows:

[0057] The RC-IGBT 10 may further include a second electrode layer 60 provided on the second surface 20R of the semiconductor layer 20. The second electrode layer 60 is electrically connected to the collector region 26C in the IGBT region 21. The second electrode layer 60 forms ohmic contact with the collector region 26C. The second electrode layer 60 may include at least one of titanium (Ti), nickel (Ni), palladium (Pd), gold (Au), silver (Ag), and aluminum (Al). In this manner, an IGBT 21A can be configured in the IGBT region 21 by the structure between the first pad electrode 40P and the second electrode layer 60 in the IGBT region 21. Therefore, it can be said that the first pad electrode 40P configures the emitter of the IGBT 21A, and the second electrode layer 60 configures the collector of the IGBT 21A.

[0058] (diode region) In the diode region 22, the second region 20Q may include a p-type anode region 25A instead of the base region 25B of the IGBT region 21. The diode region 22 does not include the emitter region 24. Therefore, the anode region 25A includes a part of the first surface 20S of the semiconductor layer 20. That is, in the diode region 22, the anode region 25A is provided in a surface layer portion closer to the first surface 20S of the semiconductor layer 20. The anode region 25A is adjacent to the first region 20P. In one example, the p-type impurity concentration of the anode region 25A is 1×10 15 cm -3 More than 1×10 18 cm-3 In one example, the p-type impurity concentration of the anode region 25A may be equal to the p-type impurity concentration of the base region 25B. In another example, the p-type impurity concentration of the anode region 25A may be different from the p-type impurity concentration of the base region 25B.

[0059] In the diode region 22, the semiconductor layer 20 may further include a p-type cathode region 26K adjacent to the first region 20P, instead of the collector region 26C of the IGBT region 21. The cathode region 26K includes a part of the second surface 20R of the semiconductor layer 20. That is, in the diode region 22, the cathode region 26K is provided in a surface layer portion closer to the second surface 20R of the semiconductor layer 20. The cathode region 26K is adjacent to the collector region 26C in a direction perpendicular to the Z direction. In one example, the n-type impurity concentration of the cathode region 26K is 1×10 19 cm -3 More than 1×10 20 cm -3 That is, the n-type impurity concentration of the cathode region 26K may be higher than the p-type impurity concentration of the collector region 26C.

[0060] In the diode region 22, the first region 20P may include a buffer region 27 and a drift region 28, similar to the IGBT region 21. On the other hand, in the diode region 22, the first region 20P does not include a carrier storage region 29. In the diode region 22, the buffer region 27 is adjacent to the cathode region 26K.

[0061] In the diode region 22, the plurality of trench structures 70 may include a plurality of diode trench structures 70D. Note that the number of diode trench structures 70D can be changed as appropriate depending on the desired characteristics of the diode 22A.

[0062] Each diode trench structure 70D includes a diode trench 71D, a diode insulating layer 72D, and a diode electrode 73D. Here, the diode trench 71D is an example of a "second trench." The diode insulating layer 72D is an example of a "second trench insulating layer." The diode electrode 73D is an example of a "second buried electrode."

[0063] The diode trench 71D has an opening in the first surface 20S of the semiconductor layer 20 and extends to penetrate the cathode region 26K. The diode trench 71D reaches the drift region .

[0064] The multiple diode trenches 71D may be arranged at intervals of 1 μm or more and 10 μm or less in the X direction. Each diode trench 71D may have a width (dimension in the X direction) of 0.5 μm or more and 3 μm or less. Each diode trench 71D may have a depth (dimension in the Z direction) of 1 μm or more and 10 μm or less. The shape of the diode trench 71D shown in FIG. 4 may be the same as the shape of the gate trench 71G. In the first embodiment, the size of the diode trench 71D may be the same as the size of the gate trench 71G. The pitch of the diode trenches 71D is 1 / 2 the pitch of the gate trenches 71G. The size of the diode trenches 71D may be different from that of the gate trenches 71G. The pitch of the diode trenches 71D may be different from 1 / 2 the pitch of the gate trenches 71G.

[0065] The diode insulating layer 72D is provided in the diode trench 71D. When the diode insulating layer 72D is formed by, for example, thermal oxidation, the diode insulating layer 72D may form the sidewalls and bottom wall of the diode trench 71D. The diode insulating layer 72D may contain at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. In other words, the diode insulating layer 72D may be made of the same material as the gate insulating layer 72G.

[0066] The diode insulating layer 72D is provided in a layered manner on the sidewalls and bottom wall of the diode trench 71D. As a result, a recess space is formed in the diode trench 71D by the diode insulating layer 72D. A diode electrode 73D is embedded in this recess space. Therefore, it can be said that the diode electrode 73D is embedded in the diode insulating layer 72D within the diode trench 71D.

[0067] The diode electrode 73D is configured to be supplied with a potential different from the gate potential, for example, an anode potential. In the first embodiment, the anode potential is the same as the emitter potential. That is, the diode electrode 73D may be electrically connected to the first pad electrode 40P (see FIG. 1). The upper end surface of the diode electrode 73D may be located closer to the bottom wall of the diode trench 71D than the first surface 20S of the semiconductor layer 20. The diode electrode 73D is made of, for example, conductive polysilicon. In this way, the diode electrode 73D may be made of the same material as the gate electrode 73G.

[0068] The second electrode layer 60 is electrically connected to the cathode region 26K in the diode region 22. The second electrode layer 60 forms ohmic contact with the cathode region 26K. In this manner, a diode 22A can be configured in the diode region 22 by the structure between the first pad electrode 40P and the second electrode layer 60 in the diode region 22. For this reason, it can be said that the first pad electrode 40P configures the anode of the diode 22A, and the second electrode layer 60 configures the cathode of the diode 22A. In this manner, the first pad electrode 40P electrically connects the emitter of the IGBT 21A and the anode of the diode 22A. The second electrode layer 60 electrically connects the collector of the IGBT 21A and the cathode of the diode 22A.

[0069] (boundary area) In the boundary region 23, the second region 20Q may include a p-type boundary well region 25W. The boundary well region 25W includes a part of the first surface 20S of the semiconductor layer 20. That is, in the boundary region 23, the boundary well region 25W is provided in a surface layer portion closer to the first surface 20S of the semiconductor layer 20. In one example, the p-type impurity concentration of the boundary well region 25W is 1×10 15 cm -3 More than 1×10 18 cm -3 In one example, the p-type impurity concentration of the boundary well region 25W may be higher than both the p-type impurity concentration of the base region 25B and the p-type impurity concentration of the anode region 25A.

[0070] In the boundary region 23, both the p-type cathode region 26K and the n-type collector region 26C adjacent to the first region 20P are arranged. That is, the boundary between the cathode region 26K and the collector region 26C is located in the boundary region 23. The boundary well region 25W is provided so as to overlap the boundary between the cathode region 26K and the collector region 26C in a plan view.

[0071] In the boundary region 23, the first region 20P may include a buffer region 27 and a drift region 28, similar to the IGBT region 21. On the other hand, in the boundary region 23, the first region 20P does not include a carrier storage region 29. In the boundary region 23, the buffer region 27 is adjacent to both the cathode region 26K and the collector region 26C.

[0072] 4, the boundary well region 25W is provided at a distance from both the base region 25B and the anode region 25A in the X direction. The boundary well region 25W is provided across the entire boundary region 23 in the X direction. Although not shown, the boundary well region 25W may be provided across the entire boundary region 23 in the Y direction. Therefore, the boundary well region 25W may be provided across the entire boundary region 23 in a plan view.

[0073] In the example shown in FIG. 4, the boundary well region 25W has a curved shape that convexly extends toward the second surface 20R of the semiconductor layer 20. The boundary well region 25W may be configured so that the depth dimension HW of the boundary well region 25W is greatest at the center of the width of the boundary well region 25W. Here, the width direction of the boundary well region 25W can be defined as a direction perpendicular to the extension direction of the boundary well region 25W in a plan view. In FIG. 4, the width direction of the boundary well region 25W coincides with the X direction. The boundary well region 25W is configured so that the depth dimension HW decreases from the center of the width of the boundary well region 25W toward the IGBT region 21. The boundary well region 25W is configured so that the depth dimension HW decreases from the center of the width of the boundary well region 25W toward the diode region 22. Here, the depth dimension HW of the boundary well region 25W can be defined by the maximum value of the distance in the Z direction between the first surface 20S of the semiconductor layer 20 and the boundary between the boundary well region 25W and the drift region .

[0074] The boundary well region 25W may be disposed apart from at least one of the trench structure 70 in the IGBT region 21 closest to the boundary region 23 and the trench structure 70 in the diode region 22 closest to the boundary region 23. In the example shown in Fig. 4, the boundary well region 25W may be disposed apart from both the trench structure 70 in the IGBT region 21 closest to the boundary region 23 and the trench structure 70 in the diode region 22 closest to the boundary region 23. Therefore, on the first surface 20S of the semiconductor layer 20, the region between the boundary well region 25W and the trench structure 70 in the IGBT region 21 closest to the boundary region 23 and the region between the boundary well region 25W and the trench structure 70 in the diode region 22 closest to the boundary region 23 are each a drift region 28.

[0075] Here, the trench structure 70 closest to the boundary region 23 in the IGBT region 21 is the emitter trench structure 70E. Therefore, it can be said that the boundary well region 25W is provided at a distance from the emitter trench 71E closest to the boundary region 23 in the IGBT region 21. It can also be said that the boundary well region 25W is provided at a distance from the diode trench 71D closest to the boundary region 23 in the diode region 22. In this way, the boundary well region 25W may be provided at a distance from at least one of the emitter trench 71E closest to the boundary region 23 in the IGBT region 21 and the diode trench 71D closest to the boundary region 23 in the diode region 22.

[0076] The depth dimension HW of the boundary well region 25W may be greater than both the depth dimension HB of the base region 25B and the depth dimension HA of the anode region 25A. The depth dimension HW of the boundary well region 25W may be greater than both the depth dimension HE of the emitter trench 71E and the depth dimension HD of the diode trench 71D. The depth dimension HW of the boundary well region 25W may also be greater than the depth dimension HG of the gate trench 71G.

[0077] Here, the depth dimension HB of the base region 25B can be defined as the distance in the Z direction between the boundary between the emitter region 24 and the base region 25B and the boundary between the base region 25B and the carrier storage region 29. The depth dimension HA of the anode region 25A can be defined as the distance in the Z direction between the first surface 20S of the semiconductor layer 20 and the boundary between the bottom surface of the anode region 25A and the drift region 28.

[0078] 3, the width dimension WW of the boundary well region 25W may be larger than both the width dimension WE of the emitter trench 71E and the width dimension WD of the diode trench 71D. Furthermore, the width dimension WW of the boundary well region 25W may be larger than the width dimension WG of the gate trench 71G. The width dimension WW of the boundary well region 25W may be larger than both the distance DEG between adjacent emitter trenches 71E and gate trenches 71G in the X direction and the distance DD between adjacent diode trenches 71D in the X direction.

[0079] Here, the width dimension WW of the boundary well region 25W can be defined by the maximum dimension in the X direction of the boundary well region 25W at the first surface 20S of the semiconductor layer 20. The width dimension WG of the gate trench 71G can be defined by the maximum value of the opening width (dimension in the X direction) of the gate trench 71G at the first surface 20S of the semiconductor layer 20. The width dimension WE of the emitter trench 71E can be defined by the maximum value of the opening width (dimension in the X direction) of the emitter trench 71E at the first surface 20S of the semiconductor layer 20. The width dimension WD of the diode trench 71D can be defined by the maximum value of the opening width (dimension in the X direction) of the diode trench 71D at the first surface 20S of the semiconductor layer 20.

[0080] (LTC area) As shown in FIG. 4, the semiconductor device 10 includes a lifetime control region (hereinafter referred to as an "LTC region 90") provided within the semiconductor layer 20. The LTC region 90 is a region in which lifetime killers are intentionally provided, for example, by implanting impurities into the semiconductor layer 20. A lifetime killer is a carrier recombination center that shortens the lifetime. An example of a lifetime killer is a crystal defect. Furthermore, lifetime is the average time that excess carriers exist in a semiconductor material before recombining and reaching equilibrium. In this way, the LTC region 90 can be said to be a region in which crystal defects are provided within the semiconductor layer 20. The LTC region 90 is formed by implanting, for example, helium (He) into the semiconductor layer 20.

[0081] The lifetime killer is not limited to a crystal defect, but may also be a vacancy, a divacancy, a complex defect of a vacancy or a divacancy and an element constituting the semiconductor layer 20, a dislocation, a rare gas element such as helium or neon (Ne), a metal element such as platinum (Pt), etc.

[0082] The LTC region 90 is provided so as to overlap the diode region 22 and the boundary region 23 in a planar view. The LTC region 90 may be provided over the entire diode region 22 in a planar view. On the other hand, the LTC region 90 is provided so as to be spaced apart from the IGBT region 21 in a planar view. The boundary well region 25W is provided so as to overlap an end 91 of the LTC region 90 in a planar view. The end 91 of the LTC region 90 is provided in the boundary region 23. The boundary well region 25W is provided so as to be spaced apart from the LTC region 90 in the Z direction. The boundary well region 25W is provided closer to the first surface 20S of the semiconductor layer 20 than the LTC region 90. The boundary well region 25W is spaced apart from the LTC region 90 in the Z direction.

[0083] (insulating layer and first electrode layer) 4, the insulating layer 30 provided on the first surface 20S of the semiconductor layer 20 includes a first insulating layer 31 in contact with the first surface 20S and a second insulating layer 32 stacked on the first insulating layer 31. In one example, the first insulating layer 31 and the second insulating layer 32 may be made of the same material. In another example, the first insulating layer 31 and the second insulating layer 32 may be made of different materials.

[0084] The first insulating layer 31 has a thickness thinner than the second insulating layer 32. The thickness of the first insulating layer 31 may be equal to the thickness of each of the gate insulating layer 72G, the emitter insulating layer 72E, and the diode insulating layer 72D, for example. The first insulating layer 31 may be integrated with the gate insulating layer 72G and the emitter insulating layer 72E. The second insulating layer 32 covers the gate electrode 73G and the field plate electrode 73E.

[0085] The insulating layer 30 may include a diode opening 33. The diode opening 33 exposes the diode region 22. The diode opening 33 may also expose the boundary region 23. In other words, the insulating layer 30 is provided in the IGBT region 21. In one example, a side surface 33A of the insulating layer 30 constituting the diode opening 33 may be inclined toward the diode region 22 from the upper surface 30S of the insulating layer 30 toward the first surface 20S of the semiconductor layer 20. The diode opening 33 may expose the entire diode region 22 in the Y direction. The diode opening 33 may expose the entire diode region 22 in the X direction. The diode opening 33 may also expose the entire boundary region 23 in the Y direction. The side surface 33A of the insulating layer 30 may be located in the boundary region 23, for example. That is, a portion of the insulating layer 30 in the X direction may be provided in the boundary region 23.

[0086] The first pad electrode 40P in the first electrode layer 40 may include a first electrode portion 41 provided corresponding to the IGBT region 21, a second electrode portion 42 provided corresponding to the diode region 22, and a third electrode portion 43 provided corresponding to the boundary region 23. The first electrode portion 41 is provided on the insulating layer 30. The first electrode portion 41 is in contact with the upper surface 30S of the insulating layer 30. The second electrode portion 42 is provided in the diode opening 33. The third electrode portion 43 is provided in the diode opening 33. The second electrode portion 42 and the third electrode portion 43 are in contact with the first surface 20S of the semiconductor layer 20. That is, the second electrode portion 42 is in contact with the anode region 25A. The third electrode portion 43 is in contact with the boundary well region 25W. In one example, the third electrode portion 43 may be in contact with the entire boundary well region 25W in the X direction. In one example, the third electrode portion 43 may be in contact with the entire boundary well region 25W in the Y direction. The second electrode portion 42 is connected to the diode electrode 73D. In this manner, the second electrode portion 42 is electrically connected to the anode region 25A and the diode electrode 73D. The third electrode portion 43 is electrically connected to the boundary well region 25W.

[0087] [Cross-sectional structure of part of the outer periphery] The cross-sectional structure of a portion of the outer peripheral region 12 will be described with reference to Fig. 5. Fig. 5 shows a schematic cross-sectional structure of a portion of the outer peripheral region 12.

[0088] As shown in FIG. 5, the peripheral region 12 is provided with a termination structure that relieves electric field concentration in the peripheral region 12. The termination structure includes, for example, a guard ring 100. Therefore, it can be said that the guard ring 100 is provided in the peripheral region 12. The guard ring 100 is composed of a plurality of field regions 101-104 containing p-type impurities. The guard ring 100 is annular in shape surrounding the cell region 11 in a planar view. That is, each of the field regions 101-104 is annular in shape surrounding the cell region 11 in a planar view. Each of the field regions 101-104 is provided at a distance from the cell region 11 on the peripheral edge side of the semiconductor layer 20 in a planar view.

[0089] Each of the field regions 101-104 includes a portion of the first surface 20S of the semiconductor layer 20. That is, each of the field regions 101-104 is provided in a surface portion closer to the first surface 20S of the semiconductor layer 20. Each of the field regions 101-104 may have a higher p-type impurity concentration than the base region 25B. Each of the field regions 101-104 may have a higher p-type impurity concentration than the anode region 25A (see FIG. 4). In one example, the p-type impurity concentration of the boundary well region 25W (see FIG. 4) may be equal to the p-type impurity concentration of the guard ring 100. Each of the field regions 101-104 may be in an electrically floating state.

[0090] In one example, the depth dimension HF of each of the field regions 101-104 may be greater than the depth dimension HA of the anode region 25A (see FIG. 4). In one example, the depth dimension HF of each of the field regions 101-104 may be greater than the depth dimension HB of the base region 25B (see FIG. 4). In one example, the depth dimension HF of each of the field regions 101-104 may be equal to the depth dimension HW of the boundary well region 25W.

[0091] Field region 104 may be wider than field regions 101-103. Field regions 101-103 have the same width dimension. In one example, width dimension WF of field regions 101-103 may be equal to width dimension WW of boundary well region 25W. That is, width dimension WF of field region 104 may be greater than width dimension WW of boundary well region 25W.

[0092] The termination structure includes, for example, an n-type channel stop region 110. The channel stop region 110 is provided at a distance from the field regions 101 to 104 on the peripheral side of the semiconductor layer 20. The channel stop region 110 may have a higher n-type impurity concentration than the semiconductor layer 20. The channel stop region 110 is annular in shape surrounding the field regions 101 to 104 in a plan view.

[0093] The termination structure includes, for example, a p-type well region 120. In the example shown in FIG. 5, the well region 120 is provided so as to extend from the outer edge of the IGBT region 21 to the outer periphery region 12. That is, the well region 120 extends from the IGBT region 21 to the peripheral edge side of the semiconductor layer 20, beyond the boundary between the cell region 11 (IGBT region 21) and the outer periphery region 12. Therefore, an inner edge 121 of the well region 120 is located in the cell region 11 (IGBT region 21). An outer edge 122 of the well region 120 is located in the outer periphery region 12. The well region 120 is located closer to the cell region 11 (IGBT region 21) than the guard ring 100. The well region 120 is provided so as to separate the IGBT region 21 from the outer periphery region 12. The well region 120 may have a higher p-type impurity concentration than the base region 25B. The p-type impurity concentration of the well region 120 may be equal to the p-type impurity concentration of the guard ring 100. The p-type impurity concentration of the well region 120 may be equal to the p-type impurity concentration of the boundary well region 25W.

[0094] The well region 120 is a layer extending along the first surface 20S of the semiconductor layer 20. The well region 120 is exposed from the first surface 20S. The well region 120 is annular in shape surrounding the cell region 11 in a plan view. The well region 120 is provided to be deeper than the base region 25B. In one example, the depth dimension HP of the well region 120 may be deeper than the depth dimension HG of the gate trench 71G (both see FIG. 4). In one example, the depth dimension HP of the well region 120 may be equal to the depth dimension HW of the boundary well region 25W (see FIG. 4).

[0095] The LTC region 90 is also provided in the peripheral region 12. The LTC region 90 is provided closer to the second face 20R of the semiconductor layer 20 than both the field regions 101 to 104 and the channel stop region 110. The LTC region 90 is provided apart from each of the field regions 101 to 104, the channel stop region 110, and the well region 120 in the Z direction.

[0096] The RC-IGBT 10 may include a peripheral insulating layer 34 that covers the first surface 20S of the semiconductor layer 20 in the peripheral region 12. The peripheral insulating layer 34 may be composed of a first insulating layer 31 and a second insulating layer 32. In other words, the insulating layer 30 may include the peripheral insulating layer 34.

[0097] The well region 120 is electrically connected to the first pad electrode 40P. More specifically, the first pad electrode 40P includes a protruding electrode portion 40R that protrudes into the peripheral region 12. The protruding electrode portion 40R is provided so as to overlap the well region 120 in a plan view. The RC-IGBT 10 includes a well-connecting electrode 123 that is provided so as to penetrate the peripheral insulating layer 34. The well-connecting electrode 123 is in contact with both the protruding electrode portion 40R and the well region 120.

[0098] The peripheral insulating layer 34 includes at least one field opening 34A that selectively exposes the field regions 101 to 104. In the example shown in Figure 5, a plurality of field openings 34A are provided corresponding to the field regions 101 to 104.

[0099] RC-IGBT 10 may include, as a termination structure, field connection electrodes 105 electrically connected to field regions 101 to 104 individually, and a field electrode 106 provided on peripheral insulating layer 34.

[0100] A plurality of field connection electrodes 105 are provided corresponding to the plurality of field openings 34A. The plurality of field connection electrodes 105 are embedded in the corresponding plurality of field openings 34A. Each field connection electrode 105 is in an electrically floating state. Each field connection electrode 105 has a layered structure of one metal film or multiple metal films. Each field connection electrode 105 may contain at least one of titanium, tungsten, aluminum, and copper.

[0101] A plurality of field electrodes 106 are provided corresponding to the plurality of field regions 101 to 104. The plurality of field electrodes 106 are connected to a plurality of field connection electrodes 105. As a result, the plurality of field electrodes 106 are individually electrically connected to the field regions 101 to 104 via the plurality of field connection electrodes 105. The plurality of field electrodes 106 are annular in shape extending along the corresponding plurality of field regions 101 to 104 in a plan view. The field electrode 106 corresponding to the field region 104 includes an extraction portion 106A that is extracted toward the peripheral edge side of the semiconductor layer 20. As a result, the field electrode 106 corresponding to the field region 104 is wider than the other field electrodes 106.

[0102] The peripheral insulating layer covers a part of the channel stop region 110. More specifically, the peripheral edge side of the semiconductor layer 20 in the channel stop region 110 is exposed from the peripheral insulating layer .

[0103] The RC-IGBT 10 includes a channel stop electrode 111 as a termination structure. The channel stop electrode 111 is provided on the peripheral insulating layer 34 and is provided so as to contact the channel stop region 110. In this way, the channel stop electrode 111 is electrically connected to the channel stop region 110.

[0104] The field electrode 106 and the channel stop electrode 111 may include at least one of aluminum, copper, an aluminum alloy, a copper alloy, tungsten, molybdenum, nickel, titanium, titanium nitride, tantalum, and tantalum nitride. The field electrode 106 and the channel stop electrode 111 may be made of the same material as the first electrode layer 40. The field electrode 106 and the channel stop electrode 111 may be provided integrally with the first electrode layer 40. In other words, the first electrode layer 40 may include the field electrode 106 and the channel stop electrode 111.

[0105] [RC-IGBT manufacturing method] An example of a manufacturing method for the RC-IGBT 10 will be described with reference to Figures 6 to 20. Figures 6 to 20 show cross-sectional structures at the same cross-sectional position as that shown in Figure 5. For ease of understanding, in Figures 6 to 20, components similar to those in Figure 5 are denoted by the same reference numerals.

[0106] 6, in the manufacturing method of the RC-IGBT 10, a semiconductor wafer 800 is prepared as a base for the semiconductor layer 20. The semiconductor wafer 800 may be an n-type single crystal silicon substrate. In one example, the n-type impurity concentration of the semiconductor wafer 800 is 1×10 13 cm -3 More than 1×10 15 cm -3The semiconductor wafer 800 includes a first surface 801 and a second surface 802 opposite to the first surface 801. Here, the first surface 801 corresponds to the first surface 20S of the semiconductor layer 20. In the semiconductor wafer 800, a plurality of IGBT regions 21, a plurality of boundary regions 23, and a plurality of diode regions 22 are formed by the steps described below. In this way, it can be said that the method for manufacturing the RC-IGBT 10 includes forming the semiconductor layer 20 including the first surface 20S on which the IGBT regions 21 and the diode regions 22 are provided.

[0107] As shown in FIG. 7, the manufacturing method for RC-IGBT 10 includes forming boundary well region 25W. In this step, first, a resist mask 900 having a predetermined pattern is formed on first surface 801 of semiconductor wafer 800. Resist mask 900 exposes a region where boundary well region 25W is to be formed. Although not shown, resist mask 900 also exposes a region where field regions 101-104 (see FIG. 5) are to be formed. Next, p-type impurities are introduced into first surface 801 of semiconductor wafer 800 by ion implantation using resist mask 900. As a result, boundary well region 25W is formed in boundary region 23. At the same time, although not shown, field regions 101-104 and well region 120 are formed in peripheral region 12. Therefore, it can be said that the manufacturing method for RC-IGBT 10 includes forming field regions 101-104. Furthermore, it can be said that forming boundary well region 25W and forming field regions 101-104 are performed in a common process. After forming the boundary well region 25W, the field regions 101 to 104, and the well region 120, the resist mask 900 is removed. Although not shown, a channel stop region 110 (see FIG. 5) may also be formed in this step.

[0108] As shown in FIG. 8 , the manufacturing method of the RC-IGBT 10 includes forming a gate trench 71G, an emitter trench 71E, and a diode trench 71D. These trenches 71G, 71E, and 71D are formed on a first surface 801 of a semiconductor wafer 800. In this process, a mask (not shown) is first formed on the first surface 801 of the semiconductor wafer 800. The mask may be, for example, a hard mask or a resist mask. The mask exposes regions of the first surface 801 of the semiconductor wafer 800 where the gate trench 71G, the emitter trench 71E, and the diode trench 71D are to be formed, while covering the remaining regions. Next, the regions exposed by the mask are etched to form the gate trench 71G, the emitter trench 71E, and the diode trench 71D. Each of the gate trench 71G, the emitter trench 71E, and the diode trench 71D has an opening in the first surface 801 of the semiconductor wafer 800. The gate trench 71G and the emitter trench 71E are formed in the IGBT region 21. The diode trench 71D is formed in the diode region 22. After these trenches 71G, 71E, and 71D are formed, the mask is removed.

[0109] 9, the method for manufacturing the RC-IGBT 10 includes forming a first insulating layer 810. The first insulating layer 810 is an insulating layer that constitutes the first insulating layer 31. The first insulating layer 810 is formed on the first surface 801 of the semiconductor wafer 800 and in the gate trench 71G, the emitter trench 71E, and the diode trench 71D. Therefore, the first insulating layer 810 includes the gate insulating layer 72G, the emitter insulating layer 72E, and the diode insulating layer 72D. In other words, the manufacturing method of the RC-IGBT 10 can be said to include forming the gate insulating layer 72G in the gate trench 71G and forming the emitter insulating layer 72E in the emitter trench 71E. The manufacturing method of the RC-IGBT 10 can be said to include forming the diode insulating layer 72D in the diode trench 71D. In this way, the gate insulating layer 72G, the emitter insulating layer 72E, and the diode insulating layer 72D are formed in a common process. Therefore, the thicknesses of the gate insulating layer 72G, the emitter insulating layer 72E, and the diode insulating layer 72D are equal to one another. Although not shown, the first insulating layer 810 is also formed in the outer periphery region 12.

[0110] The first insulating layer 810 can be formed by, for example, a chemical vapor deposition (CVD) method, an oxidation treatment method (for example, a thermal oxidation method), etc. The first insulating layer 810 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide.

[0111] Next, the manufacturing method of the semiconductor device 10 includes removing the first insulating layer 810 formed on the first surface 801 of the semiconductor wafer 800 corresponding to the diode region 22. In this step, the first insulating layer 810 formed on the upper ends of the plurality of diode trenches 71D is also removed. As a result, the first surface 801 in the diode region 22 and the upper ends of each diode trench 71D are exposed.

[0112] Additionally, the method for manufacturing the semiconductor device 10 includes removing the first insulating layer 810 formed on the first surface 801 of the semiconductor wafer 800 corresponding to the boundary region 23. This exposes the boundary well region 25W. Although not shown, the first insulating layer 810 is removed so as to expose a portion of the channel stop region 110.

[0113] As shown in FIG. 10 , the manufacturing method of the RC-IGBT 10 includes forming a first metal layer 820. The first metal layer 820 is formed on a first insulating layer 810. The first metal layer 820 is formed in the gate trench 71G, the emitter trench 71E, and the diode trench 71D. More specifically, the first metal layer 820 is embedded in the gate insulating layer 72G in the gate trench 71G. The first metal layer 820 is embedded in the emitter insulating layer 72E in the emitter trench 71E. The first metal layer 820 is embedded in the diode insulating layer 72D in the diode trench 71D. Thus, the first metal layer 820 includes the gate electrode 73G, the field plate electrode 73E, and the diode electrode 73D. The first metal layer 820 is formed of, for example, conductive polysilicon. The first metal layer 820 may be formed by a CVD method.

[0114] 11, the method for manufacturing RC-IGBT 10 includes partially removing first metal layer 820. In this step, first metal layer 820 on first surface 801 of semiconductor wafer 800 is removed. At this time, the upper ends of first metal layer 820 in gate trench 71G, emitter trench 71E, and diode trench 71D are also removed.

[0115] 12, the method for manufacturing the RC-IGBT 10 includes forming the emitter region 24, the base region 25B, and the carrier storage region 29 in the IGBT region 21. The method for manufacturing the RC-IGBT 10 also includes forming the anode region 25A in the diode region 22. The order in which these impurity regions are formed is arbitrary. The emitter region 24, the base region 25B, and the carrier storage region 29 in the IGBT region 21 are formed by implanting n-type or p-type impurities through a mask (not shown) having a predetermined pattern. In this step, the portion of the semiconductor wafer 800 into which the n-type or p-type impurities are not implanted may include the drift region 28.

[0116] 13, the method for manufacturing the RC-IGBT 10 includes forming a second insulating layer 830. The second insulating layer 830 is an insulating layer that constitutes the second insulating layer 32. The second insulating layer 830 is formed to cover the upper surfaces of the gate electrode 73G, the field plate electrode 73E, and the diode electrode 73D, as well as the upper surface of the first insulating layer 810. Therefore, the second insulating layer 830 extends into the upper ends of the gate trench 71G, the emitter trench 71E, and the diode electrode 73D. Although not shown, the second insulating layer 830 is also provided to cover the upper surface of the first insulating layer 810 in the peripheral region 12 (see FIG. 5). In one example, the second insulating layer 830 may be formed by a CVD method. The second insulating layer 830 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide.

[0117] As shown in FIGS. 14 to 16, the method for manufacturing the semiconductor device 10 includes forming a contact structure 80. As shown in FIG. As shown in FIG. 14 , forming the contact structure 80 includes forming a plurality of contact holes 81. In this step, a mask 910 is formed on the second insulating layer 830. The mask 910 exposes regions of the second insulating layer 830 where the plurality of contact holes 81 are to be formed, while covering the remaining regions. The mask 910 may be, for example, a resist mask or a hard mask. Then, the second insulating layer 830 is etched using the mask 910, thereby selectively removing the second insulating layer 830, the first insulating layer 810, and the semiconductor wafer 800. As a result, the plurality of contact holes 81 are formed.

[0118] Each of the multiple contact holes 81 penetrates the second insulating layer 830 and the first insulating layer 810 to expose the semiconductor wafer 800 between the gate trench 71G and the emitter trench 71E. Each contact hole 81 is formed to reach the emitter region 24. Note that each contact hole 81 may penetrate the emitter region 24 to reach the base region 25B.

[0119] As shown in FIG. 14 , forming the contact structure 80 includes forming base contact regions 83 through each contact hole 81. In this step, ion implantation is performed to implant p-type impurities into the semiconductor wafer 800. The p-type impurities are implanted into the semiconductor wafer 800 using a mask 910. As a result, the p-type impurities are implanted into portions of the semiconductor wafer 800 exposed by the multiple contact holes 81, thereby simultaneously forming multiple base contact regions 83. Each base contact region 83 is formed in the base region 25B. The base contact region 83 is connected to the contact hole 81. After each base contact region 83 is formed, the mask 910 is removed.

[0120] 15 and 16, forming the contact structure 80 includes forming an emitter contact 82 in each contact hole 81. In this process, as shown in FIG. 15, first, forming the contact structure 80 includes forming a second metal layer 840. The second metal layer 840 is formed on the second insulating layer 830 and along the sidewalls and bottom walls of the contact hole 81. The second metal layer 840 may be formed by at least one of a sputtering method or a CVD method. The second metal layer 840 may include at least one of titanium, titanium nitride, tantalum, and tantalum nitride.

[0121] Next, forming the contact structure 80 includes forming a third metal layer 850. The third metal layer 850 is formed on the second metal layer 840 and is filled in the contact hole 81. The third metal layer 850 may be formed by at least one of a sputtering method, a CVD method, and a plating method. The third metal layer 850 may also include at least one of tungsten, molybdenum, nickel, aluminum, copper, an aluminum alloy, and a copper alloy.

[0122] 16, forming the contact structure 80 includes removing a portion of each of the second metal layer 840 and the third metal layer 850. In one example, both the second metal layer 840 and the third metal layer 850 may be removed by etching (e.g., dry etching, wet etching, etc.). The second metal layer 840 and the third metal layer 850 are removed until the second insulating layer 830 is exposed. Through the above steps, the contact structure 80 is formed.

[0123] As shown in FIGS. 17 and 18, the method for manufacturing the RC-IGBT 10 includes forming a diode opening 33. 17, a resist mask 920 is formed on the second insulating layer 830. The resist mask 900 is formed so as to cover the portion of the second insulating layer 830 corresponding to the IGBT region 21, while exposing the portions corresponding to the boundary region 23 and the diode region 22.

[0124] Next, as shown in FIG. 18, the second insulating layer 830 and the first insulating layer 810 exposed from the resist mask 920 (see FIG. 17) are removed by etching. The etching may be anisotropic etching. The anisotropic etching is dry etching (specifically, RIE (Reactive Ion Etching)). As a result, the diode opening 33 is formed. After the diode opening 33 is formed, the resist mask 920 is removed.

[0125] As shown in FIG. 19 , the manufacturing method of the RC-IGBT 10 includes forming a fourth metal layer 860. The fourth metal layer 860 is a metal layer that constitutes the first electrode layer 40 (see FIG. 4 ). The fourth metal layer 860 is formed on the second insulating layer 830 and on the first surface 20S of the semiconductor layer 20. In the first embodiment, the fourth metal layer 860 is formed of a single metal layer. The fourth metal layer 860 may be made of aluminum silicon copper (AlSiCu). Next, the fourth metal layer 860 is patterned to form the first pad electrode 40P and the gate pad electrode 40G. Although not shown, the fourth metal layer 860 is also formed in the peripheral region 12, thereby filling a portion of the fourth metal layer 860 in the field opening. This forms the field connection electrode 105 (see FIG. 5 ). Next, the fourth metal layer 860 is patterned to form the field electrode 106 and the channel stop electrode 111. That is, the first pad electrode 40P, the gate pad electrode 40G, the field electrode 106, and the channel stop electrode 111 may be formed in a common process.

[0126] As shown in FIG. 20, the method for manufacturing the RC-IGBT 10 includes thinning the semiconductor wafer 800, forming the buffer region 27, the collector region 26C, and the cathode region 26K, forming the LTC region 90, and forming the second electrode layer 60.

[0127] Thinning the semiconductor wafer 800 is performed by grinding or etching the second surface 802 of the semiconductor wafer 800. Next, the buffer region 27, the collector region 26C, and the cathode region 26K may be formed by implanting n-type or p-type impurities into the second surface 802 of the semiconductor wafer 800. The buffer region 27, the collector region 26C, and the cathode region 26K may be formed in any order. The cathode region 26K may be formed by implanting n-type impurities through a first mask (not shown) having a predetermined pattern. The buffer region 27 may be formed by implanting n-type impurities through a second mask (not shown) having a predetermined pattern. The anode region 25A may be formed by implanting p-type impurities through a third mask (not shown) having a predetermined pattern.

[0128] Forming the LTC region 90 includes irradiating the semiconductor wafer 800 with helium. In one example, a metal mask (not shown) having a predetermined pattern is formed on the second surface 802 of the semiconductor wafer 800. The metal mask covers the IGBT region 21 and exposes the boundary region 23, the diode region 22, and the peripheral region 12. Next, helium is irradiated from the second surface 802 side of the semiconductor wafer 800. As a result, crystal defects are formed in the boundary region 23, the diode region 22, and the peripheral region 12, which are regions of the semiconductor wafer 800 exposed from the metal mask. Through the above steps, the LTC region 90 is formed.

[0129] In forming the second electrode layer 60, the second electrode layer 60 is formed on the second surface 802 of the thinned semiconductor wafer 800. The second electrode layer 60 can be formed by at least one of a sputtering method and a CVD method. The semiconductor wafer 800 is then divided into individual pieces by dicing. Through the above steps, the RC-IGBT 10 is manufactured.

[0130] [Operation of the first embodiment] The operation of the RC-IGBT 10 of the first embodiment will be described. 21 is a schematic diagram showing the cross-sectional structure of the RC-IGBT 10X of the comparative example. The RC-IGBT 10X of the comparative example differs from the RC-IGBT 10 of the first embodiment mainly in the configuration of the boundary region. In the following description, components common to the RC-IGBT 10 of the first embodiment are designated by the same reference numerals, and description thereof will be omitted.

[0131] 21, in the RC-IGBT 10X of the comparative example, a boundary trench structure 70X is provided in a boundary region 23X. The boundary trench structure 70X includes a boundary trench 71X, a boundary insulating layer 72X provided in the boundary trench 71X, and a boundary electrode 73X embedded in the boundary insulating layer 72X.

[0132] The boundary insulating layer 72X is provided in the same manner as the diode insulating layer 72D. When the first insulating layer 810 in the boundary region 23 is removed by etching in the manufacturing process of the RC-IGBT 10X, a hole (not shown) may be provided in a part of the upper portion of the boundary insulating layer 72X in the boundary trench 71X.

[0133] Because the diode opening 33 of the insulating layer 30 is located in the boundary region 23, the sloped portion of the third electrode portion 43 of the first electrode layer 40 is located near the boundary trench structure 70X. This may cause a portion of the first electrode layer 40 to intrude into the boundary trench 71X. If a portion of the first electrode layer 40 intrudes into the boundary trench 71X, the embedded portion 40X that has intruded into the boundary trench 71X may come into contact with the drift region 28 through the hole in the boundary insulating layer 72X. As a result, crystal defects due to alloy spikes may occur in the drift region 28. These crystal defects may cause leakage current.

[0134] 4, in the RC-IGBT 10 of the first embodiment, a boundary well region 25W is provided in the boundary region 23 instead of the boundary trench structure 70X (see FIG. 21). As a result, the boundary trench 71X (see FIG. 21) is not provided in the boundary region 23, and therefore it is possible to prevent the first electrode layer 40 from entering the boundary trench 71X. Therefore, it is possible to prevent crystal defects due to alloy spikes from occurring in the drift region 28, and therefore it is possible to suppress the occurrence of leakage current.

[0135] [Effects of the first embodiment] According to the RC-IGBT 10 of the first embodiment, the following effects can be obtained. (1-1) The RC-IGBT 10 includes a semiconductor layer 20 including a first surface 20S and an n-type drift region 28, an IGBT region 21 and a diode region 22 spaced apart in the X direction, which is a first direction in a plan view seen from a direction perpendicular to the first surface 20S, a boundary region 23 provided between the IGBT region 21 and the diode region 22 in the X direction, a gate trench 71G and an emitter trench 71E as first trenches provided corresponding to the IGBT region 21, a diode trench 71D as a second trench provided corresponding to the diode region 22, a gate insulating layer 72G as a first insulating layer provided in the gate trench 71G, an emitter insulating layer 72E as a first insulating layer provided in the emitter trench 71E, a diode insulating layer 72D as a second insulating layer provided in the diode trench 71D, and a gate insulating layer 72G in the gate trench 71G. a gate electrode 73G as a first buried electrode buried in the layer 72G, a field plate electrode 73E as a first buried electrode buried in the emitter insulating layer 72E in the emitter trench 71E, a diode electrode 73D as a second buried electrode buried in the diode insulating layer 72D in the diode trench 71D, a p-type base region 25B provided in the IGBT region 21, a p-type anode region 25A provided in the diode region 22, an insulating layer 30 provided on the first surface 20S to cover the IGBT region 21 while exposing both the diode region 22 and the boundary region 23, and a first electrode layer 40 including a first electrode portion 41 provided on the insulating layer 30 in the IGBT region 21, a second electrode portion 42 provided on the first surface 20S in the diode region 22, and a third electrode portion 43 provided on the first surface 20S in the boundary region 23. The boundary region 23 includes a p-type boundary well region 25W. The boundary well region 25W is provided spaced apart from both the base region 25B and the anode region 25A in the X direction.

[0136] According to this configuration, the boundary region 23 is provided with the boundary well region 25W, and no trench structure is provided. Therefore, the first electrode layer 40 does not intrude into the trench in the boundary region 23. This prevents the first electrode layer 40 from intruding into the trench, thereby suppressing the occurrence of alloy spikes and thus the occurrence of leakage current. In addition, the boundary well region 25W balances the electric fields in the IGBT region 21, the diode region 22, and the boundary region 23. This prevents a decrease in the breakdown voltage of the RC-IGBT 10.

[0137] (1-2) The depth dimension HW of the boundary well region 25W is greater than both the depth dimension HB of the base region 25B and the depth dimension HA of the anode region 25A. According to this configuration, the depletion around the boundary well region 25W can suppress a decrease in the breakdown voltage in the boundary region 23. Therefore, a decrease in the breakdown voltage of the RC-IGBT 10 can be suppressed.

[0138] (1-3) The depth dimension HW of the boundary well region 25W is greater than each of the depth dimension HG of the gate trench 71G, the depth dimension HE of the emitter trench 71E, and the depth dimension HD of the diode trench 71D.

[0139] According to this configuration, the depletion around the boundary well region 25W can further suppress the decrease in the breakdown voltage in the boundary region 23. Therefore, the decrease in the breakdown voltage of the RC-IGBT 10 can be further suppressed.

[0140] (1-4) The RC-IGBT 10 includes an LTC region 90 provided in the semiconductor layer 20. The LTC region 90 is provided to overlap the diode region 22 and the boundary region 23 in a planar view. The boundary well region 25W is provided to overlap an end 91 of the LTC region 90 in a planar view.

[0141] According to this configuration, holes are injected from the boundary well region 25W into the LTC region 90 when the RC-IGBT 10 operates as a diode. This makes it easier for carriers to disappear when the RC-IGBT 10 is turned off.

[0142] (1-5) The p-type impurity concentration of the boundary well region 25W is higher than both the p-type impurity concentration of the base region 25B and the p-type impurity concentration of the anode region 25A. According to this configuration, the migration path of holes flowing into the base region 25B is restricted, so that holes can be accumulated in the region directly below the base region 25B, thereby achieving low on-resistance and low on-voltage from within the semiconductor layer 20.

[0143] (1-6) The RC-IGBT 10 includes a cell region 11 including an IGBT region 21, a diode region 22, and a boundary region 23, a peripheral region 12 surrounding the cell region 11 in a plan view, and a guard ring 100 provided in the peripheral region 12. The p-type impurity concentration of the boundary well region 25W is equal to the p-type impurity concentration of the guard ring 100.

[0144] According to this configuration, the boundary well region 25W and the guard ring 100 can be formed in a common process, thereby simplifying the manufacturing process of the RC-IGBT 10.

[0145] (1-7) The RC-IGBT 10 includes a well region 120 that surrounds the cell region 11 in a plan view. The p-type impurity concentration of the boundary well region 25W is equal to the p-type impurity concentration of the well region 120.

[0146] According to this configuration, the boundary well region 25W and the well region 120 can be formed in a common process, thereby simplifying the manufacturing process of the RC-IGBT 10.

[0147] (1-8) The width dimension WW of the boundary well region 25W is larger than both the width dimension WG of the gate trench 71G and the width dimension WD of the diode trench 71D. According to this configuration, a depletion layer is likely to be formed over a wide range in the width direction of the boundary well region 25W in the boundary region 23. Therefore, a decrease in the breakdown voltage of the RC-IGBT 10 can be suppressed.

[0148] (1-9) The width dimension WW of the boundary well region 25W is larger than both the distance DEG between the emitter trench 71E and the gate trench 71G adjacent to each other in the X direction and the distance DD between the diode trenches 71D adjacent to each other in the X direction.

[0149] According to this configuration, a depletion layer is more likely to be formed over a wider range in the width direction of the boundary well region 25W in the boundary region 23. Therefore, a decrease in the breakdown voltage of the RC-IGBT 10 can be further suppressed.

[0150] (1-10) The boundary well region 25W is provided over the entire boundary region 23 in the X direction. According to this configuration, a depletion layer is more likely to be formed in the width direction of the boundary well region 25W across the entire boundary region 23. Therefore, the decrease in the breakdown voltage of the RC-IGBT 10 can be further suppressed.

[0151] (1-11) The boundary well region 25W is provided over the entire boundary region 23 in the Y direction. This configuration makes it easier to form a depletion layer over the entire boundary region 23. Therefore, the decrease in the breakdown voltage of the RC-IGBT 10 can be further suppressed.

[0152] Second Embodiment The RC-IGBT 10 of the second embodiment will be described with reference to Figures 22 to 24. The RC-IGBT 10 of the second embodiment differs from the RC-IGBT 10 of the first embodiment mainly in the configurations of the insulating layer 30, the first electrode layer 40, and the boundary region 23. In the following, components common to the first embodiment are denoted by the same reference numerals, and their description will be omitted.

[0153] [RC-IGBT configuration] The configuration of the RC-IGBT 10 of the second embodiment will be described with reference to Fig. 22. Fig. 22 schematically shows a cross-sectional structure of a portion of the RC-IGBT 10. The detailed configurations of the boundary region 23, the insulating layer 30, and the first electrode layer 40 will be described below.

[0154] As shown in FIG. 22, a boundary trench structure 70B is provided in the boundary region 23 instead of the boundary well region 25W of the first embodiment. A plurality of boundary trench structures 70B (two in the second embodiment) may be provided in one boundary region 23. Each boundary trench structure 70B includes a boundary trench 71B, a boundary insulating layer 72B, and a boundary electrode 73B. Here, the boundary trench 71B is an example of a "third trench." The boundary insulating layer 72B is an example of a "third trench insulating layer." The boundary electrode 73B is an example of a "third buried electrode."

[0155] The boundary trench 71B extends in the Z direction and has an opening in the first surface 20S of the semiconductor layer 20. The boundary trench 71B may have a width (dimension in the X direction) of 0.5 μm or more and 3 μm or less. The boundary trench 71B may have a depth (dimension in the Z direction) of 1 μm or more and 10 μm or less. The shape of the boundary trench 71B shown in FIG. 22 may be the same as the shape of the gate trench 71G. In the first embodiment, the size of the boundary trench 71B may be the same as the size of the gate trench 71G. The size of the boundary trench 71B may be different from that of the gate trench 71G.

[0156] The boundary insulating layer 72B is provided in the boundary trench 71B. When the boundary insulating layer 72B is formed by, for example, thermal oxidation, the boundary insulating layer 72B may constitute the sidewalls and bottom wall of the boundary trench 71B. The boundary insulating layer 72B may contain at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. That is, the boundary insulating layer 72B may be made of the same material as the gate insulating layer 72G. The boundary insulating layer 72B is integrated with the insulating layer 30 provided on the first surface 20S of the semiconductor layer 20. Therefore, it can be said that the insulating layer 30 includes the boundary insulating layer 72B.

[0157] The boundary insulating layer 72B is provided in a layered form on the sidewalls and bottom wall of the boundary trench 71B. As a result, a recess space is formed in the boundary trench 71B by the boundary insulating layer 72B. A boundary electrode 73B is embedded in this recess space. Therefore, it can be said that the boundary electrode 73B is embedded in the boundary insulating layer 72B within the boundary trench 71B.

[0158] The boundary electrode 73B is configured to be applied with an emitter potential. That is, the boundary electrode 73B may be electrically connected to the first pad electrode 40P. In one example (not shown), the boundary electrode 73B may be electrically connected to the diode electrode 73D at one end of the boundary trench 71B in the Y direction. As a result, the boundary electrode 73B is electrically connected to the first pad electrode 40P via the diode electrode 73D. The upper end surface of the boundary electrode 73B may be located closer to the bottom wall of the boundary trench 71B than the first surface 20S of the semiconductor layer 20. The boundary electrode 73B may be made of, for example, conductive polysilicon. In this way, the boundary electrode 73B may be made of the same material as the gate electrode 73G.

[0159] The boundary region 23 does not have the boundary well region 25W of the first embodiment, and is therefore constituted by the first region 20P. That is, the second region 20Q is not provided in the boundary region 23. In the boundary region 23, the first region 20P includes a buffer region 27 and a drift region 28. That is, the carrier storage region 29 is not provided in the boundary region 23. Therefore, in the boundary region 23, the drift region 28 constitutes a part of the first surface 20S of the semiconductor layer 20. As in the first embodiment, the boundary between the collector region 26C and the cathode region 26K, which are provided closer to the second surface 20R of the semiconductor layer 20, is located in the boundary region 23.

[0160] As in the first embodiment, an end 91 of the LTC region 90 is located in the boundary region 23. The multiple boundary trench structures 70B are provided at a distance from the LTC region 90 in the Z direction. The multiple boundary trench structures 70B are provided closer to the first surface 20S of the semiconductor layer 20 than the LTC region 90. Of the multiple boundary trench structures 70B, one boundary trench structure 70B closer to the diode region 22 is provided at a position overlapping with the LTC region 90 in plan view. Of the multiple boundary trench structures 70B, one boundary trench structure 70B closer to the IGBT region 21 is disposed closer to the IGBT region 21 than the LTC region 90 in plan view.

[0161] The insulating layer 30 of the second embodiment is provided over both the IGBT region 21 and the boundary region 23. As a result, the upper end surface of the boundary electrode 73B is covered with the insulating layer 30. The diode opening 33 of the insulating layer 30 exposes the diode region 22 but does not expose the boundary region 23.

[0162] A first pad electrode 40P in a first electrode layer 40 in the second embodiment includes a first electrode portion 41 and a second electrode portion 42. The first electrode portion 41 is provided on the insulating layer 30 in the IGBT region 21. The second electrode portion 42 is provided on the first surface 20S of the semiconductor layer 20 in the diode region 22. In the second embodiment, the first electrode portion 41 and the second electrode portion 42 are spaced apart from each other via the boundary region 23. Therefore, the insulating layer 30 includes an exposed insulating portion 35 that is exposed in the boundary region 23 without being covered by the first pad electrode 40P (first electrode layer 40). In the second embodiment, the exposed insulating portion 35 is provided over the entire boundary region 23. In other words, the first pad electrode 40P (first electrode layer 40) exposes the entire portion of the insulating layer 30 that corresponds to the boundary region 23.

[0163] The second electrode portion 42 is provided at the same position as the insulating layer 30 in the Z direction. The second electrode portion 42 includes an end face 42A that contacts a side face 33A that constitutes the diode opening 33 of the insulating layer 30. The end face 42A of the second electrode portion 42 is an end face of the second electrode portion 42 that is closer to the boundary region 23. In the example shown in FIG. 21 , the end face 42A of the second electrode portion 42 is provided along the side face 33A of the insulating layer 30. The side face 33A of the insulating layer 30 is inclined in the Z direction so that the opening area of ​​the diode opening 33 increases with increasing distance from the first surface 20S of the semiconductor layer 20. Therefore, the end face 42A of the second electrode portion 42 is inclined along the side face 33A of the insulating layer 30. Furthermore, an end of the second electrode portion 42 may be located on the insulating layer 30 beyond the diode opening 33. As a result, the entire diode opening 33 is covered by the end of the second electrode portion 42.

[0164] [RC-IGBT manufacturing method] A method for manufacturing the RC-IGBT 10 of the second embodiment will be described with reference to FIGS.

[0165] The manufacturing method of the RC-IGBT 10 of the second embodiment includes forming the boundary trench 71B, forming the boundary insulating layer 72B, and forming the boundary electrode 73B, but does not include forming the boundary well region 25W.

[0166] The boundary trench 71B is formed in a common process with the process of forming the gate trench 71G, the emitter trench 71E, and the diode trench 71D (see FIG. 8). That is, the boundary trench 71B is formed simultaneously with the gate trench 71G, the emitter trench 71E, and the diode trench 71D.

[0167] The boundary insulating layer 72B is formed in a common step with the step of forming the gate insulating layer 72G, the emitter insulating layer 72E, and the diode insulating layer 72D, i.e., the step of forming the first insulating layer 810 (see FIG. 9). In other words, the boundary insulating layer 72B is formed simultaneously with the gate insulating layer 72G, the emitter insulating layer 72E, and the diode insulating layer 72D.

[0168] The boundary electrode 73B is formed in the same step as the step of forming the gate electrode 73G, the field plate electrode 73E, and the diode electrode 73D, that is, the step of forming the first metal layer 820 (see FIG. 10). In other words, the boundary electrode 73B is formed simultaneously with the gate electrode 73G, the field plate electrode 73E, and the diode electrode 73D.

[0169] The second embodiment differs from the first embodiment in that a diode opening 33 is formed in the second insulating layer 830. Specifically, in the second embodiment, the diode opening 33 is formed so as to expose the diode region 22 but not the boundary region 23. As a result, the upper end surface of the boundary electrode 73B and the upper portion of the boundary trench 71B are covered with the second insulating layer 830. Through the above steps, the insulating layer 30 is formed.

[0170] The second embodiment differs from the first embodiment in that a first electrode layer 40 is formed. Specifically, as shown in FIG. 23, a resist mask 930 is formed on the insulating layer 30 in the boundary region 23. Then, as shown in FIG. 24, a fourth metal layer 860 is formed. The fourth metal layer 860 is formed on the insulating layer 30 and on the first surface 20S of the semiconductor layer 20 in the diode opening 33. In the second embodiment, the fourth metal layer 860 is composed of a single metal layer. The fourth metal layer 860 may be composed of aluminum silicon copper (AlSiCu). Then, the resist mask 930 is removed.

[0171] Next, the fourth metal layer 860 is patterned to form the first pad electrode 40P and the gate pad electrode 40G. Although not shown, the fourth metal layer 860 is formed in the peripheral region 12, so that a portion of the fourth metal layer 860 is embedded in the field opening. This forms the field connection electrode 105 (see FIG. 5). Subsequently, the fourth metal layer 860 is patterned to form the field electrode 106 and the channel stop electrode 111. In other words, the first pad electrode 40P, the gate pad electrode 40G, the field electrode 106, and the channel stop electrode 111 may be formed in a common process. The subsequent processes are the same as those in the first embodiment.

[0172] [Effects of the second embodiment] According to the RC-IGBT 10 of the second embodiment, the following effects can be obtained. (2-1) The RC-IGBT 10 includes a semiconductor layer 20 including a first surface 20S and an n-type drift region 28, an IGBT region 21 and a diode region 22 spaced apart in the X direction in a plan view seen from a direction perpendicular to the first surface 20S, a boundary region 23 provided between the IGBT region 21 and the diode region 22 in the X direction, a gate trench 71G and an emitter trench 71E provided corresponding to the IGBT region 21, a diode trench 71D provided corresponding to the diode region 22, a gate insulating layer 72G provided in the gate trench 71G, an emitter insulating layer 72E provided in the emitter trench 71E, a diode insulating layer 72D provided in the diode trench 71D, and a gate insulating layer 72G in the gate trench 71G. The semiconductor device includes a gate electrode 73G buried in a base insulating layer 72G, a field plate electrode 73E buried in the emitter insulating layer 72E in the emitter trench 71E, a diode electrode 73D buried in the diode insulating layer 72D in the diode trench 71D, a p-type base region 25B provided in the IGBT region 21, a p-type anode region 25A provided in the diode region 22, an insulating layer 30 provided on the first surface 20S to cover both the IGBT region 21 and the boundary region 23 while exposing the diode region 22, and a first electrode layer 40 including a first electrode portion 41 provided on the insulating layer 30 in the IGBT region 21 and a second electrode portion 42 provided on the first surface 20S in the diode region 22. The first electrode portion 41 and the second electrode portion 42 are arranged spaced apart from each other via the boundary region 23. The insulating layer 30 includes an exposed insulating portion 35 that is not covered by the first electrode layer 40 and is exposed in the boundary region 23 .

[0173] According to this configuration, the insulating layer 30 is provided in the boundary region 23, but the first electrode layer 40 is not provided. Therefore, the first electrode layer 40 is not in contact with the semiconductor layer 20 in the boundary region 23. Therefore, the occurrence of alloy spikes due to the first electrode layer 40 entering the trench can be suppressed, and the occurrence of leakage current can be suppressed.

[0174] (2-2) The insulating layer 30 includes a diode opening 33 that exposes the diode region 22. An end surface 42A of the second electrode portion 42 that is closer to the boundary region 23 contacts a side surface 33A of the insulating layer 30 that constitutes the diode opening 33.

[0175] This configuration makes it possible to increase the area where the second electrode portion 42 is in contact with the first surface 20S (anode region 25A) of the semiconductor layer 20 in the diode region 22. This allows the RC-IGBT 10 to have improved diode characteristics.

[0176] (2-3) The RC-IGBT 10 includes a boundary trench 71B provided corresponding to the boundary region 23, a boundary insulating layer 72B provided in the boundary trench 71B, and a boundary electrode 73B embedded in the boundary insulating layer 72B in the boundary trench 71B.

[0177] According to this configuration, the boundary trench 71B, the boundary insulating layer 72B, and the boundary electrode 73B can maintain a balance in the electric field strength in the IGBT region 21, the diode region 22, and the boundary region 23. Therefore, a decrease in the breakdown voltage of the RC-IGBT 10 can be suppressed.

[0178] (2-4) The boundary electrode 73B is electrically connected to at least one of the field plate electrode 73E and the diode electrode 73D. This configuration makes it possible to maintain a balance between the electric field strengths in the IGBT region 21, the diode region 22, and the boundary region 23. Therefore, a decrease in the breakdown voltage of the RC-IGBT 10 can be suppressed.

[0179] <Example of change> The above-described embodiments can be modified as follows: Furthermore, the above-described embodiments and the following modifications can be combined with each other within the scope of technical compatibility.

[0180] The first and second embodiments can be combined with each other. For example, the configuration of the first electrode layer 40 of the second embodiment may be applied to the configuration of the first embodiment. In the first embodiment, the formation range of the boundary well region 25W can be changed as desired. For example, as shown in FIG. 25 , the boundary well region 25W may be provided so as to contact the trench of the trench structure 70 closest to the boundary region 23 among the multiple trench structures 70 in the IGBT region 21 (the emitter trench 71E of the emitter trench structure 70E in the example shown in FIG. 25 ). Alternatively, the boundary well region 25W may be provided so as to contact the diode trench 71D closest to the boundary region 23 among the multiple diode trench structures 70D in the diode region 22. Even in this case, the boundary well region 25W is provided spaced apart from both the base region 25B and the anode region 25A.

[0181] In the first embodiment, the depth dimension HW of the boundary well region 25W can be changed as desired. For example, the depth dimension HW of the boundary well region 25W may be equal to the depth dimension HB of the base region 25B. For another example, the depth dimension HW of the boundary well region 25W may be smaller than the depth dimension HB of the base region 25B. For example, the depth dimension HW of the boundary well region 25W may be equal to the depth dimension HA of the anode region 25A. For another example, the depth dimension HW of the boundary well region 25W may be smaller than the depth dimension HA of the anode region 25A. For another example, the depth dimension HW of the boundary well region 25W may be equal to the depth dimension HG of the gate trench 71G. For another example, the depth dimension HW of the boundary well region 25W may be smaller than the depth dimension HG of the gate trench 71G. For another example, the depth dimension HW of the boundary well region 25W may be equal to the depth dimension HD of the diode trench 71D. In another example, the depth dimension HW of boundary well region 25W may be smaller than the depth dimension HD of diode trench 71D. Also, in one example, the depth dimension HW of boundary well region 25W may be equal to the depth dimension HE of emitter trench 71E. In another example, the depth dimension HW of boundary well region 25W may be smaller than the depth dimension HE of emitter trench 71E.

[0182] In the first embodiment, the width dimension WW of the boundary well region 25W can be changed as desired. For example, the boundary well region 25W may be provided in a portion of the boundary region 23 in the X direction. For example, the width dimension WW of the boundary well region 25W may be equal to the width dimension WG of the gate trench 71G. For another example, the width dimension WW of the boundary well region 25W may be smaller than the width dimension WG of the gate trench 71G. For another example, the width dimension WW of the boundary well region 25W may be equal to the width dimension WD of the diode trench 71D. For another example, the width dimension WW of the boundary well region 25W may be smaller than the width dimension WD of the diode trench 71D. For another example, the width dimension WW of the boundary well region 25W may be equal to the width dimension WE of the emitter trench 71E. For another example, the width dimension WW of the boundary well region 25W may be smaller than the width dimension WE of the emitter trench 71E.

[0183] In the first embodiment, the boundary well region 25W may be provided partially in the boundary region 23 in the Y direction. In the first embodiment, the p-type impurity concentration of the boundary well region 25W can be changed as desired. In one example, the p-type impurity concentration of the boundary well region 25W may be equal to the p-type impurity concentration of the base region 25B. In another example, the p-type impurity concentration of the boundary well region 25W may be lower than the p-type impurity concentration of the base region 25B. In another example, the p-type impurity concentration of the boundary well region 25W may be equal to the p-type impurity concentration of the anode region 25A. In another example, the p-type impurity concentration of the boundary well region 25W may be lower than the p-type impurity concentration of the anode region 25A. In another example, the p-type impurity concentration of the boundary well region 25W may be higher than the p-type impurity concentration of the guard ring 100. In another example, the p-type impurity concentration of the boundary well region 25W may be lower than the p-type impurity concentration of the guard ring 100.

[0184] In the first embodiment, the boundary well region 25W may be provided at a position that does not overlap the boundary between the collector region 26C and the cathode region 26K in plan view. In the first embodiment, the boundary well region 25W may be provided closer to the IGBT region 21 than the end 91 of the LTC region 90 in a plan view. In this case, the boundary well region 25W may be provided to a depth that allows it to overlap with the LTC region 90 when viewed from the X direction.

[0185] In the second embodiment, the second electrode portion 42 of the first electrode layer 40 may be provided at a position spaced apart from the side surface 33A that constitutes the diode opening 33 of the insulating layer 30. In the second embodiment, the boundary electrode 73B may be electrically connected to the gate electrode 73G instead of the diode electrode 73D. In another example, the boundary electrode 73B may be electrically connected to the field plate electrode 73E instead of the diode electrode 73D.

[0186] In the second embodiment, the formation range of the first electrode layer 40 (first pad electrode 40P) can be changed as desired. For example, as shown in FIG. 26 , the first pad electrode 40P may include a protruding portion 40PA in which a part of the first electrode portion 41 extends beyond the boundary between the IGBT region 21 and the boundary region 23 and into the boundary region 23. In another example, although not shown, the first pad electrode 40P may include a protruding portion in which a part of the second electrode portion 42 extends beyond the boundary between the diode region 22 and the boundary region 23 and into the boundary region 23. In other words, as long as the first electrode portion 41 and the second electrode portion 42 are provided at a distance from each other in the boundary region 23, a part of the first pad electrode 40P may be provided in the boundary region 23.

[0187] In the second embodiment, the boundary region 23 may be provided with a boundary well region 25W. In the second embodiment, the boundary electrode 73B of the boundary trench structure 70B may be electrically connected to the field plate electrode 73E instead of the diode electrode 73D. In another example, the boundary electrode 73B may be electrically connected to both the diode electrode 73D and the field plate electrode 73E. In another example, the boundary electrode 73B may be electrically connected to the gate electrode 73G instead of the diode electrode 73D.

[0188] In the second embodiment, the boundary trench structure 70B may be omitted. In the second embodiment, the end 91 of the LTC region 90 may be located in the diode region 22 .

[0189] In each embodiment, the LTC region 90 may be omitted. In each embodiment, the emitter trench structure 70E may be changed to a gate trench structure 70G.

[0190] In each embodiment, the configuration of the first electrode layer 40 can be changed as desired. For example, as shown in FIG. 27 , the first electrode layer 40 may have a stacked structure of a first conductive layer 44, a second conductive layer 45, and a third conductive layer 46. The first conductive layer 44 is a conductive layer in contact with the insulating layer 30. The first conductive layer 44 may be made of, for example, aluminum silicon copper (AlSiCu). The second conductive layer 45 is provided on the first conductive layer 44. The second conductive layer 45 may be made of, for example, titanium nitride. The third conductive layer 46 is provided on the second conductive layer 45. The third conductive layer 46 may be made of, for example, aluminum. The second conductive layer 45 may be made of titanium. The second conductive layer 45 is thinner than both the first conductive layer 44 and the third conductive layer 46. Although FIG. 27 shows a modified example of the first embodiment, the first electrode layer 40 of the second embodiment can also have a laminated structure of a first conductive layer 44, a second conductive layer 45, and a third conductive layer 46.

[0191] One or more of the various examples described in the present disclosure may be combined to the extent that they are not technically inconsistent. The term "on" as used in this disclosure includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" means that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0192] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" in the Z axis direction described in this disclosure being "up" and "down" in the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0193] <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0194] [Appendix 1] a semiconductor layer (20) including a first surface (20S) and a drift region (28) of a first conductivity type; an IGBT region (21) and a diode region (22) spaced apart in a first direction (X) in a plan view seen from a direction perpendicular to the first surface (20S); a boundary region (23) provided between the IGBT region (21) and the diode region (22) in the first direction (X); a first trench (71G, 71E) provided corresponding to the IGBT region (21); a second trench (71D) provided corresponding to the diode region (22); a first trench insulating layer (72G, 72E) provided in the first trench (71G, 71E); a second trench insulating layer (72D) provided in the second trench (71D); first buried electrodes (73G, 73E) buried in the first trench insulating layers (72G, 72E) in the first trenches (71G, 71E); a second buried electrode (73D) buried in the second trench insulating layer (72D) in the second trench (71D); a second conductivity type base region (25B) provided in the IGBT region (21); a second conductivity type anode region (25A) provided in the diode region (22); an insulating layer (30) provided on the first surface (20S) to cover the IGBT region (21) while exposing both the diode region (22) and the boundary region (23); an electrode layer (40) including a first electrode portion (41) provided on the insulating layer (30) in the IGBT region (21), a second electrode portion (42) provided on the first surface (20S) in the diode region (22), and a third electrode portion (43) provided on the first surface (20S) in the boundary region (23); Including, the boundary region (23) includes a boundary well region (25W) of a second conductivity type; The boundary well region (25W) is provided spaced apart from both the base region (25B) and the anode region (25A) in the first direction (X). RC-IGBT(10).

[0195] [Appendix 2] The depth dimension (HW) of the boundary well region (25W) is greater than both the depth dimension (HB) of the base region (25B) and the depth dimension (HA) of the anode region (25A). RC-IGBT as described in Appendix 1.

[0196] [Appendix 3] The depth dimension (HW) of the boundary well region (25W) is greater than both the depth dimensions (HG, HE) of the first trenches (71G, 71E) and the depth dimension (HD) of the second trench (71D). RC-IGBTs as described in Appendix 1 or 2.

[0197] [Appendix 4] The boundary well region (25W) is provided apart from at least one of the first trenches (71G, 71E) and the second trench (71D) in the first direction (X). 10. The RC-IGBT according to claim 1, wherein the RC-IGBT is a conductor.

[0198] [Appendix 5] The semiconductor layer (20) is a second surface (20R) opposite to the first surface (20S); a collector region (26C) provided in a portion close to the second surface (20R) and at a position corresponding to the IGBT region (21); a cathode region (26K) provided in a portion close to the second surface (20R) and at a position corresponding to the diode region (22); Including, the boundary between the collector region (26C) and the cathode region (26K) is located in the boundary region (23); The boundary well region (25W) is provided so as to overlap the boundary between the collector region (26C) and the cathode region (26K) in a plan view. 10. The RC-IGBT according to claim 1, wherein the RC-IGBT is a conductor.

[0199] [Appendix 6] a lifetime control region (90) provided in the semiconductor layer (20) and overlapping the diode region (21) and the boundary region (23) in a plan view; The boundary well region (25W) is provided so as to overlap the end (91) of the lifetime control region (90) in a plan view. 10. The RC-IGBT according to claim 1, wherein the RC-IGBT is a conductor.

[0200] [Appendix 7] The boundary well region (25W) is provided closer to the first surface (20S) than the lifetime control region (90). RC-IGBT as described in Appendix 6.

[0201] [Appendix 8] The impurity concentration of the boundary well region (25W) is higher than both the impurity concentration of the base region (25B) and the impurity concentration of the anode region (25A). 10. The RC-IGBT according to any one of appendices 1 to 7.

[0202] [Appendix 9] a cell region (11) including the IGBT region (21), the diode region (22), and the boundary region (23); an outer peripheral region (12) surrounding the cell region (11) in a plan view; a guard ring (100) provided in the outer peripheral region (12); Including, The impurity concentration of the boundary well region (25W) is equal to the impurity concentration of the guard ring (100). 10. The RC-IGBT according to any one of appendices 1 to 8.

[0203] [Appendix 10] The width dimension (WW) of the boundary well region (25W) is larger than both the width dimensions (WG, WE) of the first trenches (71G, 71E) and the width dimension (WD) of the second trench (71D). 10. The RC-IGBT according to any one of Supplementary Notes 1 to 9.

[0204] [Appendix 11] The width dimension (WW) of the boundary well region (25W) is greater than both the distance (DEG) between the first trenches (71G, 71E) adjacent to each other in the first direction (X) and the distance (DD) between the second trenches (71D) adjacent to each other in the first direction (X). 11. The RC-IGBT according to any one of Supplementary Notes 1 to 10.

[0205] [Appendix 12] The boundary well region (25W) is provided over the entire boundary region (23) in the first direction (X). 12. The RC-IGBT according to any one of Supplementary Notes 1 to 11.

[0206] [Appendix 13] A direction perpendicular to the first direction (X) in a plan view is defined as a second direction (Y), The boundary well region (25W) is provided over the entire boundary region (23) in the second direction (Y). 13. The RC-IGBT according to any one of Supplementary Notes 1 to 12.

[0207] [Appendix 14] a semiconductor layer (20) including a first surface (20S) and a drift region (28) of a first conductivity type; an IGBT region (21) and a diode region (22) spaced apart in a first direction (X) in a plan view seen from a direction perpendicular to the first surface (20S); a boundary region (23) provided between the IGBT region (21) and the diode region (22) in the first direction (X); a first trench (71G, 71E) provided corresponding to the IGBT region (21); a second trench (71D) provided corresponding to the diode region (22); a first trench insulating layer (72G, 72E) provided in the first trench (71G, 71E); a second trench insulating layer (72D) provided in the second trench (71D); first buried electrodes (73G, 73E) buried in the first trench insulating layers (72G, 72E) in the first trenches (71G, 71E); a second buried electrode (73D) buried in the second trench insulating layer (72D) in the second trench (71D); a second conductivity type base region (25B) provided in the IGBT region (21); a second conductivity type anode region (25A) provided in the diode region (22); an insulating layer (30) provided on the first surface (20S) to cover both the IGBT region (21) and the boundary region (23) while exposing the diode region (22); an electrode layer (40) including a first electrode portion (41) provided on the insulating layer (30) in the IGBT region (21) and a second electrode portion (42) provided on the first surface (20S) in the diode region (22); Including, the first electrode portion (41) and the second electrode portion (42) are disposed apart from each other via the boundary region (23), The insulating layer (30) includes an exposed insulating portion (35) that is not covered by the electrode layer (40) in the boundary region (23). RC-IGBT(10).

[0208] [Appendix 15] In the boundary region (23), the drift region (28) forms a part of the first surface (20S) of the semiconductor layer (20). RC-IGBT as described in Appendix 14.

[0209] [Appendix 16] the insulating layer (30) includes a diode opening (33) that exposes the diode region (22); An end face (42A) of the second electrode portion (42) closer to the boundary region (23) is in contact with a side face (33A) of the insulating layer (30) that forms the diode opening (33). 16. The RC-IGBT described in Appendix 14 or 15.

[0210] [Appendix 17] a third trench (71B) provided in correspondence with the boundary region (23); a third trench insulating layer (72B) provided in the third trench (71B); a third buried electrode (73B) buried in the third trench insulating layer (72B) in the third trench (71B); Contains 17. The RC-IGBT according to any one of Supplementary Notes 14 to 16.

[0211] [Appendix 18] The third buried electrode (73B) is electrically connected to at least one of the first buried electrode (73E) and the second buried electrode (73D). RC-IGBT as described in Appendix 17.

[0212] [Appendix 19] The semiconductor layer (20) is a second surface (20R) opposite to the first surface (20S); a collector region (26C) provided in a portion close to the second surface (20R) and at a position corresponding to the IGBT region (21); a cathode region (26K) provided in a portion close to the second surface (20R) and at a position corresponding to the diode region (22); Including, The boundary between the collector region (26C) and the cathode region (26K) is located in the boundary region (23). 19. The RC-IGBT according to any one of Supplementary Notes 14 to 18.

[0213] [Appendix 20] a lifetime control region (90) provided in the semiconductor layer (20) and overlapping the diode region (22) and the boundary region (23) in a plan view; The end (91) of the lifetime control region (90) is located in the boundary region (23). 20. The RC-IGBT according to any one of Supplementary Notes 14 to 19.

[0214] [Appendix 21] The electrode layer (40) exposes the entire portion of the insulating layer (30) that corresponds to the boundary region (23). 21. The RC-IGBT according to any one of Supplementary Notes 14 to 20.

[0215] [Appendix 22] The first electrode portion (41) partially covers a portion of the insulating layer (30) corresponding to the boundary region (23). 21. The RC-IGBT according to any one of Supplementary Notes 14 to 20.

[0216] [Appendix 23] a well region (120) surrounding the cell region (11) in a plan view; The impurity concentration of the boundary well region (25W) is equal to the impurity concentration of the well region (120). RC-IGBT as described in Appendix 9.

[0217] [Appendix 24] forming a semiconductor layer (800) including a first surface (801) provided with an IGBT region (21), a diode region (22), and a boundary region (23); forming an insulating layer (30) on the first surface (801) so as to cover the IGBT region (21) while exposing both the diode region (22) and the boundary region (23); forming a base region (25B) in the IGBT region (21) of the first surface (801); forming an anode region (25A) in the diode region (22) of the first surface (801); forming a boundary well region (25W) in the boundary region (23) of the first surface (801); forming an electrode layer (40) over the IGBT region (21), the boundary region (23), and the diode region (22); Including, The formation of the electrode layer (40) forming a first electrode portion (41) on the insulating layer (30) corresponding to the IGBT region (21); forming a second electrode portion (42) on the first surface (801) corresponding to the diode region (22); forming a third electrode portion (43) on the first surface (801) corresponding to the boundary region (23); Contains A manufacturing method of RC-IGBT (10).

[0218] [Appendix 25] forming a semiconductor layer (800) including a first surface (801) provided with an IGBT region (21), a diode region (22), and a boundary region (23); forming an insulating layer (30) on the first surface (801) so as to cover the IGBT region (21) while exposing both the diode region (22) and the boundary region (23); forming an electrode layer (40) over the IGBT region (21), the boundary region (23), and the diode region (22); Including, The formation of the electrode layer (40) forming a first electrode portion (41) on the insulating layer (30) corresponding to the IGBT region (21); forming a second electrode portion (42) on the first surface (801) corresponding to the diode region (22); Including, The first electrode portion (41) and the second electrode portion (42) are formed to be spaced apart from each other via the boundary region (23). A manufacturing method of RC-IGBT (10).

[0219] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0220] 10...Semiconductor device 11...Cell area 12...Outer area 20...Semiconductor layer 20S...Side 1 20R...2nd stage 20A...Sub-area 20P…1st area 20Q…Second area 21…IGBT area 21A IGBT 22...Diode region 22A...Diode 23…boundary area 24...Emitter area 25B...base area 25A...Anode area 25W…Border well area 26C...Collector region 26K...cathode region 27...Buffer area 28...Drift region 29...Carrier storage area 30...insulating layer 30S…Top surface 31...First insulating layer 32...Second insulating layer 33...Diode opening 33A…Side 34...Outer insulating layer 34A...Field opening 35...Exposed insulation 40...First electrode layer 40G...Gate pad electrode 40P...First pad electrode 40PA...protruding part 40R...protruding electrode part 41...First electrode part 42…Second electrode part 42A…End face 43…Third electrode part 44...First conductive layer 45...Second conductive layer 46...Third conductive layer 50...Gate wiring 51...Gate Finger 60…Second electrode layer 70...Trench structure 70G...Gate trench structure 71G...Gate trench 72G...Gate insulating layer 73G...Gate electrode 70E...Emitter trench structure 71E…Emitter trench 72E...Emitter insulating layer 73E...Field plate electrode 70D...Diode trench structure 71D...Diode trench 72D...Diode insulating layer 73D...Diode electrode 70B...Boundary trench structure 71B...Boundary trench 72B...Boundary insulation layer 73B…boundary electrode 80...Contact structure 81...Contact hole 82...Emitter contact 82A...First conductive layer 82B…Second conductive layer 83...Base contact region 90...LTC region (lifetime control region) 91...End 100...Guard Ring 101~104...Field area 105...Field connection electrode 106...Field electrode 106A...drawer section 110...Channel stop region 111...Channel stop electrode 120...Well area 121...Common-law marriage 122...Outer edge 123...Well connecting electrode 800...Semiconductor wafers 801...Side 1 802…Second side 810...First insulating layer 820...first metal layer 830...Second insulating layer 840…Second metal layer 850…Third metal layer 860…4th metal layer 900...Resist mask 910...Mask 920...Resist mask 930...Resist mask DD: Distance between adjacent diode trenches DEG: Distance between emitter trench and gate trench HA: Depth dimension of the anode area HB: Depth dimension of base area HD: Diode trench depth HE: Emitter trench depth HF...Field area depth dimension HG: Gate trench depth HP: Depth dimension of well area HW: Depth dimension of the boundary well area PT...Pitch WD: Width of diode trench WE: Emitter trench width WF: Width of the field area WG: Gate trench width WW: Width of the boundary well area

Claims

1. a semiconductor layer including a first surface and a drift region of a first conductivity type; an IGBT region and a diode region spaced apart in a first direction in a plan view seen from a direction perpendicular to the first surface; a boundary region provided between the IGBT region and the diode region in the first direction; a first trench provided corresponding to the IGBT region; a second trench provided corresponding to the diode region; a first trench insulating layer provided in the first trench; a second trench insulating layer provided in the second trench; a first buried electrode buried in the first trench insulating layer in the first trench; a second buried electrode buried in the second trench insulating layer in the second trench; a second conductivity type base region provided in the IGBT region; an anode region of a second conductivity type provided in the diode region; an insulating layer provided on the first surface to cover the IGBT region while exposing both the diode region and the boundary region; an electrode layer including a first electrode portion provided on the insulating layer in the IGBT region, a second electrode portion provided on the first surface in the diode region, and a third electrode portion provided on the first surface in the boundary region; Including, the boundary region includes a boundary well region of a second conductivity type; The boundary well region is spaced apart from both the base region and the anode region in the first direction. RC-IGBT.

2. The depth dimension of the boundary well region is greater than both the depth dimension of the base region and the depth dimension of the anode region. The RC-IGBT according to claim 1.

3. The depth dimension of the boundary well region is greater than both the depth dimension of the first trench and the depth dimension of the second trench. The RC-IGBT according to claim 1.

4. The boundary well region is spaced apart from at least one of the first trench and the second trench in the first direction. The RC-IGBT according to claim 1.

5. The semiconductor layer is a second surface opposite the first surface; a collector region provided in a portion close to the second surface and at a position corresponding to the IGBT region; a cathode region provided in a portion close to the second surface and at a position corresponding to the diode region; Including, a boundary between the collector region and the cathode region is located in the boundary region; The boundary well region is provided so as to overlap the boundary between the collector region and the cathode region in a plan view. The RC-IGBT according to claim 1.

6. a lifetime control region provided in the semiconductor layer and overlapping the diode region and the boundary region in a plan view; The boundary well region is provided so as to overlap an end of the lifetime control region in a plan view. The RC-IGBT according to claim 1.

7. The boundary well region is provided closer to the first surface than the lifetime control region. The RC-IGBT according to claim 6.

8. The impurity concentration of the boundary well region is higher than both the impurity concentration of the base region and the impurity concentration of the anode region. The RC-IGBT according to claim 1.

9. a cell region including the IGBT region, the diode region, and the boundary region; a peripheral region surrounding the cell region in a plan view; a guard ring provided in the outer circumferential region; Including, The impurity concentration of the boundary well region is equal to the impurity concentration of the guard ring. The RC-IGBT according to claim 1.

10. The width dimension of the boundary well region is greater than both the width dimension of the first trench and the width dimension of the second trench. The RC-IGBT according to claim 1.

11. The width dimension of the boundary well region is greater than both the distance between the first trenches adjacent to each other in the first direction and the distance between the second trenches adjacent to each other in the first direction. The RC-IGBT according to claim 1.

12. The boundary well region is provided across the entire boundary region in the first direction. The RC-IGBT according to claim 1.

13. A direction perpendicular to the first direction in a plan view is defined as a second direction, The boundary well region is provided across the entire boundary region in the second direction. The RC-IGBT according to any one of claims 1 to 12.

14. a semiconductor layer including a first surface and a drift region of a first conductivity type; an IGBT region and a diode region spaced apart in a first direction in a plan view seen from a direction perpendicular to the first surface; a boundary region provided between the IGBT region and the diode region in the first direction; a first trench provided corresponding to the IGBT region; a second trench provided corresponding to the diode region; a first trench insulating layer provided in the first trench; a second trench insulating layer provided in the second trench; a first buried electrode buried in the first trench insulating layer in the first trench; a second buried electrode buried in the second trench insulating layer in the second trench; a second conductivity type base region provided in the IGBT region; an anode region of a second conductivity type provided in the diode region; an insulating layer provided on the first surface to cover both the IGBT region and the boundary region while exposing the diode region; an electrode layer including a first electrode portion provided on the insulating layer in the IGBT region and a second electrode portion provided on the first surface in the diode region; Including, the first electrode portion and the second electrode portion are disposed apart from each other via the boundary region, The insulating layer includes an exposed insulating portion that is not covered by the electrode layer in the boundary region. RC-IGBT.

15. In the boundary region, the drift region forms a part of the first surface of the semiconductor layer. The RC-IGBT according to claim 14.

16. the insulating layer includes a diode opening exposing the diode region; An end face of the second electrode portion closer to the boundary region is in contact with a side face of the insulating layer that forms the diode opening. The RC-IGBT according to claim 14.

17. a third trench provided corresponding to the boundary region; a third trench insulating layer provided in the third trench; a third buried electrode buried in the third trench insulating layer in the third trench; Contains The RC-IGBT according to claim 14.

18. The third buried electrode is electrically connected to at least one of the first buried electrode and the second buried electrode. The RC-IGBT according to claim 17.

19. The semiconductor layer is a second surface opposite the first surface; a collector region provided in a portion close to the second surface and at a position corresponding to the IGBT region; a cathode region provided in a portion close to the second surface and at a position corresponding to the diode region; Including, The boundary between the collector region and the cathode region is located in the boundary region. The RC-IGBT according to claim 14.

20. a lifetime control region provided in the semiconductor layer and overlapping the diode region and the boundary region in a plan view; The end of the lifetime control region is located in the boundary region. The RC-IGBT according to any one of claims 14 to 19.

Images