Laminated structure and electronic device

Abstract

To provide a laminated structure and an electronic device capable of improving insulation of a dielectric film and reducing a leakage current flowing between a lower electrode and an upper electrode.SOLUTION: The multilayer structure 10 includes a conductor film 13 formed on the substrate 11, a dielectric film 14 formed on the conductor film 13, and a conductor film 15 formed on the dielectric film 14. The dielectric film 14 includes a crystallized layer 14a which is expressed by the following compositional formula (Chemical Formula 1) and is crystallized, and x satisfies 0 ≤ x ≤ 1. The dielectric film 14 includes an amorphous layer 14a interposed between the crystallized layer 14b and the conductor film 15, or the conductor film 15 is directly formed on the crystallized layer 14a. When the dielectric film 14 includes the amorphous layer 14b, the ratio of the thickness of the amorphous layer 14a to the thickness of the crystallized layer 14b is 0.5% or less. Pb (Zr1-xTix) O3 (Chemical Formula 1) SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a laminated structure and an electronic device. [Background technology]

[0002] Dielectric films made of lead zirconate titanate (Pb(Zr,Ti)O3) (hereinafter referred to as PZT), which has excellent piezoelectric and ferroelectric properties, are being investigated, and such dielectric films are being applied to memory elements such as nonvolatile memory (FeRAM), as well as MEMS (Micro Electro Mechanical Systems) technology such as inkjet heads and acceleration sensors.

[0003] Japanese Patent No. 6498821 (Patent Document 1) discloses a technology for a film structure including a silicon substrate having a main surface formed of a (100) plane, a first film formed on the main surface, including a first zirconium oxide film having a cubic crystal structure and oriented in a (100) direction, and a conductive film serving as a lower electrode formed on the first film, including a platinum film having a cubic crystal structure and oriented in a (100) direction. In the technology described in Patent Document 1, the film structure includes a piezoelectric film formed on the conductive film serving as the lower electrode, including a lead zirconate titanate film having a tetragonal crystal structure and oriented in a (001) direction. Furthermore, in the technology described in Patent Document 1, when the film structure includes a conductive film serving as an upper electrode formed on the piezoelectric film, a ferroelectric capacitor is formed by the lower electrode, the piezoelectric film, and the upper electrode. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 6498821 Summary of the Invention [Problem to be solved by the invention]

[0005] In the technology described in Patent Document 1, if the insulating properties of the dielectric film are not sufficiently ensured, it is difficult to reduce the leakage current that flows between the lower electrode and the upper electrode when an electric field is applied between them. Furthermore, if the insulating properties of the dielectric film are not sufficiently ensured, it is not possible to apply a large electric field to the dielectric film, making it difficult to improve the electrical properties of the dielectric film, such as the piezoelectricity and ferroelectricity.

[0006] The present invention aims to provide a laminated structure having a dielectric film formed on a substrate, and an electronic device equipped with the laminated structure, which can improve the insulating properties of the dielectric film and reduce the leakage current that flows between a lower electrode and an upper electrode when an electric field is applied between the lower electrode and the upper electrode, and an electronic device equipped with the laminated structure. [Means for solving the problem]

[0007] As a result of extensive investigation, the present inventors have found that the above-mentioned problems can be solved by the following configuration. [1] A substrate; a first conductive film formed on the substrate; a dielectric film formed on the first conductive film; a second conductive film formed on the dielectric film; In a laminated structure having The dielectric film includes a crystallized layer that is represented by the following composition formula (Chemical Formula 1) and is crystallized: Pb(Zr 1-x Ti x )O3...(Chemical 1) wherein x satisfies 0≦x≦1; the dielectric film is interposed between the crystallized layer and the second conductive film and includes an amorphous layer containing Pb, Zr, or Ti, or the second conductive film is formed directly on the crystallized layer; A laminated structure, wherein when the dielectric film includes the amorphous layer, the ratio of the thickness of the amorphous layer to the thickness of the crystallized layer is 0.5% or less. [2] The second conductive film is made of Pt, The stacked structure according to [1], wherein the difference between the work function of the second conductive film and 5.93 eV is larger than the difference between the work function of the second conductive film and 5.66 eV. [3] A substrate; a first conductive film formed on the substrate; a dielectric film formed on the first conductive film; a second conductive film formed on the dielectric film; In a laminated structure having The dielectric film includes a crystallized layer that is represented by the following composition formula (Chemical Formula 1) and is crystallized: Pb(Zr 1-x Ti x )O3...(Chemical 1) wherein x satisfies 0≦x≦1; the second conductive film is made of Pt, a stacked structure in which the difference between the work function of the second conductive film and 5.93 eV is larger than the difference between the work function of the second conductive film and 5.66 eV. [4] A substrate; a first conductive film formed on the substrate; a dielectric film formed on the first conductive film; a second conductive film formed on the dielectric film; In a laminated structure having The dielectric film includes a crystallized layer that is represented by the following composition formula (Chemical Formula 1) and is crystallized: Pb(Zr 1-x Ti x )O3...(Chemical 1) wherein x satisfies 0≦x≦1; A laminated structure in which, when a cross section of the laminated structure along the lamination direction is observed at a magnification of 100,000 to 1,000,000 times using a scanning transmission electron microscope, an intervening layer between the crystallized layer and the second conductive film cannot be visually recognized. [5] The first conductive film is epitaxially grown on the substrate; the crystallized layer is epitaxially grown on the first conductive film, The laminated structure according to any one of [1] to [4], wherein the second conductive film is epitaxially grown directly on the crystallized layer. [6] The first conductive film is epitaxially grown on the substrate; the crystallized layer is epitaxially grown on the first conductive film, The laminated structure according to [1] or [4], wherein the second conductive film is made of Pt epitaxially grown directly on the crystallized layer. [7] The substrate includes a main surface; the laminated structure further includes a buffer film formed on the main surface, the first conductive film is formed on the buffer film; the substrate is a Si substrate or an SOI substrate including a base body made of a Si substrate, an insulating layer on the base body, and an SOI layer on the insulating layer; The buffer film is made of a metal oxide represented by the following composition formula (Chemical Formula 2) or a metal nitride represented by the following composition formula (Chemical Formula 3), (Hf 1-y Zr y )O2...(Chemical 2) (Hf 1-z Zr z )N...(C3) The y satisfies 0≦y<1 or y=1, The multilayer structure according to any one of [1] to [6], wherein z satisfies 0≦z≦1. [8] The substrate is a Si(100) substrate including a main surface made of a Si(100) plane, or an SOI substrate including: a base body made of a Si substrate; the insulating layer on the base body; and the SOI layer made of a Si(100) film on the insulating layer and including the main surface made of a Si(100) plane; the buffer film is made of the metal oxide oriented in a (100) plane in a pseudo cubic crystal representation or the metal nitride oriented in a (100) plane in a pseudo cubic crystal representation, the first conductive film is made of Pt oriented in a (100) cubic crystal representation, the dielectric film includes the crystallized layer oriented in a (100) direction in the pseudocubic crystal representation, The laminated structure according to [7], wherein the second conductive film is made of Pt oriented in a (100) plane in cubic crystal representation. [9] At 30°C, 1 × 10 8 When an electric field of 1.83 × 10 V / cm is applied, the leakage current density flowing between the first conductive film and the second conductive film is 1.83 × 10 -7 A / cm 2 The laminate structure according to any one of [1] to [8], wherein

[10] The thickness of the dielectric film is 100 to 200 nm; The horizontal axis is in V and the vertical axis is in μC / cm 2 The laminated structure according to any one of [1] to [9], wherein, in a polarization voltage hysteresis curve obtained by plotting the polarization of the dielectric film when a voltage is applied between the first conductive film and the second conductive film, the average slope angle of the curve portion showing the voltage dependence of the polarization when the voltage is reduced from a maximum voltage to 0 is 9.5 to 10.37°.

[11] An electronic device comprising the laminated structure according to any one of [1] to

[10] . [Effects of the Invention]

[0008] The laminated structure of the present invention and an electronic device including the laminated structure can improve the insulating properties of the dielectric film and reduce the leakage current that flows between the lower electrode and the upper electrode when an electric field is applied between the lower electrode and the upper electrode. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view showing an example of a laminated structure according to a first embodiment. [Figure 2] FIG. 3 is a cross-sectional view showing another example of the laminated structure of the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view showing another example of the laminated structure of the first embodiment. [Figure 4] FIG. 3 is a cross-sectional view showing another example of the laminated structure of the first embodiment. [Figure 5] FIG. 10 is a cross-sectional view of an electronic device according to a second embodiment. [Figure 6] 1 is a graph showing the diffraction pattern of the laminated structure of Example 1. [Figure 7] 1 is a graph showing a φ scan of the laminated structure of Example 1. [Figure 8] 1 is a graph showing the diffraction pattern of the laminated structure of Example 1. [Figure 9] 1 is a graph showing a φ scan of the laminated structure of Example 1. [Figure 10] 1 is a graph showing a φ scan of the laminated structure of Example 1. [Figure 11] 1 is a graph showing the diffraction pattern of the laminated structure of Example 1. [Figure 12] 10 is a graph showing a diffraction pattern of a laminated structure of a comparative example. [Figure 13] 1 is a photograph showing a cross-sectional STEM image of the layered structure of Example 1. [Figure 14] 1 is a graph showing the voltage dependence of polarization of the laminated structure of Example 1. [Figure 15] FIG. 10 is a diagram for explaining a method for calculating the average slope angle of a polarization voltage hysteresis loop. [Figure 16] 10 is a graph showing the voltage dependence of polarization of the laminated structure of Example 2. [Figure 17] 10 is a graph showing the voltage dependence of polarization of the laminated structure of Example 2. [Figure 18] 1 is a graph showing the measurement results of leakage current of the stacked structure of Example 1. [Figure 19] 1 is a graph showing the measurement results of leakage current of the stacked structure of Example 1. [Figure 20] 1 is a graph showing the measurement results of leakage current of the stacked structure of Example 1. [Figure 21] 1 is a graph showing the measurement results of leakage current of the stacked structure of Example 1. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, each embodiment of the present invention will be described with reference to the drawings.

[0011] (Embodiment 1) First, a description will be given of the laminated structure of embodiment 1. Fig. 1 is a cross-sectional view showing an example of the laminated structure of embodiment 1. Figs. 2 to 4 are cross-sectional views showing other examples of the laminated structure of embodiment 1.

[0012] The laminated structure 10 shown in Figures 1 to 4 has a substrate 11 including a main surface 11p, a buffer film 12 formed on the main surface 11p, a conductive film (first conductive film) 13 formed on the buffer film 12, a dielectric film 14 formed on the conductive film 13, and a conductive film (second conductive film) 15 formed on the dielectric film 14.

[0013] 1 and 2, the substrate 11 is a silicon (Si)(100) substrate including a main surface 11p made of a Si(100) plane. In the example shown in Figures 3 and 4, the substrate 11 is an SOI (Silicon On Insulator) substrate including a base 11a made of a Si substrate, an insulating layer 11b on the base 11a, and an SOI (Silicon On Insulator) layer 11c made of a Si(100) film on the insulating layer 11b and including the main surface 11p made of a Si(100) plane.

[0014] The buffer film 12 is epitaxially grown on the main surface 11p, has a (100) orientation in pseudo cubic crystal notation, and is made of a metal oxide represented by the following composition formula (Chemical Formula 4), or a metal nitride represented by the following composition formula (Chemical Formula 5): That is, the buffer film 12 is made of a metal oxide of hafnium (Hf) and / or zirconium (Zr), or a metal nitride of Hf and / or Zr. (Hf 1-y Zr y )O2...(Chemical 4) (Hf 1-z Zr z )N...(C5) In the above compositional formula (Formula 4), y satisfies 0 ≦ y < 1 or y = 1, and in the above compositional formula (Formula 5), z satisfies 0 ≦ z ≦ 1. Note that the above compositional formula (Formula 4) is the same compositional formula as the above compositional formula (Formula 2), and the above compositional formula (Formula 5) is the same compositional formula as the above compositional formula (Formula 3).

[0015] In the present specification, when a metal oxide or a metal nitride is (100)-oriented in a pseudo-cubic crystal representation, it means that the metal oxide or the metal nitride has a cubic crystal structure at room temperature and is (100)-oriented, or even if it has a tetragonal or monoclinic crystal structure at room temperature, it is (100)-oriented when it undergoes a phase transition to have a cubic crystal structure at a high temperature. Further, hereinafter, among the metal oxides represented by the above compositional formula (Formula 4), when y = 0, it is HfO2, and when y = 1, it is ZrO2, but the case where 0 < y < 1 is sometimes referred to as HZO. Further, hereinafter, among the metal nitrides represented by the above compositional formula (Formula 5), when z = 0, it is HfN, and when z = 1, it is ZrN, but the case where 0 < z < 1 is sometimes referred to as HZN.

[0016] In the present specification, when a certain film is epitaxially grown, it means that the film is oriented in any of three directions orthogonal to each other, that is, three-dimensionally oriented.

[0017] The conductor film 13 is epitaxially grown on the buffer film 12, is made of platinum (Pt), and is (100)-oriented in a cubic crystal representation.

[0018] The dielectric film 14 is epitaxially grown on the conductor film 13 and includes a crystallized layer 14a represented by the following compositional formula (Formula 6) and crystallized. That is, the crystallized layer 14a is made of a metal oxide of lead (Pb) and zirconium (Zr) and / or titanium (Ti). Pb(Zr 1-x Ti x )O3···(Formula 6) In the above composition formula (Chemical Formula 6), x satisfies 0≦x≦1. Note that the above composition formula (Chemical Formula 6) is the same as the above composition formula (Chemical Formula 1). In the following, the metal oxide represented by the above composition formula (Chemical Formula 6) may be referred to as lead zirconate titanate (PZT).

[0019] The conductive film 15 is made of Pt and is formed on the dielectric film 14. That is, in the stacked structure 10 of the first embodiment, the conductive film 13 functions as a lower electrode, and the conductive film 15 functions as an upper electrode.

[0020] The dielectric film 14 includes an amorphous layer 14b containing Pb, Zr, or Ti and interposed between the crystallized layer 14a and the conductive film 15, or the conductive film 15 is formed directly on the crystallized layer 14a. Here, the amorphous layer 14b is formed when excess Pb or amorphous portions of uncrystallized PZT are pushed onto the crystallized layer 14a or deposited on the crystallized layer 14a during the crystallization of PZT to form the crystallized layer 14a. In the example shown in FIGS. 1 and 3, the dielectric film 14 includes the amorphous layer 14b. In the example shown in FIGS. 2 and 4, the amorphous layer 14b (see FIGS. 1 and 3) is not interposed between the crystallized layer 14a and the conductive film 15, and the conductive film 15 is formed directly on the crystallized layer 14a.

[0021] 1 and 3, when the dielectric film 14 includes an amorphous layer 14b, the ratio of the thickness of the amorphous layer 14b to the thickness of the crystallized layer 14a is 0.5% or less. When the ratio of the thickness of the amorphous layer 14b to the thickness of the crystallized layer 14a is 0.5% or less, the conductive film 15 serving as the upper electrode is more likely to grow epitaxially directly on the crystallized layer 14a made of PZT contained in the dielectric film 14, compared to when the ratio of the thickness of the amorphous layer 14b to the thickness of the crystallized layer 14a exceeds 0.5%. Whether the conductive film 15 serving as the upper electrode has grown epitaxially can be easily determined, for example, by X-ray diffraction measurement, as will be described later with reference to FIGS. 11 and 12.

[0022] The dielectric film 14 can be formed by, for example, a sputtering method. When forming the dielectric film 14 by a sputtering method, in order to prevent the amorphous layer 14b from being interposed between the crystallized layer 14a and the conductor film 15 or to ensure that the ratio of the thickness of the amorphous layer 14b to the thickness of the crystallized layer 14a is 0.5% or less, for example, the amorphous layer 14b formed on the upper surface of the dielectric film 14 can be removed by etching after the dielectric film 14 is formed. Alternatively, when the dielectric film 14 is successively formed by a sputtering method, for example, the substrate 11 can be temporarily cooled from a temperature higher than the film-forming temperature for PZT to a temperature lower than the film-forming temperature, the amorphous layer 14b formed on the upper surface of the dielectric film 14 on the cooled substrate 11 can be etched with plasma, and then the substrate 11 can be temporarily heated again from a temperature lower than the film-forming temperature to a temperature higher than the film-forming temperature. This process can be repeated intermittently to remove the amorphous layer 14b formed on the upper surface of the dielectric film 14.

[0023] In the technology described in Patent Document 1, if the insulating properties of the dielectric film are not sufficiently ensured, it is difficult to reduce the leakage current that flows between the lower electrode and the upper electrode when an electric field is applied between them. Furthermore, if the insulating properties of the dielectric film are not sufficiently ensured, it is not possible to apply a large electric field to the dielectric film, making it difficult to improve the electrical properties of the dielectric film, such as the piezoelectricity and ferroelectricity.

[0024] For example, the presence of an amorphous layer between the dielectric film and the upper electrode reduces the energy barrier between the upper electrode and the dielectric film, making it easier for charges to be injected from the upper electrode into the PZT contained in the dielectric film, which could result in the dielectric film not having sufficient insulating properties.

[0025] Furthermore, assuming that the PZT contained in the dielectric film has become a p-type semiconductor due to lead deficiency or the like, when the work function of the upper electrode is large, the energy barrier between the upper electrode and the dielectric film becomes small, making it easier for charge to be injected from the upper electrode into the PZT contained in the dielectric film, and there is a risk that the insulating properties of the dielectric film will not be sufficiently ensured.

[0026] Furthermore, because an amorphous layer having a lower dielectric constant than the crystallized layer is present between the dielectric film and the upper electrode, when a voltage is applied between the lower electrode and the upper electrode, the voltage applied to the PZT contained in the dielectric film decreases, which could result in a deterioration of the electrical properties of the dielectric film, such as its piezoelectricity and ferroelectricity.

[0027] On the other hand, in the stacked structure of the first embodiment, the stacked structure 10 includes an amorphous layer 14b containing Pb, Zr, or Ti and interposed between the crystallized layer 14a of the dielectric film 14 and the conductive film 15, or the conductive film 15 is formed directly on the crystallized layer 14a. In the stacked structure of the first embodiment, the insulating properties of the dielectric can be improved compared to the technique described in Patent Document 1. Therefore, for example, when an electric field is applied between the lower electrode and the upper electrode, the leakage current flowing between the lower electrode and the upper electrode can be reduced.

[0028] In the stacked structure of the present embodiment 1, for example, by not having an amorphous layer interposed between the dielectric film 14 and the conductive film 15 serving as the upper electrode, or by reducing the thickness of the amorphous layer that is interposed, the energy barrier between the conductive film 15 serving as the upper electrode and the dielectric film 14 becomes large, making it difficult for charge to be injected from the conductive film 15 serving as the upper electrode into the PZT contained in the dielectric film 14, and the insulating properties of the dielectric film 14 can be easily improved.

[0029] Furthermore, in the stacked structure of this embodiment 1, even if it is assumed that the PZT contained in the dielectric film 14 has become a p-type semiconductor due to lead deficiency or the like, the work function of the conductive film 15 serving as the upper electrode becomes smaller, thereby increasing the energy barrier between the conductive film 15 serving as the upper electrode and the dielectric film 14, making it difficult for charge to be injected from the conductive film 15 serving as the upper electrode into the PZT contained in the dielectric film 14, and the insulating properties of the dielectric film 14 can be easily improved.

[0030] Furthermore, in the laminated structure of the first embodiment, there is no amorphous layer 14b having a lower dielectric constant than the crystallized layer 14a between the dielectric film 14 and the conductive film 15 serving as the upper electrode, or the conductive film 15 serving as the upper electrode is formed directly on the crystallized layer 14a of the dielectric film 14. In such a case, when a voltage is applied between the conductive film 13 serving as the lower electrode and the conductive film 15 serving as the upper electrode, there is no risk of a decrease in the voltage applied to the PZT contained in the dielectric film 14, and the electrical properties of the dielectric film 14, such as the piezoelectricity and ferroelectricity, can be easily improved.

[0031] Preferably, the conductive film 15 is made of Pt, and the difference between the work function of the conductive film 15 and 5.93 eV is greater than the difference between the work function of the conductive film 15 and 5.66 eV. Here, the work function of Pt depends on the orientation direction of Pt, being 5.66 eV for a (100) orientation in cubic crystal notation and 5.93 eV for a (111) orientation in cubic crystal notation. Therefore, the fact that the difference between the work function of the conductive film 15 and 5.93 eV is greater than the difference between the work function of the conductive film 15 and 5.66 eV means that, for example, in terms of weight fraction, the Pt contained in the conductive film 15 has a greater proportion of its portion oriented in the (100) orientation in cubic crystal notation than its portion oriented in the (111) orientation in cubic crystal notation.

[0032] In such a case, the work function of the conductive film 15 is smaller than when the difference between the work function of the conductive film 15 and 5.93 eV is smaller than the difference between the work function of the conductive film 15 and 5.66 eV. Therefore, even if it is assumed that the PZT contained in the dielectric film 14 has become a p-type semiconductor due to lead deficiency or the like, as described above, the energy barrier between the conductive film 15 as the upper electrode and the dielectric film 14 becomes larger due to the smaller work function of the conductive film 15, making it difficult for charge to be injected from the conductive film 15 as the upper electrode into the PZT contained in the dielectric film 14, and the insulating properties of the dielectric film 14 can be easily improved.

[0033] Therefore, in the laminated structure of this embodiment 1, instead of satisfying the requirement that the dielectric film 14 includes an amorphous layer 14b interposed between the crystallized layer 14a and the conductive film 15, containing Pb, Zr or Ti, and having a film thickness ratio to the crystallized layer 14a of 0.5% or less, or that the conductive film 15 is formed directly on the crystallized layer 14a, the laminated structure may also satisfy the requirement that the difference between the work function of the conductive film 15 and 5.93 eV is greater than the difference between the work function of the conductive film 15 and 5.66 eV.

[0034] Alternatively, the conductive film 15 may be made of Pt oriented in the (100) cubic crystal system. In this case, the requirement that the difference between the work function of the conductive film 15 and 5.93 eV is greater than the difference between the work function of the conductive film 15 and 5.66 eV can be satisfied, and the insulating properties of the dielectric film 14 can be easily improved.

[0035] Furthermore, with regard to the laminated structure of the first embodiment, instead of satisfying the requirement that the dielectric film 14 includes an amorphous layer 14b interposed between the crystallized layer 14a and the conductive film 15, containing Pb, Zr, or Ti, and having a film thickness ratio of 0.5% or less to the crystallized layer 14a, or that the conductive film 15 is formed directly on the crystallized layer 14a, the laminated structure may also satisfy the requirement that when a cross section of the laminated structure 10 along the lamination direction is observed at a magnification of 100,000 to 1,000,000 times by scanning transmission electron microscopy (STEM), no intervening layer interposed between the crystallized layer 14a and the conductive film 15 is visible. In this way, by observing the cross section at a magnification by STEM, it can be confirmed that no layer is interposed between the crystallized layer 14a and the conductive film 15.

[0036] According to the stacked structure of the first embodiment, the conductive film 13 and the dielectric film 14 can be easily epitaxially grown on the substrate 11 made of a Si substrate or an SOI substrate via the buffer film 12 made of HfO2, HZO, or ZrO2. This is thought to be due to a crystal growth mechanism in which the dynamic lattice matching effect due to the twin martensitic transformation exhibited by the metal oxide made of HfO2, HZO, or ZrO2, which is the main component of the buffer film 12, acts as a driving force, a motive force, and a propulsive force during the epitaxial growth of the conductive film 13 and the dielectric film 14. The same can be said for the case in which the buffer film 12 contains a metal nitride made of HfN, HZN, or ZrN. However, the present invention is not necessarily bound by such a theory.

[0037] In the stacked structure of the present embodiment 1, the conductive film 13 made of Pt is formed on the substrate 11 via the buffer film 12 made of HfO2, HZO, or ZrO2. However, the stacked structure of the present embodiment 1 is not limited to the case where the conductive film 13 made of Pt is formed on the substrate 11 via the buffer film 12 made of HfO2, HZO, or ZrO2, nor is the conductive film 13 limited to being made of Pt. Therefore, in the stacked structure of the present embodiment 1, the conductive film 13 made of a metal other than Pt may be formed on the substrate 11 without the buffer film made of HfO2, HZO, or ZrO2.

[0038] Furthermore, in the stacked structure of the first embodiment, the buffer film 12 does not have to be made of a metal oxide or metal nitride epitaxially grown on the main surface 11p of the substrate 11, the conductor film 13 does not have to be made of Pt epitaxially grown on the buffer film 12, and the dielectric film 14 does not have to be epitaxially grown on the conductor film 13. Even in such cases, for example, after forming the dielectric film 14, the amorphous layer 14b formed on the dielectric film 14 can be removed by etching, so that the amorphous layer 14b is not interposed between the crystallized layer 14a and the conductor film 15, or the ratio of the thickness of the amorphous layer 14b to the thickness of the crystallized layer 14a can be set to 0.5% or less. However, when the buffer film 12 is made of a metal oxide or metal nitride epitaxially grown on the main surface 11p of the substrate 11, the conductive film 13 is made of Pt epitaxially grown on the buffer film 12, and the dielectric film 14 is epitaxially grown on the conductive film 13, the leakage current flowing between the conductive film 13 as the lower electrode and the conductive film 15 as the upper electrode when an electric field is applied between them can be made smaller.

[0039] Furthermore, in the stacked structure of the present first embodiment, the substrate 11 does not have to be a Si(100) substrate including a main surface 11p consisting of a Si(100) plane, or an SOI substrate including an SOI layer including a main surface 11p consisting of a Si(100) plane, the buffer film 12 does not have to be made of a metal oxide or metal nitride oriented in (100) in pseudo cubic crystal notation, and the conductor film 13 does not have to be oriented in (100) in cubic crystal notation. However, when the substrate 11 is a Si(100) substrate including a main surface 11p consisting of a Si(100) plane, or an SOI substrate including an SOI layer including a main surface 11p consisting of a Si(100) plane, the buffer film 12 is made of a metal oxide or metal nitride oriented in (100) in pseudo cubic crystal representation, and the conductive film 13 is oriented in (100) in cubic crystal representation, the leakage current flowing between the lower electrode and the upper electrode when an electric field is applied between them can be made smaller.

[0040] Preferably, a conductive film 13a made of a metal oxide represented by the composition formula SrRuO3 is interposed between the conductive film 13 and the dielectric film 14. That is, the conductive film 13a is made of a metal oxide of ruthenium (Ru) and strontium (Sr). In the following, the metal oxide represented by the composition formula SrRuO3 may be referred to as strontium ruthenate (SRO).

[0041] When the conductive film 13a is interposed between the conductive film 13 and the dielectric film 14, the dielectric film 14 made of PZT can be easily epitaxially grown on the conductive film 13 made of Pt compared to when the conductive film 13a is not interposed between the conductive film 13 and the dielectric film 14, because SRO has a perovskite structure similar to PZT.

[0042] Preferably, the thickness of the dielectric film 14 is 100 to 200 nm. The horizontal axis is in V, and the vertical axis is in μC / cm 2 In the polarization voltage hysteresis curve obtained by plotting the polarization of the dielectric film 14 when a voltage is applied between the conductive film 13 and the conductive film 15, the average slope angle of the curve portion showing the voltage dependency of the polarization when the voltage is reduced from the maximum voltage to 0 is 9.5 to 10.37°. As a result, the remanent polarization value of the laminated structure of the present embodiment 1 is set to 100 μC / cm 2 The remanent polarization can be made extremely large.

[0043] Preferably, the thickness of the conductive film 13 and the conductive film 15 is 1×10 8 When an electric field of 1.83 V / cm is applied, the leakage current density flowing between the conductive film 13 and the conductive film 15 is 1.83×10 -7 A / cm 2 This makes it possible to reduce the leakage current flowing between the lower electrode and the upper electrode.

[0044] (Embodiment 2) Next, an electronic device according to a second embodiment of the present invention will be described. The electronic device according to the second embodiment is an inkjet printhead as a fluid discharge device, which includes the film structure according to the first embodiment. Fig. 5 is a cross-sectional view of the electronic device according to the second embodiment.

[0045] As shown in FIG. 5, an electronic device 20 according to the second embodiment includes a stacked structure 10 having a substrate 11 made of a Si substrate, a buffer film 12 made of ZrO, HZO, or HfO, a conductive film 13 made of Pt, a dielectric film 14 made of PZT, and a conductive film 15 made of Pt. In the electronic device 20 according to the second embodiment, the dielectric film 14 includes an amorphous layer containing Pb, Zr, or Ti and interposed between the crystallized layer 14a made of PZT and the conductive film 15, or the conductive film 15 is formed directly on the crystallized layer 14a. The electronic device 20 also includes a conductive film 13a made of SRO and interposed between the conductive film 13 and the dielectric film 14. Similarly to FIGS. 2 and 4, FIG. 5 illustrates a case in which no amorphous layer is interposed between the crystallized layer 14a and the conductive film 15.

[0046] Moreover, the electronic device 20 of the second embodiment is a piezoelectric actuator in which the conductive film 13 and the conductive film 13a function as lower electrodes, and the conductive film 15 functions as an upper electrode.

[0047] The electronic device 20 of the second embodiment also includes a chamber 23 for storing a fluid. The chamber 23 is configured to take in the fluid from a tank (not shown) via a flow path 24.

[0048] A buffer film 12 is formed as a dielectric layer on a substrate 11 made of a Si substrate, and the buffer film 12 faces the chamber 23. As described above, the buffer film 12 made of HZO or the like is used as the dielectric layer, which provides better adhesion to the Si substrate and crystallinity than when SiO2, SiN or the like is used as the dielectric layer, and also provides better piezoelectric properties and durability.

[0049] The electronic device 20 of the second embodiment further includes an insulating film 25 , a conductive path 26 , and a passivation film 27 .

[0050] The crystallized layer 14a included in the dielectric film 14 is formed on a lower electrode made of the conductor film 13 and the conductor film 13a, and on the crystallized layer 14a included in the dielectric film 14 and an upper electrode made of the conductor film 15. The material for the insulator film 25 is not particularly limited, but may be a dielectric material such as SiO2, SiN, or Al2O3. The thickness of the insulator film 25 is not particularly limited, but is preferably between about 10 nm and about 10 μm.

[0051] The conductive path 26 is formed on the insulating film 25 and is electrically connected to the lower electrode made of the conductive film 13 and the conductive film 13a, respectively, and the upper electrode made of the conductive film 15, thereby enabling selective access when using the electronic device 20. Although the material constituting the conductive path 26 is not particularly limited, the material constituting the conductive path 26 may be a conductive material such as aluminum (Al).

[0052] The passivation film 27 is formed on the insulating film 25, the lower electrode made of the conductive film 13 and the conductive film 13a, the upper electrode made of the conductive film 15, and the conductive path 26. The passivation film 27 functions as a barrier layer that protects the piezoelectric element from humidity and the like. The material that constitutes the passivation film 27 is not particularly limited, but a dielectric material such as SiN or SiON (silicon oxynitrate) can be used as the material that constitutes the passivation film 27. The thickness of the passivation film 27 is not particularly limited, but is preferably between about 0.1 μm and about 3 μm. Similarly, a conductive pad 28 is provided along the piezoelectric actuator and is electrically connected to the conductive path 26.

[0053] According to the second embodiment, the dielectric film 14 includes an amorphous layer containing Pb, Zr, or Ti and is interposed between the crystallized layer 14a and the conductive film 15, or the conductive film 15 is formed directly on the crystallized layer 14a. In such a case, the insulating properties of the dielectric can be improved compared to the technique described in Patent Document 1. Therefore, for example, when an electric field is applied between the lower electrode and the upper electrode, the leakage current flowing between the lower electrode and the upper electrode can be reduced. Therefore, the electrical characteristics of the piezoelectric actuator can be improved, for example, the power consumption of the piezoelectric actuator can be reduced.

[0054] As described above, the stacked structure 10 provided in the electronic device 20 of the second embodiment can also use an SOI substrate, which is a semiconductor substrate, instead of a Si substrate as the substrate 11, similarly to the stacked structure 10 of the first embodiment. Furthermore, the electronic device including the stacked structure is not limited to a piezoelectric actuator, and various electronic devices such as an FBAR (Film Bulk Acoustic Resonator) can be mentioned. [Example]

[0055] The present invention will be described in more detail below based on examples, but the present invention is not limited to the following examples.

[0056] (Example 1, Example 2 and Comparative Example) [Formation of laminated structure] The stacked structure of Example 1 was fabricated. First, the crystal growth surface side of a Si (100) substrate serving as substrate 11 (see FIG. 1 ) was treated by reactive ion etching (RIE), and then heated in the presence of oxygen to form a thermal oxide film. Then, without using oxygen, molecular beam epitaxy (MBE) was performed to thermally react metals (Hf, Zr) from the deposition source with oxygen in the oxide film on the Si substrate, forming a single-crystal film of metal oxide on the Si substrate as buffer film 12 (see FIG. 1 ). Next, oxygen was introduced, the temperature was lowered, and the pressure was increased, and a single-crystal film of metal oxide was formed on the Si substrate as buffer film 12 (see FIG. 1 ) by MBE. The MBE conditions for this film formation were as follows: The target Hf:Zr ratio was 25:75 (y in the above composition formula (Chemical Formula 4) was 0.75). Vapor deposition source: Hf, Zr Voltage: 3.5~4.75V Pressure: 3×10 -2 ~6×10 -2 Pa Substrate temperature: 450~700℃

[0057] Next, a metal film of Pt was formed as the conductive film 13 by sputtering on the single crystal film of metal oxide as the buffer film 12. The conditions at this time are as follows: Equipment: ULVAC sputtering equipment QAM-4 Pressure: 1.20×10 -1 Pa Target: Pt Power: 100W(DC) Thickness: 80nm Substrate temperature: 450~600℃

[0058] Next, a conductive film 13a made of an SRO film was formed by sputtering on the Pt metal film serving as the conductive film 13. The conditions for this were as follows: Equipment: ULVAC sputtering equipment QAM-4 Power: 150W(RF) Gas: Ar Pressure: 1.8Pa Substrate temperature: 600℃ Thickness: 10nm

[0059] Next, a Pb(Zr 0.30 Ti 0.70 A PZT film having a composition of 0 was formed by sputtering under the following conditions: Equipment: RF magnetron sputtering equipment Power: 2500W Gas: Ar / O2 Pressure: 0.14Pa Substrate temperature: 425~525℃ Thickness: 100nm

[0060] Next, the amorphous layer formed on the dielectric film 14 was removed by etching.

[0061] Next, a Pt metal film was formed as the conductor film 15 by sputtering on the PZT film as the crystallized layer 14a included in the dielectric film 14. The conditions at this time are as follows. Equipment: ULVAC sputtering equipment QAM-4 Pressure: 1.20×10 -1 Pa Target: Pt Power: 100W(DC) Thickness: 50nm Substrate temperature: 450~600℃

[0062] In this manner, the buffer film 12, the conductive film 13, the dielectric film 14, and the conductive film 15 were sequentially formed to produce the stacked structure of Example 1. As described above, the conductive film 13a may not be formed between the conductive film 13 and the dielectric film 14, and the dielectric film 14 may be formed on the conductive film 13 without the conductive film 13a interposed therebetween.

[0063] [X-ray diffraction measurement] After forming the buffer film 12 on the main surface 11p of the substrate 11, but before forming the conductive film 13, the stacked structure was positioned so that the diffraction plane in the X-ray diffraction (XRD) measurement was parallel to the main surface 11p using the θ-2θ method, and the diffraction pattern of the stacked structure was measured by the X-ray diffraction measurement. The measured diffraction pattern of the stacked structure of Example 1 is shown in Figure 6. The XRD measurement was performed using an X-ray diffractometer SmartLab manufactured by Rigaku Corporation.

[0064] As shown in Figure 6, a strong diffraction peak of the (200) plane of HZO, which is composed of the (200) plane of tetragonal ZrO2 (T-ZrO2) and the (200) plane of monoclinic HfO2 (M-HfO2), was observed in the diffraction pattern. This revealed that the HZO contained in the metal oxide has a (100) orientation in the pseudocubic crystal representation.

[0065] In addition, the stacked structure was positioned so that the diffraction plane in the X-ray diffraction measurement was inclined by 90° relative to the main surface 11p (in-plane measurement), and a φ scan was performed on the tetragonal (110) plane (2θ=35°) of HZO contained in the metal oxide. The φ scan measured for the stacked structure of Example 1 is shown in FIG.

[0066] As shown in Figure 7, in the φ scan, four strong diffraction peaks of the tetragonal (110) plane of HZO were observed at 90° intervals. That is, in the φ scan, diffraction peaks showing four-fold symmetry of HZO were observed. This revealed that the HZO contained in the metal oxide has its crystal axis aligned in the in-plane direction along the main surface 11p of the substrate 11, i.e., it has grown epitaxially.

[0067] After forming the conductive film 13, the conductive film 13a, and the dielectric film 14, the obtained laminated structure of Example 1 was positioned so that the diffraction plane in X-ray diffraction measurement using the θ-2θ method was parallel to the main surface 11p, and the diffraction pattern of the laminated structure of Example 1 was measured by the X-ray diffraction measurement. The measured diffraction pattern of the laminated structure of Example 1 is shown in FIG.

[0068] 8, a strong diffraction peak of the (200) plane of Pt, a strong diffraction peak of the (200) plane of SRO, and strong diffraction peaks of the (001) and (002) planes of PZT were observed in the diffraction pattern of Example 1. Therefore, it was revealed that in Example 1, Pt contained in the conductive film 13 has a (100) orientation in the cubic crystal representation, SRO contained in the conductive film 13a has a (100) orientation in the pseudo cubic crystal representation, and PZT contained in the dielectric film 14 has a (100) orientation in the pseudo cubic crystal representation.

[0069] In addition, the stacked structure was positioned so that the diffraction plane in the X-ray diffraction measurement was inclined by 90° with respect to the main surface 11p (in-plane measurement), and a φ scan was performed on the Pt (220) plane (2θ=67°). The measured φ scan is shown in FIG.

[0070] As shown in Figure 9, in the φ scan, four strong diffraction peaks of the (220) plane of Pt were observed at 90° intervals. That is, in the φ scan, diffraction peaks showing four-fold symmetry of Pt were observed. This revealed that the Pt contained in the conductive film 13 has its crystal axis aligned in the in-plane direction along the main surface 11p of the substrate 11, that is, it has grown epitaxially.

[0071] In addition, the laminated structure was positioned so that the diffraction plane in the X-ray diffraction measurement was inclined at 45° with respect to the main surface 11p, and a φ scan was performed on the (110) plane (2θ=31°) of the PZT. The measured φ scan is shown in FIG.

[0072] As shown in Figure 10, in the φ scan, four strong diffraction peaks of the (110) plane of PZT were observed at 90° intervals. That is, in the φ scan, diffraction peaks showing four-fold symmetry of PZT were observed. This revealed that the PZT contained in the crystallized layer 14a of the dielectric film 14 has its crystal axis aligned in the in-plane direction along the main surface 11p of the substrate 11, i.e., epitaxial growth.

[0073] Although detailed explanation is omitted, even when the conductive film 13a made of SRO is not formed between the conductive film 13 and the dielectric film 14, strong diffraction peaks of the (001) and (002) planes of PZT are observed in the diffraction pattern obtained by X-ray diffraction measurement using the θ-2θ method, and it is clear that the PZT contained in the dielectric film 14 has a (100) orientation in the pseudo-cubic crystal representation. Furthermore, in a φ scan of the (110) plane of PZT, diffraction peaks showing four-fold symmetry are observed, and it is clear that the PZT contained in the dielectric film 14 has grown epitaxially.

[0074] After forming the conductive film 15, the diffraction pattern of the laminated structure of Example 1 was measured by X-ray diffraction measurement in the 2θ range of 38 to 50°. The results are shown in FIG. 11. After forming the dielectric film 14, the upper surface of the dielectric film 14 was not etched, so that the ratio of the film thickness of the amorphous layer 14b to the film thickness of the crystallized layer 14a exceeded 0.5%, and a diffraction pattern of the laminated structure of the comparative example was measured by X-ray diffraction measurement in the 2θ range of 38 to 50°. The results are shown in FIG. 12.

[0075] 12, a diffraction peak of the (111) plane of Pt was clearly observed in the diffraction pattern of the layered structure of the comparative example. This diffraction peak of the (111) plane of Pt was not observed before the formation of the conductive film 15 as the upper electrode, and therefore was derived from the conductive film 15 as the upper electrode.

[0076] On the other hand, as shown in Figure 11, in the diffraction pattern of the laminated structure of Example 1, a diffraction peak of the (002) plane of Pt was observed, but a diffraction peak of the (111) plane of Pt was not observed. It is also known that Pt tends to be (111) oriented when not epitaxially grown. This demonstrates that in the laminated structure of Example 1, the conductive film 15 serving as the upper electrode is included in the dielectric film 14 and is epitaxially grown directly on the crystallized layer 14a made of PZT.

[0077] [Scanning transmission electron microscope measurement] The cross section of the laminated structure of Example 1 along the lamination direction of the laminated structure was observed by scanning transmission electron microscopy (STEM) at magnifications of 100,000 to 1,000,000 times. The resulting cross-sectional STEM image is shown in FIG.

[0078] As shown in FIG. 13 , an HZO film as a buffer film 12, a Pt film as a conductor film 13, an SRO film as a conductor film 13a, a PZT film as a dielectric film 14, and a Pt film as a conductor film 15 are formed on a Si substrate as a substrate 11. As shown in FIG. 13 , an intervening layer interposed between the PZT film as a crystallized layer 14a included in the dielectric film 14 and the Pt film as a conductor film 15 is not visible. In other words, when a cross section of the stacked structure 10 along the stacking direction is observed at a magnification of 100,000 to 1,000,000 times using a scanning transmission electron microscope, an amorphous layer 14b as an intervening layer interposed between the crystallized layer 14a and the conductor film 15 is not visible. Therefore, it was revealed that in the stacked structure of Example 1, no amorphous layer is interposed between the crystallized layer 14a and the conductor film 15, and the conductor film 15 is formed directly on the crystallized layer 14a.

[0079] [Voltage dependence of polarization] The voltage dependence of polarization of the laminated structure of Example 1 was measured by applying a voltage between the conductive film 13 and the conductive film 15. The results are shown in FIGS.

[0080] Fig. 14 is a graph showing the voltage dependence of polarization of the laminated structure of Example 1. Fig. 15 is a diagram for explaining a method for calculating the average slope angle of the polarization voltage hysteresis loop when a maximum voltage of 100 V is applied and then the applied voltage is reduced to 0 V. Here, the thickness of the dielectric film 14 was 100 nm, and the conductive film 15 serving as the upper electrode was made of Pt and had a diameter of 1 mmφ. The Pt contained in the conductive film 15 serving as the upper electrode was (100) oriented in cubic crystal notation.

[0081] The following results were obtained from the graph shown in Figure 14: Remanent polarization value Pr = 99.6 μC / cm 2 When used as a ferroelectric memory, 2Pr=99.6×2=199.2μC / cm 2 An extremely large value was obtained as the residual polarization value Pr. Meanwhile, as shown in FIG. 15, the following relationship was obtained for the average slope angle θ of the curve portion of the polarization voltage hysteresis curve that shows the voltage dependence of polarization when the voltage is decreased from the maximum voltage to 0, and an extremely small θ was obtained. In other words, excellent characteristics were obtained as the polarization voltage hysteresis curve. Pmax-Pr=114.7-99.6=15.1μC / cm 2 Vc = 19.3 + 63.16 = 82.46 V ≒ 8 MV / cm Tanθ=0.183→θ=10.37°

[0082] In addition, the film thickness is 100 nm and Pb(Zr 0.30 Ti 0.70 Instead of the PZT film having a composition of Pb(Zr 0.60 Ti 0.40 The laminated structure of Example 2 was fabricated in the same manner as in Example 1, except that a PZT film having a composition of )O3 was formed, and a voltage was applied between the conductive film 13 and the conductive film 15 to measure the voltage dependence of polarization. The results are shown in FIGS. 16 and 17. Note that FIGS. 16 and 17 were measured using different upper electrodes of the laminated structure of Example 2, which were made of conductive film 15 and spaced apart from each other.

[0083] The following results were obtained from the graph shown in Figure 16: Remanent polarization value Pr = 97 μC / cm 2and an extremely large value was obtained as the remanent polarization value Pr. Meanwhile, in the polarization voltage hysteresis curve described with reference to FIG. 16, the following relationship was obtained for the average slope angle θ of the curve portion showing the voltage dependence of polarization when the voltage was decreased from the maximum voltage to 0, and an extremely small θ was obtained. In other words, excellent characteristics were obtained as a polarization voltage hysteresis curve. Pmax-Pr=107-97=10μC / cm 2 Vc=13.3+46=59.3V Tanθ=10 / 59.3=0.168→θ=9.5°

[0084] The following results were obtained from the graph shown in Figure 17: Remanent polarization value Pr = 96.5 μC / cm 2 and an extremely large value was obtained as the remanent polarization value Pr. Meanwhile, in the polarization voltage hysteresis curve described with reference to FIG. 17, the following relationship was obtained for the average slope angle θ of the curve portion showing the voltage dependence of polarization when the voltage was decreased from the maximum voltage to 0, and an extremely small θ was obtained. In other words, excellent characteristics were obtained as a polarization voltage hysteresis curve. Pmax-Pr=107-96.5=10.5μC / cm 2 Vc=14+48=62V Tanθ=10.5 / 62=0.169→θ=9.6°

[0085] From the results shown in FIGS. 14 to 17, it can be seen that the thickness of the dielectric film 14 is 100 to 200 nm, the horizontal axis is in units of V, and the vertical axis is in units of μC / cm 2 In the polarization voltage hysteresis curves obtained by plotting the polarization of the dielectric film 14 when a voltage is applied between the conductive film 13 and the conductive film 15, the average slope angle of the curve portion showing the voltage dependency of polarization when the voltage is reduced from the maximum voltage to 0 was 9.5 to 10.37°. As a result, the residual polarization values ​​of the laminated structures of Examples 1 and 2 were 100 μC / cm 2 The remanent polarization can be made extremely large.

[0086] [Current-voltage characteristics] For the laminated structure of Example 1, the leakage current (leakage current density) flowing between the conductive film 13 and the conductive film 15 was measured when a voltage (electric field) was applied between the conductive film 13 and the conductive film 15. The results are shown in Figures 18 to 21. Figures 18, 19, 20, and 21 show the measurement results of the leakage current at -45°C, 30°C, 85°C, and 125°C, respectively.

[0087] As shown in FIG. 19, when a voltage of 10 V is applied between the conductive film 13 and the conductive film 15 at 30° C., that is, when the film thickness of the dielectric film 14 is 100 nm, the 8 When an electric field of 1.83 V / cm is applied, the leakage current density flowing between the conductive film 13 and the conductive film 15 is 1.83×10 -7 A / cm 2 It was.

[0088] From the above results, it became clear that the leakage current flowing between the lower electrode and the upper electrode in the film structure of Example 1 is significantly smaller than the leakage current flowing between the lower electrode and the upper electrode in a conventional PZT film.

[0089] Although detailed explanation is omitted, even when the Hf:Zr ratio was other than 25:75 and y in the above composition formula (Chemical Formula 4) satisfied 0≦y<1 or y=1, the same results as in Example 1, in which the Hf:Zr ratio was 25:75 (y in the above composition formula (Chemical Formula 4) was 0.75), were obtained.

[0090] Furthermore, although detailed explanation is omitted, when a buffer film 12 containing a metal nitride made of HfN, HZN or ZrN was used as the buffer film 12 instead of the buffer film 12 containing a metal oxide made of HfO2, HZO or ZrO2, the same results as in Example 1, in which the buffer film 12 containing a metal oxide made of HfO2, HZO or ZrO2 was used, were obtained.

[0091] Furthermore, although detailed explanation is omitted, even when the Zr:Ti ratio was a composition other than 30:70 and x in the above composition formula (Chemical Formula 6) satisfied the condition of 0≦x≦1, the same results as those in Example 1 where the Zr:Ti ratio was 30:70 (x in the above composition formula (Chemical Formula 6) was 0.70) were obtained, as shown in the results of the polarization electric field hysteresis curves of Example 2 in FIGS. 16 and 17, for example. [Explanation of symbols]

[0092] 10. Laminated structure 11 Circuit Board 11a Base 11b Insulating layer 11c SOI layer 11p Main surface 12 Buffer film 13, 13a, 15 Conductive film 14 Dielectric film 14a Crystallized layer 14b Amorphous layer 20 Electronic Devices 23 Chamber 24 flow paths 25 Insulator film 26 Conductive Path 27 Passivation film 28 Conductive Pad

Claims

1. A substrate; a first conductive film formed on the substrate; a dielectric film formed on the first conductive film; a second conductive film formed on the dielectric film; In a laminated structure having The dielectric film includes a crystallized layer that is represented by the following composition formula (Chemical Formula 1) and is crystallized: Pb(Zr １－ｘ Ti ｘ )O ３ ...(Formula 1) wherein x satisfies 0≦x≦1; the dielectric film includes an amorphous layer interposed between the crystallization layer and the second conductor film and containing Pb, Zr, or Ti, or the second conductor film is formed directly on the crystallization layer; A laminated structure, wherein when the dielectric film includes the amorphous layer, the ratio of the thickness of the amorphous layer to the thickness of the crystallized layer is 0.5% or less.

2. the second conductive film is made of Pt, 2. The stacked structure according to claim 1, wherein a difference between the work function of the second conductive film and 5.93 eV is larger than a difference between the work function of the second conductive film and 5.66 eV.

3. A substrate; a first conductive film formed on the substrate; a dielectric film formed on the first conductive film; a second conductive film formed on the dielectric film; In a laminated structure having The dielectric film includes a crystallized layer that is represented by the following composition formula (Chemical Formula 1) and is crystallized: Pb(Zr １－ｘ Ti ｘ )O ３ ...(Formula 1) wherein x satisfies 0≦x≦1; the second conductive film is made of Pt, a difference between the work function of the second conductive film and 5.93 eV is greater than a difference between the work function of the second conductive film and 5.66 eV;

4. A substrate; a first conductive film formed on the substrate; a dielectric film formed on the first conductive film; a second conductive film formed on the dielectric film; In a laminated structure having The dielectric film includes a crystallized layer that is represented by the following composition formula (Chemical Formula 1) and is crystallized: Pb(Zr １－ｘ Ti ｘ )O ３ ...(Formula 1) wherein x satisfies 0≦x≦1; A laminated structure in which, when a cross section of the laminated structure along the lamination direction is observed at a magnification of 100,000 to 1,000,000 times using a scanning transmission electron microscope, an intervening layer interposed between the crystallized layer and the second conductive film cannot be visually recognized.

5. the first conductive film is epitaxially grown on the substrate; the crystallized layer is epitaxially grown on the first conductive film, 5. The laminated structure according to claim 1, wherein the second conductive film is epitaxially grown directly on the crystallized layer.

6. the first conductive film is epitaxially grown on the substrate; the crystallized layer is epitaxially grown on the first conductive film, 5. The laminated structure according to claim 1, wherein the second conductive film is made of Pt epitaxially grown directly on the crystallized layer.

7. the substrate includes a major surface; the laminated structure further includes a buffer film formed on the main surface, the first conductive film is formed on the buffer film; the substrate is a Si substrate or an SOI substrate including a base body made of a Si substrate, an insulating layer on the base body, and an SOI layer on the insulating layer; The buffer film is made of a metal oxide represented by the following composition formula (Chemical Formula 2) or a metal nitride represented by the following composition formula (Chemical Formula 3), (Hf １－ｙ Zr ｙ )O ２ ... (Formula 2) (Hf １－ｚ Zr ｚ )N...(Formula 3) The y satisfies 0≦y<1 or y=1, 5. The laminate structure according to claim 1, wherein z satisfies 0≦z≦1.

8. the substrate is a Si(100) substrate including the main surface made of a Si(100) plane, or an SOI substrate including: the base made of a Si substrate; the insulating layer on the base; and the SOI layer made of a Si(100) film on the insulating layer and including the main surface made of a Si(100) plane; the buffer film is made of the metal oxide oriented in a (100) plane in pseudo cubic crystal notation or the metal nitride oriented in a (100) plane in pseudo cubic crystal notation, the first conductive film is made of Pt oriented in a (100) direction in cubic crystal representation, the dielectric film includes the crystallized layer oriented in a (100) direction in the pseudocubic crystal representation, 8. The laminated structure according to claim 7, wherein the second conductive film is made of Pt oriented in the (100) direction in cubic crystal notation.

9. At 30° C., a 1×10 ８ When an electric field of 1.83×10 V / cm is applied, the leakage current density flowing between the first conductive film and the second conductive film is 1.83×10 －７ A / cm ２ The laminate structure according to any one of claims 1 to 4, wherein

10. the thickness of the dielectric film is 100 to 200 nm; The horizontal axis is in V, and the vertical axis is in μC / cm ２ 5. The laminated structure according to claim 1, wherein, in a polarization voltage hysteresis curve obtained by plotting polarization of the dielectric film when a voltage is applied between the first conductor film and the second conductor film, an average slope angle of a curve portion showing voltage dependence of the polarization when the voltage is reduced from a maximum voltage to 0 is 9.5 to 10.37°.

11. An electronic device comprising the laminate structure according to any one of claims 1 to 4.

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