Semiconductor device and method of manufacturing the same

Abstract

According to one embodiment, a semiconductor integrated circuit device includes a first semiconductor element, a second semiconductor element, and a I / O.SOLUTION: A semiconductor device according to the present disclosure includes a plurality of bonding pads, the plurality of bonding pads being constituted by an uppermost layer of a wiring layer and including at least first and third bonding pads that are connected to a power supply external to a semiconductor chip, second and fourth bonding pads that are connected to ground, a fifth bonding pad that is connected to the third bonding pad via a first inner wire, and a sixth bonding pad that is connected to the fourth bonding pad via a second inner wire. In the first and second bonding pads, the wiring constituting the second circuit does not exist in the layer immediately below the uppermost layer of the wiring layer, and in the third to sixth bonding pads, the wiring constituting the second circuit exists in the layer immediately below the uppermost layer of the wiring layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a plurality of bonding pads and a method for manufacturing the same. [Background technology]

[0002] 2. Description of the Related Art A semiconductor device including a semiconductor chip has electrode pads for connection to externally provided electrode terminals, and wire bonding technology is sometimes used to connect the external electrode terminals to the electrode pads.

[0003] For example, Patent Document 1 discloses a semiconductor device in which power supply pads for supplying power to a semiconductor chip are arranged in a grid pattern and are wire-bonded to each other. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-085829 Summary of the Invention [Problem to be solved by the invention]

[0005] Within semiconductor chips, for example, logic circuits are required to be highly integrated, and in order to reduce the L / S ratio (ratio of wiring width to wiring spacing), it is necessary to thin the metal layers that form the wiring.

[0006] On the other hand, for I / O circuits (input / output circuits), it is preferable to reduce the impedance of the metal layer that serves as the wiring in order to improve I / O capabilities and ESD resistance (Electro-Static Discharge), and it is preferable that the film thickness of the metal layer that serves as the wiring is thick.

[0007] Therefore, it can be said that there is room for further consideration in providing a plurality of circuits within a semiconductor chip. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] According to one embodiment, for the power supply or GND (ground) in a semiconductor device, multiple bonding pads are provided in a semiconductor chip, and bonding pads provided on different sides of the semiconductor chip are connected by inner wire bonding. This makes it possible to reduce the impedance of the power supply or GND. Other features will be described in detail below. [Effects of the Invention]

[0009] According to the embodiment, it is possible to provide a semiconductor device and a method for manufacturing the semiconductor device that can achieve both high integration in a semiconductor chip and improved I / O performance and ESD resistance. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a diagram schematically showing the cross-sectional structure of a bonding pad. [Figure 3] FIG. 3 is a diagram showing the positional relationship between the bonding pads and the probes. [Figure 4] FIG. 4 is a diagram schematically showing the cross-sectional structure of a bonding pad. [Figure 5] FIG. 5 is a plan view showing the configuration of the semiconductor device according to the second embodiment. [Figure 6] FIG. 6 is a plan view showing the configuration of the semiconductor device according to the second embodiment. [Figure 7] FIG. 7 is a plan view showing the configuration of a semiconductor device according to the third embodiment. [Figure 8]FIG. 8 is a diagram schematically showing the cross-sectional structure of a bonding pad. [Figure 9] FIG. 9 is a diagram schematically showing a cross-sectional structure of a semiconductor device. [Figure 10] FIG. 10 is a cross-sectional view of the semiconductor chip taken along dashed line II-II shown in FIG. [Figure 11] FIG. 11 is a diagram illustrating a method for manufacturing a semiconductor device according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] <First Embodiment> Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the present embodiments, the state of "connecting" includes the state of "electrically connecting."

[0012] 1 is a plan view showing an example of a semiconductor device 1 according to the present disclosure. The semiconductor device 1 includes a semiconductor chip 10. The semiconductor chip 10 includes a first circuit region 11, a second circuit region 12, and a plurality of bonding pads 101-106.

[0013] The first circuit region 11 is a region where memory circuits, logic circuits, analog circuits, etc. are formed. The second circuit region 12 is arranged in a frame shape so as to surround the first circuit region 11, and is a region where I / O (input / output) circuits such as input buffer circuits and output buffer circuits, level shifters, etc. are formed.

[0014] Bonding pad 101 is connected to a power supply via wiring 111. Bonding pad 102 is connected to GND (ground) via wiring 121. Bonding pad 103 is connected to bonding pad 101 via power supply wiring 112 provided inside second circuit region 12, thereby enabling connection to the power supply. Bonding pad 104 is connected to bonding pad 102 via GND wiring 122 provided inside second circuit region 12, thereby enabling connection to GND.

[0015] In the semiconductor device 1 according to the present disclosure, the bonding pad 105 is connected to the bonding pad 103 via the inner wire 130 arranged above the semiconductor chip 10. Therefore, the bonding pad 105 can be connected to a power supply via the inner wire 130, the bonding pad 103, and the bonding pad 101. Similarly, the bonding pad 106 is connected to the bonding pad 104 via the inner wire 140 arranged above the semiconductor chip 10. Therefore, the bonding pad 106 can be connected to GND via the inner wire 140, the bonding pad 104, and the bonding pad 102.

[0016] In the semiconductor device 1 according to the present disclosure, by connecting the bonding pads 103 and 105 using the inner wire 130, the effects of voltage drop can be suppressed more effectively than when power is supplied only through the power supply wiring 112 provided inside the second circuit region 12.

[0017] There are no particular restrictions on the arrangement of bonding pads 101 to 106, but considering the above-mentioned effects, it is preferable to provide one of the bonding pads 103 and 104 on the same side as bonding pads 101 and 102, which are directly connected to the power supply and GND, and to provide the other bonding pads 105 and 106 on the opposite side.

[0018] In the semiconductor device 1 according to the present disclosure, the number of terminals connected to an external power supply can be reduced by one by using the inner wire 130. Similarly, the number of terminals connected to GND can be reduced by one by using the inner wire 140. This allows for additional I / O terminal specifications, improving design freedom.

[0019] The semiconductor chip 10 included in the semiconductor device 1 has a plurality of bonding pads used for input / output in addition to the bonding pads 101 to 106 in the second circuit region 12. Since the plurality of bonding pads used for input / output have the same function, the following description will be given using the bonding pad 107 and the wiring 171 connected to the bonding pad 107 shown in FIG.

[0020] 9 is a schematic diagram of a cross-sectional structure of a semiconductor device 1 according to the present disclosure. A semiconductor chip 10 included in the semiconductor device 1 is fixed by a die pad 20 and sealed by the resin of the package 2 and the leads of the lead frame 3. Wiring 111 connected to the bonding pad 101 in FIG. 1 connects to the power bar 21 and supplies power to the semiconductor chip 10. Wiring 121 connected to the bonding pad 102 in FIG. 1 connects to the GND ring 22 and grounds the semiconductor chip 10.

[0021] As shown in FIG. 9, the inner wires 130, 140 provided in the semiconductor device 1 according to the present disclosure are configured to connect bonding pads provided in the semiconductor chip 10 on the upper part of the semiconductor chip 10 to each other.

[0022] 10 shows a cross-sectional view of the semiconductor chip 10 taken along dashed line II-II in Fig. 1. In the first circuit region 11 and the second circuit region 12, a first circuit 31 and a second circuit 32 are formed on a substrate 30, respectively. Each of the first circuit 31 and the second circuit 32 has a structure in which a plurality of wiring layers 35 are stacked with an interlayer insulating film 33 interposed therebetween, and the wiring layers 35 are connected to each other through via wirings 34.

[0023] The number of layers of the first circuit 31 and the second circuit 32 is not particularly limited, but here we will explain an example configuration in which a first wiring layer 41, a second wiring layer 42, a third wiring layer 43, a fourth wiring layer 44, a fifth wiring layer 45, a sixth wiring layer 46, and a top layer, a seventh wiring layer 47, are stacked in this order from the substrate 30.

[0024] In the second circuit region 12, the bonding pad 101 corresponding to the seventh wiring layer 47 is the top layer, and when the inspection probe 40 contacts it, a probe mark 50 is formed on the bonding pad 101 due to physical pressure. Considering the effect of the physical pressure applied by the probe 40, it is preferable to configure the sixth wiring layer 46, which is the layer one layer below the top layer, so that the wiring constituting the second circuit 32 is not provided directly below the area where the probe 40 contacts. In other words, it is preferable to configure the sixth wiring layer 46 so that the wiring constituting the second circuit 32 is not present in the sixth wiring layer 46. This can prevent disconnection due to contact by the probe 40. On the other hand, in the first circuit region 11, wiring can be provided in the sixth wiring layer 46, so there is no limit to the degree of design freedom.

[0025] In the semiconductor chip 10 according to the present disclosure, the bonding pads 101 and 102 are bonding pads with which the probes 40 come into contact.

[0026] On the other hand, since bonding pads 103, 104, 105, and 106 are connected via inner wires 130 and 140, the probe 40 does not come into contact with these bonding pads. By doing so, even in the second circuit region 12, wiring can be provided directly below the bonding pads 103, 104, 105, and 106, thereby improving the degree of freedom in design.

[0027] The bonding pads 101 to 107 will be described in detail with reference to Fig. 2. Fig. 2(a) shows a plan view of the bonding pad 101 provided on the semiconductor chip 10 according to the present disclosure, and Fig. 2(b) shows a cross-sectional view. The probe 40 can be connected to the second circuit 32 formed in the second circuit region 12 via the opening 110 provided in the bonding pad 101 and the pad metal layer 147 formed on the seventh wiring layer 47 in Fig. 10.

[0028] Since bonding pad 101 is the bonding pad that probe 40 comes into contact with, it is preferable that no wiring that constitutes second circuit 32 is provided in region 48 (corresponding to sixth wiring layer 46) directly below the region that probe 40 comes into contact with. On the other hand, to mitigate the physical pressure applied by probe 40, dummy via wiring that does not constitute second circuit 32 or a thick oxide film for buffering may be provided in region 48. The same configuration is also used for bonding pads 102 and 107 that are bonding pads that probe 40 comes into contact with.

[0029] 3 is a diagram showing the positional relationship between the area where the probe 40 contacts and the bonding pad 101. In the semiconductor chip 10 according to the present disclosure, it is preferable that the probe mark 50 formed by the contact of the probe 40 with the bonding pad 101 and the bonding hole 51 overlap each other.

[0030] 4(a) shows a plan view of bonding pad 103, and FIG. 4(b) shows a cross-sectional view. Bonding pad 103 is configured so that probe 40 does not come into contact with it because inner wire 130 is connected to it. Therefore, wiring that constitutes second circuit 32 can also be provided in region 49 (corresponding to sixth wiring layer 46) directly below opening 131 of bonding pad 103. Bonding pads 104, 105, and 106, which are bonding pads to which inner wire 130 or 140 is connected, have a similar configuration.

[0031] In this way, by connecting bonding pads 103 and 105 using inner wire 130, the effects of voltage drop can be suppressed, the impedance of the power supply and GND can be reduced, and the number of power supply terminals and GND terminals can be reduced. Also, by configuring so that wiring constituting second circuit 32 is not provided in region 48 directly below the region where bonding pads 101, 102, and 107 are formed, it is possible to prevent disconnection due to contact with probe 40. Furthermore, since wiring constituting second circuit 32 can be provided in region 49 directly below the region where bonding pads 103 to 106 are formed, the degree of freedom in design is improved.

[0032] <Embodiment 2> In this embodiment, a semiconductor device will be described which is an improved version of embodiment 1. Fig. 5 is a plan view showing an example of a semiconductor device 1 according to this embodiment. Components that overlap with those in Fig. 1 are omitted to avoid repetitive explanation.

[0033] The semiconductor device 1 according to this embodiment has a configuration that further includes a power supply wiring 113 and a GND wiring 123 in addition to the configuration of the semiconductor device 1 of the first embodiment, i.e., the semiconductor device 1 shown in Fig. 1. The power supply wiring 113 and the GND wiring 123 are formed in the seventh wiring layer 47 in Fig. 10, and overlap not only the second circuit region 12 but also the first circuit region 11.

[0034] Bonding pads 101 and 103 are connected by power supply wiring 113, and bonding pads 103 and 105 are connected by inner wire 130. Bonding pads 102 and 104 are connected by GND wiring 123, and bonding pads 104 and 106 are connected by inner wire 140. This allows the current value to be increased, thereby broadening the range of product specifications.

[0035] Furthermore, in the semiconductor device 1 according to this embodiment, by providing the power supply wiring 113, the GND wiring 123, and the inner wires 130 and 140, it becomes easy to supply power to the bonding pads 105 and 106. Therefore, the power supply wiring 112 and the GND wiring 123 in the second circuit region 12 can be omitted, resulting in a semiconductor chip with a space-saving configuration (see FIG. 6).

[0036] <Third Embodiment> This embodiment describes a modified example of the semiconductor device of embodiments 1 and 2. Fig. 7 is a plan view showing an example of a semiconductor device 1 according to this embodiment. Components that overlap with those in Fig. 1, such as the power supply wiring 112 and the GND wiring 123 provided in the second circuit region 12, are omitted to avoid repetitive explanation.

[0037] 1, the semiconductor device 1 according to this embodiment has a configuration in which the bonding pads 103 and 104 provided in the second circuit region 12 are omitted, and bonding pads 108 and 109 are provided in the first circuit region 11. Also, similar to the semiconductor device 1 according to the second embodiment, i.e., the semiconductor device 1 shown in FIG. 5, the semiconductor device 1 according to this embodiment has a power supply wiring 113 and a GND wiring 123 formed in the seventh wiring layer 47 in FIG. 10 and overlapping not only the second circuit region 12 but also the first circuit region 11.

[0038] 10, like the power supply wiring 113 and the GND wiring 123. In addition, the bonding pads 108 and 109 provided in the first circuit region 11 are preferably not provided in the region where an analog circuit is formed, in order to avoid changes in characteristics.

[0039] Bonding pad 108 is connected to bonding pad 101 by power supply wiring 113, and to bonding pad 105 by inner wire 130. Bonding pad 109 is connected to bonding pad 102 by GND wiring 123, and to bonding pad 106 by inner wire 140. Since space is created for bonding pads 103 and 104 that were provided in the second circuit region 12, it becomes possible to add I / O terminal specifications.

[0040] 8(a) shows a plan view of the bonding pad 108 provided in the first circuit region 11, and FIG. 8(b) shows a cross-sectional view. The bonding pad 108 is configured so that the probe 40 does not come into contact with it because the inner wire 130 is connected to it. Therefore, wiring that constitutes the first circuit 31 can also be provided in the region 49 (corresponding to the sixth wiring layer 46) directly below the opening 180 of the bonding pad 108. The same configuration is also used for the bonding pad 109, which is a bonding pad that is connected to the inner wire 140 and provided in the first circuit region 11.

[0041] <Fourth Embodiment> 11(a) and 11(b) will be used to explain a manufacturing method of the semiconductor device 1 according to the first to third embodiments. First, the semiconductor device 1 is prepared in a state before the inner wires 130 and 140 are formed, that is, the semiconductor device 1 in a state in which the semiconductor chip 10 is fixed to the die pad and the wirings 111, 121, and 171 are connected to the power bar 21, the GND ring 22, and the leads of the lead frame 3, respectively.

[0042] Next, the package 2 having the inner wires 130 and 140 is mounted on the semiconductor device 1 using resin. As a result, a plurality of bonding pads in the semiconductor chip 10 are connected by the inner wires 130 and 140, and the semiconductor device 1 is manufactured.

[0043] In this way, it is possible to provide a method for manufacturing a semiconductor device that can achieve both high integration in a semiconductor chip and improved I / O performance and ESD resistance.

[0044] The invention made by the present inventors has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention. [Explanation of symbols]

[0045] 1. Semiconductor device 2 packages 3 Lead Frame 10 Semiconductor chips 11 1st circuit area 12 Second circuit area 20 die pad 21 Power Bar 22 GND ring 30 boards 31 1st circuit 32 2nd circuit 33 Interlayer insulating film 34 Via wiring 35 wiring layer 40 probes 41 1st wiring layer 42 2nd wiring layer 43 3rd wiring layer 44 4th wiring layer 45 5th wiring layer 46 6th wiring layer 47 7th wiring layer 48, 49 area 50 Probe marks 51 Bonding Hall 101~109 Bonding pads 110, 131, 180 openings 111, 121, 171 wiring 112, 113 Power wiring 122, 123 GND wiring 130, 140 inner wire 147 Pad Metal Layer

Claims

1. A semiconductor device including a semiconductor chip, The semiconductor chip comprises: A substrate; a first circuit area on the substrate; a second circuit region disposed on the substrate so as to surround the first circuit region in a plan view of the semiconductor device; a plurality of bonding pads; the substrate includes stacked wiring layers; the first circuit region is provided with a first circuit configured by the wiring layer, the second circuit region is provided with a second circuit configured by the wiring layer, the plurality of bonding pads are formed in the second circuit region and are configured by the uppermost layer of the wiring layer; The plurality of bonding pads include: a first bonding pad and a third bonding pad connected to an external power supply of the semiconductor chip; a second bonding pad and a fourth bonding pad connected to ground; a fifth bonding pad connected to the third bonding pad via a first inner wire; a sixth bonding pad connected to the fourth bonding pad via a second inner wire; In a cross-sectional view of the semiconductor device, In a region where the first bonding pad and the second bonding pad are formed, there is no wiring constituting the second circuit in a layer immediately below the uppermost layer of the wiring layer, In a region where the third bonding pad, the fourth bonding pad, the fifth bonding pad, and the sixth bonding pad are formed, wiring constituting the second circuit is present in a layer immediately below the uppermost layer of the wiring layer. Semiconductor device.

2. the first circuit is a memory circuit or a logic circuit, the second circuit is an input / output circuit or a level shifter; The semiconductor device according to claim 1 .

3. In a cross-sectional view of the semiconductor device, wiring constituting the first circuit is present in a layer immediately below the uppermost layer of the wiring layer. The semiconductor device according to claim 2 .

4. Further, a power supply wiring and a ground wiring are formed on the uppermost layer of the wiring layers, the power supply wiring and the ground wiring overlap with the first circuit area and the second circuit area, the first bonding pad and the third bonding pad are connected to each other by the power supply wiring; the second bonding pad and the fourth bonding pad are connected to each other by the ground wiring; The semiconductor device according to claim 1 .

5. A semiconductor device including a semiconductor chip, The semiconductor chip comprises: A substrate; a first circuit area on the substrate; a second circuit region disposed on the substrate so as to surround the first circuit region in a plan view of the semiconductor device; a plurality of bonding pads; the substrate includes stacked wiring layers; the first circuit region is provided with a first circuit configured by the wiring layer, the second circuit region is provided with a second circuit configured by the wiring layer, the plurality of bonding pads are formed by the uppermost layer of the wiring layer; The plurality of bonding pads include: a first bonding pad formed in the second circuit region and connected to a power supply external to the semiconductor chip; a second bonding pad formed in the second circuit region and connected to ground; a third bonding pad formed in the first circuit region and connected to a power supply external to the semiconductor chip; a fourth bonding pad formed in the first circuit region and connected to ground; a fifth bonding pad formed in the second circuit region and connected to the third bonding pad via a first inner wire; a sixth bonding pad formed in the second circuit region and connected to the fourth bonding pad via a second inner wire; In a cross-sectional view of the semiconductor device, In a region where the first bonding pad and the second bonding pad are formed, there is no wiring constituting the second circuit in a layer immediately below the uppermost layer of the wiring layer, In a region where the third bonding pad and the fourth bonding pad are formed, there is no wiring constituting the first circuit in a layer immediately below the uppermost layer of the wiring layer, In a region where the fifth bonding pad and the sixth bonding pad are formed, wiring constituting the second circuit is present in a layer immediately below the uppermost layer of the wiring layer. Semiconductor device.

6. the first circuit is a memory circuit or a logic circuit, the second circuit is an input / output circuit or a level shifter; The semiconductor device according to claim 5 .

7. In a cross-sectional view of the semiconductor device, wiring constituting the first circuit is present in a layer immediately below the uppermost layer of the wiring layer. The semiconductor device according to claim 6.

8. A method for manufacturing a semiconductor device including a semiconductor chip, The semiconductor chip comprises: A substrate; a first circuit area on the substrate; a second circuit region disposed on the substrate so as to surround the first circuit region in a plan view of the semiconductor device; a plurality of bonding pads; the substrate includes stacked wiring layers; the first circuit region is provided with a first circuit configured by the wiring layer, the second circuit region is provided with a second circuit configured by the wiring layer, the plurality of bonding pads are formed in the second circuit region and are configured by the uppermost layer of the wiring layer; The plurality of bonding pads include: a first bonding pad and a third bonding pad connected to an external power supply of the semiconductor chip; a second bonding pad and a fourth bonding pad connected to ground; a fifth bonding pad connected to the third bonding pad; a sixth bonding pad connected to the fourth bonding pad; In a cross-sectional view of the semiconductor device, In a region where the first bonding pad and the second bonding pad are formed, there is no wiring constituting the second circuit in a layer immediately below the uppermost layer of the wiring layer, in a region where the third bonding pad, the fourth bonding pad, the fifth bonding pad, and the sixth bonding pad are formed, a wiring constituting the second circuit is present in a layer immediately below the uppermost layer of the wiring layer; By mounting a package including a first inner wire and a second inner wire on the semiconductor device, the third bonding pad and the fifth bonding pad are connected to each other via the first inner wire, and the fourth bonding pad and the sixth bonding pad are connected to each other via the second inner wire. A method for manufacturing a semiconductor device.

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