Semiconductor device

Abstract

To provide a semiconductor device capable of improving a breakdown voltage.SOLUTION: The semiconductor device includes a semiconductor substrate, a semiconductor layer provided on the semiconductor substrate, a high voltage element region 50 and a low voltage element region provided in the semiconductor layer, an isolation structure formed on a surface of the semiconductor layer via an insulating film and surrounding a periphery of the high voltage element region so as to isolate the high voltage element region 50 from the low voltage element region, and a buried layer BL interposed between the semiconductor substrate and the semiconductor layer. In a plan view, the high-voltage-element region 50 includes an outer edge 51 having linear side portions 52A to 52D and corner portions 53A to 53D, the buried layer BL includes an overlap portion 20 that overlaps the high-voltage-element region 50 and an outer edge portion 25 that protrudes from the outer edge 51, the outer edge portion 25 includes an extension portion 30 corresponding to the side portions 52A to 52D and a bent portion 35 corresponding to the corner portions 53A to 53D, and the extension portion 30 is wider than the bent portion 35.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a high-voltage element region, a low-voltage element region, an element isolation well that separates these regions, and a buried layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-011089

[0004] [overview] The present disclosure provides a semiconductor device capable of improving breakdown voltage.

[0005] The semiconductor device of the present disclosure includes a semiconductor substrate, a semiconductor layer provided on the semiconductor substrate, a high-voltage element region and a low-voltage element region provided in the semiconductor layer, an isolation structure formed on a surface of the semiconductor layer via an insulating film and surrounding the high-voltage element region to isolate the high-voltage element region from the low-voltage element region, and a buried layer interposed between the semiconductor substrate and the semiconductor layer. In a plan view, the high-voltage element region includes an outer edge having linear sides and corners, the buried layer has an overlapping portion overlapping the high-voltage element region and an outer edge portion extending beyond the outer edge, the outer edge portion including an extension portion corresponding to the side portion and a bend portion corresponding to the corner portion, the width of the extension portion being greater than the width of the bend portion. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is an enlarged view of the device region I shown in FIG. [Figure 3]FIG. 3 is a cross-sectional view taken along line III-III shown in FIG. [Figure 4] FIG. 4 is a schematic diagram showing the relationship between the buried layer and the high-voltage device region in the first embodiment. [Figure 5] FIG. 5 is an enlarged view of region V shown in FIG. [Figure 6] FIG. 6 is a schematic diagram showing the relationship between the buried layer and the high-voltage element region in the comparative example. [Figure 7] FIG. 7 is an enlarged view of region VII shown in FIG. [Figure 8] Fig. 8(a) is a cross-sectional view taken along line VIIIa-VIIIa shown in Fig. 5. Fig. 8(b) is a cross-sectional view taken along line VIIIb-VIIIb shown in Fig. 5. [Figure 9] 9(a) is a cross-sectional view taken along line IXa-IXa shown in FIG. 7, and FIG. 9(b) is a cross-sectional view taken along line IXb-IXb shown in FIG. [Figure 10] FIG. 10 is a graph comparing the impurity concentration along the line L1 shown in FIG. 8 with the impurity concentration along the line L2 shown in FIG. [Figure 11] FIG. 11 is a photograph showing the results of the pressure resistance experiment. [Figure 12] FIG. 12 is an enlarged view showing a main part of the semiconductor device according to the second embodiment. [Figure 13] FIG. 13 is an enlarged view showing a main part of the semiconductor device according to the third embodiment.

[0007] [Detailed explanation] Various exemplary embodiments will be described in detail below with reference to the drawings. Note that the same or equivalent parts in each drawing will be denoted by the same reference numerals, and duplicated explanations will be omitted.

[0008] (First embodiment) FIG. 1 is a plan view of a semiconductor device according to the first embodiment. The semiconductor device 1 according to the first embodiment is a semiconductor chip having a rectangular parallelepiped shape. The thickness direction of the semiconductor device 1 is defined as the Z-axis direction, the direction perpendicular to the Z-axis is defined as the X-axis direction, and the direction perpendicular to both the Z-axis and the X-axis is defined as the Y-axis direction. The semiconductor device 1 has a first main surface 3 and a second main surface 4 (see FIG. 3) that face opposite each other in the Z-axis direction. In the first embodiment, the first main surface 3 is the front surface, and the second main surface 4 is the back surface. The direction from the first main surface 3 to the second main surface 4 is defined as the positive direction of the Z-axis, and the direction from the second main surface 4 to the first main surface 3 is defined as the negative direction of the Z-axis. The semiconductor device 1 has four side surfaces connecting the first main surface 3 and the second main surface 4.

[0009] The first main surface 3 and the second main surface 4 are each perpendicular to the Z axis. The planar shape (shape in plan view) of the first main surface 3 when viewed from the normal direction (Z-axis direction) of the first main surface 3 is rectangular (quadrilateral). The shape of the second main surface 4 in plan view is rectangular (quadrilateral). A pair of opposing side surfaces extend along the XZ plane made up of the X axis and the Z axis. Another pair of opposing side surfaces extend along the YZ plane made up of the Y axis and the Z axis. These adjacent side surfaces are perpendicular to each other, but can also intersect at an angle other than perpendicular.

[0010] The semiconductor device 1 includes a plurality of device regions 10 provided on the first main surface 3. A gap is provided between each device region 10 and each side surface of the semiconductor device 1. These device regions 10 are divisions used for convenience of explanation, and the actual device regions 10 do not have physical boundaries.

[0011] Various devices are formed in each device region 10. In the first embodiment, at least one device region 10 (device region I) includes a high-voltage element region 50 and an isolation structure 15 provided in the semiconductor layer 13. At least one high-voltage element operating at a high reference voltage is disposed in the high-voltage element region 50. The high-voltage element may be an FET such as an LDMISFET (Lateral Double Diffused MISFET). To operate the high-voltage element, a high voltage of, for example, about 100 V or more is applied to the high-voltage element region 50. When the high-voltage element is an LDMISFET, a drain voltage of, for example, 800 V or more can be applied in its off state.

[0012] At least one device region 10 other than the device region I includes a low-voltage element region 55 in which low-voltage elements are arranged, and is arranged adjacent to the device region I. A voltage of, for example, about 0 V to 100 V is applied to the low-voltage element region 55 to operate the low-voltage elements.

[0013] The isolation structure 15 is formed on the first main surface 3 and surrounds the high-voltage element region 50 so as to isolate the high-voltage element region 50 from the low-voltage element region 55. The isolation structure 15 has an overall ring shape in a plan view.

[0014] The semiconductor material constituting the semiconductor device 1 in the first embodiment is silicon (Si). Compound semiconductors can also be used as the semiconductor material constituting the semiconductor device 1. Compound semiconductors include III-V compound semiconductors, IV-IV compound semiconductors, and alloy semiconductors using these semiconductors. Ga-containing semiconductors such as GaAs and GaN can be used as III-V compound semiconductors. Silicon-containing semiconductors such as silicon carbide (SiC) and silicon germanium (SiGe) can be used as IV-IV compound semiconductors.

[0015] 2 is an enlarged view of device region I shown in FIG. 1. Device region I is an example of device region 10 that includes high-voltage device region 50 and isolation structure 15.

[0016] As shown in Fig. 2, the isolation structure 15 includes a field electrode 125 arranged in a spiral shape. The pattern located in the lower right of Fig. 2 illustrates a detailed view of the field electrode 125 near one corner 53 of the high-voltage element region 50. The isolation structure 15 is not limited to a spiral field electrode as long as it provides an isolation effect between the high-voltage element region 50 and the low-voltage element region 55 (see Fig. 1).

[0017] The high-voltage element region 50 has an active region 65. The active region 65 has a rectangular ring shape corresponding to the shape (rectangle) of the high-voltage element region 50 in a plan view, and surrounds the portion where the high-voltage elements are arranged. An outer edge 51 of the high-voltage element region 50 is formed by the outer edge of the active region 65.

[0018] 3 is a cross-sectional view taken along line III-III in FIG. 2, showing a partial cross-sectional configuration of device region I. As shown in FIG. 3, semiconductor device 1 includes semiconductor substrate 11, semiconductor layer 13, buried layer BL, insulating film 60, and isolation structure 15.

[0019] The semiconductor substrate 11 has the second main surface 4 of the semiconductor device 1. The semiconductor layer 13 is provided on the main surface of the semiconductor substrate 11 opposite to the second main surface 4. The semiconductor layer 13 has the first main surface 3 of the semiconductor device 1. A high-voltage element region 50 and a low-voltage element region 55 (see FIG. 1 ) are provided in the semiconductor layer 13. A buried layer BL is provided so as to be interposed between the semiconductor substrate 11 and the semiconductor layer 13. An insulating film 60 is formed on the first main surface 3 of the semiconductor layer 13. An isolation structure 15 is formed on the first main surface 3 of the semiconductor layer 13 via the insulating film 60.

[0020] The semiconductor layer 13 is made of an n-type (first conductivity type) semiconductor. The semiconductor substrate 11 is made of a p-type (second conductivity type) semiconductor. In the first embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the reverse is also possible.

[0021] The device region I includes a first potential region 111, a second potential region 112, and a drift region 113. The first potential region 111 is a region to which a first potential is applied and is located in the center of the device region I. The second potential region 112 is a region to which a second potential different from the first potential is applied and is spaced apart from the first potential region 111 in a cross-sectional view. The second potential region 112 surrounds the first potential region 111 and the drift region 113 in a planar view. For example, the first potential region 111 is a high potential region to which a high potential (first potential) is applied, and the second potential region 112 is a low potential region to which a low potential (second potential) less than the high potential is applied. The drift region 113 is located between the first potential region 111 and the second potential region 112.

[0022] In the semiconductor device 1, the first potential region 111 in the device region I is the high-voltage element region 50. The second potential region 112 in the device region I may be connected to the low-voltage element region 55 in the device region 10 other than the device region I.

[0023] The first potential region 111 includes a drain region 114 and a well region 115. The drain region 114 and the well region 115 are each provided above the semiconductor layer 13. The well region 115 surrounds and is in contact with the drain region 114 in a plan view. The drain region 114 is spaced apart from the inner and outer peripheries of the well region 115 in a plan view. In other words, the drain region 114 is located inside the outer periphery of the well region 115 and outside the inner periphery of the well region 115 in a plan view. The drain region 114 is located inside the well region 115 in a plan view. In a plan view, the center of the drain region 114 in the width direction coincides with the center of the well region 115 in the width direction. The drain region 114 constitutes a part of the first main surface 3.

[0024] The n-type impurity concentration of the well region 115 is higher than the n-type impurity concentration of the semiconductor layer 13. The n-type impurity concentration of the drain region 114 is higher than the n-type impurity concentration of the well region 115. The n-type impurity concentration of the well region 115 is, for example, 1.0×10 15 cm -3 Over 1.0 x 10 18 cm -3 The n-type impurity concentration of the drain region 114 is, for example, 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The following is the result.

[0025] In the first embodiment, the drain region 114 and the well region 115 have a rectangular ring shape in a plan view, but are not limited to this. The drain region 114 and the well region 115 may have a ring shape extending along the outer edge 51 of the high-voltage element region 50. When the high-voltage element region 50 has a polygonal shape other than a rectangular shape (for example, a triangular shape or an L-shape) in a plan view, the drain region 114 and the well region 115 may have a polygonal ring shape corresponding to the shape of the high-voltage element region 50.

[0026] In the first embodiment, the n-type impurity concentration of the buried layer BL is higher than the n-type impurity concentration of the semiconductor layer 13. The n-type impurity concentration of the buried layer BL may be higher than the n-type impurity concentration of the well region 115. The buried layer BL is provided at a position separated from the well region 115 in the Z-axis direction. Therefore, a part of the semiconductor layer 13 is located between the buried layer BL and the well region 115 in the Z-axis direction. The buried layer BL suppresses leakage current from high-voltage elements toward a depth of the semiconductor substrate.

[0027] In a plan view, the buried layer BL is provided so as to overlap the entire high-voltage element region 50. In a plan view, the buried layer BL is provided, for example, outward from the outer periphery of the well region 115. The buried layer BL has a substantially rectangular shape in a plan view, but is not limited to this. The buried layer BL only needs to have a shape that overlaps the entire high-voltage element region 50 in a plan view, and when the high-voltage element region 50 has a polygonal shape other than a rectangular shape (for example, a triangular shape or an L-shape) in a plan view, the buried layer BL may have a polygonal shape corresponding to the shape of the high-voltage element region 50. The area of ​​the buried layer BL in a plan view may be larger than the area of ​​the well region 115.

[0028] The second potential region 112 includes a p-type body region 116 spaced apart from the well region 115 in a plan view. The body region 116 extends, for example, along the periphery of the semiconductor layer 13. Specifically, the body region 116 has a rectangular ring shape surrounding the periphery of the isolation structure 15 in a plan view. The body region 116 extends in the Z-axis direction from the first main surface 3 through the semiconductor layer 13 to the semiconductor substrate 11. Therefore, the body region 116 is electrically connected to the semiconductor substrate 11 and is fixed to the potential of the semiconductor substrate 11 (for example, the back gate potential). The body region 116 may be provided in both the semiconductor substrate 11 and the semiconductor layer 13. The p-type impurity concentration of the body region 116 is, for example, 1.0×10 15 cm -3 Over 1.0 x 10 18 cm -3 The following is the result.

[0029] The semiconductor device 1 includes a source region 117 provided in the body region 116. The source region 117 is an n-type region and is fixed to a source potential. A source potential is applied to the source region 117 from the outside. In the semiconductor layer 13, a p-type channel region 118 in the FET structure is formed between the source region 117 and the drift region 113 in the X-axis direction. Therefore, a current path extending in the X-axis direction is formed in the drift region 113 between the source region 117 and the drift region 113 in the X-axis direction. The source potential corresponds to the second potential. The n-type impurity concentration of the source region 117 is higher than the n-type impurity concentration of the well region 115. The n-type impurity concentration of the source region 117 may be equal to the n-type impurity concentration of the drain region 114. The n-type impurity concentration of the source region 117 is, for example, 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The channel region 118 controls whether the current path between the drain region 114 and the source region 117 is conductive or non-conductive.

[0030] In plan view, the source region 117 is located within the body region 116 and inside the outer periphery of the body region 116. The source region 117 constitutes part of the first main surface 3, that is, part of the surface layer portion of the body region 116.

[0031] The second potential region 112 includes a contact region 119 provided in the body region 116. In the first embodiment, the semiconductor device 1 includes the contact region 119. The contact region 119 is a p-type region. The p-type impurity concentration of the contact region 119 may be higher than the p-type impurity concentration of the body region 116. For example, the p-type impurity concentration of the contact region 119 is, for example, 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The following is the result.

[0032] In a plan view, the contact region 119 is located within the body region 116 and inside the outer periphery of the body region 116. The contact region 119 is located closer to the outer periphery of the body region 116 than the source region 117. The contact region 119 constitutes part of the first main surface 3, i.e., part of the surface layer portion of the body region 116.

[0033] In a plan view, the contact region 119 is located between the corresponding source region 117 and the outer periphery of the body region 116. In a plan view, the contact region 119 is adjacent to the source region 117. Therefore, in the surface layer portion of the body region 116, the source region 117, which is fixed to the source potential, and the contact region 119, which is fixed to a potential different from the source potential, coexist.

[0034] The semiconductor device 1 includes an n-type drift region 113 located between the drain region 114 and the source region 117 and in a surface layer portion of the semiconductor layer 13. The drift region 113 has, for example, a rectangular ring shape surrounding the drain region 114 in a plan view. The width of the drift region 113 corresponds to the distance between the first potential region 111 and the second potential region 112.

[0035] The insulating film 60 selectively covers the first main surface 3 in the device region I. The insulating film 60 contains silicon oxide. The insulating film 60 includes a LOCOS film (Local oxidation of silicon film) formed by selective oxidation of the first main surface 3, a buried oxide film (STI: Shallow Trench Isolation) that fills shallow trenches provided in the first main surface 3, and the like. The insulating film 60 may have a single-layer structure or a multilayer structure.

[0036] The insulating film 60 is located above the drift region 113 in the Z-axis direction and covers the region between the drain region 114 and the source region 117 on the first main surface 3. The insulating film 60 has, for example, a rectangular ring shape surrounding the drain region 114 in a plan view and includes an inner edge portion 60a and an outer edge portion 60b. In the first embodiment, the inner edge portion 60a of the insulating film 60 overlaps the outer edge portion of the drain region 114 in the Z-axis direction, but it does not have to overlap the drain region 114. The outer edge portion 60b of the insulating film 60 is located inside the inner edge of the body region 116 in a plan view.

[0037] The drain region 114, the body region 116, the source region 117, the contact region 119, and the drift region 113 have exposed surfaces that are exposed from the insulating film 60. The exposed surface of the drain region 114 constitutes an active region 65. Since the drain region 114 is part of the first main surface 3, it can be said that the first main surface 3 has an annular active region 65 that is exposed from the insulating film 60.

[0038] The semiconductor device 1 includes a field electrode 125 located on the insulating film 60 in the device region I. The field electrode 125 has functions such as suppressing electric field disturbances in the semiconductor layer 13, suppressing localized electric field concentration, and monitoring the high drain-gate voltage Vdg. The field electrode 125 is a high-resistance film connected to the first potential region 111 and the second potential region 112.

[0039] The field electrode 125 overlaps the drift region 113 in the Z-axis direction. In the first embodiment, the field electrode 125 does not overlap the channel region 118 in the Z-axis direction. The field electrode 125 includes, for example, polysilicon. The field electrode 125 is electrically connected to at least the drain region 114. In the first embodiment, the field electrode 125 forms a potential gradient that gradually changes from the first potential region 111 toward the second potential region 112. By providing such a field electrode 125, bias in the electric field distribution in the drift region 113 is suppressed. The thickness of the field electrode 125 is, for example, not less than 50 nm and not more than 100 nm.

[0040] For example, the field electrode 125 surrounds the first potential region 111 multiple times in a plan view. In the first embodiment, the field electrode 125 has a spiral shape surrounding the first potential region 111 in a plan view.

[0041] The field electrode 125 has one end 129 located near the drain region 114, another end 127 located near the body region 116, and a spiral portion 128 extending between the one and other ends.

[0042] One end 129 of the field electrode 125 is a connection portion that is electrically connected to the drain region 114. The one end 129 is the innermost portion (innermost periphery) of the field electrode 125. The potential of the one end 129 is fixed to a first potential. The one end 129 may overlap the well region 115 in the Z-axis direction.

[0043] The other end 127 of the field electrode 125 is the outermost portion (outermost periphery) of the field electrode 125. The potential applied to the other end 127 is the second potential or a potential close to the second potential. The other end 127 may overlap the drift region 113 in the Z-axis direction.

[0044] The spiral portion 128 of the field electrode 125 is a portion that connects the one end 129 and the other end 127 described above. The spiral portion 128 is wound in a rectangular spiral shape from the one end 129 to the other end 127 so as to surround the first potential region 111 in a plan view. The spiral portion 128 overlaps with the drift region 113 in the Z axis direction. A portion of the spiral portion 128 may overlap with the well region 115.

[0045] Field electrode 125 forms a potential gradient in the spiral direction from one end 129 to the other end 127. Field electrode 125 forms a potential gradient that gradually decreases in a direction perpendicular to the spiral direction from first potential region 111 to second potential region 112 in accordance with the winding pitch of the spiral portion. Field electrode 125 thins out the electric field in drift region 113, suppressing bias in the electric field distribution in drift region 113.

[0046] The field electrode 125 may have a line width of 0.5 μm or more and 5 μm or less. The line width is defined by the width in a direction perpendicular to the extension direction (i.e., the spiral direction) of the field electrode 125. One end 129 may be formed wider than the other end 127 and the spiral portion 128. The field electrode 125 may have a resistance value of 10 MΩ or more and 100 MΩ or less.

[0047] The pitch of the field electrode 125 may be 1 μm or more and 10 μm or less. The pitch of the field electrode 125 is defined by the distance between adjacent line portions (i.e., the winding pitch of the spiral portion). The number of turns of the field electrode 125 is, for example, 5 to 100. The number of turns may be 75 or less, or 50 or less.

[0048] The semiconductor device 1 includes a gate insulating film 131 that is in contact with the semiconductor layer 13 and located on the channel region 118. A portion of the gate insulating film 131 overlaps the insulating film 60. The thickness of the gate insulating film 131 is less than that of the insulating film 60, and is, for example, 10 nm to 200 nm. The gate insulating film 131 has a single-layer structure or a multilayer structure and includes, for example, a silicon oxide film. In the first embodiment, the gate insulating film 131 has a rectangular ring shape that surrounds the insulating film 60 in a plan view. The gate insulating film 131 covers a portion of the drift region 113 and a portion of the body region 116.

[0049] The semiconductor device 1 includes a gate electrode 132 located on a gate insulating film 131. The gate electrode 132 includes, for example, a metal film, an alloy film, or conductive polysilicon. When the gate electrode 132 includes conductive polysilicon, the conductive polysilicon includes at least one of an n-type region and a p-type region. The gate electrode 132 overlaps not only the channel region 118 but also the drift region 113 in the Z-axis direction. In a plan view, the gate electrode 132 has a rectangular ring shape extending along the channel region 118, but is not limited to this. The gate electrode 132 has a lead portion 133 that is led from the gate insulating film 131 onto the insulating film 60. In a plan view, the lead portion 133 has a rectangular ring shape surrounding the field electrode 125 and is located above the drift region 113. In addition, the entire gate electrode 132 is located outside the field electrode 125 in a plan view.

[0050] The semiconductor device 1 includes an insulating layer 40 that covers a plurality of device regions 10 on the first main surface 3. The insulating layer 40 has a layered structure including a plurality of interlayer insulating films 41 stacked on top of each other. The number of stacked interlayer insulating films 41 is arbitrary and is not limited to a specific number. The insulating layer 40 may include three or more interlayer insulating films 41. FIG. 3 shows a first interlayer insulating film 41A and a second interlayer insulating film 41B among the plurality of interlayer insulating films 41.

[0051] The first interlayer insulating film 41A and the second interlayer insulating film 41B are stacked in this order in the Z-axis direction. The first interlayer insulating film 41A covers at least the first main surface 3, the insulating film 60, the gate insulating film 131, and the gate electrode 132. The second interlayer insulating film 41B covers the first interlayer insulating film 41A. The thicknesses of the first interlayer insulating film 41A and the second interlayer insulating film 41B are determined depending on, for example, the function required of the field electrode 125, the thickness of the insulating film 60, and the like. The first interlayer insulating film 41A and the second interlayer insulating film 41B each include at least one of a silicon oxide film and a silicon nitride film. Therefore, the first interlayer insulating film 41A and the second interlayer insulating film 41B may each have a single-layer structure or a multilayer structure.

[0052] A plurality of wiring films 42 are provided within the insulating layer 40. In the first embodiment, a plurality of interlayer insulating films 41 and a plurality of wiring films 42 are alternately stacked. Therefore, a multilayer wiring structure is provided on the semiconductor layer 13. The number of stacked wiring films 42 is arbitrary and is not limited to a specific number. FIG. 3 shows, of the plurality of wiring films 42, a first wiring film 42A located on a first interlayer insulating film 41A and a second wiring film 42B located on a second interlayer insulating film 41B. Each wiring film 42 includes, for example, at least one of an Al film, a Cu film, an AlSiCu alloy film, an AlSi alloy film, and an AlCu alloy film. Therefore, each of the first wiring film 42A and the second wiring film 42B may have a single-layer structure or a multilayer structure.

[0053] A plurality of first vias 43 and a plurality of second vias 49 are provided in the insulating layer 40. Each of the plurality of first vias 43 is a conductive portion that electrically connects conductive portions, such as the first potential region 111, the second potential region 112, and the field electrode 125, located below the first interlayer insulating film 41A to the first wiring film 42A, and penetrates the first interlayer insulating film 41A. Each of the plurality of second vias 49 is a conductive portion that electrically connects conductive portions, such as the first wiring film 42A located below the second interlayer insulating film 41B, to the second wiring film 42B, and penetrates the second interlayer insulating film 41B. Each of the plurality of first vias 43 and the plurality of second vias 49 is, for example, a tungsten plug.

[0054] The first wiring film 42A includes, for example, a first drain wiring 44, a first source wiring 45, a first gate wiring 46, and a field wiring 48. The first drain wiring 44 is electrically connected to the drain region 114 and one end 129 of the field electrode 125 through one or more first vias 43. The first source wiring 45 is electrically connected to the source region 117 through one or more first vias 43. The first gate wiring 46 is electrically connected to the gate electrode 132 through one or more first vias 43. The field wiring 48 is electrically connected to the other end 127 of the field electrode 125 through one or more first vias 43. The field wiring 48 may be part of the first source wiring 45.

[0055] The multiple second wiring films 42B include, for example, a second drain wiring 150, a second source wiring 151, and a second gate wiring (not shown). The second drain wiring 150 is electrically connected to the first drain wiring 44 through multiple second vias 49. The second drain wiring 150 overlaps the drain region 114. The second drain wiring 150 may overlap the entire drain region 114. The second drain wiring 150 may overlap one end 129 of the field electrode 125. The second source wiring 151 is electrically connected to the first source wiring 45 and the field wiring 48 through multiple second vias 49. The second source wiring 151 has a ring shape extending along the body region 116 in a plan view. The second source wiring 151 may overlap the gate electrode 132 and the field wiring 48. The second source wiring 151 may overlap the entire body region 116, the entire gate electrode 132, and the entire field wiring 48.

[0056] 4 is a schematic diagram showing the relationship between the buried layer and the high-voltage element region in the first embodiment. In FIG. 4, only the buried layer BL and the high-voltage element region 50 are shown in plan view, and other parts are omitted.

[0057] As shown in FIG. 4, the high-voltage element region 50 has a substantially rectangular shape in plan view. In plan view, the high-voltage element region 50 has a square shape, for example, but may have a rectangular shape as shown in FIG. 1. The high-voltage element region 50 includes an outer edge 51. The outer edge 51 has linear sides 52 and corners 53. The sides 52 have four sides 52A to 52D. The corners 53 have four corners 53A to 53D. The buried layer BL is located below the high-voltage element region 50 in the Z-axis direction. In plan view, the buried layer BL has a substantially rectangular shape. The buried layer BL has a larger area than the high-voltage element region 50.

[0058] 4, the buried layer BL has an overlapping portion 20 that overlaps with the high-voltage element region 50, and an outer edge portion 25 that protrudes from an outer edge 51 of the high-voltage element region 50. The outer edge portion 25 of the buried layer BL includes extension portions 30 that correspond to the side portions 52 of the high-voltage element region 50, and bent portions 35 that correspond to the corner portions 53 of the high-voltage element region 50. The number of extension portions 30 is equal to the number of side portions 52, which is four in the first embodiment. The number of bent portions 35 is equal to the number of corner portions 53, which is four in the first embodiment.

[0059] Furthermore, the configuration of the vicinity of the bent portion 35 corresponding to the corner 53A will be described using FIG. 5. FIG. 5 is an enlarged view of region V shown in FIG. 4. FIG. 5 also shows the active region 65 in addition to the buried layer BL and the high-voltage element region 50. As shown in FIGS. 4 and 5, the radius of curvature of the bent portion 35 is larger than the radius of curvature of the corner 53. As a result, in a plan view, the outer edge of the buried layer BL at the bent portion 35 has a shape that is set back (set back) toward the outer edge 51 of the high-voltage element region 50 compared to the extension portion 30. Because the outer edge of the buried layer BL is close to the outer edge 51 of the high-voltage element region 50 at the bent portion 35 in this way, the width W1 of the extension portion 30 is larger than the width W2 (not shown) of the bent portion 35.

[0060] The width W1 is the distance by which the buried layer BL in the extension portion 30 protrudes from the side portion 52 of the high-voltage element region 50. The width W1 may be a constant value along the extension direction of the extension portion 30, or may vary. The width W1 is, for example, the maximum width of the extension portion 30. The width W1 may be the width of the outer edge portion 25 at the midpoint of the side portion 52. In this case, the width W1 is the distance by which the buried layer BL protrudes from the midpoint of the side portion 52 in a direction perpendicular to the side portion 52.

[0061] The width W2 is the distance by which the buried layer BL protrudes from the corner 53 of the high-voltage device region 50 at the bent portion 35. The width W2 is, for example, the width of the outer edge 25 at the vertex of the corner 53. In other words, the width W2 is the distance by which the buried layer BL protrudes from the vertex of the corner 53 in a direction perpendicular to the tangent to the vertex of the corner 53. The width W2 may also be the distance between the vertex of the bent portion 35 and the vertex of the corner 53.

[0062] 4 and 5 show, as an example, a case where the vertex of bent portion 35 overlaps with the vertex of corner portion 53. That is, the distance (width W2) between the vertex of bent portion 35 and the vertex of corner portion 53 is zero.

[0063] The principle of the improved breakdown voltage of the semiconductor device 1 will be explained below by comparing it with a semiconductor device 100 according to a comparative example. FIG. 6 is a schematic diagram showing the relationship between the buried layer and the high-voltage element region in the comparative example. FIG. 7 is an enlarged view of region VII shown in FIG. 6. As shown in FIGS. 4 to 7, the semiconductor device according to the comparative example differs from the semiconductor device 1 according to the first embodiment in that it includes a buried layer BL1 instead of the buried layer BL, but is the same in other respects.

[0064] The buried layer BL has a setback shape at the bent portion 35, whereas the buried layer BL1 does not have a setback shape. In plan view, the outer edge of the buried layer BL1 protrudes from the outer edge 51 by approximately the same amount at both the bent portion 35 and the extended portion 30. That is, in the buried layer BL1, the width W1 is equal to the width W2.

[0065] Further, the description will be made by comparing cross-sectional views at the same position in Fig. 5 and Fig. 7. Fig. 8(a) is a cross-sectional view taken along line VIIIa-VIIIa shown in Fig. 5, and Fig. 8(b) is a cross-sectional view taken along line VIIIb-VIIIb shown in Fig. 5. Fig. 9(a) is a cross-sectional view taken along line IXa-IXa shown in Fig. 7, and Fig. 9(b) is a cross-sectional view taken along line IXb-IXb shown in Fig. 7.

[0066] 8(a) and 8(b) are cross-sectional views showing the positional relationship between the buried layer BL1 and the active region 65 in the extension portion 30 and the bending portion 35 according to the first embodiment. FIGS. 9(a) and 9(b) are cross-sectional views showing the positional relationship between the buried layer BL1 and the active region 65 in the extension portion 30 and the bending portion 35 according to a comparative example. Comparing FIGS. 8(a) and 8(b) reveals that in the first embodiment, the outer edge of the buried layer BL in the bending portion 35 is recessed toward the active region 65 from the outer edge of the buried layer BL in the extension portion 30. Comparing FIGS. 9(a) and 9(b) reveals that the outer edge of the buried layer BL1 in the bending portion 35 and the outer edge of the buried layer BL1 in the extension portion 30 protrude from the outer edge 51 of the active region 65 by approximately the same amount. Comparing FIGS. 8(a) and 9(a) reveals that in the extension portion 30, the extent to which the buried layer BL protrudes is the same as the extent to which the buried layer BL1 protrudes.

[0067] Furthermore, in FIGS. 8(b) and 9(b), the impurity concentration was measured along lines L1 and L2, respectively, which pass through one end 129 of the field electrode 125 and extend in the Z-axis direction. FIG. 10 is a graph comparing the impurity concentration along line L1 in FIG. 8 with the impurity concentration along line L2 in FIG. 9. As shown in FIG. 10, when moving along the Z-axis direction, the impurity concentration changes gradually along line L1, whereas the impurity concentration changes rapidly along line L2. This is because the comparative example includes a buried layer BL1 with a high impurity concentration between the semiconductor layer 13 and the semiconductor substrate 11, whereas the example corresponding to the first embodiment includes only the semiconductor layer 13 and the semiconductor substrate 11. In particular, electric field concentration is likely to occur near the corners 53 of the high-voltage device region 50, and a sudden increase in the impurity concentration may cause a breakdown.

[0068] The inventors conducted a breakdown voltage experiment for each of the example and comparative example. Figure 11 is a photograph showing the results of the breakdown voltage experiment. More specifically, while applying a voltage to the high-voltage element region of the semiconductor device according to the example and comparative example, the location where breakdown occurred was analyzed by light emission analysis. Figure 11 shows that breakdown occurred near a corner of the high-voltage element region. In this experiment, a semiconductor device was used in which one electrode pad was arranged over the entire portion of the inside of the active region where the high-voltage element was arranged.

[0069] The inventors conducted a breakdown voltage experiment for each of the example and the comparative example, and measured the breakdown voltage. The breakdown voltage of the example was 62 V higher than that of the comparative example. That is, in the first embodiment, the width by which the bent portion 35 of the buried layer BL protrudes from the outer edge 51 of the high-voltage element region 50 is made smaller than the width by which the extended portion 30 of the buried layer BL protrudes from the outer edge 51 of the high-voltage element region 50, thereby alleviating electric field concentration near the corners 53 of the high-voltage element region 50 and improving the breakdown voltage.

[0070] (Second embodiment) FIG. 12 is an enlarged view showing a main portion of a semiconductor device according to the second embodiment. In the semiconductor device 1A according to the second embodiment, the bent portion 35A of the buried layer BL is provided to include a first portion 70 having the same impurity concentration as the extension portion 30 and a second portion 75 having a lower impurity concentration than the extension portion 30. In FIG. 12, the first portion 70 and the second portion 75 are alternately arranged in a striped pattern. This reduces the average impurity concentration in the bent portion 35A. Therefore, the impurity concentration in the extension portion 30 is higher than the impurity concentration in the bent portion 35A. This reduces electric field concentration near the corner 53 of the high-voltage element region 50, improving the breakdown voltage.

[0071] The first portions 70 and the second portions 75 each have a shape that follows the outer shape of the corner 53 of the high-voltage element region 50. In the illustrated example, the first portions 70 and the second portions 75 each have an arc shape that follows the arc of the corner 53. The first portions 70 and the second portions 75 are alternately arranged from the inside to the outside of the bent portion 35A. In the illustrated example, the second portion 75 is arranged at the innermost part of the bent portion 35A and is adjacent to the arc of the corner 53 of the high-voltage element region 50. A second portion 75 is also arranged at the outermost part of the bent portion 35A. Thus, the number of second portions 75 is greater than the number of first portions 70. However, the arrangement order of the first portions 70 and the second portions 75 may be reversed, and the number of first portions 70 and second portions 75 may be changed. The pitch width P, which is the total width of a pair of adjacent first portions 70 and second portions 75, is, for example, 1 μm.

[0072] The arrangement and shape of the first portion 70 and the second portion 75 can be adjusted as appropriate, for example, by the pattern of a mask used when forming the buried layer BL by ion implantation.

[0073] The inventors also conducted a breakdown voltage experiment on an example corresponding to the illustrated example of the second embodiment. The breakdown voltage of the example corresponding to the illustrated example of the second embodiment was improved by 15 V compared to the breakdown voltage of the comparative example.

[0074] (Third embodiment) 13 is an enlarged view showing a main portion of a semiconductor device according to the third embodiment. In the semiconductor device 1B according to the third embodiment, the bent portion 35B of the buried layer BL is provided to include a first portion 70 having the same impurity concentration as the impurity concentration in the extension portion 30, and a second portion 75 having an impurity concentration lower than the impurity concentration in the extension portion 30. In FIG. 13, the first portions 70 and the second portions 75 are alternately arranged in a matrix. This reduces the electric field near the corners of the high-voltage element region 50, thereby improving the breakdown voltage.

[0075] According to the embodiment described above, it is possible to provide a semiconductor device capable of improving the breakdown voltage.

[0076] In the embodiments described above, one or more elements of one embodiment may be combined with one or more elements of another embodiment.

[0077] Below, examples of features extracted from the description of this specification and the drawings are shown.

[0078] [A1] A semiconductor substrate (11), a semiconductor layer (13) provided on the semiconductor substrate; a high-voltage element region (50) and a low-voltage element region (55) provided in the semiconductor layer; an isolation structure (15) formed on the surface (3) of the semiconductor layer via an insulating film (60), surrounding the periphery of the high-voltage element region (50) so as to isolate the high-voltage element region (50) from the low-voltage element region (55); a buried layer (BL) interposed between the semiconductor substrate and the semiconductor layer; Equipped with In plan view, the high-voltage element region (50) includes an outer edge (51) having linear sides (52A to 52D) and corners (53A to 53D); the buried layer (BL) has an overlapping portion (20) overlapping with the high-voltage element region and an outer edge portion (25) extending beyond the outer edge, The outer edge portion includes an extension portion (30) corresponding to the side portion and a bent portion (35) corresponding to the corner portion, The semiconductor device (1) has a width (W1) of the extending portion greater than a width (W2) of the bent portion.

[0079] [A2] the surface of the semiconductor layer includes an annular active region (65) exposed from the insulating film (60); the outer edge is formed by the outer edge of the active area. The semiconductor device according to [A1].

[0080] [A3] In plan view, the high-voltage device region has a rectangular shape; The semiconductor device according to [A2], wherein the active region has a rectangular ring shape corresponding to the shape of the high-voltage element region.

[0081] [A4] The semiconductor device according to any one of [A1] to [A3], wherein, in a plan view, the radius of curvature of the bent portion is larger than the radius of curvature of the corner portion.

[0082] [A5] The semiconductor device according to [A4], wherein, in a plan view, a vertex of the bent portion and a vertex of the corner portion overlap.

[0083] [A6] a semiconductor substrate; a semiconductor layer provided on the semiconductor substrate; a high-voltage element region and a low-voltage element region provided in the semiconductor layer; an isolation structure formed on the surface of the semiconductor layer via an insulating film, the isolation structure surrounding the high-voltage element region so as to isolate the high-voltage element region from the low-voltage element region; a buried layer interposed between the semiconductor substrate and the semiconductor layer; Equipped with In plan view, the high-voltage element region includes an outer edge having linear sides and corners; the buried layer has an overlapping portion that overlaps with the high-voltage element region and an outer edge portion that protrudes from the outer edge, the outer edge portion includes an extension portion corresponding to the side portion and a bent portion corresponding to the corner portion, The semiconductor device, wherein the extension portion has a higher impurity concentration than the bent portion.

[0084] [A7] the surface of the semiconductor layer includes an annular active region exposed from the insulating film; The semiconductor device according to [A6], wherein the outer edge is formed by the outer edge of the active region.

[0085] [A8] In plan view, the high-voltage device region has a rectangular shape; The semiconductor device according to [A7], wherein the active region has a rectangular ring shape corresponding to the shape of the high-voltage element region.

[0086] [A9] The semiconductor device according to any one of [A6] to [A8], wherein the bent portion includes a first portion (70) having the same impurity concentration as the impurity concentration in the extension portion, and a second portion (75) having an impurity concentration lower than the impurity concentration in the extension portion.

[0087] [A10] The semiconductor device according to [A9], wherein the first portions and the second portions are alternately arranged in a striped pattern.

[0088] [A11] The semiconductor device according to [A9], wherein the first portions and the second portions are alternately arranged in a matrix. [Explanation of symbols]

[0089] 1, 1A, 1B...Semiconductor device 3...First main surface (front surface) 4...Second main surface (back surface) 10,I...Device area 11...Semiconductor substrate 13...Semiconductor layer 15...Separated structure 20...Overlapping section 25...Outer edge 30...Extension part 35,35A,35B…Bending part 40...insulating layer 41...Interlayer insulating film 41A...First interlayer insulating film 41B...Second interlayer insulating film 42...Wiring film 42A…1st wiring film 42B…Second wiring film 43...First via 44...First drain wiring 45...First source wiring 46...First gate wiring 48...Field wiring 49...Second via 50...High voltage element area 51...Outer edge 52,52A~52D…side part 53,53A~53D…Corner part 55...Low voltage element area 60...Insulating film 60a...inner edge 60b...Outer edge 65...Active area 70…Part 1 75…Second part 100...Semiconductor device 111...first potential region 112…Second potential area 113...Drift region 114...Drain region 115...Well area 116...Body area 117...Source region 118...Channel region 119…Contact area 125...Field electrode 127...Other end 128...Spiral part 129...One end 131...Gate insulating film 132...gate electrode 133...Drawer section 150...Second drain wiring 151...Second source wiring BL, BL1...embedding layer P: Pitch width L1,L2…straight line W1, W2...Width

Claims

1. a semiconductor substrate; a semiconductor layer provided on the semiconductor substrate; a high-voltage element region and a low-voltage element region provided in the semiconductor layer; an isolation structure formed on the surface of the semiconductor layer via an insulating film, the isolation structure surrounding the high-voltage element region so as to isolate the high-voltage element region from the low-voltage element region; a buried layer interposed between the semiconductor substrate and the semiconductor layer; Equipped with In plan view, the high-voltage element region includes an outer edge having linear sides and corners; the buried layer has an overlapping portion that overlaps with the high-voltage element region and an outer edge portion that protrudes from the outer edge, the outer edge portion includes an extension portion corresponding to the side portion and a bent portion corresponding to the corner portion, The semiconductor device, wherein the width of the extending portion is greater than the width of the bent portion.

2. the surface of the semiconductor layer includes an annular active region exposed from the insulating film; the outer edge is formed by the outer edge of the active area. The semiconductor device according to claim 1 .

3. In plan view, the high-voltage device region has a rectangular shape; 3. The semiconductor device according to claim 2, wherein said active region has a rectangular ring shape corresponding to the shape of said high-voltage element region.

4. 3. The semiconductor device according to claim 1, wherein the radius of curvature of the bent portion is larger than the radius of curvature of the corner portion in a plan view.

5. The semiconductor device according to claim 4 , wherein an apex of the bent portion and an apex of the corner portion overlap each other in a plan view.

6. a semiconductor substrate; a semiconductor layer provided on the semiconductor substrate; a high-voltage element region and a low-voltage element region provided in the semiconductor layer; an isolation structure formed on the surface of the semiconductor layer via an insulating film, the isolation structure surrounding the high-voltage element region so as to isolate the high-voltage element region from the low-voltage element region; a buried layer interposed between the semiconductor substrate and the semiconductor layer; Equipped with In plan view, the high-voltage element region includes an outer edge having linear sides and corners; the buried layer has an overlapping portion that overlaps with the high-voltage element region and an outer edge portion that protrudes from the outer edge, the outer edge portion includes an extension portion corresponding to the side portion and a bent portion corresponding to the corner portion, The semiconductor device, wherein the extension portion has a higher impurity concentration than the bent portion.

7. the surface of the semiconductor layer includes an annular active region exposed from the insulating film; the outer edge is formed by the outer edge of the active area. The semiconductor device according to claim 6.

8. In plan view, the high-voltage device region has a rectangular shape; 8. The semiconductor device according to claim 7, wherein said active region has a rectangular ring shape corresponding to the shape of said high-voltage element region.

9. 8. The semiconductor device according to claim 6, wherein the bent portion includes a first portion having the same impurity concentration as the impurity concentration in the extending portion, and a second portion having an impurity concentration lower than the impurity concentration in the extending portion.

10. The semiconductor device according to claim 9 , wherein the first portions and the second portions are alternately arranged in a striped pattern.

11. The semiconductor device according to claim 9 , wherein the first portions and the second portions are alternately arranged in a matrix.

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