Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device capable of improving a breakdown voltage, and to provide a method of manufacturing the semiconductor device.SOLUTION: The semiconductor device 1 includes a semiconductor substrate 11, a buried semiconductor layer 13, an epitaxial semiconductor layer 14, a device 50, and an isolation structure 20. The isolation structure 20 has a trench 21 extending from the 14a of the epitaxial layer 14 to a position penetrating the buried layer 13, an insulating film 22 covering the side 21b of the trench 21, and a conductive material 23 provided in the trench 21 so as to be surrounded by the insulating film 22. An angle θ between a partial side 21b of the side 21b1 located in the epitaxial layer 14 and a front side 13a of the buried layer 13 facing the epitaxial layer 14 satisfies θ> 90 °.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a deep trench isolation (DTI) structure. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-2623

[0004] [overview] The present disclosure provides a semiconductor device and a method for manufacturing the semiconductor device that can improve the breakdown voltage.

[0005] The semiconductor device of the present disclosure comprises a semiconductor substrate, a buried semiconductor layer provided on the semiconductor substrate, a first epitaxial semiconductor layer provided on the buried semiconductor layer, a device provided in the first epitaxial semiconductor layer, and an isolation structure surrounding the device, wherein the isolation structure has a trench extending from a surface of the first epitaxial semiconductor layer to a position penetrating the buried semiconductor layer, an insulating film covering a side surface of the trench, and a conductive region provided in the trench so as to be surrounded by the insulating film, and an angle θ formed between a portion of the side surface located within the first epitaxial semiconductor layer and a surface of the buried semiconductor layer facing the first epitaxial semiconductor layer satisfies θ>90°. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a diagram showing a cross-sectional configuration of a device region in the semiconductor device of FIG. [Figure 3] FIG. 3 is an enlarged view showing the cross-sectional configuration of the isolation structure of FIG. [Figure 4] FIG. 4 is an enlarged view showing a cross-sectional configuration of an isolation structure according to a modified example. [Figure 5] FIG. 5 is a diagram illustrating a cross-sectional configuration of a device according to an example. [Figure 6] 6(A) to 6(F) are cross-sectional views for explaining a method for manufacturing a semiconductor device. [Figure 7] 7(A) to 7(F) are cross-sectional views for explaining a method for manufacturing a semiconductor device. [Figure 8] FIG. 8 is an enlarged view showing a cross-sectional configuration of an isolation structure according to a comparative example.

[0007] [Detailed explanation] Various exemplary embodiments will be described in detail below with reference to the drawings. Note that the same or equivalent parts in the drawings will be denoted by the same reference numerals, and redundant explanations will be omitted.

[0008] (Semiconductor Devices) FIG. 1 is a plan view of a semiconductor device according to an embodiment. The semiconductor device 1 according to the embodiment is a semiconductor chip having a rectangular parallelepiped shape. The thickness direction of the semiconductor device 1 is defined as the Z-axis direction, the direction perpendicular to the Z-axis is defined as the X-axis direction, and the direction perpendicular to both the Z-axis and the X-axis is defined as the Y-axis direction. The semiconductor device 1 has a first main surface 3 and a second main surface 4 (see FIG. 2) that face opposite each other in the Z-axis direction. The direction from the first main surface 3 toward the second main surface 4 is defined as the positive direction of the Z-axis, and the direction from the second main surface 4 toward the first main surface 3 is defined as the negative direction of the Z-axis. The semiconductor device 1 has a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D that connect the first main surface 3 and the second main surface 4.

[0009] The first main surface 3 and the second main surface 4 are each perpendicular to the Z axis. The planar shape (shape in plan view) of the first main surface 3 when viewed from the normal direction (Z axis direction) of the first main surface 3 is a rectangle (quadrilateral). The shape of the second main surface 4 is also a rectangle (quadrilateral). The first side surface 5A and the second side surface 5B, which constitute two opposing sides of the rectangle in plan view, each extend along the X axis direction. The third side surface 5C and the fourth side surface 5D, which constitute the other two opposing sides of the rectangle in plan view, each extend along the Y axis direction. These adjacent side surfaces are perpendicular to each other in plan view, but can also intersect at an angle other than perpendicular.

[0010] The semiconductor device 1 includes a plurality of device regions 10 provided on the first main surface 3. A gap is provided between each device region 10 and each side surface (first side surface 5A to fourth side surface 5D) of the semiconductor device 1. These device regions 10 are divisions used for convenience of explanation, and the actual device regions 10 do not have physical boundaries.

[0011] Various devices are formed in each device region 10. In this embodiment, at least one device region 10 includes a device 50 and an isolation structure 20. The isolation structure 20 is annular in plan view and surrounds the device 50.

[0012] The semiconductor material constituting the semiconductor device 1 of this embodiment is silicon (Si). Compound semiconductors can also be used as the semiconductor material constituting the semiconductor device 1. Compound semiconductors include III-V compound semiconductors, IV-IV compound semiconductors, and alloy semiconductors using these semiconductors. Ga-containing semiconductors such as GaAs and GaN can be used as III-V compound semiconductors. Silicon-containing semiconductors such as silicon carbide (SiC) and silicon germanium (SiGe) can be used as IV-IV compound semiconductors.

[0013] Fig. 2 is a diagram showing a cross-sectional configuration of a device region in the semiconductor device of Fig. 1. This diagram shows a cross-sectional configuration of a device region 10 taken along the arrow line II-II in Fig. 1. The semiconductor device 1 includes a semiconductor substrate 11, an epitaxial semiconductor layer 12 (second epitaxial semiconductor layer), a buried semiconductor layer 13, an epitaxial semiconductor layer 14 (first epitaxial semiconductor layer), and an insulating region 15. A buffer layer may be formed between the epitaxial semiconductor layer 12 and the buried semiconductor layer 13.

[0014] The semiconductor substrate 11 has the second main surface 4 of the semiconductor device 1. The epitaxial semiconductor layer 12 is provided on the main surface of the semiconductor substrate 11 opposite the second main surface 4. The epitaxial semiconductor layer 12 is provided between the semiconductor substrate 11 and the buried semiconductor layer 13. The buried semiconductor layer 13 is provided on the epitaxial semiconductor layer 12. The buried semiconductor layer 13 is provided on the semiconductor substrate 11 with the epitaxial semiconductor layer 12 interposed therebetween. The buried semiconductor layer 13 has a surface 13a facing the epitaxial semiconductor layer 14. The epitaxial semiconductor layer 14 is formed on the buried semiconductor layer 13.

[0015] The semiconductor substrate 11 and the epitaxial semiconductor layer 12 are made of silicon and have P-type conductivity. The buried semiconductor layer 13 and the epitaxial semiconductor layer 14 are made of silicon and have N-type conductivity. These conductivity types are interchangeable. An exemplary P-type impurity (trivalent element) is boron (B). An exemplary N-type impurity (pentavalent element) is phosphorus (P) or arsenic (As). Although the exemplary semiconductor material is silicon, other semiconductor materials may also be used.

[0016] The impurity concentration of the semiconductor substrate 11 is 1×10 17 cm -3 More than 1×10 20 cm -3The thickness of the semiconductor substrate 11 may be 50 μm or more and 500 μm or less. The material of the semiconductor substrate 11 may be an insulator such as Al2O3, depending on the type of device. The impurity concentration of the epitaxial semiconductor layer 12 is lower than the impurity concentration of the semiconductor substrate 11, and is 1×10 14 cm -3 More than 1×10 17 cm -3 The thickness of the epitaxial semiconductor layer 12 may be 1 μm or more and 20 μm or less. The impurity concentration of the buried semiconductor layer 13 may be 1×10 16 cm -3 More than 1×10 21 cm -3 The thickness of the buried semiconductor layer 13 may be 0.1 μm or more and 5 μm or less. The impurity concentration of the epitaxial semiconductor layer 14 is lower than the impurity concentration of the buried semiconductor layer 13, and may be 1×10 14 cm -3 More than 1×10 17 cm -3 The thickness of the epitaxial semiconductor layer 14 may be 0.5 μm or more and 20 μm or less.

[0017] The insulating region 15 is formed on the surface 14a of the epitaxial semiconductor layer 14. The portion where the insulating region 15 is formed may constitute shallow trench isolation (STI). The material of the insulating region 15 is, for example, an insulator such as silicon dioxide (SiO2), but may also be an insulator such as silicon nitride (Si3N4). The insulating region 15 may be a field oxide film. The insulating region 15 constitutes a part of the first main surface 3 of the semiconductor device 1.

[0018] The isolation structure 20 is a deep trench isolation structure (DTI). The isolation structure 20 has a trench 21, an insulating film 22, and a conductive material 23 (conductive region). In this embodiment, the number of isolation structures 20 is singular, but it may be plural. As logic becomes finer and the drive voltage of memory decreases, leakage current and back electromotive force from the power section cause problems such as malfunction of logic and memory, noise in high-precision analog sections, and destruction due to latch-up. Therefore, a through-type DTI and a P + A method is adopted in which the substrate is used to absorb leakage current from the power section and suppress potential fluctuations within the silicon substrate.

[0019] FIG. 3 is an enlarged view of the cross-sectional configuration of the isolation structure of FIG. 2. As shown in FIG. 3, the trench 21 extends from the surface 14a of the epitaxial semiconductor layer 14 to a position where it penetrates the buried semiconductor layer 13. The trench 21 extends from the surface 14a to the semiconductor substrate 11. The depth direction of the trench 21 is the positive direction of the Z axis. The depth direction of the trench 21 is also the axial direction of the trench 21. Hereinafter, the depth direction of the trench 21 will also be simply referred to as the "depth direction." A tip 21a of the trench 21 in the depth direction is located in the semiconductor substrate 11. The trench 21 has a side surface 21b extending in the depth direction from the surface 14a to the tip 21a. The side surface 21b is the inner surface of the trench 21 facing inward.

[0020] The angle θ formed between the portion 21b1 of the side surface 21b of the trench 21 and the surface 13a of the buried semiconductor layer 13 satisfies θ>90°. The angle θ is an obtuse angle. The angle θ may also satisfy θ<120°. This prevents the internal space of the trench 21 from becoming too large, making it easier to fill the internal space of the trench 21 with the conductive material 23.

[0021] The trench 21 has an inverted tapered shape in which the width increases along the depth direction. The width of the trench 21 is narrowest at the surface 14a of the epitaxial semiconductor layer 14 and widest at the tip 21a. The width of the trench 21 at the surface 14a is the opening dimension W of the trench 21 that opens to the surface 14a. The opening dimension W may be 0.5 μm or more and 5 μm or less. The opening dimension W is the so-called top dimension of the trench 21. The width of the trench 21 at the tip 21a is the so-called bottom dimension of the trench 21.

[0022] The insulating film 22 covers the side surface 21b of the trench 21. The insulating film 22 is provided inside the trench 21. The material of the insulating film 22 is, for example, an insulator such as silicon dioxide (SiO2), but may also be an insulator such as silicon nitride (Si3N4). The ratio T / W of the thickness T of the insulating film 22 to the opening dimension W of the trench 21 may satisfy T / W>0.20. In this case, the breakdown voltage can be further improved. The thickness T of the insulating film 22 may be 0.1 μm or more and 1.0 μm or less.

[0023] The conductive material 23 is provided in the trench 21 so as to be surrounded by the insulating film 22. The conductive material 23 fills the inside of the insulating film 22. The conductive material 23 penetrates the insulating film 22 provided on the bottom surface of the trench 21 in the depth direction. The conductive material 23 contacts the semiconductor substrate 11 at the tip 21a of the trench 21. The material of the conductive material 23 is, for example, polysilicon doped with an impurity. A P-type additive such as boron (B) can be used as the impurity to be doped into the polysilicon. The conductive material 23 may be a metal such as copper (Cu) or aluminum (Al), a silicide, or an alloy. A bias potential application terminal E is electrically connected to the conductive material 23. The bias potential application terminal E may be connected to a ground potential.

[0024] The conductive material 23 has a first conductive region 25 and a second conductive region 26. The first conductive region 25 is provided inside the insulating film 22. The first conductive region 25 is in contact with the insulating film 22. The first conductive region 25 is provided between the insulating film 22 and the second conductive region 26. The first conductive region 25 is spaced apart from the surface 14a. The first conductive region 25 is spaced apart from the tip 21a of the trench 21.

[0025] The second conductive region 26 is provided inside the first conductive region 25. The second conductive region 26 has a forward tapered shape in which the width narrows along the depth direction. The second conductive region 26 may also have a straight shape in which the width is constant. The second conductive region 26 extends from the surface 14a to the tip 21a of the trench 21 and is in contact with the semiconductor substrate 11. A boundary 27 is formed between the first conductive region 25 and the second conductive region 26.

[0026] The first conductive region 25 and the second conductive region 26 are, for example, polysilicon doped with impurities. The first conductive region 25 and the second conductive region 26 may have different impurity concentrations. In this case, the impurity concentration of the first conductive region 25 may be lower than the impurity concentration of the second conductive region 26.

[0027] The first conductive region 25 and the second conductive region 26 may have the same composition. Even in this case, the first conductive region 25 and the second conductive region 26 are formed at different times, so the boundary 27 can be visually confirmed by cross-sectional observation. The cross-sectional observation is performed using, for example, a scanning electron microscope.

[0028] 4 is an enlarged view showing a cross-sectional configuration of an isolation structure according to a modified example. The isolation structure 20A according to the modified example has a sinker region 24. The sinker region 24 is provided along the side surface 21b of the trench 21. The sinker region 24 has N-type conductivity. The sinker region 24 is provided outside the insulating film 22 so as to be adjacent to the insulating film 22. The impurity concentration of the sinker region 24 is higher than the impurity concentration of the epitaxial semiconductor layer 14. The impurity concentration of the sinker region 24 is 1×10 17 cm -3 More than 1×10 20 cm -3 It may be the following:

[0029] The sinker region 24 extends from the surface 14a of the epitaxial semiconductor layer 14 to a position where it penetrates the buried semiconductor layer 13, and applies a potential to the buried semiconductor layer 13. The sinker region 24 extends to the semiconductor substrate 11. A tip 24a of the sinker region 24 in the depth direction may be located in the epitaxial semiconductor layer 12, away from the semiconductor substrate 11.

[0030] In the isolation structure 20A, the angle θ formed between a portion 21b1 of the side surface 21b of the trench 21 located within the epitaxial semiconductor layer 14 and the surface 13a of the buried semiconductor layer 13 is an obtuse angle, and the angle θ satisfies θ>90°. The angle θ may also satisfy θ<100°. Setting the angle θ to less than 100° facilitates the formation of the sinker region 24 by ion implantation.

[0031] 5 is a diagram illustrating a cross-sectional configuration of a device according to an example. The device 50 may include at least one of a semiconductor switching device, a semiconductor rectifying device, and a passive device. The semiconductor switching device may include at least one of a JFET (Junction Field Effect Transistor), a FET (FET: Field-Effect Transistor), and a BJT (Bipolar Junction Transistor). The FET may be a MISFET (Metal Insulator Semiconductor Field Effect Transistor). The BJT may be an IGBT (Insulated Gate Bipolar Junction Transistor).

[0032] A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) can be used as the MISFET. The device 50 can also be a power transistor. A DMOS-FET (Double-Diffused MOSFET) can be used as the power MOSFET, and types such as a vertical (VDMOS) and a lateral (LDMOS) can be used. MISFETs with drain-source voltages of high voltage (HV: for example, 100 V or more and 1000 V or less), medium voltage (MV: for example, 30 V or more and 100 V or less), and low voltage (LV: for example, 1 V or more and 30 V or less) are known. Alternatively, an optical device such as a light-emitting element or a light-receiving element can be used as the device 50.

[0033] The device 50 in the illustrated example is a DMOS-FET. The device 50 is provided in the epitaxial semiconductor layer 14. The device 50 includes a semiconductor well region 51, a source region 54, a first drain region 521, a first insulating film 551, a first gate electrode 561, a second drain region 522, a second insulating film 552, a second gate electrode 562, a buried semiconductor layer 57, and a body region 53. The semiconductor well region 51, the source region 54, the first drain region 521, and the second drain region 522 are made of silicon and have N-type conductivity. The buried semiconductor layer 57 and the body region 53 are made of silicon and have P-type conductivity.

[0034] The semiconductor well region 51 is provided in the epitaxial semiconductor layer 14. Carriers constituting the channel of the FET can travel in the semiconductor well region 51. The semiconductor well region 51 includes a carrier drift region. The source region 54 is formed on the surface of the semiconductor well region 51. The first drain region 521 is formed on the surface of the semiconductor well region 51. The first drain region 521 is spaced apart from the source region 54 along the X-axis direction and is positioned at a distance from the source region 54.

[0035] The first insulating film 551 is formed on the semiconductor well region 51 between the source region 54 and the first drain region 521. The first insulating film 551 is a gate insulating film. The material of the first insulating film 551 is, for example, silicon dioxide (SiO2).

[0036] The first gate electrode 561 is formed on the first insulating film 551. The first gate electrode 561 is disposed between the source region 54 and the first drain region 521 with the first insulating film 551 interposed therebetween. The material of the first gate electrode 561 is, for example, polysilicon doped with impurities. The material of the first gate electrode 561 may be a metal such as copper (Cu) or aluminum (Al), an alloy containing one or more types of metal, or a compound (silicide) of metal and silicon.

[0037] The second drain region 522 is formed on the surface of the semiconductor well region 51. The second drain region 522 is spaced apart from the source region 54 along the X-axis direction and is located on the opposite side of the first drain region 521 with a gap therebetween.

[0038] The second insulating film 552 is formed on the semiconductor well region 51 between the source region 54 and the second drain region 522. The second insulating film 552 is a gate insulating film. In this embodiment, the second insulating film 552 is made of silicon dioxide (SiO2).

[0039] The second gate electrode 562 is formed on the second insulating film 552. The second gate electrode 562 is disposed between the source region 54 and the second drain region 522 with the second insulating film 552 interposed therebetween. The material of the second gate electrode 562 is, for example, polysilicon doped with impurities. The material of the second gate electrode 562 may be a metal such as copper (Cu) or aluminum (Al), an alloy containing one or more types of metal, or a compound (silicide) of metal and silicon. The first gate electrode 561 and the second gate electrode 562 may be physically and electrically connected at their ends in the Y-axis direction.

[0040] The buried semiconductor layer 57 is disposed in a region directly below the semiconductor well region 51, is in contact with the semiconductor well region 51, and is connected to the body region 53. The buried semiconductor layer 57 extends along the XY plane and is electrically connected to the body region 53. This makes it easier for the electric field strength in the semiconductor well region 51 to be distributed evenly.

[0041] More specifically, when a ground potential is applied to the source region 54 and a high voltage of, for example, +100 V is applied to the first drain region 521 and the second drain region 522, this high voltage is applied to the semiconductor well region 51 connected to the drain region. The buried semiconductor layer 57 is connected to the body region 53, which is connected to the ground potential. Therefore, an equipotential surface parallel to the surface of the buried semiconductor layer 57 is easily formed in the semiconductor well region 51. This structure suppresses the concentration of electric field strength at a specific location. Therefore, this structure further improves the breakdown voltage.

[0042] Electrons in the source region 54 are attracted to the positive potential of the drain region, but can move smoothly because the electric field distribution in the semiconductor well region 51 is not locally concentrated. The device 50 may also have a structure that does not include the buried semiconductor layer 57. In this case, the body region 53 does not need to penetrate the semiconductor well region 51.

[0043] The body region 53 has a source region 54 therein. The body region 53 extends from the surface position of the semiconductor well region 51 toward the depth thereof, reaching the inside of the buried semiconductor layer 57. The N-type semiconductor well region 51 and the P-type body region 53 are joined. The width of the body region 53 in the X-axis direction is wider than the width of the source region 54 in the X-axis direction. The body region 53 is interposed between the source region 54 and the semiconductor well region 51. The interposed region of the body region 53 is located directly below the gate electrode, and an N-type channel is formed in this region.

[0044] The insulating region 15 includes a first outer insulating region 151, a first inner insulating region 152, a second inner insulating region 153, and a second outer insulating region 154, which are arranged between the trenches 21 along the X-axis direction. The first outer insulating region 151 and the first inner insulating region 152 are spaced apart, and a first drain region 521 is formed therebetween. The second outer insulating region 154 and the second inner insulating region 153 are spaced apart, and a second drain region 522 is formed therebetween. The first inner insulating region 152 and the second inner insulating region 153 are spaced apart, and a body region 53 and a source region 54 are formed therebetween.

[0045] The impurity concentration of the semiconductor well region 51 is higher than the impurity concentration of the epitaxial semiconductor layer 14, and is 1×10 16 / cm 3 More than 1×10 18 / cm 3 The impurity concentration of the body region 53 is higher than the impurity concentration of the epitaxial semiconductor layer 14 and may be 1×10 16 / cm 3 More than 1×10 18 / cm 3 The impurity concentration of the buried semiconductor layer 57 is higher than the impurity concentration of the epitaxial semiconductor layer 14, and may be 1×10 16 / cm 3 More than 1×10 21 / cm 3 The impurity concentration in the drain region, source region, and contact region constituting the device 50 is higher than the impurity concentration in the well region, and may be 1×10 15 / cm 3 5x10 or more 19 / cm 3 It may be the following:

[0046] If device 50 is a P-channel FET, the N-type and P-type regions are swapped. The impurities added to the conductive material in the trench can be P-type, and it is also possible to add P-type impurities to a semiconductor region deeper than the bottom of the trench. The P-type impurity concentration added to the conductive material in the trench is 1×10 21 / cm 3 More than 1×10 22 / cm 3 It can also be the following:

[0047] (Method of manufacturing a semiconductor device) The following describes a method for manufacturing the semiconductor device 1. Figures 6(A) to 6(F) and 7(A) to 7(F) are cross-sectional views for explaining the method for manufacturing the semiconductor device, and mainly show the steps for forming an isolation structure.

[0048] The method for manufacturing the semiconductor device 1 includes a step of preparing a silicon substrate formed by stacking a semiconductor substrate 11 (see FIG. 3), an epitaxial semiconductor layer 12 (see FIG. 3), a buried semiconductor layer 13, and an epitaxial semiconductor layer 14 (see FIG. 3) in this order. The step of preparing the silicon substrate includes a step of forming the buried semiconductor layer 13 on the semiconductor substrate 11 by ion implantation, and a step of forming the epitaxial semiconductor layer 14 on the buried semiconductor layer 13.

[0049] The method for manufacturing the semiconductor device 1 includes the steps of forming a device 50 (see FIG. 2) provided in the epitaxial semiconductor layer 14 and forming an isolation structure 20 surrounding the device 50. Both of these steps are performed after the step of preparing a silicon substrate. Either the device 50 or the isolation structure 20 can be formed first. The device 50 is formed by a known method.

[0050] The process of forming the isolation structure 20 will be described in detail. First, as shown in Figure 6(A), a first insulating film 301, a second insulating film 302, and a third insulating film 303 are stacked on a silicon substrate. The material of the first insulating film 301 is silicon dioxide (SiO2). The material of the second insulating film 302 is silicon nitride (Si3N4). The material of the third insulating film 303 is silicon dioxide (SiO2).

[0051] When silicon dioxide is formed on the surface of an exposed silicon substrate, as in the first insulating film 301, thermal oxidation of silicon can be used. When silicon nitride is formed, as in the second insulating film 302, low-pressure CVD (chemical vapor deposition) for silicon nitride formation can be used. An example of a source gas for the CVD method for silicon nitride formation is a mixed gas of dichlorosilane gas (SiH2Cl2), ammonia gas (NH3), and nitrogen gas (N2). When a relatively thick silicon dioxide is formed, as in the third insulating film 303, the CVD method can be used. An example of a CVD method for silicon dioxide formation is a formation method using TEOS (Si(OC2H5)4).

[0052] Next, a resist material 304 is formed on the third insulating film 303. The resist material 304 is patterned to form an opening 305.

[0053] As shown in FIG. 6(B), the third insulating film 303, the second insulating film 302, and the first insulating film 301 are sequentially etched using the patterned resist material 304 (see FIG. 6(A)) as a mask, and are patterned into the same shape as the mask opening. Anisotropic dry etching for insulating films can be used as the etching method. A stack of the patterned third insulating film 303, the second insulating film 302, and the first insulating film 301 is used as a hard mask. When anisotropic dry etching for insulating films is performed, a fluorocarbon-based etching gas is exemplified. After etching, the resist material 304 is removed. If the resist material 304 is made of resin, it can be removed using an organic solvent.

[0054] As shown in FIG. 6(C), the surface of the silicon substrate is etched through the opening in the hard mask including the third insulating film 303 to form trenches 21. The trenches 21 have an inverted tapered shape and are formed to penetrate the buried semiconductor layer 13. The trenches 21 are formed so that the angle θ (see FIG. 3) satisfies θ>90°. As the etching method, wet etching for silicon can be used.

[0055] Examples of etching solutions used in wet etching of silicon include acidic etching solutions such as hydrofluoric acid and nitric acid, and alkaline etching solutions such as potassium hydroxide (KOH) and ammonia. When using these wet etching solutions, isotropic etching is performed on the underside of the hard mask. It is also possible to use wet etching at the initial stage of etching, followed by dry etching. Known dry etching methods include anisotropic etching such as reactive ion etching (RIE) and isotropic dry etching using activated species. Therefore, it is possible to use only isotropic dry etching to form the trench 21. By changing the control parameters during etching (temperature, time, type of etching solution or etching gas, etc.), etching of a desired shape can be performed. An example of an anisotropic dry etching method for silicon is a method using reactive ion etching (RIE). Examples of etching gases for dry etching include fluorine-containing gases such as CF4 and SF6.

[0056] 6(C), the silicon substrate may be etched through an opening in a mask (a hard mask including the third insulating film 303) provided on the silicon substrate to form a space (trench 21) directly below the opening and directly below a region outside both ends of the opening in the width direction. In this case, the width of the upper part of the trench 21 (top dimension) expands to a position where the lower surface of the first insulating film 301 is exposed.

[0057] Although not shown, when forming the sinker region 24 (see FIG. 4), N-type impurities are implanted into the inner surface of the trench 21 using an ion implantation method. This forms the sinker region 24. During the ion implantation, the direction of ion movement is tilted with respect to the depth direction of the trench 21. After the Nth ion implantation is completed, the silicon substrate is rotated, for example, around the ion movement direction as the central axis, and the N+1th ion implantation is performed (N is a natural number). For example, the silicon substrate is rotated 90 degrees from the initial position for three rotations, for a total of four ion implantations. Note that the rotation angles and the number of rotations are not limited to these.

[0058] The tilt angle α of the ion implantation when forming the sinker region 24, i.e., the angle by which the ion traveling direction is inclined with respect to the depth direction of the trench 21, is set in consideration of the inverse tapered shape of the trench 21. Specifically, the tilt angle α is set to satisfy α>θ-90°. In other words, the trench 21 is formed so that the angle θ satisfies θ<90°+α.

[0059] 6(D), an insulating film 22 is formed on the exposed side and bottom surfaces of the trench 21. Thermal oxidation of silicon can be used as a formation method, and silicon dioxide can be formed as the insulating film 22. In this process, the insulating film 22 is formed not only on the exposed surface of the trench 21 but also on the exposed surface of the hard mask including the third insulating film 303.

[0060] As shown in FIG. 6(F), a portion of the insulating film 22 located on the bottom surface of the trench 21 is removed to expose the semiconductor substrate 11 (see FIG. 3) located on the bottom surface of the trench 21. Anisotropic dry etching for insulating films can be used as a removal method. Subsequently, a first semiconductor region 306 is formed inside the insulating film 22. The first semiconductor region 306 is formed using, for example, polysilicon doped with impurities such as boron. A CVD method can be used to form the first semiconductor region 306. In this process, the first semiconductor region 306 is formed not only inside the trench 21 but also on the trench 21 and the hard mask. A cavity 307 that is not filled with polysilicon is formed inside the trench 21. The cavity 307 is formed in the center of the trench 21, away from the inner surface of the trench 21.

[0061] 7(A), the first semiconductor region 306 formed on the trench 21 and the hard mask is removed by chemical mechanical polishing (CMP) to expose the upper surface of the insulating film 22. Subsequently, the portion of the first semiconductor region 306 provided in the center of the trench 21 is removed together with the cavity 307 by electron beam lithography to form a recess 308 inside the trench 21.

[0062] As shown in FIG. 7(B), a second semiconductor region 309 is formed inside the recess 308, i.e., inside the first semiconductor region 306. The second semiconductor region 309 has an impurity concentration lower than that of the first semiconductor region 306. The second semiconductor region 309 is formed using, for example, pure polysilicon to which no impurities have been added. The CVD method can be used as a method for forming the second semiconductor region 309. In this process, the second semiconductor region 309 is formed not only inside the trench 21, but also on the trench 21 and the hard mask. The inside of the trench 21 is filled with the first semiconductor region 306 and the second semiconductor region 309 without any gaps.

[0063] 7(C), the second semiconductor region 309 formed on the trench 21 and the hard mask is removed by chemical mechanical polishing to expose the upper surface of the insulating film 22. As shown in FIG. 7(D), the insulating film 22 formed around the trench 21 is removed together with the third insulating film 303 by chemical mechanical polishing to expose the surface of the second insulating film 302.

[0064] As shown in FIG. 7(E), the second insulating film 302 is removed. Wet etching can be used to remove the second insulating film 302 made of silicon nitride. An example of an etchant is phosphoric acid (H3PO4). Next, the first insulating film 301 is removed. Wet etching can be used to remove the first insulating film 301 made of silicon dioxide. An example of an etchant is hydrofluoric acid (HF).

[0065] As shown in FIG. 7(F), an insulating region 15 is formed in the surface portion of the silicon substrate by a known method. Subsequently, a heat treatment is performed to diffuse impurities from the first semiconductor region 306 to the second semiconductor region 309. As a result, the impurity concentrations of the first semiconductor region 306 and the second semiconductor region 309 become uniform, and a first conductive region 25 and a second conductive region 26, which are electrically conductive to each other, are formed. That is, the heat treatment forms the first conductive region 25 from the first semiconductor region 306 and the second conductive region 26 from the second semiconductor region 309. The heat treatment step may be performed any time after both the first semiconductor region 306 and the second semiconductor region 309 have been formed, and may be performed multiple times. In this manner, the isolation structure 20 is formed.

[0066] 8 is an enlarged view showing a cross-sectional configuration of an isolation structure according to a comparative example. As shown in the figure, in an isolation structure 120 according to the comparative example, trench 21 has a forward tapered shape throughout the entire depth direction. An angle θ formed between portion 21b1 of side surface 21b of trench 21 and surface 13a of buried semiconductor layer 13 is an acute angle, not an obtuse angle.

[0067] When the electric field intensity distribution of the isolation structure according to the comparative example was confirmed, it was found that the boundary between the buried semiconductor layer 13, the epitaxial semiconductor layer 14, and the insulating film 22 became an electric field concentration point where the electric field was concentrated due to a large bend in the dense equipotential lines. In the isolation structure 120, the angle θ is acute, so electric field concentration is likely to occur. As a result, improvement in the breakdown voltage of the semiconductor device is hindered.

[0068] In contrast, in the isolation structures 20 and 20A, the angle θ is an obtuse angle, satisfying θ>90°. The angle at which the dense equipotential lines bend is reduced, thereby reducing the electric field concentration at the electric field concentration point. As a result, the breakdown voltage of the semiconductor device 1 can be improved. In the isolation structures 20 and 20A, the trench 21 has an inverse tapered shape, so the angle θ can be reliably set to an obtuse angle.

[0069] The relationship between the angle θ and the breakdown voltage was investigated for both cases where a sinker region was not provided and where one was provided. It was confirmed that, regardless of whether a sinker region was provided or not, the breakdown voltage was improved when the angle θ was an obtuse angle compared to an acute angle. When a sinker region was not provided, the breakdown voltage improved by up to 2.9 V. When a sinker region was provided, the breakdown voltage improved by up to 3.5 V. The tilt angle for ion implantation when providing the sinker region was set to 7°. It was also found that the larger the angle θ, that is, the more inversely tapered the trench, the less ion implantation into the sinker region, and the less effective the sinker region was in improving the breakdown voltage.

[0070] The isolation structure 20A includes the sinker region 24, which can further improve the breakdown voltage of the semiconductor device 1. The sinker region 24 penetrates the buried semiconductor layer 13 and extends to the semiconductor substrate 11. The sinker region 24 is provided at the electric field concentration point described above, which can more reliably improve the breakdown voltage.

[0071] In the method for manufacturing the semiconductor device 1, the trench 21 is formed so that the angle θ satisfies θ>90°, thereby enabling the manufacture of a semiconductor device 1 capable of improving the breakdown voltage. The trench 21 is formed so that the angle θ satisfies θ<90°+α, where α is the tilt angle of the ion implantation used to form the sinker region 24. For example, when the tilt angle α is 7°, the angle θ is set to less than 97°. This allows the sinker region 24 to be formed by ion implantation. As a result, a semiconductor device 1 capable of further improving the breakdown voltage can be manufactured.

[0072] In the step of forming the conductive material 23, the conductive material 23 is not formed all at once, but is formed separately into a first semiconductor region 306 that becomes the first conductive region 25 and a second semiconductor region 309 that becomes the second conductive region 26. This allows the conductive material 23 to be filled into the trench 21 without leaving any gaps. Because the impurity concentration of the second semiconductor region 309 is lower than the impurity concentration of the first semiconductor region 306, the hardness of the second semiconductor region 309 is lower than the hardness of the first semiconductor region 306. This makes the second semiconductor region 309 easier to process than the first semiconductor region 306. Using the second semiconductor region 309 makes it easier to manufacture the semiconductor device 1 than filling the entire trench 21 with the first semiconductor region 306.

[0073] In the above-described embodiments, one or more elements of one embodiment may be combined with one or more elements of another embodiment.

[0074] In the isolation structures 20 and 20A, the trench 21 has a reverse tapered shape throughout the entire depth direction, but may have a partial reverse tapered shape at the electric field concentration point described above so that at least the angle θ is an obtuse angle. The trench 21 may have a forward tapered shape or a straight shape other than the electric field concentration point.

[0075] Below, examples of features extracted from the description of this specification and the drawings are shown.

[0076] [A1] (Figures 1 to 3) A semiconductor substrate (11), a buried semiconductor layer (13) provided on the semiconductor substrate; a first epitaxial semiconductor layer (14) provided on the buried semiconductor layer; a device (50) disposed within the first epitaxial semiconductor layer; an isolation structure (20) surrounding the device; Equipped with The isolation structure includes: a trench (21) extending from the surface (14a) of the first epitaxial semiconductor layer to a position penetrating the buried semiconductor layer; an insulating film (22) covering the side surface (21b) of the trench; a conductive region (23) provided in the trench so as to be surrounded by the insulating film; and an angle θ formed between a portion (21b1) of the side surface located in the first epitaxial semiconductor layer and a surface (13a) of the buried semiconductor layer facing the first epitaxial semiconductor layer satisfies θ>90°; Semiconductor device (1).

[0077] [A2] The trench has an inverse tapered shape in which the width increases along the depth direction of the trench. The semiconductor device according to [A1].

[0078] [A3] The angle θ satisfies θ<120°. The semiconductor device according to [A1] or [A2].

[0079] [A4] a sinker region (24) provided along the side surface and having an impurity concentration higher than the impurity concentration of the first epitaxial semiconductor layer; The semiconductor device according to [A1] or [A2].

[0080] [A5] The angle θ satisfies θ<100°. The semiconductor device according to [A4].

[0081] [A6] the sinker region extends from the surface of the first epitaxial semiconductor layer to a position penetrating the buried semiconductor layer; The semiconductor device according to [A4] or [A5].

[0082] [A7] Further comprising a second epitaxial semiconductor layer (12) provided between the semiconductor substrate and the buried semiconductor layer, the sinker region extends to the semiconductor substrate; The semiconductor device according to [A6].

[0083] [A8] a ratio T / W of a thickness T of the insulating film to an opening dimension W of the trench satisfies T / W>0.20; The semiconductor device according to any one of [A1] to [A7].

[0084] [A9] The conductive region is a first conductive region (25) provided inside the insulating film; a second conductive region (26) provided inside the first conductive region, A boundary (27) is formed between the first conductive region and the second conductive region. The semiconductor device according to any one of [A1] to [A8].

[0085] [A10] the first conductive region and the second conductive region have different impurity concentrations; The semiconductor device according to [A9].

[0086] [A11] the impurity concentration of the first conductive region is lower than the impurity concentration of the second conductive region; The semiconductor device according to [A9].

[0087] [A12] forming a buried semiconductor layer on the semiconductor substrate by ion implantation; forming a first epitaxial semiconductor layer on the buried semiconductor layer; forming a device disposed in the first epitaxial semiconductor layer; forming an isolation structure surrounding the device; Including, The step of forming the isolation structure includes: forming a trench extending from a surface of the first epitaxial semiconductor layer to a position penetrating the buried semiconductor layer; forming an insulating film on the side surface of the trench; forming a conductive region inside the insulating film; Including, the trench is formed so that an angle θ formed between a portion of the side surface facing the first epitaxial semiconductor layer and a surface of the buried semiconductor layer facing the first epitaxial semiconductor layer satisfies θ>90°. A method for manufacturing a semiconductor device.

[0088] [A13] the step of forming the isolation structure further includes a step of forming a sinker region surrounding the trench by ion implantation into the side surface after forming the trench and before forming the insulating film; The trench is formed so that the angle θ satisfies θ<90°+α, where α is a tilt angle of ion implantation when forming the sinker region. A method for manufacturing a semiconductor device according to [A12].

[0089] [A14] The step of forming the conductive region includes: forming a first semiconductor region inside the insulating film; forming a second semiconductor region inside the first semiconductor region, the second semiconductor region having an impurity concentration lower than the impurity concentration of the first semiconductor region; forming a first conductive region from the first semiconductor region and a second conductive region from the second semiconductor region by heat treatment; A method for manufacturing a semiconductor device according to [A12] or [A13]. [Explanation of symbols]

[0090] 1...Semiconductor device 3...First main surface 4...Second main surface 5A…1st side 5B…Second side 5C…Third side 5D…Fourth side 10...Device area 11...Semiconductor substrate 12...Epitaxial semiconductor layer (second epitaxial semiconductor layer) 13...Buried semiconductor layer 13a…Surface 14...Epitaxial semiconductor layer (first epitaxial semiconductor layer) 14a…Surface 15...Isolation area 151...First outer insulation area 152...First inner insulating region 153...Second inner insulating region 154…Second outer insulation area 20, 20A...Isolation structure 21...Trench 21a...tip 21b...side 21b1…part 22...insulating film 23...Conductive material (conductive region) 24...Sinker area 24a...tip 25...first conductive region 26…Second conductive region 27…boundary 50…devices 51...Semiconductor well region 521...First drain region 522...Second drain region 53...Body area 54...Source region 551...first insulating film 552...Second insulating film 561...First gate electrode 562...Second gate electrode 57...Buried semiconductor layer 120...Isolation structure 301...first insulating film 302...Second insulating film 303...Third insulating film 304...Resist material 305…Aperture 306...first semiconductor region 307...Cavity 308...recess 309...Second semiconductor region E: Bias potential application terminal T...Thickness W...Opening dimension θ…Angle

Claims

1. a semiconductor substrate; a buried semiconductor layer provided on the semiconductor substrate; a first epitaxial semiconductor layer provided on the buried semiconductor layer; a device disposed within the first epitaxial semiconductor layer; an isolation structure surrounding the device; Equipped with The isolation structure includes: a trench extending from a surface of the first epitaxial semiconductor layer to a position penetrating the buried semiconductor layer; an insulating film covering a side surface of the trench; a conductive region provided in the trench so as to be surrounded by the insulating film; and an angle θ formed between a portion of the side surface located within the first epitaxial semiconductor layer and a surface of the buried semiconductor layer facing the first epitaxial semiconductor layer satisfies θ>90°; Semiconductor device.

2. The trench has an inverse tapered shape in which the width increases along the depth direction of the trench. The semiconductor device according to claim 1 .

3. The angle θ satisfies θ<120°.

3. The semiconductor device according to claim 1.

4. a sinker region provided along the side surface and having an impurity concentration higher than an impurity concentration of the first epitaxial semiconductor layer; 3. The semiconductor device according to claim 1.

5. The angle θ satisfies θ<100°. The semiconductor device according to claim 4 .

6. the sinker region extends from the surface of the first epitaxial semiconductor layer to a position penetrating the buried semiconductor layer; The semiconductor device according to claim 4 .

7. a second epitaxial semiconductor layer provided between the semiconductor substrate and the buried semiconductor layer; the sinker region extends to the semiconductor substrate; The semiconductor device according to claim 6.

8. a ratio T / W of a thickness T of the insulating film to an opening dimension W of the trench satisfies T / W>0.20; 3. The semiconductor device according to claim 1.

9. The conductive region is a first conductive region provided inside the insulating film; a second conductive region provided inside the first conductive region, a boundary is formed between the first conductive region and the second conductive region; 3. The semiconductor device according to claim 1.

10. the first conductive region and the second conductive region have different impurity concentrations; The semiconductor device according to claim 9 .

11. an impurity concentration of the first conductive region is lower than an impurity concentration of the second conductive region; The semiconductor device according to claim 9 .

12. forming a buried semiconductor layer on the semiconductor substrate by ion implantation; forming a first epitaxial semiconductor layer on the buried semiconductor layer; forming a device disposed in the first epitaxial semiconductor layer; forming an isolation structure surrounding the device; Including, The step of forming the isolation structure includes: forming a trench extending from a surface of the first epitaxial semiconductor layer to a position penetrating the buried semiconductor layer; forming an insulating film on the side surface of the trench; forming a conductive region inside the insulating film; Including, the trench is formed so that an angle θ formed between a portion of the side surface facing the first epitaxial semiconductor layer and a surface of the buried semiconductor layer facing the first epitaxial semiconductor layer satisfies θ>90°. A method for manufacturing a semiconductor device.

13. the step of forming the isolation structure further includes a step of forming a sinker region surrounding the trench by ion implantation into the side surface after forming the trench and before forming the insulating film; The trench is formed so that the angle θ satisfies θ<90°+α, where α is a tilt angle of ion implantation when forming the sinker region. The method for manufacturing a semiconductor device according to claim 12.

14. The step of forming the conductive region includes: forming a first semiconductor region inside the insulating film; forming a second semiconductor region inside the first semiconductor region, the second semiconductor region having an impurity concentration lower than the impurity concentration of the first semiconductor region; forming a first conductive region from the first semiconductor region and a second conductive region from the second semiconductor region by heat treatment; The method for manufacturing a semiconductor device according to claim 12 or 13.

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