Highest data state program verify skip for improved program performance

Abstract

To provide a nonvolatile memory device with improved performance and a method of operating the same.SOLUTION: The apparatus includes a memory cell coupled to a word line and storing a threshold voltage corresponding to a data state. The data states include a highest data state in which the threshold voltages of the memory cells associated therewith are higher than those of the other data states. The control means applies, during each of a plurality of program loops of a program operation, each of a series of programming pulses at a program voltage followed by verify pulses at a plurality of program verify voltages each associated with one of the data states to a selected one of the word lines to program and verify the memory cells connected to the word line, and skips verifying memory cells targeted for a highest data state in at least one of the plurality of program loops.SELECTED DRAWING: Figure 28

Description

[Technical Field]

[0001] The present technology relates to the operation of memory devices. [Background technology]

[0002] Semiconductor memory devices or apparatuses are widely used in various electronic devices, such as laptops, digital audio players, digital cameras, mobile phones, video game consoles, scientific instruments, industrial robots, medical electronics, solid-state drives, automotive electronics, Internet of Things (IOT) devices, and universal serial bus (USB) devices. Semiconductor memory includes both nonvolatile and volatile memory. Nonvolatile memory retains stored information without requiring an external power source. Examples of nonvolatile memory include flash memory (e.g., NAND and NOR flash memory) and electrically erasable programmable read-only memory (EEPROM).

[0003] A memory device may be coupled to one or more hosts, and one or more interfaces are used to access the memory device. In addition, memory devices are often managed by a controller, which, among other roles, is configured to interface between the hosts and the memory device.

[0004] To improve performance, some memory devices utilize various techniques to limit verify iterations to specific data states during programming. However, while such techniques can reduce program time, they can have some adverse effects. Therefore, there is a need for improved non-volatile memory devices and methods of operation. Summary of the Invention

[0005] This section provides a general overview of the disclosure, but is not an exhaustive disclosure of its entire scope or all of its features and advantages.

[0006] It is an object of the present disclosure to provide a memory device and a method of operating a memory device that addresses and overcomes the shortcomings described herein.

[0007] Accordingly, one aspect of the present disclosure is to provide a memory device including memory cells each connected to one of a plurality of word lines and configured to hold a threshold voltage corresponding to one of a plurality of data states. The plurality of data states includes a highest data state in which the threshold voltage of the memory cell associated with the data state is higher than that of the other data states of the plurality of data states. The memory device also includes control means configured to apply, to a selected word line of the plurality of word lines, each of a series of programming pulses of a program voltage followed by a verify pulse of a plurality of program verify voltages, each of the program verify pulses being associated with one of the plurality of data states. Thus, the memory cells connected to the selected word line of the plurality of word lines are programmed and verified during each of a plurality of program loops of a program operation. The control means is also configured to skip verifying the memory cell targeted for the highest data state in at least one of the plurality of program loops.

[0008] According to another aspect of the present disclosure, a controller is also provided in communication with a memory device including memory cells each connected to one of a plurality of word lines. The memory cells are configured to hold a threshold voltage corresponding to one of a plurality of data states. The plurality of data states includes a highest data state in which the threshold voltage of the memory cell associated with the data state is higher than that of the other data states of the plurality of data states. The controller is configured to instruct the memory device to apply, to selected word lines of the plurality of word lines, each of a series of programming pulses of a program voltage followed by a verify pulse of a plurality of program verify voltages, each of the program verify pulses being associated with one of the plurality of data states. Thus, the memory cells connected to selected word lines of the plurality of word lines are programmed and verified during each of a plurality of program loops of a program operation. The controller is also configured to instruct the memory device to skip verifying memory cells subject to the highest data state in at least one of the plurality of program loops.

[0009] According to an additional aspect of the present disclosure, a method for operating a memory device is provided. The memory device includes memory cells each connected to one of a plurality of word lines. The memory cells are configured to hold a threshold voltage corresponding to one of a plurality of data states. The plurality of data states includes a highest data state in which the threshold voltage of the memory cell associated with the data state is higher than that of the other data states of the plurality of data states. The method includes, during each of a plurality of program loops of a program operation, applying to a selected word line of the plurality of word lines each a series of programming pulses of a program voltage followed by a verify pulse of a plurality of program verify voltages each associated with one of the plurality of data states to program and verify the memory cells connected to the word line. The method also includes, during at least one of the plurality of program loops, skipping verify of the memory cell targeted for the highest data state.

[0010] Further areas of applicability will become apparent from the description provided herein. The description and specific examples in this summary are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure. [Brief explanation of the drawings]

[0011] The drawings described herein are for purposes of illustrating selected embodiments only, not all possible implementations, and are not intended to limit the scope of the present disclosure. [Figure 1A] FIG. 1 illustrates a top view of an embodiment of a NAND string, in accordance with aspects of the present disclosure. [Figure 1B] FIG. 2 is an equivalent circuit diagram of a NAND string according to an embodiment of the present disclosure. [Figure 2] 1 illustrates a non-volatile storage device that may include one or more memory dies or chips, according to an embodiment of the present disclosure. [Figure 3] FIG. 2 is a block diagram illustrating one embodiment of a sense block, in accordance with aspects of the present disclosure. [Figure 4] 3 illustrates a block of NAND flash memory cells in the memory array of FIG. 2 according to an embodiment of the present disclosure. [Figure 5] 1 illustrates an exemplary set of threshold voltage distributions for an 8-state memory device in which each storage element stores 3 bits of data, according to an embodiment of the present disclosure. [Figure 6] 10 illustrates that Vt distributions may overlap, according to embodiments of the present disclosure. [Figure 7] 1 is a flowchart illustrating one embodiment of a programming process including one or more verification steps, according to aspects of the present disclosure. [Figure 8] 1 illustrates a program verify operation according to an aspect of the present disclosure. [Figure 9A] 10 illustrates a program verify operation that does not detect a bit count above a threshold, according to aspects of the present disclosure. [Figure 9B]10 illustrates a program verify operation to detect a bit count above a threshold, according to aspects of the present disclosure. [Figure 10A] 10 illustrates voltage levels in a program verify iteration according to aspects of the present disclosure. [Figure 10B] 10 illustrates voltage levels in a program verify iteration according to aspects of the present disclosure. [Figure 10C] 10 illustrates voltage levels in a program verify iteration according to aspects of the present disclosure. [Figure 11] 1 is a flowchart of one embodiment of a process for operating data latches while programming and verifying non-volatile storage in accordance with aspects of the present disclosure. [Figure 12] 1 is a flowchart of one embodiment of a process for operating data latches while programming and verifying non-volatile storage in accordance with aspects of the present disclosure. [Figure 13A] 13 is a table illustrating the status of data latches throughout various stages of the process of FIG. 12 in accordance with an embodiment of the present disclosure. [Figure 13B] 13 is a table illustrating the status of data latches throughout various stages of the process of FIG. 12 in accordance with an embodiment of the present disclosure. [Figure 13C] 13 is a table illustrating the status of data latches throughout various stages of the process of FIG. 12 in accordance with an embodiment of the present disclosure. [Figure 13D] 13 is a table illustrating the status of data latches throughout various stages of the process of FIG. 12 in accordance with an embodiment of the present disclosure. [Figure 14] 1 illustrates latch usage during various stages of one embodiment of programming, according to aspects of the present disclosure. [Figure 15] 1 is a table illustrating the number of program loops and verify iterations for each data state in a program operation for a ternary cell, along with the time period involved in each of the program loops, according to an embodiment of the present disclosure. [Figure 16] 10 is a plot of threshold voltage distributions when program verify of the highest data state is skipped entirely, according to aspects of the present disclosure. [Figure 17A]10 is a table illustrating information stored in a first data latch, a second data latch, a third data latch, and a fourth data latch for each data state of a ternary memory cell, according to an embodiment of the present disclosure. [Figure 17B] 10 is a table illustrating unused bit combinations of bits in a first data latch, a second data latch, a third data latch, and a fourth data latch, according to an embodiment of the present disclosure. [Figure 18] FIG. 10 illustrates an example tracking of memory cells subject to the highest data state through subsequent program loops of multiple program loops using two unused bit combinations for Option 1, in accordance with aspects of the present disclosure. [Figure 19] 10 is another table illustrating information stored in the first data latch, the second data latch, the third data latch, and the fourth data latch for each data state for Option 1, in accordance with aspects of the present disclosure. [Figure 20] 10 is a table illustrating impact on cache freeing according to aspects of the present disclosure. [Figure 21] 12 summarizes parameter variations that affect the operation of a memory device using Option 1, according to aspects of the present disclosure. [Figure 22] 10 illustrates an example sequence of program loops for option 2, according to an embodiment of the present disclosure. [Figure 23] 10 is a plot of threshold voltage distributions when the program verify of the highest data state is skipped after the next highest data state is completed, and a counter is used to track program loops for slow cells targeted for the highest data state, according to aspects of the present disclosure. [Figure 24] FIG. 10 illustrates exemplary tracking of memory cells with corresponding plots of threshold voltage distributions for Option 3, according to aspects of the present disclosure. [Figure 25] 10 shows simulation results for options 1, 2, and 3 compared to no skip of program verify for the highest data state, according to aspects of the present disclosure. [Figure 26] 10 is a comparison of no skip program verify for the highest data state, option 1, option 2, and option 3, according to an aspect of the present disclosure. [Figure 27A] 10 is a table illustrating information stored in a first data latch, a second data latch, a third data latch, and a different fourth and fifth data latch for each data state of a quaternary memory cell, according to an embodiment of the present disclosure. [Figure 27B] 10 is a table illustrating unused bit combinations of bits in a first data latch, a second data latch, a third data latch, and different fourth and fifth data latches, according to an embodiment of the present disclosure. [Figure 28] 1 illustrates steps of a method of operating a memory device according to an aspect of the present disclosure.

[0012] For ease of understanding, wherever possible, like reference numerals have been used to designate like elements common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized in other embodiments without specific recitation. DETAILED DESCRIPTION OF THE INVENTION

[0013] In the following description, details are set forth to provide an understanding of the present disclosure. In some instances, specific circuits, structures and techniques are not described or shown in detail in order to avoid obscuring the present disclosure.

[0014] In general, the present disclosure relates to a type of nonvolatile memory device well suited for use in many applications. The nonvolatile memory device and associated method of operation of the present disclosure will be described in conjunction with one or more exemplary embodiments. However, the specific exemplary embodiments disclosed are provided merely to explain the concepts, features, advantages, and objects of the present invention with sufficient clarity to enable those skilled in the art to understand and practice the disclosure. Specifically, the exemplary embodiments are provided so that this disclosure will be thorough and will fully convey the scope to those skilled in the art. Numerous specific details are set forth, such as examples of specific components, devices, and methods, to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that specific details need not be employed, that the exemplary embodiments may be embodied in many different forms, and that none of these should be construed to limit the scope of the present disclosure. In some exemplary embodiments, well-known processes, well-known device structures, and well-known techniques are not described in detail.

[0015] In some memory devices or arrangements, memory cells are coupled together in blocks or sub-blocks, such as NAND strings. Each NAND string comprises several memory cells connected in series between one or more drain-side select gate SG transistors (SGD transistors) on the drain side of the NAND string, which are connected to bit lines, and one or more source-side select gate SG transistors (SGS transistors) on the source side of the NAND string, which are connected to source lines. Furthermore, the memory cells may be arranged with a common control gate line (e.g., word line) that serves as the control gate. A set of word lines extends from the source side of the block to the drain side of the block. Memory cells may also be connected in other types of strings and in other ways.

[0016] In a 3D memory structure, memory cells can be arranged in vertical strings in a stack, with the stack comprising alternating conductive and dielectric layers. The conductive layers act as word lines connecting the memory cells. The memory cells can include data memory cells that are eligible to store user data and dummy or non-data memory cells that are not eligible to store user data.

[0017] Before programming certain non-volatile memory devices, the memory cells are typically erased. In some devices, the erase operation removes electrons from the floating gates of the erased memory cells. Alternatively, the erase operation removes electrons from the charge trapping layer.

[0018] A programming operation for a set of memory cells typically involves applying a series of program voltages to the memory cells after the memory cells are provided in an erased state. Each program voltage is provided in a program loop, also referred to as a program verify iteration. For example, the program voltage may be applied to a word line connected to the control gate of the memory cell. In one approach, incremental step pulse programming is performed, increasing the program voltage by a step size in each program loop. A verify operation may be performed after each program voltage to determine whether the memory cell has completed programming. Once programming is complete for a memory cell, the memory cell may be locked out from further programming while programming continues for other memory cells in subsequent program loops.

[0019] Each memory cell can be associated with a data state according to the write data in a program command. Based on the data state of the memory cell, the memory cell either remains in the erased state or is programmed to a data state (programmed data state) different from the erased state. For example, in a two-bit-per-cell memory device, there are four data states, including the erased state and three higher data states, referred to as the A, B, and C data states. In a three-bit-per-cell memory device, there are eight data states, including the erased state and seven higher data states, referred to as the A, B, C, D, E, F, and G data states (see FIGS. 5 and 6). In a four-bit-per-cell memory device, there are sixteen data states, including the erased state and fifteen higher data states, referred to as the Er or S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, and S15 data states.

[0020] When a program command is issued, write data is stored in a latch associated with the memory cell. During programming, the memory cell's latch can be read to determine the data state to which the cell should be programmed. Each programmed data state is associated with a verify voltage, such that a memory cell having a given data state is considered to have completed programming when a sense operation determines that the threshold voltage (Vth) of the sense operation is above the associated verify voltage. A sense operation can determine whether a memory cell has a Vth above the associated verify voltage by applying the associated verify voltage to the control gate and sensing the current through the memory cell. If the current is relatively high, this indicates that the memory cell is in a conductive state where Vth is less than the control gate voltage. If the current is relatively low, this indicates that the memory cell is in a non-conductive state where Vth is above the control gate voltage.

[0021] The verify voltage used to determine that a memory cell has completed programming may be referred to as a final or lockout verify voltage. In some cases, additional verify voltages may be used to determine that a memory cell is near completion of programming. For example, in FIGS. 5 and 6, a memory cell to be programmed to the A data state may be subjected to a verify test at VvA, which is the verify voltage for the A data state. To improve programming time, some later data states may not be verified until certain previous data states have finished programming. Nevertheless, significant programming time is consumed because all data states are verified.

[0022] FIG. 1A is a top view of one NAND string 90. FIG. 1B is an equivalent circuit diagram of NAND string 90. The NAND string shown includes four transistors 100, 102, 104, and 106 in series and sandwiched between a first select gate 120 and a second select gate 122. Select gate 120 connects the NAND string to a bit line 126. Select gate 122 connects the NAND string to a source line 128. Select gates 120 and 122 are controlled by applying appropriate voltages to control gates 120CG and 122CG, respectively. Transistors 100, 102, 104, and 106 each have a control gate and a floating gate. Transistor 100 has a control gate 100CG and a floating gate 100FG. Transistor 102 includes a control gate 102CG and a floating gate 102FG. Transistor 104 includes a control gate 104CG and a floating gate 104FG. Transistor 106 includes a control gate 106CG and a floating gate 106FG. Control gates 100CG, 102CG, 104CG, and 106CG are connected to word lines WL3, WL2, WL1, and WL0, respectively. In one embodiment, transistors 100, 102, 104, and 106 are each memory cells. In other embodiments, the memory cells may include multiple transistors or may differ from the memory cells shown. Select gates 120 and 122 are connected to drain side select line SGD and source side select line SGS, respectively. In addition to NAND flash memory, other types of non-volatile memory may be used.

[0023] FIG. 2 illustrates a non-volatile storage device 210 that may include one or more memory dies or chips 212. The memory die 212 includes an array 200 of memory cells (two-dimensional or three-dimensional), control circuitry 220, and read / write circuits 230A and 230B. In one embodiment, access to the memory array 200 by various peripheral circuits is implemented symmetrically on both sides of the array, resulting in a reduction in the density of access lines and circuits on each side by half. The read / write circuits 230A and 230B include multiple sense blocks 300 that allow pages of memory cells to be read or programmed in parallel. The memory array 200 is addressable by word lines via row decoders 240A and 240B and by bit lines via column decoders 242A and 242B. In a typical embodiment, a controller 244 is included in the same memory device 210 (e.g., a removable storage card or package) as the one or more memory dies 212. Commands and data are transferred between the host and the controller 244 via lines 232, and between the controller and one or more memory dies 212 via lines 234. An implementation may include multiple chips 212.

[0024] Control circuitry 220 cooperates with read / write circuits 230A and 230B to perform memory operations on memory array 200. Control circuitry 220 includes a state machine 222, an on-chip address decoder 224, and a power control module 226. State machine 222 provides chip-level control of memory operations. On-chip address decoder 224 provides an address interface for translating between addresses used by a host or memory controller and hardware addresses used by decoders 240A, 240B, 242A, and 242B. Power control module 226 controls the power and voltages supplied to the word lines and bit lines during memory operations. In one embodiment, power control module 226 includes one or more charge pumps capable of generating voltages greater than the supply voltage.

[0025] In one embodiment, one or any combination of the control circuit 220, the power control circuit 226, the decoder circuit 224, the state machine circuit 222, the decoder circuit 242A, the decoder circuit 242B, the decoder circuit 240A, the decoder circuit 240B, the read / write circuit 230A, the read / write circuit 230B, and / or the controller 244 may be referred to as one or more managing circuits.

[0026] 3 is a block diagram illustrating one embodiment of a sense block 300. Each sense block 300 is divided into a core portion, referred to as a sense module 380, and a common portion 390. In one embodiment, there is a separate sense module 380 for each bit line and one common portion 390 for a set of sense modules 380. In one example, the sense block 300 includes one common portion 390 and eight sense modules 380. Each of the sense modules in a group communicates with its associated common portion via a data bus 372.

[0027] The sense module 380 includes a sense circuit 370 that determines whether the conduction current in the connected bit line is above or below a predetermined threshold level. The sense module 380 also includes a bit line latch 382 that is used to set a voltage condition for the connected bit line. For example, a predetermined state latched in the bit line latch 382 results in the connected bit line being pulled to a state that specifies program inhibit (e.g., 1.5-3V). As an example, a flag=0 can inhibit programming, and a flag=1 does not inhibit programming.

[0028] Common portion 390 includes a processor 392, a set of five exemplary data latches 394, and an I / O interface 398 coupled between the set of data latches 394 and data bus 320. One set of data latches may be provided for each sense module, and five data latches, identified as ADL, BDL, CDL, DDL, and XDL, may be provided in each set. The use of data latches is described further below.

[0029] Processor 392 performs calculations. For example, one of the functions of processor 392 is to determine data stored in sensed storage elements and store the determined data in a set of data latches. At least some of the data latches in the set of data latches (e.g., 394) are used to store data bits determined by processor 392 during a read operation. At least some of the data latches in the set of data latches are also used to store data bits imported from data bus 320 during a program operation. The imported data bits represent write data to be programmed into the memory. I / O interface 398 provides an interface between data latches 394-397 and data bus 320.

[0030] In one embodiment, a user can stream data to be programmed into a storage element into the XDL latch. This program data can be transferred to the ADL, BDL, and CDL latches at the beginning of a program operation. Note that this describes programming three bits per memory cell. In one embodiment, during a read operation, the ADL, BDL, and CDL latches are used to store the three bits read from the memory cell. In one embodiment, a user can toggle the read data out through the XDL latch.

[0031] In one embodiment, a user has access to the XDL latch, but not the ADL, BDL, or CDL latches. For example, a user may be able to access the XDL latch to perform background caching during a program operation. Background caching is described in more detail below. In one embodiment, a user has limited access to the XDL latch during a program operation. For example, a user may be able to stream program data into the XDL latch before a programming operation. However, a user may not have access to the XDL latch during an embodiment of programming. In one embodiment, the XDL latch is used to store "lockout data" for a memory cell during a program operation. Briefly, the lockout data may indicate that the storage element is locked out from further programming. Further details are provided below.

[0032] During a read or other sensing operation, state machine 222 controls the application of different control gate voltages to the addressed storage element. As sense module 380 steps through various control gate voltages corresponding to the various memory states supported by the memory, sense module 380 may trip at one of these voltages, providing an output from sense module 380 to processor 392 via bus 372. At that point, processor 392 determines the resulting memory state by considering the sense module trip event and information about the control gate voltage applied from the state machine via input line 393. Processor 392 then calculates a binary encoding for the memory state and stores the resulting data bit in a data latch (e.g., 394). In another embodiment of the core portion, bit line latch 382 serves both as a latch for latching the output of sense module 380 and as a bit line latch as described above.

[0033] Some implementations may include multiple processors 392. In one embodiment, each processor 392 includes an output line (not shown), each of which is connected to a wired-OR. In some embodiments, the output line is inverted before being connected to the wired-OR line. This configuration allows for a quick determination of when the programming process is complete during the program verify process, because the state machine receiving the wired-OR line can determine when all bits being programmed have reached their desired levels. For example, as each bit reaches its desired level, a logic 0 for that bit is sent to the wired-OR line (or an inverted data 1). When all bits output a data 0 (or an inverted data 1), the state machine knows to terminate the programming process. Because each processor communicates with eight sense modules, logic is added to the processor 192 to accumulate the results of the associated bit lines, so that the state machine either needs to read the wired-OR line eight times, or the state machine needs to read the wired-OR line only once. Similarly, by choosing the right logic levels, the global state machine can detect when the first bit changes state and change the algorithm accordingly.

[0034] During programming or verify, data to be programmed is stored in a set of data latches 394-397 from data bus 320. A programming operation under the control of a state machine involves a series of programming voltage pulses applied to the control gates of addressed storage elements. Each program pulse is followed by a readback (verify) to determine whether the storage elements have been programmed to the desired memory state. Processor 392 monitors the readback memory state against the desired memory state. If the two match, processor 392 sets bit line latch 382 to pull the bit line to a state specifying program inhibit. This inhibits the storage elements coupled to the bit line from further programming, even if a program pulse appears at the control gate of the storage element. In another embodiment, the processor initially loads bit line latch 382, ​​and the sense circuitry sets bit line latch 382 to an inhibit value during the verify process.

[0035] Each set of data latch stacks 394-397, in one embodiment, contains a stack of data latches corresponding to a sense module 380. In one embodiment, there are five data latches per sense module 380. The ADL, BDL, and CDL data latches may be implemented as shift registers, such that parallel data stored in these data latches is converted to serial data in the XDL latches for transfer over data bus 320, and vice versa. All ADL, BDL, and CDL data latches corresponding to a read / write block of m storage elements may be chained together to form a block shift register, such that blocks of data may be input or output via serial transfer. In particular, a bank of read / write modules may be adapted such that each set of ADL, BDL, and CDL data latches of the bank sequentially shifts data into and out of the XDL latches as if these data latches were part of a shift register for the entire read / write block.

[0036] In one embodiment, one purpose of the ADL, BDL, and CDL latches is to store data to be programmed into the storage element. For example, the storage element may store three bits per storage element. In one embodiment, the storage element stores four bits per storage element. In this case, there may be an additional data latch (not shown in FIG. 3) to store the fourth bit of data to be programmed into the storage element. In one embodiment, the storage element stores only two bits per storage element, in which case one of the ADL, BDL, and CDL latches is not needed. The storage element can store five or more bits per storage element, in which case there may be one data latch for each bit.

[0037] In one embodiment, the ADL, BDL, and CDL latches may also be used to store status information during programming. For example, after a storage element reaches its target threshold voltage, each latch (ADL, BDL, CDL) may be set to "1" to indicate that programming is complete for that storage element. In one embodiment, the latches are used differently as programming progresses through different stages. In one embodiment, the ADL latch is released during programming. In one embodiment, the BDL latch is also released during programming. Further details are provided in connection with Figures 12, 13A-13D, and 14, as well as elsewhere.

[0038] In one embodiment, the DDL latch is used to store status information during programming. In one embodiment, programming slows as the storage element approaches a target threshold level. For example, the DDL latch may identify that the Vth of the storage element is above a lower verify level (e.g., VvaL or VvbL in FIG. 5). If the storage element is not already locked out, the storage element may receive slower programming. If the DDL latch indicates that the Vth of the storage element is below the lower verify level, the storage element may be in a fast programming mode. Further details are provided below.

[0039] In one embodiment, the XDL latch is used to store status information during programming. After data from the XDL latch is shifted into the ADL, BDL, and CDL data latches, the XDL latch may be set to an initial state (e.g., "0"). After the memory cell reaches its target threshold voltage, the XDL latch may be set to another state (e.g., "1"). Thus, the XDL latch may store a "lockout status." Thus, program data in the ADL, BDL, and CDL latches may be preserved both during and after the program operation. Further details are provided below.

[0040] FIG. 4 illustrates blocks of NAND flash memory cells in the memory array 200 of FIG. 2. The memory array may include many blocks 400. Two exemplary blocks 400 are shown in FIG. 4. Each block 400 includes several NAND strings. A set of bit lines, e.g., BL0, BL1, ..., may be shared among the blocks. Thus, each NAND string is associated with one bit line. Each NAND string is connected at one end to a drain select gate (SGD), whose control gate is connected via a common SGD line. The NAND string is connected at the other end to a source select gate, which is connected to a common source line 420. Sixty-four word lines, e.g., WL0 through WL63, extend between the source select gates and the drain select gates.

[0041] In addition to NAND flash memory, other types of nonvolatile memory can also be used. For example, another type of memory cell useful in flash EEPROM systems utilizes a nonconductive dielectric material instead of a conductive floating gate to store charge in a nonvolatile manner. A triple-layer dielectric formed of silicon oxide, silicon nitride, and silicon oxide ("ONO") is sandwiched between a conductive control gate and the surface of a semiconductor substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a confined region. This stored charge then detectably changes the threshold voltage of a portion of the cell's channel. The cell is erased by injecting hot holes into the nitride. Similar cells can be provided in a split-gate configuration, where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor.

[0042] Another approach uses NROM cells. For example, two bits are stored in each NROM cell, where an ONO dielectric layer extends across the channel between the source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. Multistate data storage is achieved by separately reading the binary states of spatially separated charge storage regions within the dielectric. Other types of nonvolatile memory are also known.

[0043] Note that there may be thousands or tens of thousands of bit lines, and thus one word line may be used by tens of thousands of storage elements. Typically, there is a driver at one end of the word line that provides a read reference voltage or programming voltage.

[0044] FIG. 5 shows an example set of threshold voltage distributions for an 8-state memory device in which each storage element stores three bits of data. A first threshold voltage (Vth) distribution is provided for erased (Er state) storage elements. Seven Vth distributions represent programmed states A through G. In one embodiment, the threshold voltage in the Er state is negative, and the threshold voltages in the A through G distributions are positive. However, all or part of the threshold distribution for the Er state may be positive. Also, all or part of the threshold distribution for the A state may be negative (as for other data states).

[0045] Read reference voltages Vra, Vrb, Vrc, etc. are also provided for reading data from the storage elements. By testing whether the threshold voltage of a given storage element is above or below Vra, Vrb Vrc, etc., the system can determine the state, e.g., programming condition, that the storage element is in.

[0046] Additionally, verify reference voltages Vva, Vvb, Vvc, etc. are provided. When programming storage elements to the A state, B state, C state, etc., the system tests whether those storage elements have threshold voltages equal to or greater than Vva, Vvb, Vvc, etc.

[0047] In one embodiment known as full sequence programming, storage elements can be directly programmed from the Er state to any of the programmed states A-G. For example, a population of storage elements to be programmed can first be erased so that all storage elements in the population are in the Er state. A series of program pulses are then used to program the storage elements to their respective target states A-G. Some storage elements are programmed from the Er state to the A state, while other storage elements are programmed from the Er state to the B state, and so on.

[0048] FIG. 5 also shows verify low reference voltages, such as VvAL, VvBL, and VvCL. These reference voltages may be used during program verify operations to determine whether a storage element is close to its intended target threshold. If so, the programming speed may be slowed down. In one embodiment, Vdd is applied to bit lines that have reached their target state and are inhibited from further programming. Bit lines of storage elements that remain below the verify low level may be grounded to enable fast programming. However, when between the verify low level and the normal verify level, the bit lines may receive an intermediate voltage (e.g., between ground and Vdd) to trigger slow or medium programming. As an example, the intermediate voltage may be approximately 0.6V to 0.8V. However, the intermediate voltage may be either below or above this range. In one embodiment, a DDL latch indicates where the storage element is in this programming sequence. Further details are provided below. In one embodiment, storage elements that are programmed to the G state do not receive slow (or medium) programming. Therefore, a verify low reference voltage is not shown in FIG. 5 for the G state. However, there may be a VvGL for the G state if desired.

[0049] In one embodiment, multiple passes may be used to program a storage element. For example, one pass may be used to program each bit. Thus, if three bits are stored per memory cell, there may be three passes. If two bits are stored per memory cell, there may be two passes. In one embodiment, a multi-state storage element stores data for three different pages: a lower page, a middle page, and an upper page. The eight states and the bits they represent may be: Er state (111), A state (011), B state (101), C state (001), D state (110), E state (010), F state (100), and G state (000). For the Er state, all pages store "1." For the A state, the lower page stores "0," the middle page stores "1," and the upper page stores "1." Other states may be inferred similarly. Note that although a specific bit pattern is assigned to each of the states, different bit patterns may be assigned. Note that this bit and page assignment may also be used for other programming sequences, such as the fast / slow programming described above.

[0050] In one embodiment, in a first programming pass, the lower page is programmed for the selected word line WLn. If the lower page remains data 1, the state of the storage element remains erased. If data is to be programmed to 0, the threshold voltage of the storage element on WLn is raised so that the storage element is programmed to an intermediate state. This intermediate state may have a lower tail just below VvD. In one embodiment, in a second programming pass, the middle page is programmed for the selected word line WLn. This results in two or more threshold voltage distributions (one added from each of the previous distributions). In one embodiment, in a third programming pass, the upper page is programmed for the selected word line WLn. This results in four or more threshold voltage distributions (one added from each of the previous four distributions).

[0051] While the programming example shows eight data states and three pages of data, the concepts taught can be applied to other implementations having more or fewer than eight states and more or fewer than three pages. Furthermore, in the exemplary programming techniques described, the Vth of the storage elements gradually increases as they are programmed to the target data state. However, programming techniques can be used in which the Vth of the storage elements gradually decreases as they are programmed to the target data state. Programming techniques that measure storage element current can be used as well. The concepts herein can be adapted to different programming techniques.

[0052] Figure 6 shows that the Vt distributions may overlap because the error correction algorithm can handle a certain percentage of erroneous cells. In some embodiments, at one point in time, the threshold voltage distributions may resemble Figure 5, and at another point in time, the threshold voltage distributions may overlap, as in Figure 6. For example, immediately after programming, the threshold voltage distributions may resemble Figure 5. However, over time, the threshold voltages of the memory cells may shift, such that there may be overlap.

[0053] However, immediately after programming, there may be overlap between at least some adjacent threshold distributions. Note that if there is overlap between adjacent Vt thresholds, it may be very difficult to detect word line defects.

[0054] Also, note that in contrast to the equal spacing / width of the threshold voltage distributions shown, various distributions may have different widths / spacing to accommodate varying amounts of susceptibility to data retention loss.

[0055] 7 is a flow chart illustrating one embodiment of a programming process that includes one or more verify steps. In step 810, a program voltage (Vpgm) is set to an initial value. Also in step 710, a program counter (PC) is initialized to 0. In step 720, a program pulse is applied.

[0056] In step 722, a verify process is performed. In one embodiment, the verify is a simultaneous coarse / fine verify. Referring to FIG. 5, some memory cells programmed to the A state are verified for the VvaL level, while other memory cells programmed to the A state are verified for the Vva level. Coarse programming is applied during the initial programming step when the memory cell's threshold voltage is well below the final level (Vva). However, after the memory cell's threshold voltage reaches VvaL, fine programming is used. Thus, some memory cells are verified for coarse programming, while other memory cells are verified for fine programming. Note that with coarse / fine programming, some memory cells are verified for one state (e.g., the A state), while other memory cells are verified for another state (e.g., the B state). Note that once a particular memory cell is verified as being programmed to its intended state, it may be locked out from further programming.

[0057] Note, however, that verify may produce erroneous results if there is an open circuit in the selected word line being programmed. As discussed above, an open circuit in a word line may result in a storage element on the far side of the open circuit receiving a reference voltage that is lower than intended. For example, a storage element intended to be programmed to the G state should receive a reference voltage VvG (see FIG. 5) at the control gate of the storage element. However, the storage element may actually receive a lower voltage due to the open circuit. Under normal circumstances, if the storage element has not yet reached its target state (e.g., the actual Vt of the storage element is less than the reference voltage), the storage element will turn on in response to the verify voltage. On the other hand, if the storage element has reached its target state (e.g., the actual Vt of the storage element is equal to or greater than the reference voltage), the storage element should not turn on. For example, consider the case where a storage element is targeted for the G state. This storage element is verified by applying VvG to the selected word line. If its actual Vt is less than VvG, it will conduct current. After the actual Vt of the storage element exceeds VvG, the storage element no longer turns on, indicating that the storage element has reached its target state.

[0058] However, a storage element that has crossed a wire break may receive an excessively low verify voltage and thus fail to turn on when the storage element's actual Vt is less than the target Vt. A storage element that has crossed a wire break may see a verify voltage lower than intended. For example, a storage element targeted for the G state may see a verify voltage of VvG but see a lower voltage at the control gate of the storage element. As one particular example, a storage element may only see a verify voltage of VvF when the storage element is crossing a wire break. Thus, in this particular example, the verify test passes when its actual Vt is greater than VvF. In general, a storage element that has crossed a wire break may pass a verify test if the storage element's actual threshold voltage is less than VvG. Thus, programming stops for that storage element. However, it may not actually be programmed.

[0059] In step 724, it is determined whether all of the memory cells have verified that their threshold voltages are at their final target voltages. If so, the programming process completes successfully (status=pass) in step 726. If not all of the memory cells have verified, it is determined whether the program counter (PC) is less than a maximum value, such as 20. If the program counter (PC) is greater than or equal to max (step 728), the programming process has failed (step 730). If the program counter (PC) is less than the maximum value (e.g., 20), in step 732, the program counter (PC) is incremented by 1 and the program voltage is stepped up to the next pulse. Following step 732, the process loops back to step 720, where the next program pulse is applied to the memory cells.

[0060] 8 shows a diagram 800 of threshold voltage (Vt) distributions during a programming operation, examining a first memory state, here shown as state B, and a second memory state, here shown as state C. While states B and C are used to illustrate the concepts, it will be appreciated that similar principles can be used for other successive states. The horizontal axis shows voltage.

[0061] In NAND memory, the logical value stored in a memory cell is determined by the voltage window within which the cell's Vt exists. Vt is the voltage stored in the cell after a program pulse. As cell sizes shrink and more bits are stored per cell, the threshold voltage window used to represent each value becomes smaller, leading to an increased error rate in determining the cell's value. This is because process variations become more prevalent as the amount of charge stored in a flash cell decreases along with feature size, leading to significantly different Vts for different cells storing the same value. Therefore, determining which logical value a cell's threshold voltage corresponds to, while necessary for reliability, is becoming increasingly difficult.

[0062] After each program pulse is applied to the memory cells, the memory system performs a verify step that can detect the distribution of voltages stored in the memory cells. Each memory state (e.g., states A through G) has its own Vt, which increases with each successive state. Vt distribution 801 results from the first program pulse applied to the memory cells and shows the bit scan count of the number of memory cells as a function of voltage. The upper tail of distribution 801 includes some scanned bits (memory cells) that exceed the voltage verify level for state B. This is represented in region 803 to the right of the voltage verify level for state B. If the bit scan count in region 803 does not exceed the threshold, the memory system applies the next program pulse, resulting in distribution 805. If the bit scan count in region 803 meets or exceeds the threshold, the memory system triggers a program verify pulse for state C, resulting in bit scan distribution 805. No prior program verify is applied to state C before triggering, saving some program verify counts and known as smart skip program verify. This subsequent program pulse and verify results in distribution 807 exceeding distribution 805 (at a higher voltage). In an exemplary embodiment, when the Vt distribution is in a particular memory cell state, e.g., one of states A-F, the verify process can trigger a verify of the next voltage level in the same verify process without triggering the next program pulse. In an exemplary embodiment, the verify process counts bits to the right of the Vt of state B and triggers a verify for state C, which occurs in the same verify loop as the detection of bits exceeding the Vt of state B.

[0063] During a program verify operation in a memory, an exemplary embodiment typically performs program verify of all states, e.g., states A through G, according to a set scheme. See, for example, FIG. 10A of U.S. Pat. No. 10,014,063, the entire contents of which are incorporated herein by reference. In some practical applications, performing verify of states C through G after the first program pulse may be time- and resource-intensive. Therefore, smart skip program verify detects when the upper tail of a lower state (e.g., state A or B) exceeds a certain threshold and triggers program verify for the next higher state before starting the next program / verify loop. This can reduce unnecessary program / verify loops for the higher states in subsequent program loops. To trigger next-state verify, there is a predetermined bit count in the memory circuit and during the program operation. When the bit scan result indicates that the upper tail has a higher bit count compared to the stored threshold (or reaches the threshold), the methodology triggers next-state verify after the next program pulse.

[0064] A smart skip program verify operation detects the upper tail of the “n” state and determines whether the triggering n+1 state verifies based on a threshold. The threshold can be set based on statistical analysis of the memory device. If it is desired to determine when to skip from the current state (n) being verified to the next state (n+1) using even a minimal voltage increase in programming voltage, any early program verify on the next loop (n+1 loop) instead of the current loop (n) may result in over-programming.

[0065] 9A shows a diagram 900 including threshold voltage distributions 901, i.e., bit scan counts, from a verify operation, which is used to verify the programmed bit values ​​stored in addressed memory cells at state verify level 903. The area 905 to the right of the voltage level and under the curve of verify pulse 901 (the upper tail of verify pulse 901) is the bit scan count (i.e., the count of memory cells whose voltage exceeds the state voltage level). Area 905 does not show enough counts in the same verify iteration to exceed the threshold and trigger a skip to the next state level.

[0066] 9B shows a diagram including a threshold voltage distribution 910, i.e., bit scan count, from a verify operation, which is used to verify the programmed bit values ​​stored in the addressed memory cells at state level 903. The area 915 to the right of the voltage level and under the curve of the verify pulse 910 (e.g., the upper tail of distribution 910) is the bit scan count (i.e., the number of memory cells whose voltage exceeds the state voltage level). Area 905 indicates a count that exceeds the threshold and is sufficient to trigger a program verify to the next state level in the same verify iteration. In an exemplary embodiment, the method triggers the verify before applying the next program pulse.

[0067] FIG. 10A illustrates a program verify operation 1000A involving two program verify iterations. Operation 1000A is a partial example of a memory cell programming operation for a multistate memory device having an erased state (Er) and three programmed memory states (e.g., A, B, C). The horizontal axis represents time. The vertical axis represents control gate voltage or word line voltage. Generally, a programming operation can involve applying a pulse train to a selected word line, where the pulse train includes multiple program loops or program verify iterations. The program portion of the program verify iteration includes a Vpgm pulse (voltage pulse 1003 or 1004), and the verify portion of the program verify iteration includes one or more verify pulses (e.g., voltage pulses 1007, 1008, or voltage pulses 1010, 1011).

[0068] For each Vpgm pulse 1003, 1004, a square waveform is shown for simplicity, but other shapes are possible, such as a multi-level or ramp shape. Additionally, in this example, step-up pulse programming (ISPP) is used, where the Vpgm pulse amplitude steps up with each successive program loop, shown as voltage increments 1005. This example uses ISPP in a single programming pass where programming is complete. ISPP may also be used in each programming pass of a multi-pass operation.

[0069] The pulse train typically includes Vpgm pulses whose amplitude increases stepwise at each program verify iteration using a fixed or variable step size, e.g., voltage step 1005. A new pulse train starts at an initial Vpgm pulse level (e.g., for an A level) and ends at a final Vpgm pulse level that does not exceed the maximum allowable level (e.g., a G level for a 3-bit multi-level memory).

[0070] Operation 1000A includes a series of Vpgm pulses 1003, 1004 applied to a selected word line for programming and an associated set of non-volatile memory cells. Depending on the target memory state being verified, by way of example, one, two, or three verify voltage pulses are provided after each Vpgm pulse. A voltage of 0V (shown here as 1015) may be applied to the selected word line between Vpgm pulses 1003, 1004 and verify voltage pulses 1007, 1008, and 1010, 1011.

[0071] In one embodiment, an A-state verify voltage VvA (e.g., waveform or signal 1007) may be applied after the first Vpgm pulse 1003. A B-state verify voltage VvB (e.g., waveform or signal 1008) may be applied after waveform 1007. A bit scan is performed to count the number of memory cells above the B-state level. This is the operation shown and described with reference to FIG. 9B. If the bit scan count exceeds a threshold, the memory controller triggers operation 1000A in the next iteration 1002 to trigger the C-state level verify signal 1001.

[0072] The next iteration 1002 increases the Vpgm pulse 1004 by a voltage 1005 from the first program pulse 1003. The signal level drops to approximately 0 volts, after which B-state and C-state program verify pulses 1010, 1011 are applied. A B-state verify voltage VvB (e.g., waveform or signal 1010) may be applied after the second Vpgm pulse 1003. A C-state verify voltage VvC (e.g., waveform or signal 1011) may be applied after waveform 1010. Thus, the B-state bit count triggered the verification of the C-state in the subsequent verify iteration.

[0073] FIG. 10B shows a program operation 1000B similar to operation 1000A, with the same signals, e.g., voltage levels, being numbered the same as in FIG. 10A. However, there are differences. When a bit count from a bit scan is performed in the B state, e.g., based on signal 1008, the bit count triggers operation 1000B to perform a C-level verify in the same iteration. That is, the C-level verify is performed in the same iteration as the preceding B state in which the bit scan count threshold was exceeded. The initial C-level verify occurs before the incremented program signal 1004. This is shown schematically in box 1020, where a bit scan count of the B state is performed and the memory controller detects that the count threshold has been met or exceeded. The memory controller then applies the next verify state level before proceeding to iteration 1002.

[0074] While the above example uses the A, B, and C states for illustrative purposes, it is within the scope of additional embodiments to apply the same determination that the bit scan count meets or exceeds a count threshold to trigger verification of the next state. For example, the C state can trigger a D state verification in the same iteration. The D state bit scan count determination can trigger an E state verification in the same iteration. The E state bit scan count determination can trigger an F state verification in the same iteration. The F state bit scan count determination can trigger a G state verification in the same iteration.

[0075] Figure 10C shows a program and verify operation 1000C that is similar to Figures 9A and 9B, with like elements having the same reference numerals, except that this operation 1000C is when the bit scan count for the B state does not exceed or meet the threshold. This is the operation 1000C that results from the embodiment shown in Figure 9A. The C state was not triggered earlier by the count in the first iteration, and therefore is not present in the second iteration 1002, nor is it triggered in the first iteration 1001.

[0076] FIG. 11 is a flowchart of one embodiment of a process 1100 for operating data latches while programming and verifying non-volatile storage. Process 1100 provides details for maintaining information indicating which storage elements have been programmed to a particular state. Note that the data latches that initially indicate which state the storage elements are to be programmed to may be released during programming. Thus, this information may be lost during the programming process. In one embodiment, process 1100 "tracks" or maintains information about one state. By tracking a state, it is meant that process 1100 maintains information about which storage elements were intended to be programmed to a particular (tracked) state after programming is complete. Note that this may be either the erased state or the programmed state.

[0077] Process 1100 provides further details of one embodiment of steps 1002 and 1004 from Figure 10. Reference is made to set of data latches 394 in Figure 3. As described above, three data latches ADL, BDL, and CDL initially store the data to be programmed into the storage element. Thus, in one embodiment, the storage element stores three bits. A fourth data latch DDL is used for what is referred to herein as a "quick pass write" (QPW) state. Note that there may be more or less than four latches.

[0078] In step 1102, the data latches are set to their target program state. In one embodiment, the ADL, BDL, and CDL latches are set as shown in Figure 13A. Note that different bit assignments may be used.

[0079] In step 1104, the DDL latches are set to an initial state. In one embodiment, the DDL latches are set as shown in FIG. 13A. In that embodiment, the DDL latches for all storage elements are set to "0" except for storage elements that are to remain in the erased state. In one embodiment, every DDL latch is set to "0." In one embodiment, setting the DDL latches for all states to "0" is used when tracking the erased state.

[0080] In step 1106, programming conditions are applied based at least in part on the data latches. In one embodiment, bit line voltages are set. In one embodiment, three categories are used: one for storage elements that are locked out (or inhibited) from any further programming, one for storage elements that continue to undergo faster programming, and one for storage elements that are close to their target threshold voltage and should receive slower programming.

[0081] In one embodiment, the bit lines for locked out or inhibited storage elements are set to Vdd, the bit lines for storage elements undergoing nominal (or fast) programming are set to ground (e.g., Vss), and the bit lines for the third category are set to an intermediate voltage between ground and Vdd, which slows programming somewhat.

[0082] One or more programming pulses are applied to the selected word lines in step 1108. A pass voltage (e.g., Vpass) may be applied to unselected word lines.

[0083] In step 1110, a verify low pulse is applied to the selected word line. Referring to FIG. 5, VvAL may be applied. In step 1112, sensing is performed to determine whether storage elements intended to be programmed to the state associated with the verify low pulse have reached the verify low point. For example, storage elements intended to be programmed to the A state (as indicated by ADL, BDL, CDL) are sensed to determine whether the threshold voltage of the storage element is greater than or equal to VvAL. In one embodiment, the current in the bit line is sensed.

[0084] In step 1114, a DDL latch is set based on the results of step 1112. Note that the DDL latch in question is the one associated with the state that was just verified. In one embodiment, the DDL latch is set to "1" to indicate that slow programming should be performed. For example, a storage element intended to be programmed to an A state, which has a threshold voltage above VvAL, will have the DDL latch of the storage element set to "1."

[0085] In step 1116, the verify reference voltage is increased to the associated verify high reference voltage for the current state being verified. For example, the reference voltage is set to VvA (see FIG. 5). In one embodiment, step 1116 involves increasing the voltage on the selected word line.

[0086] In step 1118, sensing is performed to determine whether a storage element intended to be programmed to a state associated with the nominal verify pulse has reached the nominal verify point. For example, a storage element intended to be programmed to the A state is sensed to determine whether the threshold voltage of the storage element is greater than or equal to VvA. In one embodiment, the current in the bit line is sensed.

[0087] In step 1120, the ADL, BDL, and CDL latches are set based on the results of step 1120. Note that the latches in question are the latches associated with the state just verified. In one embodiment, one or more of the ADL, BDL, and CDL latches are set to "1" to indicate that programming is inhibited. For example, a storage element intended to be programmed to the A state, which has a threshold voltage above VvA, has the ADL, BDL, and CDL latches of the storage element set to "1."

[0088] Under some conditions, only one or two of the data latches may be needed to indicate a lockout condition. Thus, step 1120, in one embodiment, includes setting one or more of latches ADL, BDL, and CDL to "1." In one embodiment, process 1100 tracks how far along the programming process it is and uses different sets of latches to indicate lockout depending on what stage the programming is at. Further details are provided below.

[0089] In step 1122, the DDL latches of the storage elements being tracked may be set to "0" if the storage elements just passed program verify. For example, if the A state is being tracked, the DDL latches of those storage elements that just passed program verify for the A state are set to "0." However, if a state other than the A state is being tracked (e.g., the A state is not being tracked), the DDL latches remain at "1." Note that if a storage element passes nominal verify (e.g., VvA) in steps 1116-1118, the storage element should also have passed verify low (e.g., VvAL) in steps 1112-1114, and therefore the DDL latch should be "1." Note that by appropriately setting the DDL latch in step 1112, it is possible to maintain information about the intended program state for one of the states.

[0090] Note that the states tracked may also include the erased state. Note that there are no verify operations for storage elements that should remain in the erased state. Therefore, for these storage elements, the status of the DDL latch should not change in step 1114. When a state other than the erased state is being tracked, the DDL latch for storage elements that remain erased may initially be set to "1." On the other hand, when the erased state is being tracked, the DDL latch may initially be set to "0." Therefore, the DDL latch should remain at "0" throughout programming. In contrast, the DDL latch for other states may be set to "1" once the verify low passes.

[0091] In step 1124, a determination is made whether there are additional states to verify. Note that not all states need to be verified early in the programming operation. If there are more states to verify, then in step 1126, the verify reference voltage is increased. The reference voltage may be increased to the verify low reference level for the next state. A verify low pulse may then be applied in step 1110. Once all states to be verified have been verified at this point, a determination is made in step 1128 whether all storage elements have passed verification. Note that a certain number of storage elements may fall short of reaching their intended state and may be ignored. This may help speed up programming.

[0092] If not all storage elements pass verification (accounting for the possibility that some may fail), process 1100 returns to step 1106 and applies programming conditions based on latch 394. For storage elements that are currently locked out (as indicated by one or more of latches ADL, BDL, CDL), the bit lines of the storage elements may be set to Vdd. For the storage elements to receive slow programming, the bit lines of the storage elements may be set to an intermediate voltage. In one embodiment, the DDL latches of those storage elements that are not locked out from further programming are checked to determine if slow programming should be performed.

[0093] 12 is a flow chart of one embodiment of a process 1200 for operating data latches while programming and verifying non-volatile storage. Process 1200 provides further details on using data latches differently depending on the stage of the programming process. FIGS. 13A-13D are tables showing the status of data latches ADL, BDL, CDL, and DDL throughout the various stages of process 1200.

[0094] FIG. 14 illustrates latch usage during various stages of one embodiment of programming. Briefly, the programming process can be divided between the following stages: In the pre-lockout stage, data latches can be set up; In the ABCDEFG stage, all states are programmed; In the EFG stage, only the E, F, and G states are programmed; In the G program stage, only the G state is programmed; In the EPD stage, false program detection is performed. In one embodiment, word line defects are detected during the EPD stage. Also, note that the ADL latch is reset between the ABCDEFG and EFG stages. Similarly, the BDL latch is reset between the EFG and G stages. Further details are provided in conjunction with the description of FIG. 12.

[0095] Process 1200 illustrates an embodiment in which the G state is the tracking state. In step 1202, the target data state is stored in a latch. Figure 13A shows a table of initial states for latches ADL, BDL, and CDL.

[0096] In step 1204, the initial state of the DDL latch is set. In this embodiment, the initial state for storage elements that are to remain in the erased state is set to "1." The DDL for all other storage elements is set to "0." Figure 13A shows a table of the initial states of the DDL latch for memory cells subject to various states. Steps 1202 and 1204 may be performed during a pre-lockout phase (see Figure 14).

[0097] In step 1206, one or more programming pulses are applied, followed by verifying one or more states. One embodiment of step 1206 includes performing steps 1108, 1110, 1112, 1116, and 1118 of Figure 11 one or more times. For example, step 1108 can be performed once, followed by steps 1110, 1112, 1116, and 1118 to verify different states.

[0098] Initially, programming begins with the ABCDEFG stage (see Figure 14). The black bars in Figure 14 indicate when data latches are actively being used for programming or EPD. During the ABCDEFG stage, the ADL, BDL, and CDL latches are used to store lockout information. The DDL latch is used to store QPW status.

[0099] FIG. 13B shows an example of the use of latches during the ABCDEFG phase. At this point, any storage element that is locked out has a "1" in all of its ADL, BDL, and CDL latches. The erase case is shown in this state. For states A through G, the data to be programmed into the storage element is shown. However, once the storage element reaches its intended target state, the ADL, BDL, and CDL latches of the storage element may be set to "1." This was previously described as one possibility in step 1120 of FIG. 11. Therefore, the status of the ADL, BDL, and CDL may be checked when determining if the storage element is locked out during the ABCDEFG phase.

[0100] 13B also shows an example of the use of the DDL latch during the ABCDEFG phase. In one embodiment, a "1" in the DDL latch means that slow programming should be used. Thus, storage elements that are not locked out and have a "1" in the DDL latch can receive slow programming.

[0101] Note that the DDL latch is used differently for the G state: for storage elements programmed to the G state, the DDL latch, in one embodiment, is maintained at "0" throughout the programming process.

[0102] In step 1208, a determination is made whether storage elements subject to states A-D have been programmed. Note that not every storage element subject to these states is required to reach its intended state. In one embodiment, some storage elements may be left unprogrammed. If programming of states A-D is not yet complete, the process returns to step 1206.

[0103] Once the storage elements targeted for states A-D have been programmed, the ADL latch is released in step 1210. This is reflected by the ADL reset in FIG. 14 after the ABCDEFG program stage. Referring to FIG. 13C, the ADL latch is free at this point. Because the ADL latch is free, it may be used, by way of example, for background caching. Further details on using released data latches during program operations are described in U.S. Pat. No. 7,502,260 to Li et al., entitled "Method for Non-Volatile Memory with Background Data Latch Caching Operations During Program Operations," which is incorporated herein in its entirety for all purposes.

[0104] Note that after the ADL latch is released, programming proceeds to the EFG program stage (see FIG. 14). At this point, in one embodiment, only the BDL and CDL latches are used to store lockout information. Also, only the BDL and CDL latches are needed to contain the information necessary to uniquely define which state the storage element is programmed to. For example, in one embodiment, the combination "01" uniquely defines the E state, the combination "10" uniquely defines the F state, the combination "00" uniquely defines the G state, and the combination "11" uniquely defines the lockout state. Other bit assignments may also be used.

[0105] Further, in Figure 13C, the DDL latches of all storage elements below the E state should be "1". Storage elements being programmed to either the E or F state can have either a "1" or a "0" in the DDL latch, depending on whether the verify low passed. As before, the DDL latches for G state storage elements remain at "0". In one embodiment, verify low is not performed for G state storage elements. Thus, the DDL latches should show "0" throughout programming. However, as an example, verify low for the G state can be performed as long as the DDL latch is set to "0" when the storage element is locked out.

[0106] Programming then continues with the EFG phase (see FIG. 14). When determining how to apply the programming conditions (step 1211 of FIG. 12), the status of the BDL and CDL latches may be used for lockout. Storage elements that are not locked out and have a "1" in the DDL latch may receive slow programming.

[0107] In step 1212, a determination is made whether the E and F states are programmed. If not, the process continues to program and verify using the status of latches BDL, CDL, and DDL.

[0108] Once the E and F states have been programmed, the BDL latch is released in step 1214. This is reflected by a BDL reset at the end of the EFG programming phase (see Figure 14). Like the ADL latch, the BDL latch is free for purposes such as background caching.

[0109] 13D shows a table representing the BDL latch being released. At this point, the only storage elements left programmed are those in the G state. Therefore, the status of the CDL latch can uniquely describe whether a storage element should be programmed to the G state ("0" in this example) or locked out ("1" in this example).

[0110] Note that the status of the DDL latch is now "0" for the G-state storage elements. As previously mentioned, the DDL latch may remain at "0" for the G-state storage elements throughout programming.

[0111] Programming then continues with the G program phase (see FIG. 14). In step 1215, program conditions based on the states of the CDL and DDL are applied. The status of the CDL latch may be used to determine which storage elements are locked out. The status of the DDL latch, in one embodiment, remains at '0' for all G-state storage elements. However, in one embodiment, the DDL latch may be used for QPW status. Thus, in this case, storage elements that are not locked out and have their DDL latch set to '1' may receive slow programming.

[0112] Once the G-state storage elements have been programmed (step 1216), the G programming phase is complete. At this point, the CDL latches for all G-state storage elements should be at "1". The DDL latches for all G-state storage elements should be at "0". Note that in one embodiment, the DDL latches are at "0" because they are not allowed to be set to "1" during a programming operation.

[0113] However, in one embodiment, the DDL latch is allowed to be set to "1" when the G-state storage element passes verify low. In this case, the DDL latch may be set to "0" when the G-state storage element passes verify high.

[0114] Regardless of whether the information from the DDL latch is retained in that latch or transferred to another latch or some other storage location, the information about which storage elements were subject to the G state is maintained after the programming operation. Note that no extra data latches are required. Also, note that two of the data latches are freed up during programming for purposes such as background caching.

[0115] As mentioned above, a significant amount of programming time is consumed when every data state is verified. Specifically, a programming operation for a triple level cell (TLC) may involve the application of a program pulse followed by a verify iteration or program verify (pvfy) for each data state, repeated until most of the memory cells pass their respective program verify voltages or levels (with an allowable amount of slow cells set by parameters). Figure 15 is a table showing the number of program loops and verify iterations (shaded) for each data state in a programming operation for a triple level cell (TLC), along with the time period included in each program loop. As shown, the program time tPROG is primarily composed of the program pulses (P, PD, PR clocks or periods) and the verify time for each state (R, QPW, RWL, QPW, RR clocks or periods). Algorithms have been developed to optimize the number of verify iterations required for each state (e.g., smart PCV) and to fine-tune the ideal starting program voltage VPGM for the optimized program pulse (e.g., smart verify). However, it is desirable to somewhat reduce the program time tPROG required when verifying memory cells of any data state.

[0116] As a result, described herein is a memory device (e.g., non-volatile storage device 210 of FIG. 2) that includes memory cells (e.g., transistors 100, 102, 104, and 106 of FIG. 1B) each connected to one of a plurality of word lines (e.g., word lines WL3, WL2, WL1, and WL0 of FIG. 1B, or WL0-WL63 of FIG. 4). The memory cells are configured to hold a threshold voltage Vt or Vth corresponding to one of a plurality of memory or data states (e.g., FIGS. 5 and 6). For the plurality of data states, including the highest data state (e.g., data state G in FIGS. 5 and 6), the threshold voltage of the memory cell associated with the highest data state is higher than those of the other data states (e.g., the erased state and data states A-F in FIGS. 5 and 6). The memory device also includes control circuitry or means (e.g., one or any combination of control circuitry 220, decoders 240A, 240B, 242A, and 242B, power control module 226, sense block 300, read / write circuits 230A and 230B, controller 244, etc., of FIG. 2). The control means is configured to apply, during each of a plurality of program loops of a program operation, each of a series of programming pulses of a program voltage followed by verify pulses of a plurality of program verify voltages, each associated with one of a plurality of data states, to selected word lines of the plurality of word lines to program and verify memory cells connected to the word lines. The control means is also configured to skip verifying memory cells targeted for the highest data state during at least one of the plurality of program loops. Therefore, as described in more detail below, the program time tPROG can be further reduced by eliminating / reducing the verification of memory cells targeted for the highest data state (e.g., the data states in Figures 5 and 6) and controlling the programming of memory cells targeted for the highest data state solely via program loop count and / or bit line bias. The highest data state is selected because it can tolerate a wider threshold voltage distribution without affecting the required read pass voltage VREAD.

[0117] According to one aspect, program verification of the highest data state (e.g., data state G) may be skipped entirely, and data latches may be used to track loop counts; such an approach is referred to herein as Option 1. As described above, memory cells may be disposed in memory holes (e.g., NAND strings in FIG. 4 ), each coupled to one of a plurality of bit lines (e.g., bit lines BL0-BL13 in FIG. 4 ). Furthermore, the memory device may further include a plurality of data latches (e.g., data latches 394, 395, 396, and 397 in FIG. 3 ), each configured to store data to be programmed during a program operation and control one of the plurality of bit lines to enable or disable programming of memory cells in the memory holes coupled to the one of the plurality of bit lines. Each of the plurality of data latches stores one bit for defining a bit combination. Accordingly, the control means may be further configured to operate and update the plurality of data latches based on the data being programmed into the memory cell, the threshold voltage of the memory cell, and which of the plurality of data states is being programmed and verified during the program operation. The control means is also configured to update the plurality of data latches to track an amount of subsequent program loops of the plurality of program loops for each of the memory cells targeted to be programmed to the highest data state using one or more of the bit combinations.

[0118] FIG. 16 is a plot of threshold voltage distributions when program verification of the highest data state is skipped entirely. As shown, the erased state or Er (inhibited) and states A through F are program verified and locked out as normal. For G-state cells, once the pvfy F level (i.e., the program verify voltage for data state F) is passed, the count program loops until lockout (inhibited). G-state cells are tracked cell by cell. As described, each memory cell may be configured to store three bits. Thus, for example, with continued reference to FIG. 16, the multiple data states may include, in order of increasing threshold voltage magnitude, an erased data state (Er), a first data state (A), a second data state (B), a third data state (C), a fourth data state (D), a fifth data state (E), a sixth data state (F), and a seventh data state (G). Thus, the highest data state is the seventh data state. Therefore, according to another aspect, the plurality of data latches includes a first data latch ADL, a second data latch BDL, and a third data latch CDL, each configured to store data to be programmed during a program operation. The plurality of data latches also includes a fourth data latch DDL configured to control one of the plurality of bit lines to enable or disable programming of memory cells of memory holes coupled to one of the plurality of bit lines. The bit combinations include 16 bit combinations.

[0119] 17A is a table showing the information stored in the first data latch ADL (L), second data latch BDL (M), third data latch CDL (U), and fourth data latch DDL (QPW) for each data state of a ternary memory cell. As shown, 14 bit combinations are required to distinguish: 12 for A-F state fast programming (bit lines set to steady-state voltage VSS) and QPW programming (bit lines set to VBLC_QPW), one for the inhibit case Er or pass program verify high VH case, and one for the G state case (no QPW). However, because the four data latches ADL, BDL, CDL, and DDL can represent 16 bit combinations, this leaves two unused bit or code combinations. 17B is a table illustrating unused bit combinations of bits in the first data latch ADL(L), second data latch BDL(M), third data latch CDL(U), and fourth data latch DDL(QPW). These unused bit combinations may be used to track memory cells in the highest data state (e.g., G state) after passing the verify voltage level for the next highest data state (data state F) for option 1. No changes to the XDL latch (user cache) limits are necessary. Thus, the control means is further configured to update at least one of the first data latch ADL, second data latch BDL, third data latch CDL, and fourth data latch DDL associated with each memory cell of the memory cells targeted for the seventh data state to a first unused bit combination of the 16 bit combinations in response to one of the memory cells having a threshold voltage sensed during one of the verify pulses of one of the program verify voltages associated with the sixth data state that is greater than one of the plurality of program verify voltages associated with the sixth data state.The control means is additionally configured to update at least one of the first data latch ADL, second data latch BDL, third data latch CDL and fourth data latch DDL associated with one of the memory cells targeted for the seventh data state from a first unused bit combination of the 16 bit combinations to a second unused bit combination of the 16 bit combinations following application of a first subsequent programming pulse of the series of programming pulses of the program voltage to one of the memory cells targeted for the seventh data state. The control means is also configured to update at least one of the first data latch ADL, second data latch BDL, third data latch CDL and fourth data latch DDL associated with one of the memory cells targeted for the seventh data state from a second unused bit combination of the 16 bit combinations to one of the 16 bit combinations associated with the erased data state following application of a second subsequent programming pulse of the series of programming pulses of the program voltage to one of the memory cells targeted for the seventh data state.

[0120] FIG. 18 illustrates an exemplary tracking of memory cells targeted for the highest data state through subsequent program loops of multiple program loops using two unused bit combinations for Option 1. FIG. 19 is another table illustrating information stored in the first data latch ADL (L), second data latch BDL (M), third data latch CDL (U), and fourth data latch DDL (QPW) for each data state of Option 1. FIG. 20 is a table illustrating the impact on cache release (i.e., in which of multiple program loops a data latch can be released to allow the next page of user data to be stored). In memory devices that do not employ Option 1, the G state does not support QPW and uses only one bit combination, but as explained, the G state of Option 1 uses three combinations of codes and therefore may require an internal cache release delay. FIG. 21 summarizes parameter variations that affect the operation of a memory device using Option 1. As shown, by using XDL (the fifth data latch) for TLC, more than two program pulses for the G state can still be implemented. Such an approach impacts user cache freeing and causes delays for internal second and third bit cache freeing.

[0121] Instead of completely skipping the program verification of the highest data state (e.g., the G state), the memory device may only skip the program verification of the highest data state after the next-highest data state (e.g., the F state) is completed. Such an approach is referred to herein as Option 2. In Option 2, a counter may be used to track program loops. As explained, for example, referring again to FIG. 16 , the multiple data states may include an erased data state (Er), the next-highest data state (F), and the highest data state (G) in order of increasing threshold voltage magnitude. Thus, the control means may be further configured to program and verify memory cells of the memory cells using a series of programming pulses of a program voltage followed by a verify pulse of a plurality of program verify voltages associated with the series of programming pulses before the next-highest data state completes verification (i.e., in response to a predetermined amount of memory cells of the memory cells targeted for the next-highest data state and the highest data state not having a threshold voltage greater than one of the plurality of verify voltages associated with the next-highest data state), and to lock out memory cells having a threshold voltage greater than one of the plurality of verify voltages of one of the plurality of targeted data states from further programming. The control means may be configured to stop further verification of memory cells among the memory cells targeted for the highest data state after the next-highest data state completes verification (i.e., in response to the next-highest data state and a predetermined amount of memory cells among the memory cells targeted for the highest data state having threshold voltages greater than one of the plurality of verify voltages associated with the next-highest data state), and count subsequent program loops among the plurality of program loops. The control means may also be configured to inhibit programming of memory cells among the memory cells targeted for the highest data state in response to the amount of subsequent program loops among the plurality of program loops exceeding a predetermined slow cell count threshold.

[0122] As described, each of the memory cells may be configured to store three bits. Thus, for example, referring again to FIG. 16 , the plurality of data states may include, in order of increasing threshold voltage magnitude, an erased data state (Er), a first data state (A), a second data state (B), a third data state (C), a fourth data state (D), a fifth data state (E), a sixth data state (F), and a seventh data state (G). Thus, the next highest data state is the sixth data state (F), and the highest data state is the seventh data state (G). Thus, the control means may be further configured to program and verify memory cells among the memory cells targeted for the first data state, the second data state, the third data state, the fourth data state, the fifth data state, the sixth data state, and the seventh data state using a series of programming pulses of the program voltage and a series of verify pulses of the plurality of program verify voltages associated with the series of programming pulses before the sixth data state is verified. The control means may be configured to lock out memory cells having a threshold voltage greater than one of the plurality of verify voltages for one of the plurality of targeted data states from further programming in response to memory cells of the memory cells targeted for the sixth data state and the seventh data state not having a threshold voltage greater than one of the plurality of verify voltages associated with the sixth data state. After the next highest data state has completed verification, in response to memory cells of the memory cells targeted for the sixth data state and the seventh data state having a threshold voltage greater than one of the plurality of verify voltages associated with the sixth data state, stop further verification of memory cells of the memory cells targeted for the seventh data state and count subsequent program loops of the plurality of program loops. The control means is also configured to inhibit programming of memory cells of the memory cells targeted for the seventh data state in response to an amount of subsequent program loops of the plurality of program loops exceeding a predetermined slow cell count threshold.

[0123] Therefore, for option 2, before the F state is completed (e.g., a failing data state F bit scan), the Er state (inhibited) and A-G states are program verified and locked out as normal. After the F state is completed (a passing data state F bit scan), no program verification occurs. The remaining G state slow cells count program loops until they are locked out (inhibited) using a counter. Figure 22 shows an example sequence of program loops for the two options. As shown, the number of program pulses applied to the slow G state cells can be tracked by a counter (not a data latch). Such an approach provides easier control and there can be more or fewer loops than two with no impact on cache release. Figure 23 is a plot of threshold voltage distributions when the program verify of the highest data state is skipped after the next highest data state (e.g., the F state) is completed, and a counter is used to track program loops for the slow cells targeted for the highest data state. As shown, after the F state is completed (i.e., detecting F pass), all G state cells that do not pass the G program verify receive the same number of program pulses, which may further widen the threshold voltage distribution for the highest data state.

[0124] According to another aspect, the memory device may skip only the program verification of the highest data state (e.g., the G state) after the next highest data state (e.g., the F state) is completed, similar to Option 2, but using a data latch to track the program loop count instead of a counter. Such an approach is referred to herein as Option 3. For Option 3, the control means is configured to program and verify the memory cells using a series of programming pulses of a program voltage followed by a verify pulse of a plurality of program verify voltages associated with the series of programming pulses before the next highest data state completes verification (i.e., in response to a predetermined amount of memory cells targeted for the next highest data state and the highest data state not having a threshold voltage greater than one of the plurality of verify voltages associated with the next highest data state). The control means locks out memory cells having a threshold voltage greater than one of the plurality of verify voltages of one of the plurality of targeted data states from further programming. After the next highest data state completes verification (i.e., in response to the next highest data state and a predetermined amount of memory cells among the memory cells targeted for the highest data state having threshold voltages greater than one of the plurality of verify voltages associated with the next highest data state), the control means stops further verification of memory cells among the memory cells targeted for the highest data state and updates the plurality of data latches to track the amount of subsequent program loops among the plurality of program loops for each of the memory cells targeted to be programmed to the highest data state using one or more of the bit combinations.

[0125] More particularly, for option 3, the control means is further configured to update at least one of the first data latch ADL, the second data latch BDL, the third data latch CDL, and the fourth data latch DDL associated with each memory cell of the memory cells targeted for the seventh data state to a first unused bit combination of the 16 bit combinations in response to one of the memory cells having a threshold voltage greater than one of the plurality of program verify voltages associated with the sixth data state sensed during one of the verify pulses of one of the plurality of program verify voltages associated with the sixth data state before the sixth data state completes verification (i.e., in response to a predetermined amount of the memory cells of the memory cells targeted for the sixth data state (e.g., data state F) and the seventh data state (e.g., data state G) not having a threshold voltage greater than one of the plurality of verify voltages associated with the sixth data state). Before the sixth data state completes verification, at least one of the first data latch ADL, the second data latch BDL, the third data latch CDL, and the fourth data latch DDL associated with one of the memory cells targeted for the seventh data state is updated to one of the 16 bit combinations associated with the erased data state to inhibit programming of one of the memory cells targeted for the seventh data state in response to one of the memory cells having a threshold voltage greater than one of the plurality of program verify voltages associated with the seventh data state sensed during one of the verify pulses of one of the plurality of program verify voltages associated with the seventh data state.Before the sixth data state completes verification, the control means updates at least one of the first data latch ADL, the second data latch BDL, the third data latch CDL, and the fourth data latch DDL associated with one of the memory cells targeted for the seventh data state from the first unused bit combination of the 16 bit combinations to a second unused bit combination of the 16 bit combinations following application of one of the series of programming pulses of the program voltage to one of the memory cells targeted for the seventh data state. After the sixth data state completes verification (i.e., in response to a predetermined amount of the memory cells targeted for the sixth data state and the seventh data state having a threshold voltage greater than one of the plurality of verify voltages associated with the sixth data state), the control means updates at least one of the first data latch ADL, second data latch BDL, third data latch CDL, and fourth data latch DDL associated with one of the memory cells targeted for the seventh data state from a second unused bit combination of the 16 bit combinations and from a first unused bit combination of the 16 bit combinations to one of the 16 bit combinations associated with the erased data state so as to inhibit programming of one of the memory cells targeted for the seventh data state in response to one of the memory cells targeted for the seventh data state having a threshold voltage greater than one of the plurality of verify voltages associated with the sixth data state and less than one of the plurality of verify voltages associated with the seventh data state following application of a first subsequent programming pulse of the series of programming pulses of the program voltage to one of the memory cells targeted for the seventh data state.After the sixth data state completes verification, the control means updates at least one of the first data latch ADL, second data latch BDL, third data latch CDL, and fourth data latch DDL associated with one of the memory cells targeted for the seventh data state from the first unused bit combination of the 16 bit combinations to a second unused bit combination of the 16 bit combinations in response to one of the memory cells targeted for the seventh data state having a threshold voltage greater than one of the plurality of verify voltages associated with the sixth data state and less than one of the plurality of verify voltages associated with the seventh data state following application of a second subsequent programming pulse of the series of programming pulses of the program voltage to one of the memory cells targeted for the seventh data state.

[0126] Therefore, before the F state is completed (e.g., a fail data state F bit scan), the Er (inhibit) and A-G states are program-verified and locked out as normal. After the F state is completed (a pass data state F bit scan), no program verification occurs. The remaining G state slow cell count program loops until lockout (inhibit) by tracking each individual slow cell loop count using the data latches. The program time tPROG savings are the same as in Option 2, but the impact of the 3-bit cache is the same as in Option 1. Figure 24 shows an example tracking of memory cells for Option 3, along with corresponding plots of threshold voltage distributions. Figure 25 shows simulation results for Options 1, 2, and 3 compared to no program verify skip (POR) for the highest data state. Specifically, to evaluate the impact from the three options, individual cell threshold voltage Vt data versus program pulse (without QPW programming) data is collected. This data is then used to simulate the options. The G state threshold voltage Vt distribution is shown in Figure 25. As shown, Options 1 and 3 are identical and very similar to POR. Option 2 has an over-programming risk. Option 1 achieves the fastest program time tPROG and also maintains a very good threshold voltage Vt distribution. Option 2 has a simpler implementation (eliminating the need for data latch loop tracking), but in exchange, has an over-programming risk. Option 3, at least in this simulation, shows no benefit compared to Option 1 and also has a smaller improvement in program time tPROG. Options 3 and 1 have the same lower tail of the threshold voltage distribution, suggesting a small risk for cells that may require more than two pulses after passing F verify. Options 3 and 1 have the same upper tail, suggesting a small risk for cells that may require only one extra pulse after passing F verify.

[0127] FIG. 26 compares the highest data states, Option 1, Option 2, and Option 3, without skipping program verify. All three options can be applied to a quaternary cell (QLC) memory device, even for saving program verify S15. FIG. 27A is a table showing the information stored in the first data latch ADL (L), second data latch BDL (M), third data latch CDL (U), and the different fourth data latch (T) and fifth data latch DDL (QPW) for each data state of a quaternary cell (QLC). As shown, 30 bit combinations are required to distinguish: 28 for fast program (bit line set to steady-state voltage VSS) and QPW program (bit line set to VBLC_QPW) of the S1-S14 states; one for inhibit (Er or pass program verify high VH); and one for one S15 state (no QPW). Nevertheless, since the five data latches can represent 32 bit combinations, two unused bit or code combinations remain. Figure 27B is a table showing unused bit combinations among the bit combinations of the bits in the first data latch ADL (L), the second data latch BDL (M), the third data latch CDL (U), and the different fourth data latch (T) and fifth data latch DDL (QPW). Again, there is no change to the XDL (user cache) limit, but there is a delay for the internal second and third bit cache release.

[0128] FIG. 28 illustrates steps in a method of operating a memory device (e.g., non-volatile storage device 210 of FIG. 2). As described above, the memory device includes memory cells (e.g., transistors 100, 102, 104, and 106 of FIG. 1B) each connected to one of a plurality of word lines (e.g., word lines WL3, WL2, WL1, and WL0 of FIG. 1B, or WL0-WL63 of FIG. 4). The memory cells are configured to hold a threshold voltage Vt or Vth corresponding to one of a plurality of memory or data states (e.g., FIGS. 5 and 6). For the plurality of data states, including the highest data state (e.g., data state G in FIGS. 5 and 6), the threshold voltage of the memory cell associated with the highest data state is higher than those of the other data states (e.g., the erased state and data states A-F in FIGS. 5 and 6). The method includes applying, during each of a plurality of program loops of a program operation, to a selected word line of a plurality of word lines, a series of programming pulses of a program voltage followed by a verify pulse of a plurality of program verify voltages each associated with one of a plurality of data states, to program and verify memory cells connected to the selected word line. The method also includes, during at least one of the plurality of program loops, skipping verify of memory cells targeted for the highest data state.

[0129] Again, program verification of the highest data state (e.g., data state G) may be skipped entirely, and data latches may be used to track loop counts for option 1. As described above, memory cells may be disposed in memory holes (e.g., NAND strings in FIG. 4 ), each coupled to one of a plurality of bit lines (e.g., bit lines BL0-BL13 in FIG. 4 ). In addition, the memory device may further include a plurality of data latches (e.g., data latches 394, 395, 396, 397 in FIG. 3 ), each configured to store data to be programmed during a program operation and control one of the plurality of bit lines to enable or disable programming of memory cells in the memory holes coupled to the one of the plurality of bit lines. Each of the plurality of data latches stores one bit to define a bit combination. Thus, the method may further include operating and updating the plurality of data latches based on the data being programmed into the memory cell, the threshold voltage of the memory cell, and which of the plurality of data states is being programmed and verified during the program operation. The method may also include updating a plurality of data latches to track an amount of subsequent program loops of the plurality of program loops for each of the memory cells targeted to be programmed to the highest data state using one or more of the bit combinations.

[0130] For example, referring again to FIG. 16 , the plurality of data states may include, in order of increasing threshold voltage magnitude, an erased data state (Er), a first data state (A), a second data state (B), a third data state (C), a fourth data state (D), a fifth data state (E), a sixth data state (F), and a seventh data state (G). Thus, the highest data state is the seventh data state. According to another aspect, the plurality of data latches include a first data latch (ADL), a second data latch (BDL), and a third data latch (CDL), each configured to store data to be programmed during a program operation. The plurality of data latches may also include a fourth data latch (DDL) configured to control one of the plurality of bit lines to enable or disable programming of a memory cell of a memory hole coupled to one of the plurality of bit lines. The bit combinations include 16 bit combinations.

[0131] 17A and 17B, when four data latches are used, there are two unused bit or code combinations. Thus, the method may further include updating at least one of the first data latch ADL, second data latch BDL, third data latch CDL, and fourth data latch DDL associated with each memory cell of the memory cells targeted for the seventh data state to a first unused bit combination of the 16 bit combinations in response to one of the memory cells having a threshold voltage sensed during one of the verify pulses of one of the program verify voltages associated with the sixth data state that is greater than one of the plurality of program verify voltages associated with the sixth data state. Additionally, the method may include updating at least one of the first data latch ADL, the second data latch BDL, the third data latch CDL, and the fourth data latch DDL associated with one of the memory cells targeted for the seventh data state from a first unused bit combination of the 16 bit combinations to a second unused bit combination of the 16 bit combinations following application of a first subsequent programming pulse of the series of programming pulses of the program voltage to one of the memory cells targeted for the seventh data state. Additionally, the method may also include updating at least one of the first data latch ADL, the second data latch BDL, the third data latch CDL, and the fourth data latch DDL associated with one of the memory cells targeted for the seventh data state from the second unused bit combination of the 16 bit combinations to one of the 16 bit combinations associated with an erased data state following application of a second subsequent programming pulse of the series of programming pulses of the program voltage to one of the memory cells targeted for the seventh data state.

[0132] Again, instead of completely skipping program verification of the highest data state (e.g., the G state), the memory device may skip only program verification of the highest data state after completing the next-highest data state (e.g., the F state) for option 2. Thus, for example, referring again to FIG. 16 , the multiple data states may include, in order of increasing threshold voltage magnitude, an erased data state (Er), the next-highest data state (F), and the highest data state (G). Accordingly, the method may further include programming and verifying memory cells of the memory cells using a series of programming pulses at a program voltage followed by verify pulses at a number of program verify voltages associated with the series of programming pulses before the next-highest data state completes verification, and locking out memory cells having a threshold voltage greater than one of the multiple verify voltages of one of the multiple data states targeted from further programming. Additionally, after the next-highest data state completes verification, further verification of memory cells of the memory cells targeted for the highest data state is stopped, and subsequent program loops of the multiple program loops are counted. The method may also include inhibiting programming of memory cells among the memory cells targeted for the highest data state in response to an amount of a subsequent program loop among the plurality of program loops exceeding a predetermined slow cell count threshold.

[0133] 16, the plurality of data states, in order of increasing threshold voltage magnitude, include an erased data state (Er), a first data state (A), a second data state (B), a third data state (C), a fourth data state (D), a fifth data state (E), a sixth data state (F), and a seventh data state (G). Thus, the next highest data state is the sixth data state (F), and the highest data state is the seventh data state (G). Thus, the method may further include programming and verifying memory cells targeted for the first, second, third, fourth, fifth, sixth, and seventh data states using a series of programming pulses at the program voltages followed by a verify pulse at a plurality of program verify voltages associated with the series of programming pulses before the sixth data state completes verification, and locking out memory cells having a threshold voltage greater than one of the verify voltages of one of the plurality of data states from further programming in response to the memory cells targeted for the sixth and seventh data states not having a threshold voltage greater than one of the verify voltages associated with the sixth data state. The method may additionally include stopping further verification of the memory cells targeted for the seventh data state after the next-highest data state completes verification in response to the memory cells targeted for the sixth and seventh data states having a threshold voltage greater than one of the verify voltages associated with the sixth data state, and counting subsequent program loops of the plurality of program loops. The method may also include inhibiting programming of memory cells among the memory cells targeted for the seventh data state in response to an amount of a subsequent program loop among the plurality of program loops exceeding a predetermined slow cell count threshold.

[0134] Again, according to another aspect, the memory device may skip only the program verification of the highest data state (e.g., the G state) after the next highest data state (e.g., the F state) is completed, similar to option 2, but using data latches to track the program loop count instead of a counter for option 3. For option 3, the method may include programming and verifying memory cells of the memory cells using a series of programming pulses at a program voltage and verify pulses at a plurality of program verify voltages associated with the series of programming pulses before the next highest data state completes verification, and locking out memory cells having a threshold voltage greater than one of the plurality of verify voltages of one of the plurality of targeted data states from further programming. The method may also include stopping further verification of memory cells of the memory cells targeted for the highest data state after the next highest data state completes verification, and updating the plurality of data latches to track the amount of subsequent program loops of the plurality of program loops for each of the memory cells targeted to be programmed to the highest data state using one or more of the bit combinations.

[0135] For option 3, the method may further include updating at least one of the first data latch ADL, the second data latch BDL, the third data latch CDL, and the fourth data latch DDL associated with each memory cell of the memory cells targeted for the seventh data state to a first unused bit combination of the 16 bit combinations in response to one of the memory cells having a threshold voltage greater than one of the plurality of program verify voltages associated with the sixth data state sensed during one of the verify pulses of one of the plurality of program verify voltages associated with the sixth data state before the sixth data state completes verification. The method may additionally include, before the sixth data state has completed verifying, updating at least one of the first data latch ADL, the second data latch BDL, the third data latch CDL, and the fourth data latch DDL associated with one of the memory cells targeted for the seventh data state to one of 16 bit combinations associated with an erased data state in response to one of the memory cells having a threshold voltage greater than one of the plurality of program verify voltages associated with the seventh data state sensed during one of the verify pulses of one of the plurality of program verify voltages associated with the seventh data state, so as to inhibit programming of one of the memory cells targeted for the seventh data state. Further, the method may include, before the sixth data state completes verification, updating at least one of the first data latch ADL, the second data latch BDL, the third data latch CDL, and the fourth data latch DDL associated with one of the memory cells targeted for the seventh data state from a first unused bit combination of the 16 bit combinations to a second unused bit combination of the 16 bit combinations following application of one of the series of programming pulses of the program voltage to one of the memory cells targeted for the seventh data state.The method may also include, after the sixth data state has completed verifying, updating at least one of the first data latch ADL, the second data latch BDL, the third data latch CDL, and the fourth data latch DDL associated with one of the memory cells targeted for the seventh data state from the second unused bit combination of the 16 bit combinations and from the first unused bit combination of the 16 bit combinations to one of the 16 bit combinations associated with the erased data state, so as to inhibit programming of one of the memory cells targeted for the seventh data state in response to one of the memory cells targeted for the seventh data state having a threshold voltage greater than one of the plurality of verify voltages associated with the sixth data state and less than one of the plurality of verify voltages associated with the seventh data state following application of a first subsequent programming pulse of the series of programming pulses of the program voltage to one of the memory cells targeted for the seventh data state. Additionally, the method may include, after the sixth data state completes verification, updating at least one of the first data latch ADL, the second data latch BDL, the third data latch CDL, and the fourth data latch DDL associated with one of the memory cells targeted for the seventh data state from the first unused bit combination of the 16 bit combinations to a second unused bit combination of the 16 bit combinations in response to one of the memory cells targeted for the seventh data state having a threshold voltage greater than one of the plurality of verify voltages associated with the sixth data state and less than one of the plurality of verify voltages associated with the seventh data state following application of a second subsequent programming pulse of the series of programming pulses of the program voltage to one of the memory cells targeted for the seventh data state.

[0136] It will be apparent that changes may be made to what has been described and illustrated herein, but without departing from the scope defined in the appended claims. The foregoing description of embodiments has been provided for purposes of illustration and description. The foregoing description is not intended to be exhaustive or to limit the present disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but may, where applicable, be interchangeable and used in selected embodiments even if not specifically shown or described. The same may also be varied in many ways. Such variations are not to be considered a departure from the present disclosure, and all such modifications are intended to be included within the scope of the present disclosure.

[0137] Various terms are used to refer to particular system components. Different companies may refer to components by different names, and this document does not intend to distinguish between components that differ in name but not function. In the following description and claims, the terms "including" and "comprising" are used in an open-ended manner and, therefore, should be interpreted to mean "including, but not limited to." Also, the terms "couple" or "couples" are intended to mean either an indirect or direct connection. Thus, when a first device couples to a second device, the connection may be by a direct connection or by an indirect connection via other devices and connections.

[0138] Additionally, when a layer or element is referred to as being "on" another layer or substrate, it can be directly on top of the other layer of the substrate, or there can be intervening layers. Furthermore, when a layer is referred to as being "under" another layer, it will be understood that it can be directly under, or there can be one or more intervening layers. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers.

[0139] As described herein, a controller may include discrete circuit components, an application-specific integrated circuit (ASIC), a microcontroller with control software, a digital signal processor (DSP), a processor with control software, a field programmable gate array (FPGA), or a combination thereof.

Claims

1. memory cells, each connected to one of a plurality of word lines and configured to hold a threshold voltage corresponding to one of a plurality of data states, the plurality of data states including a highest data state, wherein the threshold voltage of the memory cell associated with the highest data state is higher than that of other data states of the plurality of data states; and a control means, wherein the control means during each of a plurality of program loops of a program operation, applying a series of programming pulses of a program voltage followed by a series of verify pulses of a plurality of program verify voltages, each associated with one of the plurality of data states, to a selected word line of the plurality of word lines to program and verify the memory cells connected to the word line; The memory device is configured to skip verifying the memory cells subject to the highest data state in at least one of the plurality of program loops.

2. The memory cells are disposed in memory holes each coupled to one of a plurality of bit lines, and the memory device further includes a plurality of data latches each configured to store data to be programmed during the program operation and to control one of the plurality of bit lines to enable or disable programming of the memory cells in the memory holes coupled to the one of the plurality of bit lines, wherein each of the plurality of data latches stores one bit to define a bit combination, and the control means operating and updating the plurality of data latches based on the data being programmed into the memory cells, the threshold voltages of the memory cells, and which of the plurality of data states are being programmed and verified during the programming operation; 2. The memory device of claim 1, further configured to: update the plurality of data latches to track an amount of subsequent program loops of the plurality of program loops for each of the memory cells targeted to be programmed to the highest data state using one or more of the bit combinations.

3. each of the memory cells is configured to store three bits, the plurality of data states including, in order of increasing magnitude of the threshold voltage, an erased data state, a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state, the highest data state being the seventh data state; the plurality of data latches including a first data latch, a second data latch, and a third data latch each configured to store the data to be programmed during the program operation; the plurality of data latches including a fourth data latch configured to control one of the plurality of bit lines to enable or disable programming of the memory cell of the memory hole coupled to the one of the plurality of bit lines; the bit combinations including 16 bit combinations; and the control means updating at least one of the first data latch, the second data latch, the third data latch, and the fourth data latch associated with each memory cell of the memory cells targeted for the seventh data state to a first unused bit combination of the 16 bit combinations in response to the one of the memory cells having the threshold voltage sensed during one of the verify pulses for the one of the plurality of program verify voltages associated with the sixth data state greater than the one of the plurality of program verify voltages associated with the sixth data state; updating at least one of the first data latch, the second data latch, the third data latch, and the fourth data latch associated with the one of the memory cells targeted for the seventh data state from the first unused bit combination of the 16 bit combinations to a second unused bit combination of the 16 bit combinations following application of a first subsequent programming pulse of the series of programming pulses of the program voltage to the one of the memory cells targeted for the seventh data state; 3. The memory device of claim 2, further configured: updating at least one of the first data latch, the second data latch, the third data latch, and the fourth data latch associated with the one of the memory cells targeted for the seventh data state from the second unused bit combination of the 16 bit combinations to one of the 16 bit combinations associated with the erased data state to inhibit programming of the one of the memory cells targeted for the seventh data state following application of a second subsequent programming pulse of the series of programming pulses of the program voltage to the one of the memory cells targeted for the seventh data state.

4. the plurality of data states including, in order of increasing magnitude of the threshold voltage, an erased data state, a next highest data state, and the highest data state, and the control means programming and verifying memory cells of the memory cells using the series of programming pulses at the program voltage and the verify pulses at the plurality of program verify voltages associated with the series of programming pulses before the next highest data state has completed verifying, and locking out memory cells having the threshold voltage greater than one of the plurality of verify voltages of the one of the plurality of data states of interest from further programming; stopping further verification of the memory cells of the memory cells subject to the next highest data state after the next highest data state has completed verification, and counting subsequent program loops of the plurality of program loops; 2. The memory device of claim 1, further configured to inhibit programming of the memory cells among the memory cells targeted for the highest data state in response to an amount of the subsequent program loop among the plurality of program loops exceeding a predetermined slow cell count threshold.

5. each of the memory cells is configured to store three bits, the plurality of data states including, in order of increasing magnitude of the threshold voltage, the erased data state, a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state, the next highest data state being the sixth data state and the highest data state being the seventh data state; and the control means: programming and verifying memory cells of the memory cells targeted for the first data state, the second data state, the third data state, the fourth data state, the fifth data state, the sixth data state, and the seventh data state using the series of programming pulses of the program voltage and the series of programming pulses followed by the verify pulses of the plurality of program verify voltages associated with the series of programming pulses before the sixth data state has completed verifying; and locking out the memory cells having the threshold voltage greater than one of the plurality of verify voltages of the one of the plurality of data states from further programming in response to the memory cells of the memory cells targeted for the sixth data state and the seventh data state not having the threshold voltage greater than one of the plurality of verify voltages associated with the sixth data state; and after the next highest data state has completed verification, in response to the memory cell of the memory cells targeted for the sixth data state and the seventh data state having the threshold voltage greater than the one of the plurality of verify voltages associated with the sixth data state, stopping further verification of the memory cell of the memory cells targeted for the seventh data state and counting a subsequent program loop of the plurality of program loops; 5. The memory device of claim 4, further configured to inhibit programming of the memory cells of the memory cells targeted for the seventh state in response to an amount of the subsequent program loop of the plurality of program loops exceeding the predetermined slow cell count threshold.

6. The memory cells are disposed in memory holes each coupled to one of a plurality of bit lines, the memory device further comprising a plurality of data latches configured to store data to be programmed during the program operation and each control one of the plurality of bit lines to enable or disable programming of the memory cells of the memory holes coupled to the one of the plurality of bit lines, the plurality of data latches each storing one bit to define a bit combination, the plurality of data states including, in order of increasing magnitude of the threshold voltage, an erased data state, a next highest data state, and the highest data state, and the control means programming and verifying memory cells of the memory cells using the series of programming pulses at the program voltage and the verify pulses at the plurality of program verify voltages associated with the series of programming pulses before the next highest data state has completed verifying, and locking out memory cells having the threshold voltage greater than one of the plurality of verify voltages of the one of the plurality of data states of interest from further programming; 2. The memory device of claim 1, further configured to: stop further verification of the memory cells among the memory cells targeted for the next highest data state after the next highest data state completes verification; and update the plurality of data latches to track an amount of subsequent program loops among the plurality of program loops for each of the memory cells targeted to be programmed to the highest data state using one or more of the bit combinations.

7. each of the memory cells is configured to store three bits, the plurality of data states including, in order of increasing magnitude of the threshold voltage, an erased data state, a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state, the highest data state being the seventh data state; the plurality of data latches including a first data latch, a second data latch, and a third data latch each configured to store the data to be programmed during the program operation; the plurality of data latches including a fourth data latch configured to control one of the plurality of bit lines to enable or disable programming of the memory cell of the memory hole coupled to the one of the plurality of bit lines; the bit combinations including 16 bit combinations; and the control means updating at least one of the first data latch, the second data latch, the third data latch, and the fourth data latch associated with each memory cell targeted for the seventh data state to a first unused bit combination of the 16 bit combinations in response to the one of the memory cells having the threshold voltage sensed during one of the verify pulses for the one of the plurality of program verify voltages associated with the sixth data state greater than the one of the plurality of program verify voltages associated with the sixth data state before the sixth data state completes verification; before the sixth data state completes verification, updating at least one of the first data latch, the second data latch, the third data latch, and the fourth data latch associated with the one of the memory cells targeted for the seventh data state to one of the 16 bit combinations associated with the erased data state to inhibit programming of the one of the memory cells targeted for the seventh data state in response to the one of the memory cells having the threshold voltage sensed during one of the verify pulses of the one of the plurality of program verify voltages associated with the seventh data state greater than the one of the plurality of program verify voltages associated with the seventh data state; before the sixth data state completes verification, updating at least one of the first data latch, the second data latch, the third data latch, and the fourth data latch associated with the one of the memory cells targeted for the seventh data state from the first unused bit combination of the 16 bit combinations to a second unused bit combination of the 16 bit combinations following application of one of the series of programming pulses of the program voltage to the one of the memory cells targeted for the seventh data state; after the sixth data state completes verification, updating at least one of the first data latch, the second data latch, the third data latch, and the fourth data latch from the second unused bit combination of the 16 bit combinations and the first unused bit combination of the 16 bit combinations associated with the one of the memory cells targeted for the seventh data state to one of the 16 bit combinations associated with the erased data state, so as to inhibit programming of the one of the memory cells targeted for the seventh data state in response to the one of the memory cells targeted for the seventh data state having the threshold voltage greater than the one of the plurality of verify voltages associated with the sixth data state and less than the one of the plurality of verify voltages associated with the seventh data state following application of a first subsequent programming pulse of the series of programming pulses of the program voltage to the one of the memory cells targeted for the seventh data state; 7. The memory device of claim 6, further configured: after a sixth data state completes verification, update at least one of the first data latch, the second data latch, the third data latch, and the fourth data latch associated with the one of the memory cells targeted for the seventh data state from the first unused bit combination of the 16 bit combinations to a second unused bit combination of the 16 bit combinations in response to the one of the memory cells targeted for the seventh data state having the threshold voltage greater than the one of the plurality of verify voltages associated with the sixth data state and less than the one of the plurality of verify voltages associated with the seventh data state following application of a second subsequent programming pulse of the series of programming pulses of the program voltage to the one of the memory cells targeted for the seventh data state.

8. 1. A controller in communication with a memory device including memory cells, each connected to one of a plurality of word lines and configured to hold a threshold voltage corresponding to one of a plurality of data states, the plurality of data states including a highest data state, wherein the threshold voltage of the memory cell associated with the highest data state is higher than that of other data states of the plurality of data states, the controller comprising: instructing the memory device to apply, during each of a plurality of program loops of a program operation, to a selected word line of the plurality of word lines, a series of programming pulses of a program voltage followed by a verify pulse of a plurality of program verify voltages each associated with one of the plurality of data states, to program and verify the memory cells connected to the word line; The controller is configured to instruct the memory device to skip verifying the memory cells subject to the highest data state in at least one of the plurality of program loops.

9. The memory cells are disposed in memory holes each coupled to one of a plurality of bit lines, the memory device further comprising a plurality of data latches each configured to store data to be programmed during the program operation and to control one of the plurality of bit lines to enable or disable programming of the memory cells in the memory holes coupled to the one of the plurality of bit lines, the plurality of data latches each storing one bit to define a bit combination, and the controller: instructing the memory device to operate and update the plurality of data latches based on the data being programmed into the memory cells, the threshold voltages of the memory cells, and which of the plurality of data states are being programmed and verified during the program operation; 9. The controller of claim 8, further configured to instruct the memory device to update the plurality of data latches to track an amount of subsequent program loops of the plurality of program loops for each of the memory cells targeted to be programmed to the highest data state using one or more of the bit combinations.

10. each of the memory cells is configured to store three bits, the plurality of data states including, in order of increasing magnitude of the threshold voltage, an erased data state, a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state, the highest data state being the seventh data state; the plurality of data latches including a first data latch, a second data latch, and a third data latch each configured to store the data to be programmed during the program operation; the plurality of data latches including a fourth data latch configured to control the one of the plurality of bit lines to enable or disable programming of the memory cell of the memory hole coupled to the one of the plurality of bit lines; the bit combinations including 16 bit combinations; and the controller: instructing the memory device to update at least one of the first data latch, the second data latch, the third data latch, and the fourth data latch associated with each memory cell of the memory cells targeted for the seventh data state to a first unused bit combination of the 16 bit combinations in response to the one of the memory cells having the threshold voltage sensed during one of the verify pulses for the one of the plurality of program verify voltages associated with the sixth data state greater than the one of the plurality of program verify voltages associated with the sixth data state; instructing the memory device to update at least one of the first data latch, the second data latch, the third data latch, and the fourth data latch associated with the one of the memory cells targeted for the seventh data state from the first unused bit combination of the 16 bit combinations to a second unused bit combination of the 16 bit combinations following application of a first subsequent programming pulse of the series of programming pulses of the program voltage to the one of the memory cells targeted for the seventh data state; 10. The controller of claim 9, further configured to instruct the memory device to update at least one of the first data latch, the second data latch, the third data latch, and the fourth data latch associated with the one of the memory cells targeted for the seventh data state from the second unused bit combination of the 16 bit combinations to one of the 16 bit combinations associated with the erased data state to inhibit programming of the one of the memory cells targeted for the seventh data state following application of a second subsequent programming pulse of the series of programming pulses of the program voltage to the one of the memory cells targeted for the seventh data state.

11. the plurality of data states including, in order of increasing magnitude of the threshold voltage, an erased data state, a next highest data state, and the highest data state, and the controller instructing the memory device to program and verify memory cells of the memory cells using the series of programming pulses at the program voltage and the verify pulses at the plurality of program verify voltages associated with the series of programming pulses before the next highest data state has completed verifying, and to lock out from further programming the memory cells having the threshold voltage greater than one of the plurality of verify voltages of the one of the plurality of data states of interest; instructing the memory device to stop further verification of the memory cells among the memory cells subject to the next highest data state after the next highest data state has completed verification and to count a subsequent program loop among the plurality of program loops; 10. The controller of claim 8, further configured to inhibit programming of the memory cells among the memory cells targeted for the highest data state in response to an amount of the subsequent program loop among the plurality of program loops exceeding a predetermined slow cell count threshold.

12. each of the memory cells is configured to store three bits, the plurality of data states including, in order of increasing magnitude of the threshold voltage, the erased data state, a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state, the next highest data state being the sixth data state and the highest data state being the seventh data state, and the controller instructing the memory device to program and verify memory cells of the memory cells targeted for the first data state, the second data state, the third data state, the fourth data state, the fifth data state, the sixth data state, and the seventh data state using the series of programming pulses of the program voltage and the series of programming pulses followed by the verify pulses of the plurality of program verify voltages associated with the series of programming pulses before the sixth data state has completed verifying, and to lock out the memory cells having the threshold voltage greater than one of the plurality of verify voltages of the one of the plurality of data states from further programming in response to the memory cells of the memory cells targeted for the sixth data state and the seventh data state not having the threshold voltage greater than one of the plurality of verify voltages associated with the sixth data state; instructing the memory device to stop further verifying of the memory cells targeted for the seventh data state and to count a subsequent program loop of the plurality of program loops in response to the memory cells targeted for the sixth data state and the seventh data state having the threshold voltage greater than the one of the plurality of verify voltages associated with the sixth data state after the next highest data state has completed verifying; 12. The controller of claim 11, further configured to instruct the memory device to inhibit programming of the memory cells of the memory cells subject to the seventh state in response to an amount of the subsequent program loop of the plurality of program loops exceeding the predetermined slow cell count threshold.

13. The memory cells are disposed in memory holes each coupled to one of a plurality of bit lines, the memory device further comprising a plurality of data latches configured to store data to be programmed during the program operation and each control one of the plurality of bit lines to enable or disable programming of the memory cells of the memory holes coupled to the one of the plurality of bit lines, the plurality of data latches each storing one bit to define a bit combination, the plurality of data states including, in order of increasing magnitude of the threshold voltage, an erased data state, a next highest data state, and the highest data state, and the controller instructing the memory device to program and verify memory cells of the memory cells using the series of programming pulses at the program voltage and the verify pulses at the plurality of program verify voltages associated with the series of programming pulses before the next highest data state has completed verifying, and to lock out from further programming the memory cells having the threshold voltage greater than one of the plurality of verify voltages of the one of the plurality of data states of interest; 9. The controller of claim 8, further configured to instruct the memory device to stop further verification of the memory cells among the memory cells targeted for the next highest data state after the next highest data state has completed verification, and to update the plurality of data latches to track an amount of subsequent program loops among the plurality of program loops for each of the memory cells targeted to be programmed to the highest data state using one or more of the bit combinations.

14. 1. A method of operating a memory device including memory cells each connected to one of a plurality of word lines and configured to hold a threshold voltage corresponding to one of a plurality of data states, the plurality of data states including a highest data state in which the threshold voltage of the memory cell associated with the highest data state is higher than that of other data states of the plurality of data states, the method comprising: applying, during each of a plurality of program loops of a program operation, to a selected word line of the plurality of word lines, each of a series of programming pulses of a program voltage followed by a verify pulse of a plurality of program verify voltages each associated with one of the plurality of data states, to program and verify the memory cells connected to the word line; and skipping verification of the memory cells subject to the highest data state in at least one of the plurality of program loops.

15. the memory cells are disposed in memory holes each coupled to one of a plurality of bit lines, the memory device further comprising a plurality of data latches each configured to store data to be programmed during the program operation and to control one of the plurality of bit lines to enable or disable programming of the memory cells in the memory holes coupled to the one of the plurality of bit lines, the plurality of data latches each storing one bit to define a bit combination, and the method comprising: operating and updating the plurality of data latches based on the data being programmed into the memory cells, the threshold voltages of the memory cells, and which of the plurality of data states are being programmed and verified during the program operation; 15. The method of claim 14, further comprising: updating the plurality of data latches to track an amount of subsequent program loops of the plurality of program loops for each of the memory cells targeted to be programmed to the highest data state using one or more of the bit combinations.

16. each of the memory cells is configured to store three bits, the plurality of data states include, in order of increasing magnitude of the threshold voltage, an erased data state, a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state, the highest data state being the seventh data state; the plurality of data latches include a first data latch, a second data latch, and a third data latch each configured to store the data to be programmed during the program operation; the plurality of data latches include a fourth data latch configured to control the one of the plurality of bit lines to enable or disable programming of the memory cell of the memory hole coupled to the one of the plurality of bit lines; and the bit combinations include 16 bit combinations; and the method comprises: updating at least one of the first data latch, the second data latch, the third data latch, and the fourth data latch associated with each memory cell of the memory cells targeted for the seventh data state to a first unused bit combination of the 16 bit combinations in response to the one of the memory cells having the threshold voltage sensed during one of the verify pulses for the one of the plurality of program verify voltages associated with the sixth data state greater than the one of the plurality of program verify voltages associated with the sixth data state; updating at least one of the first data latch, the second data latch, the third data latch, and the fourth data latch associated with the one of the memory cells targeted for the seventh data state from the first unused bit combination of the 16 bit combinations to a second unused bit combination of the 16 bit combinations following application of a first subsequent programming pulse of the series of programming pulses of the program voltage to the one of the memory cells targeted for the seventh data state; 16. The method of claim 15, further comprising: updating at least one of the first data latch, the second data latch, the third data latch, and the fourth data latch associated with one of the memory cells targeted for the seventh data state from the second unused bit combination of the 16 bit combinations to one of the 16 bit combinations associated with the erased data state to inhibit programming of the one of the memory cells targeted for the seventh data state following application of a second subsequent programming pulse of the series of programming pulses of the program voltage to the one of the memory cells targeted for the seventh data state.

17. the plurality of data states including, in order of increasing magnitude of the threshold voltage, an erased data state, a next highest data state, and the highest data state, the method comprising: programming and verifying memory cells of the memory cells using the series of programming pulses at the program voltage and the verify pulses at the plurality of program verify voltages associated with the series of programming pulses before the next highest data state has completed verifying, and locking out memory cells having the threshold voltage greater than one of the plurality of verify voltages of the one of the plurality of data states of interest from further programming; after the next highest data state has completed verification, stopping further verification of the memory cells among the memory cells subject to the highest data state and counting subsequent program loops among the plurality of program loops; 15. The method of claim 14, further comprising: inhibiting programming of the memory cells among the memory cells targeted for the highest data state in response to an amount of the subsequent program loop among the plurality of program loops exceeding a predetermined slow cell count threshold.

18. each of the memory cells is configured to store three bits, the plurality of data states including, in order of increasing magnitude of the threshold voltage, the erased data state, a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state, the next highest data state being the sixth data state and the highest data state being the seventh data state, and the method comprises: programming and verifying memory cells of the memory cells targeted for the first data state, the second data state, the third data state, the fourth data state, the fifth data state, the sixth data state, and the seventh data state using the series of programming pulses of the program voltage and the series of programming pulses followed by the verify pulses of the plurality of program verify voltages associated with the series of programming pulses, before the sixth data state has completed verifying, and locking out the memory cells having the threshold voltage greater than one of the plurality of verify voltages of the one of the plurality of data states from further programming in response to the memory cells of the memory cells targeted for the sixth data state and the seventh data state not having the threshold voltage greater than one of the plurality of verify voltages associated with the sixth data state; after the next highest data state has completed verifying, in response to the memory cell of the memory cells targeted for the sixth data state and the seventh data state having the threshold voltage greater than the one of the plurality of verify voltages associated with the sixth data state, stopping further verifying of the memory cell of the memory cells targeted for the seventh data state and counting a subsequent program loop of the plurality of program loops; 18. The method of claim 17, further comprising: inhibiting programming of the memory cells of the memory cells targeted for the seventh state in response to an amount of the subsequent program loop of the plurality of program loops exceeding the predetermined slow cell count threshold.

19. the memory cells are disposed in memory holes each coupled to one of a plurality of bit lines, the memory device further comprising a plurality of data latches each configured to store data to be programmed during the program operation and to control one of the plurality of bit lines to enable or disable programming of the memory cells of the memory holes coupled to the one of the plurality of bit lines, the plurality of data latches each storing one bit to define a bit combination, the plurality of data states including, in order of increasing magnitude of the threshold voltage, an erased data state, a next highest data state, and the highest data state, the method comprising: programming and verifying memory cells of the memory cells using the series of programming pulses at the program voltage and the verify pulses at the plurality of program verify voltages associated with the series of programming pulses before the next highest data state has completed verifying, and locking out memory cells having the threshold voltage greater than one of the plurality of verify voltages of the one of the plurality of data states of interest from further programming; 15. The method of claim 14, further comprising: stopping further verification of the memory cells among the memory cells targeted for the highest data state after the next highest data state has completed verification; and updating the plurality of data latches to track an amount of subsequent program loops among the plurality of program loops for each of the memory cells targeted to be programmed to the highest data state using one or more of the bit combinations.

20. each of the memory cells is configured to store three bits, the plurality of data states include, in order of increasing magnitude of the threshold voltage, an erased data state, a first data state, a second data state, a third data state, a fourth data state, a fifth data state, a sixth data state, and a seventh data state, the highest data state being the seventh data state; the plurality of data latches include a first data latch, a second data latch, and a third data latch each configured to store the data to be programmed during the program operation; the plurality of data latches include a fourth data latch configured to control the one of the plurality of bit lines to enable or disable programming of the memory cell of the memory hole coupled to the one of the plurality of bit lines; and the bit combinations include 16 bit combinations; and the method comprises: updating at least one of the first data latch, the second data latch, the third data latch, and the fourth data latch associated with each memory cell targeted for the seventh data state to a first unused bit combination of the 16 bit combinations in response to the one of the memory cells having the threshold voltage sensed during one of the verify pulses for the one of the plurality of program verify voltages associated with the sixth data state greater than the one of the plurality of program verify voltages associated with the sixth data state before the sixth data state completes verification; before the sixth data state completes verification, updating at least one of the first data latch, the second data latch, the third data latch, and the fourth data latch associated with the one of the memory cells targeted for the seventh data state to one of the 16 bit combinations associated with the erased data state to inhibit programming of the one of the memory cells targeted for the seventh data state in response to the one of the memory cells having the threshold voltage sensed during one of the verify pulses of the one of the plurality of program verify voltages associated with the seventh data state greater than the one of the plurality of program verify voltages associated with the seventh data state; before the sixth data state completes verification, updating at least one of the first data latch, the second data latch, the third data latch, and the fourth data latch associated with the one of the memory cells targeted for the seventh data state from the first unused bit combination of the 16 bit combinations to a second unused bit combination of the 16 bit combinations following application of one of the series of programming pulses of the program voltage to the one of the memory cells targeted for the seventh data state; after the sixth data state completes verification, updating at least one of the first data latch, the second data latch, the third data latch, and the fourth data latch from the second unused bit combination of the sixteen bit combinations and the first unused bit combination of the sixteen bit combinations associated with the one of the memory cells targeted for the seventh data state to one of the sixteen bit combinations associated with the erased data state, so as to inhibit programming of the one of the memory cells targeted for the seventh data state in response to the one of the memory cells targeted for the seventh data state having the threshold voltage greater than the one of the plurality of verify voltages associated with the sixth data state and less than the one of the plurality of verify voltages associated with the seventh data state following application of a first subsequent programming pulse of the series of programming pulses of the program voltage to the one of the memory cells targeted for the seventh data state; 20. The method of claim 19, further comprising: after a sixth data state completes verification, updating at least one of the first data latch, the second data latch, the third data latch, and the fourth data latch associated with the one of the memory cells targeted for the seventh data state from a first unused bit combination of the 16 bit combinations to a second unused bit combination of the 16 bit combinations in response to the one of the memory cells targeted for the seventh data state having the threshold voltage greater than the one of the plurality of verify voltages associated with the sixth data state and less than the one of the plurality of verify voltages associated with the seventh data state following application of a second subsequent programming pulse of the series of programming pulses of the program voltage to the one of the memory cells targeted for the seventh data state.

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