Electro-optical device and electronic apparatus

Abstract

In the configuration using the concave ion adsorption portion, suppression of deterioration in display quality due to ionic impurities may be insufficient.SOLUTION: An electro-optical device includes an electro-optical layer having a pixel region, a first electrode disposed outside the pixel region, a second electrode disposed outside the pixel region and to which a potential different from that of the first electrode is applied, and an uneven member disposed between the first electrode and the second electrode in a plan view.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present disclosure relates to an electro-optical device and an electronic device. [Background technology]

[0002] Electro-optical devices using a liquid crystal material as an electro-optical material are known. The electro-optical device described in Patent Document 1 includes a pair of substrates, a sealant for bonding the pair of substrates together, and an electro-optical material. At least one of the pair of substrates has a concave ion-adsorbing portion on a surface that contacts the electro-optical material. The ion-adsorbing portion adsorbs ionic impurities in the electro-optical material. The ion-adsorbing portion suppresses degradation of display quality caused by the ionic impurities. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-252032 Summary of the Invention [Problem to be solved by the invention]

[0004] In a configuration using a concave ion adsorption portion, there are cases where the suppression of the deterioration of display quality caused by ionic impurities is insufficient. [Means for solving the problem]

[0005] The electro-optical device of the present disclosure comprises an electro-optical layer having a pixel region, a first electrode arranged outside the pixel region, a second electrode arranged outside the pixel region and to which a potential different from that of the first electrode is applied, and a concave-convex member arranged between the first electrode and the second electrode in a planar view.

[0006] The electro-optical device of the present disclosure comprises an electro-optical layer having a pixel region, a first electrode arranged outside the pixel region, a second electrode arranged outside the pixel region and to which a potential different from that of the first electrode is applied, and an uneven member covering at least one of the first electrode and the second electrode.

[0007] An electronic device according to the present disclosure includes the electro-optical device described above. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing a schematic configuration of a liquid crystal device. [Figure 2] FIG. 1 is a diagram schematically illustrating a configuration of a liquid crystal device. [Figure 3] FIG. 2 is a diagram showing the electrical configuration of an element substrate. [Figure 4] FIG. 1 is a diagram showing a schematic configuration of a liquid crystal device. [Figure 5] FIG. 1 is a diagram showing an example of a schematic configuration of a liquid crystal device. [Figure 6] FIG. 1 is a diagram showing an example of a schematic configuration of a liquid crystal device. [Figure 7] FIG. 1 is a diagram showing an example of a schematic configuration of a liquid crystal device. [Figure 8] FIG. 1 is a diagram showing an example of a schematic configuration of a liquid crystal device. [Figure 9] FIG. 1 is a diagram showing an example of a schematic configuration of a liquid crystal device. [Figure 10] 5A to 5C are diagrams showing a manufacturing process of an element substrate of a liquid crystal device. [Figure 11] 5A to 5C are diagrams showing a manufacturing process of an element substrate of a liquid crystal device. [Figure 12] 5A to 5C are diagrams showing a manufacturing process of an element substrate of a liquid crystal device. [Figure 13] 5A to 5C are diagrams showing a manufacturing process of an element substrate of a liquid crystal device. [Figure 14] 5A to 5C are diagrams showing a manufacturing process of an element substrate of a liquid crystal device. [Figure 15] 5A to 5C are diagrams showing a manufacturing process of an element substrate of a liquid crystal device. [Figure 16] 5A to 5C are diagrams showing a manufacturing process of an element substrate of a liquid crystal device. [Figure 17] 5A to 5C are diagrams showing a manufacturing process of an element substrate of a liquid crystal device. [Figure 18] FIG. 1 is a diagram showing an example of a schematic configuration of a liquid crystal device. [Figure 19] FIG. 1 is a diagram showing an example of a schematic configuration of a liquid crystal device. [Figure 20] FIG. 1 is a diagram showing a schematic configuration of a projection display device. DETAILED DESCRIPTION OF THE INVENTION

[0009] FIG. 1 shows a schematic configuration of a liquid crystal device 100. The liquid crystal device 100 corresponds to an example of an electro-optical device. As an example, the liquid crystal device 100 is configured with an active matrix drive type TFT (Thin Film Transistor) liquid crystal. FIG. 1 shows the liquid crystal device 100 in a plan view from the +Z direction. The liquid crystal device 100 includes an element substrate 10, a counter substrate 20, a liquid crystal layer 50 (described later), and a sealing material 60. The liquid crystal device 100 has a display region E.

[0010] In some figures, including Figure 1, the dimensions of each component may be drawn differently from their actual dimensions to make each component easier to understand. The dimensional ratios of each component in the drawings may differ from those of the actual components.

[0011] Several figures, including FIG. 1, illustrate an XYZ coordinate system. The X-axis, Y-axis, and Z-axis are mutually orthogonal. The Z-axis is an axis parallel to the stacking direction of the element substrate 10, the liquid crystal layer 50, and the counter substrate 20. The +Z direction is the direction from the element substrate 10 toward the counter substrate 20. The -Z direction is the direction from the counter substrate 20 toward the element substrate 10. The X-axis is an axis parallel to the arrangement direction of the external connection terminals 104 (described later). The +X direction is the direction from left to right in FIG. 1. The -X direction is the direction from right to left in FIG. 1. The Y-axis is an axis perpendicular to the X-axis and Z-axis. The +Y direction is the direction from bottom to top in FIG. 1. The -Y direction is the direction from top to bottom in FIG. 1.

[0012] The element substrate 10 is disposed on the light-emitting side of the liquid crystal layer 50. The element substrate 10 is made of a light-transmitting material. Light-transmitting means that the substrate is transparent to visible light. Light-transmitting preferably means that the transmittance of visible light is 50% or more. The element substrate 10 is configured to be approximately rectangular in plan view from the +Z direction. The element substrate 10 is bonded to the counter substrate 20 via a sealant 60. The element substrate 10 is configured to be larger than the counter substrate 20 in plan view from the +Z direction. The element substrate 10 has a data line driving circuit 101, a scanning line driving circuit, an inspection circuit, and a plurality of external connection terminals 104. The scanning line driving circuit and the inspection circuit are not shown.

[0013] The data line driving circuit 101 is electrically connected to a plurality of data lines 6, which will be described later. The data line driving circuit 101 supplies an image signal to each of the plurality of data lines 6. The data line driving circuit 101 is provided between a plurality of external connection terminals 104 and the sealing material 60 in a plan view from the +Z direction.

[0014] The scanning line driving circuit is electrically connected to the plurality of scanning lines 3, which will be described later. The scanning line driving circuit supplies a scanning signal to each of the plurality of scanning lines 3.

[0015] The test circuit is electrically connected to the plurality of data lines 6. The test circuit supplies a test signal to each of the plurality of data lines 6.

[0016] The external connection terminals 104 are mounting terminals on which external connection lines such as flexible printed circuits (FPCs) (not shown) are mounted. Various signals such as image signals, synchronization signals, inspection signals, common potentials, and power supply potentials are supplied from the outside via the external connection lines to the external connection terminals 104. The external connection terminals 104 are provided in an area of ​​the element substrate 10 that does not overlap with the counter substrate 20.

[0017] The counter substrate 20 is disposed on the light incident side of the liquid crystal layer 50. The counter substrate 20 is configured to have a substantially rectangular shape when viewed in a plan view from the +Z direction. The counter substrate 20 is configured from a light-transmitting material. The counter substrate 20 is bonded to the element substrate 10 via a sealing material 60. The counter substrate 20 is provided with a plurality of vertical conductive portions 106.

[0018] The plurality of vertical conductive portions 106 are provided at the corners of the counter substrate 20. The liquid crystal device 100 shown in Fig. 1 has four vertical conductive portions 106. The vertical conductive portions 106 electrically connect a common electrode 21 (described later) to any of the plurality of external connection terminals 104.

[0019] The sealant 60 bonds the element substrate 10 and the counter substrate 20. The sealant 60 is disposed along the outer edge of the counter substrate 20. The sealant 60 is made of a resin material having a curing property such as thermosetting or ultraviolet curing. The resin material contains ionic impurities Im derived from raw materials such as a curing agent. The ionic impurities Im may dissolve into the liquid crystal layer 50. The sealant 60 may also contain a gap material made of an inorganic material such as glass.

[0020] The display area E is provided in an area inside the sealing material 60. The display area E is a pixel area including a plurality of pixels P. The plurality of pixels P are arranged in a matrix along the X axis and the Y axis. Dummy pixels that do not contribute to display may be arranged on the outer periphery of the cover area E or outside the display area E.

[0021] A parting portion 24 is provided between the sealing material 60 and the display region E. The parting portion 24 surrounds the outside of the display region E. The parting portion 24 is configured in a substantially rectangular shape with sides along the X-axis and Y-axis. The scanning line driving circuit and the inspection circuit are disposed at positions overlapping the parting portion 24 in a plan view from the +Z direction.

[0022] Fig. 2 schematically illustrates the configuration of the liquid crystal device 100. Fig. 2 illustrates a cross section along the YZ plane, including the line segment HH in Fig. 1. Fig. 2 illustrates the size and number of liquid crystals 50a included in the liquid crystal layer 50 in a manner different from the actual size and number.

[0023] The liquid crystal device 100 shown in FIG. 2 is a transmissive liquid crystal device. Incident light L is incident on the +Z direction surface of the counter substrate 20. The incident light L passes through the liquid crystal layer 50 and exits from the -Z direction surface of the element substrate 10. When passing through the liquid crystal layer 50, the incident light L is modulated according to the alignment state of the liquid crystals 50a. The incident surface of the incident light L is not limited to the +Z direction surface of the counter substrate 20. The incident surface of the incident light L may also be the -Z direction surface of the element substrate 10. The liquid crystal device 100 is not limited to a transmissive liquid crystal device. The liquid crystal device 100 may be a reflective liquid crystal device. The liquid crystal device 100 employs an optical design for a normally white mode or a normally black mode. The liquid crystal device 100 may include a polarizing element.

[0024] The element substrate 10 and the counter substrate 20 are disposed opposite each other with a sealant 60 interposed therebetween. The liquid crystal layer 50 is disposed between the element substrate 10 and the counter substrate 20. The liquid crystal layer 50 is disposed at a position surrounded by the element substrate 10, the counter substrate 20, and the sealant 60.

[0025] The liquid crystal layer 50 has a display region E. The liquid crystal layer 50 corresponds to an example of an electro-optical layer. The liquid crystal layer 50 includes liquid crystals 50a. The liquid crystals 50a have positive or negative dielectric anisotropy. The liquid crystals 50a shown in FIG. 2 have negative dielectric anisotropy, for example. The liquid crystals 50a represent individual liquid crystal molecules or an aggregate of individual liquid crystal molecules.

[0026] The element substrate 10 has an element substrate base 10s, a wiring layer (not shown), pixel electrodes 15, and a first alignment film 18. The element substrate base 10s, the wiring layer, the pixel electrodes 15, and the first alignment film 18 are arranged facing the liquid crystal layer 50 in this order: element substrate base 10s, wiring layer, pixel electrodes 15, and first alignment film 18.

[0027] The element substrate base 10s is a flat plate having light-transmitting and insulating properties. The element substrate base 10s is made of a glass substrate or a quartz substrate. The element substrate base 10s is disposed on the exit side of the liquid crystal layer 50, from which light that has passed through the liquid crystal layer 50 is emitted.

[0028] The wiring layer includes transistors 30, scanning lines 3, data lines 6, etc., which will be described later. The wiring layer is made up of a plurality of layers. The wiring layer has the function of blocking light from reaching the transistors 30.

[0029] The pixel electrodes 15 are provided in the display region E. The pixel electrodes 15 are translucent. For example, the pixel electrodes 15 are made of ITO (Indium Tin Oxide). The pixel electrodes 15 may also be made of transparent conductive materials such as IZO (Indium Zinc Oxide) and FTO (Fluorine-doped tin oxide).

[0030] The first alignment film 18 aligns the liquid crystal 50a. The first alignment film 18 is formed based on the optical design of the liquid crystal device 100. The first alignment film 18 is disposed in a position where it contacts the sealant 60. The first alignment film 18 has a region that contacts the -Z direction surface of the sealant 60 and a region that faces the liquid crystal layer 50. The first alignment film 18 is disposed between the multiple pixel electrodes 15 and the liquid crystal layer 50. The first alignment film 18 includes a first evaporated film 18a and a second evaporated film 18b.

[0031] The first deposited film 18a is formed by vacuum deposition from above the +Z direction surface of the element substrate 10. The first deposited film 18a includes a plurality of columns whose major axes are aligned with the Z axis. The first deposited film 18a is made of silicon oxide, aluminum oxide, magnesium oxide, or the like.

[0032] The second deposited film 18b is formed on the first deposited film 18a. The thickness of the second deposited film 18b along the Z axis is thinner than the thickness of the first deposited film 18a along the Z axis. The second deposited film 18b includes multiple columns whose major axes intersect with the Z axis at a predetermined angle. The columns of the second deposited film 18b are columnar crystals of silicon oxide. The columns of the second deposited film 18b are formed by oblique deposition using a vacuum deposition method.

[0033] The counter substrate 20 has a counter substrate base 20s, a parting portion 24, an insulating layer 25, a common electrode 21, and a second alignment film 22. The counter substrate base 20s, the parting portion 24, the insulating layer 25, the common electrode 21, and the second alignment film 22 are arranged in this order facing the liquid crystal layer 50.

[0034] The counter substrate base 20s is a flat plate having light-transmitting and insulating properties. The counter substrate base 20s is disposed on the incident side where the incident light L is incident. The counter substrate base 20s is made of a glass substrate or a quartz substrate. As an example, the counter substrate base 20s is made of silicon oxide (SiO2) with a refractive index of 1.48.

[0035] The parting portion 24 is made of a light-shielding metal film, etc. The parting portion 24 is located at a position further away from the common electrode 21 in the +Z direction.

[0036] The insulating layer 25 has light-transmitting and insulating properties. The insulating layer 25 is made of an inorganic material such as silicon oxide. The insulating layer 25 may function as an optical path adjustment layer that adjusts the optical path of the incident light L.

[0037] The common electrode 21 is disposed opposite the plurality of pixel electrodes 15. The common electrode 21 is formed of ITO. The common electrode 21 may also be formed of a transparent conductive material such as IZO or FTO. The common electrode 21 and the pixel electrodes 15 apply an electric field to the liquid crystal layer 50. The common electrode 21 is electrically connected to one of the plurality of external connection terminals 104 provided on the element substrate 10 via the vertical conductive portion 106. A common electrode potential is applied to the common electrode 21 via the external connection terminal 104. The common electrode potential is, for example, 6.5 V.

[0038] The second alignment film 22 aligns the liquid crystal 50a. The second alignment film 22 is formed based on the optical design of the liquid crystal device 100. The second alignment film 22 is disposed in a position where it contacts the sealant 60. The second alignment film 22 has a region that contacts the surface of the sealant 60 in the +Z direction and a region that faces the liquid crystal layer 50. The second alignment film 22 is disposed between the common electrode 21 and the liquid crystal layer 50. The second alignment film 22 includes a third evaporated film 22a and a fourth evaporated film 22b.

[0039] The third deposited film 22a is formed by vacuum deposition on the −Z direction surface of the opposing substrate 20. The third deposited film 22a includes a plurality of columns whose major axes are aligned with the Z axis. The third deposited film 22a is made of silicon oxide, aluminum oxide, magnesium oxide, or the like.

[0040] The fourth deposited film 22b is formed on the third deposited film 22a. The thickness of the fourth deposited film 22b along the Z axis is thinner than the thickness of the third deposited film 22a along the Z axis. The fourth deposited film 22b includes multiple columns whose major axes intersect with the Z axis at a predetermined angle. The columns of the fourth deposited film 22b are columnar crystals of silicon oxide. The columns of the fourth deposited film 22b are formed by oblique deposition using a vacuum deposition method.

[0041] The first alignment film 18 and the second alignment film 22 align the liquid crystal 50a, which has negative dielectric anisotropy, in a substantially vertical direction. The substantially vertical alignment is an inverted alignment state that is achieved by providing a pretilt angle of less than 90°. The first alignment film 18 and the second alignment film 22 provide a pretilt to align the liquid crystal 50a vertically. The tilt direction of the pretilt is along a direction intersecting the X-axis and Y-axis. When the liquid crystal layer 50 is driven, the alignment state of the liquid crystal 50a, which has been vertically aligned by providing a pretilt, changes in the tilt direction.

[0042] 2 are each made up of two layers, but are not limited to this. The first alignment film 18 and the second alignment film 22 may each be made up of three or more layers.

[0043] FIG. 3 shows the electrical configuration of the element substrate 10. FIG. 3 shows the electrical configuration of the element substrate 10 in the form of an equivalent circuit diagram. A plurality of scanning lines 3, a plurality of data lines 6, a plurality of capacitance lines 8, a plurality of pixel electrodes 15, a plurality of capacitance elements 16, and a plurality of transistors 30 are provided in the display region E of the element substrate 10. The plurality of scanning lines 3, the plurality of data lines 6, and the plurality of capacitance lines 8 are insulated from one another. The pixel electrodes 15, the capacitance elements 16, and the transistors 30 are provided in a region of a pixel P partitioned by the scanning lines 3 and the data lines 6. The pixel electrodes 15, the capacitance elements 16, and the transistors 30 constitute a pixel circuit of the pixel P.

[0044] The scanning lines 3 are electrically connected to the gates of the transistors 30. The scanning lines 3 shown in FIG. 3 extend along the X-axis. The scanning lines 3 simultaneously control the on and off of the transistors 30 arranged in the same row. The scanning lines 3 are electrically connected to a scanning line driving circuit. The scanning lines 3 supply scanning signals supplied from the scanning line driving circuit to the pixels P. The scanning signals are supplied to the scanning lines 3 at predetermined timings.

[0045] The data line 6 is electrically connected to the data line side source-drain region of the transistor 30. The data line 6 shown in FIG. 3 extends along the Y axis. The data line 6 is electrically connected to a data line driving circuit 101. The data line 6 supplies an image signal supplied from the data line driving circuit 101 to the pixel P.

[0046] The capacitance line 8 is electrically connected to the capacitance element 16. The capacitance line 8 shown in FIG. 3 extends along the Y-axis. The capacitance line 8 may extend along the X-axis. A constant potential such as a common electrode potential applied to the common electrode 21 or a ground potential is supplied to the capacitance line 8 via the external connection terminal 104.

[0047] The pixel electrode 15 is electrically connected to the source / drain region on the capacitance line side of the transistor 30. When the transistor 30 is turned on for a certain period by inputting a scanning signal, an image signal is applied to the pixel electrode 15 at a predetermined timing. The image signal is written at a predetermined level into the liquid crystal layer 50 via the pixel electrode 15. The image signal is held for a certain period between the pixel electrode 15 and the common electrode 21 sandwiching the liquid crystal layer 50. The orientation state of the liquid crystal 50a changes depending on the voltage applied in accordance with the image signal.

[0048] The capacitor 16 has two electrodes. One electrode of the capacitor 16 is electrically connected to the capacitor line 8. The other electrode of the capacitor 16 is electrically connected to the pixel electrode 15. The other electrode of the capacitor 16 holds the potential of an image signal or the like supplied to the pixel electrode 15. The capacitor 16 prevents the image signal held in the pixel electrode 15 from leaking.

[0049] The transistors 30 are switching elements provided in the pixel electrodes 15. The transistors 30 are, for example, thin film transistors (TFTs). The transistors 30 are provided at the intersections of the plurality of scanning lines 3 and the plurality of data lines 6.

[0050] Fig. 4 shows a schematic configuration of the liquid crystal device 100. Fig. 4 shows the liquid crystal device 100 in a plan view from the +Z direction. Fig. 4 shows a first peripheral electrode 108 and a second peripheral electrode 109.

[0051] The first peripheral electrode 108 attracts ionic impurities Im. The first peripheral electrode 108 is arranged in a position that surrounds the display region E in a frame shape. The first peripheral electrode 108 is arranged in a direction along the X axis and a direction along the Y axis. The first peripheral electrode 108 is arranged outside the display region E. The first peripheral electrode 108 is arranged inside the sealing material 60. The first peripheral electrode 108 is arranged in a position that does not overlap with the sealing material 60. The first peripheral electrode 108 is arranged in a position that at least partially overlaps with the parting portion 24 in a plan view from the +Z direction. The first peripheral electrode 108 is formed of a transparent conductive film such as ITO or IZO. The first peripheral electrode 108 corresponds to an example of a first electrode.

[0052] The first peripheral electrode 108 is electrically connected to one of the plurality of external connection terminals 104. A DC potential of positive polarity relative to the common electrode potential applied to the common electrode 21 is applied to the first peripheral electrode 108. The DC potential applied to the first peripheral electrode 108 is a constant potential with the common electrode potential as a reference. The DC potential applied to the first peripheral electrode 108 is, for example, +0.5 V or more and +3.0 V or less. The DC potential may be applied to the first peripheral electrode 108 constantly or intermittently while the liquid crystal device 100 is in operation.

[0053] The second peripheral electrode 109 attracts ionic impurities Im. The second peripheral electrode 109 is disposed in a position surrounding the display region E in a frame shape. The second peripheral electrode 109 is disposed in a direction along the X-axis and a direction along the Y-axis. The second peripheral electrode 109 is disposed outside the display region E. The second peripheral electrode 109 is disposed in a position surrounding the first peripheral electrode 108 in a frame shape. The second peripheral electrode 109 is disposed in a position surrounded by the sealing material 60 disposed in a frame shape. The second peripheral electrode 109 is disposed in a position not overlapping with the first peripheral electrode 108 and the sealing material 60. The second peripheral electrode 109 is formed of a transparent conductive film such as ITO or IZO. The second peripheral electrode 109 corresponds to an example of a second electrode.

[0054] The second peripheral electrode 109 is electrically connected to one of the plurality of external connection terminals 104. A DC potential having a negative polarity relative to the common electrode potential applied to the common electrode 21 is applied to the second peripheral electrode 109. The DC potential applied to the second peripheral electrode 109 is a constant potential based on the common electrode potential. For example, the DC potential applied to the second peripheral electrode 109 is −3.0 V or more and −0.5 V or less. The DC potential may be applied to the second peripheral electrode 109 constantly or intermittently while the liquid crystal device 100 is in operation.

[0055] The width along the X-axis of the first peripheral electrode 108 extending along the Y-axis is shorter than the width along the X-axis of the second peripheral electrode 109 extending along the Y-axis. The width along the Y-axis of the first peripheral electrode 108 extending along the X-axis is shorter than the width along the Y-axis of the second peripheral electrode 109 extending along the X-axis. The width of the first peripheral electrode 108 is shorter than the width of the second peripheral electrode 109 over the entire periphery. The width of the first peripheral electrode 108 is, for example, approximately 300 μm. The width of the second peripheral electrode 109 is, for example, approximately 600 μm. The widths of the first peripheral electrode 108 and the second peripheral electrode 109 are set as appropriate.

[0056] Fig. 5 shows an example of the schematic configuration of the liquid crystal device 100. Fig. 5 shows the schematic configuration of a first liquid crystal device 100a, which is an example of the liquid crystal device 100. Fig. 5 shows the first liquid crystal device 100a in a plan view from the +Z direction. The first liquid crystal device 100a includes a first concave-convex member 111 and a second concave-convex member 115 that are aligned with the first peripheral electrode 108.

[0057] The first concave-convex member 111 of the first liquid crystal device 100a is disposed between the first peripheral electrode 108 and the second peripheral electrode 109 in a plan view from the +Z direction. The first concave-convex member 111 is configured in a frame shape in a plan view from the +Z direction. The first concave-convex member 111 is disposed along the first peripheral electrode 108 and the second peripheral electrode 109.

[0058] The second concave-convex member 115 of the first liquid crystal device 100a is disposed between the first peripheral electrode 108 and the display region E in a plan view from the +Z direction. The second concave-convex member 115 is configured in a frame shape in a plan view from the +Z direction. The second concave-convex member 115 is disposed along the periphery of the first peripheral electrode 108 and the display region E.

[0059] FIG. 6 shows an example of the schematic configuration of the liquid crystal device 100. FIG. 6 shows the schematic configuration of a first liquid crystal device 100a, which is an example of the liquid crystal device 100. FIG. 6 shows an example of the schematic configuration of the peripheral region S. FIG. 6 shows the JJ cross section shown in FIG. 5 in a plan view from the -Y direction. FIG. 6 shows a part of the display region E and the peripheral region S. The peripheral region S indicates an area outside the display region E. A plurality of pixel electrodes 15 are arranged in the display region E. A sealing material 60, a first peripheral electrode 108, a second peripheral electrode 109, a first concave-convex member 111, and a second concave-convex member 115 are arranged in the peripheral region S.

[0060] The first concave-convex member 111 shown in FIG. 6 is disposed in a direction along the Y axis. The direction along the Y axis corresponds to an example of a first direction. The first concave-convex member 111 prevents ionic impurities Im from moving into the display region E. The first concave-convex member 111 corresponds to an example of a concave-convex member.

[0061] The first concave-convex member 111 is preferably made of silicon oxide (SiO2). The first concave-convex member 111 is formed into the shape shown in Fig. 6 by etching the silicon oxide. The method for forming the first concave-convex member 111 will be described later.

[0062] The first concave-convex member height, which is the height of the first concave-convex member 111 along the Z axis with respect to the surface of the element substrate 10 in the +Z direction, is configured to be higher than the first peripheral electrode height and the second peripheral electrode height. The +Z direction surface of the element substrate 10 is the surface on which the first peripheral electrode 108 and the second peripheral electrode 109 are arranged and corresponds to an example of an arrangement surface. The first peripheral electrode height is the height of the first peripheral electrode 108 along the Z axis with respect to the surface of the element substrate 10 in the +Z direction. The second peripheral electrode height is the height of the second peripheral electrode 109 along the Z axis with respect to the surface of the element substrate 10 in the +Z direction. The first concave-convex member height corresponds to an example of a concave-convex member height. The first peripheral electrode height corresponds to an example of a first electrode height. The second peripheral electrode height corresponds to an example of a second electrode height. By configuring the first concave-convex member height to be higher than the first peripheral electrode height and the second peripheral electrode height, it is possible to further suppress the migration of ionic impurities Im toward the display region E.

[0063] The width of the first concave-convex member 111 is set to 10 to 100 μm. The first concave-convex member 111 may extend continuously along the X-axis and Y-axis, or may be divided at predetermined lengths along the X-axis and Y-axis. When the first concave-convex member 111 is divided, the first concave-convex member 111 has a length of 10 to 100 μm and is set at a pitch of 1 to 10 μm, for example.

[0064] The surface of the first uneven member 111 is preferably configured with a first uneven surface 112. As an example, the first uneven surface 112 is formed on the first uneven member 111 by etching the first uneven member 111. The first uneven surface 112 shown in FIG. 6 is configured on the side surface of the first uneven member 111. As an example, the first uneven surface 112 is configured with a surface roughness of 10 to 50 nm. By configuring the first uneven surface 112, the first uneven member 111 can further hinder the movement of ionic impurities Im. The first uneven surface 112 corresponds to an example of an uneven surface.

[0065] 6 is disposed in the direction along the Y axis. The second concave-convex member 115 prevents ionic impurities Im from moving into the display region E. The second concave-convex member 115 corresponds to an example of a concave-convex member.

[0066] The second concave-convex member 115 is preferably made of silicon oxide (SiO2) The second concave-convex member 115 is formed into the shape shown in FIG.

[0067] The second concave-convex member height, which is the height of the second concave-convex member 115 along the Z axis, is configured to be higher than the first peripheral electrode height and the second peripheral electrode height. The second concave-convex member height corresponds to an example of the concave-convex member height. By configuring the second concave-convex member height to be higher than the first peripheral electrode height and the second peripheral electrode height, it is possible to further suppress the movement of ionic impurities Im into the display region E.

[0068] The width of the second concave-convex member 115 is set to 10 to 100 μm. The second concave-convex member 115 may extend continuously along the X-axis and Y-axis, or may be divided at predetermined lengths along the X-axis and Y-axis. When the second concave-convex member 115 is divided, the second concave-convex member 115 has a length of 10 to 100 μm and is set at a pitch of 1 to 10 μm, for example.

[0069] The second concave-convex member 115 may be configured in the same shape as the first concave-convex member 111, or may be configured in a different shape. The second concave-convex member 115 is preferably configured in the same shape as the first concave-convex member 111. By making the first concave-convex member 111 and the second concave-convex member 115 have the same configuration, the first concave-convex member 111 and the second concave-convex member 115 can be easily molded.

[0070] The surface of the second uneven member 115 is preferably configured with a second uneven surface 116. For example, the second uneven surface 116 is formed on the second uneven member 115 by etching the second uneven member 115. The second uneven surface 116 shown in FIG. 6 is configured on the side surface of the second uneven member 115. For example, the second uneven surface 116 has a surface roughness of 10 to 50 nm. By configuring the second uneven surface 116, the second uneven member 115 can better prevent the movement of ionic impurities Im.

[0071] 6 includes a first concave-convex member 111 and a second concave-convex member 115, but is not limited to this. The liquid crystal device 100 does not necessarily include the second concave-convex member 115. It is preferable that the liquid crystal device 100 includes the first concave-convex member 111 and the second concave-convex member 115.

[0072] FIG. 6 shows the configuration of the JJ cross section shown in FIG. 5. The configuration of the KK cross section shown in FIG. 5 is the same as the configuration shown in FIG. 6. The KK cross section is not shown. In the KK cross section, the first peripheral electrode 108, the second peripheral electrode 109, the first concave-convex member 111, and the second concave-convex member 115 extend in a direction along the X-axis. The configurations of the first peripheral electrode 108, the second peripheral electrode 109, the first concave-convex member 111, and the second concave-convex member 115 in the KK cross section are the same as the configuration shown in FIG.

[0073] FIG. 7 shows an example of the schematic configuration of the liquid crystal device 100. FIG. 7 shows the schematic configuration of a first liquid crystal device 100a, which is an example of the liquid crystal device 100. FIG. 7 shows an example of the schematic configuration of the peripheral region S. FIG. 7 shows the JJ cross section shown in FIG. 5 in a plan view from the -Y direction. FIG. 7 shows a part of the display region E and the peripheral region S. FIG. 7 schematically shows ionic impurities Im. The ionic impurities Im are, for example, anionic.

[0074] When the first liquid crystal device 100a is operating, a positive DC potential is applied to the first peripheral electrode 108, and a negative DC potential is applied to the second peripheral electrode 109. While the first liquid crystal device 100a is operating, a transverse electric field is generated between the pixel electrodes 15 and the first peripheral electrode 108, and ionic impurities Im are attracted to the first peripheral electrode 108. When the liquid crystal device 100 is stopped operating, the application of DC potentials to the first peripheral electrode 108 and the second peripheral electrode 109 is stopped. The ionic impurities Im are attracted to the second peripheral electrode 109 due to ion concentration distribution diffusion. The ionic impurities Im move in the +X direction and the -X direction at predetermined timing.

[0075] The first uneven member 111 and the second uneven member 115 prevent the movement of ionic impurities Im in the +X direction and the -X direction. By providing the first uneven member 111 and the second uneven member 115, the ionic impurities Im are retained in the peripheral region S as shown in FIG. 7. The first uneven member 111 and the second uneven member 115 prevent the ionic impurities Im from moving into the display region E.

[0076] The first uneven surface 112 provided on the side surface of the first uneven member 111 and the second uneven surface 116 provided on the side surface of the second uneven member 115 prevent the ionic impurities Im from moving in the +X direction and the -X direction. By providing the first uneven surface 112 and the second uneven surface 116, the first uneven member 111 and the second uneven member 115 can further prevent the ionic impurities Im from moving into the display region E.

[0077] The first liquid crystal device 100a comprises a liquid crystal layer 50 having a display region E, a first peripheral electrode 108 arranged in a peripheral region S, a second peripheral electrode 109 arranged in the peripheral region S and having a DC potential different from that of the first peripheral electrode 108 applied thereto, and a first uneven member 111 arranged between the first peripheral electrode 108 and the second peripheral electrode 109 when viewed in a plane from the +Z direction. The provision of the first concave-convex member 111 prevents the ionic impurities Im from migrating to the display region E. This further reduces the degradation of display quality caused by the ionic impurities Im.

[0078] The first peripheral electrode 108, the second peripheral electrode 109, and the first concave-convex member 111 are each arranged along the Y-axis. The first peripheral electrode 108, the second peripheral electrode 109, and the first concave-convex member 111 prevent the ionic impurities Im moving along the X-axis from moving into the display region E.

[0079] The first concave-convex member height of the first concave-convex member 111 is higher than the first peripheral electrode height of the first peripheral electrode 108 and the second peripheral electrode height of the second peripheral electrode 109. By configuring the height of the first concave-convex member to be higher than the height of the first peripheral electrode and the height of the second peripheral electrode, the movement of ionic impurities Im into the display region E can be further suppressed.

[0080] The side surface of the first uneven member 111 is formed as a first uneven surface 112 . The side surface of the first concave-convex member 111 is formed by the first concave-convex surface 112, so that the migration of ionic impurities Im to the display region E can be further suppressed.

[0081] The first concave-convex member 111 is preferably made of silicon oxide. This makes it easier to form the first concave-convex member 111 into a desired shape.

[0082] FIG. 8 shows an example of the schematic configuration of the liquid crystal device 100. FIG. 8 shows the schematic configuration of a second liquid crystal device 100b, which is an example of the liquid crystal device 100. FIG. 8 shows an example of the schematic configuration of the peripheral region S. FIG. 8 shows the JJ cross section shown in FIG. 4 in a plan view from the -Y direction. FIG. 8 shows a part of the display region E and the peripheral region S. A plurality of pixel electrodes 15 are arranged in the display region E. In the peripheral region S, a sealing material 60, a first peripheral electrode 108, a second peripheral electrode 109, a first concave-convex member 111, and a second concave-convex member 115 are arranged.

[0083] The first uneven member 111 of the second liquid crystal device 100b is formed on the first peripheral electrode 108. The first uneven member 111 covers the entire first peripheral electrode 108. The first uneven member 111 is arranged along the first peripheral electrode 108. By having the first uneven member 111 cover the first peripheral electrode 108, it becomes difficult for ionic impurities Im attracted to the first peripheral electrode 108 to move, and it is possible to prevent the ionic impurities Im from moving toward the display region E.

[0084] The second uneven member 115 of the second liquid crystal device 100b is formed on the second peripheral electrode 109. The second uneven member 115 covers the entire second peripheral electrode 109. The second uneven member 115 is arranged along the second peripheral electrode 109. By having the second uneven member 115 cover the second peripheral electrode 109, it becomes difficult for ionic impurities Im attracted to the second peripheral electrode 109 to move, and it is possible to prevent the movement of ionic impurities Im to the display region E.

[0085] 8, the first concave-convex member 111 and the second concave-convex member 115 are configured to have the same shape, but are not limited to this. The first concave-convex member 111 and the second concave-convex member 115 may be configured to have different shapes. As an example, the second concave-convex member 115 may be molded in a shape in which the height of the second concave-convex member is smaller than the height of the first concave-convex member.

[0086] The second liquid crystal device 100b shown in FIG. 8 includes a first concave-convex member 111 and a second concave-convex member 115, but is not limited to this. The second liquid crystal device 100b may include either the first concave-convex member 111 or the second concave-convex member 115. In the second liquid crystal device 100b shown in FIG. 8, the first concave-convex member 111 covers the first peripheral electrode 108, and the second concave-convex member 115 covers the second peripheral electrode 109, but is not limited to this. The second liquid crystal device 100b may also have a configuration in which the second concave-convex member 115 covers the first peripheral electrode 108, and the first concave-convex member 111 covers the second peripheral electrode 109. The presence of the first concave-convex member 111 or the second concave-convex member 115 suppresses the migration of ionic impurities Im to the display region E.

[0087] The second liquid crystal device 100b comprises a liquid crystal layer 50 having a display region E, a first peripheral electrode 108 arranged in a peripheral region S, a second peripheral electrode 109 arranged in the peripheral region S and to which a DC potential different from that of the first peripheral electrode 108 is applied, and a first uneven member 111 covering at least one of the first peripheral electrode 108 and the second peripheral electrode 109. The provision of the first concave-convex member 111 prevents the ionic impurities Im from migrating to the display region E. This suppresses a decrease in display quality caused by the ionic impurities Im.

[0088] FIG. 9 shows an example of the schematic configuration of the liquid crystal device 100. FIG. 9 shows the schematic configuration of a third liquid crystal device 100c, which is an example of the liquid crystal device 100. FIG. 9 shows an example of the schematic configuration of the peripheral region S. FIG. 9 shows the JJ cross section shown in FIG. 4 in a plan view from the -Y direction. FIG. 9 shows a part of the display region E and the peripheral region S. A plurality of pixel electrodes 15 are arranged in the display region E. In the peripheral region S, a sealing material 60, a first peripheral electrode 108, a second peripheral electrode 109, a first concave-convex member 111, and a second concave-convex member 115 are arranged.

[0089] The first uneven member 111 of the third liquid crystal device 100c is formed on the first peripheral electrode 108. The first uneven member 111 covers the entire first peripheral electrode 108. The first uneven member 111 is arranged along the first peripheral electrode 108. By having the first uneven member 111 cover the first peripheral electrode 108, it becomes difficult for ionic impurities Im attracted to the first peripheral electrode 108 to move, and it is possible to prevent the ionic impurities Im from moving toward the display region E.

[0090] The second uneven member 115 of the third liquid crystal device 100c is formed on the second peripheral electrode 109. The second uneven member 115 covers the entire second peripheral electrode 109. The second uneven member 115 is arranged along the second peripheral electrode 109. By having the second uneven member 115 cover the second peripheral electrode 109, it becomes difficult for ionic impurities Im attracted to the second peripheral electrode 109 to move, and it is possible to prevent the movement of ionic impurities Im to the display region E.

[0091] The first uneven member 111 and the second uneven member 115 of the third liquid crystal device 100c are bonded to each other. The first uneven member 111 and the second uneven member 115 are bonded between the first peripheral electrode 108 and the second peripheral electrode 109. By bonding the first uneven member 111 and the second uneven member 115, migration of ionic impurities Im to the display region E is suppressed.

[0092] 10 to 17 show manufacturing processes for the element substrate 10 of the liquid crystal device 100. Figures 10 to 17 show manufacturing processes for the element substrate 10 of a third liquid crystal device 100c, which is an example of the liquid crystal device 100. The first concave-convex member 111 and the second concave-convex member 115 are formed on the element substrate 10 by the manufacturing processes of Figures 10 to 17.

[0093] 10 shows the element substrate 10 after the ITO film formation process. By performing the ITO film formation process, the pixel electrode 15, the first peripheral electrode 108, and the second peripheral electrode 109 are formed. The pixel electrode 15, the first peripheral electrode 108, and the second peripheral electrode 109 are formed by photoetching the ITO film. The pixel electrode 15, the first peripheral electrode 108, and the second peripheral electrode 109 are simultaneously formed on the element substrate 10.

[0094] 11 shows the element substrate 10 after the silicon oxide film formation process. The silicon oxide film formation process is performed after the ITO film formation process. In the silicon oxide film formation process, a silicon oxide layer SR is formed on the element substrate 10. The silicon oxide layer SR is formed on the pixel electrode 15, the first peripheral electrode 108, and the second peripheral electrode 109.

[0095] FIG. 12 shows the element substrate 10 after the first mask formation process. The first mask formation process is performed after the silicon oxide film formation process. In the first mask formation process, a first mask Mk1 is formed on the silicon oxide layer SR. The first mask Mk1 is formed on the silicon oxide layer SR by applying a resist material onto the silicon oxide layer SR, followed by exposure and development. The first mask Mk1 is formed on the first peripheral electrode 108 and the second peripheral electrode 109. The first mask Mk1 is not formed on the pixel electrodes 15.

[0096] FIG. 13 shows the element substrate 10 after the first dry etching process. The first dry etching process is performed after the first mask formation process. The first dry etching process removes the silicon oxide film SR in the area where the first mask Mk1 is not formed. An example of the dry etching used in the first dry etching process is RIE (Reactive Ion Etching), which uses fluorine gas such as CHF3 (Trifluoromethane) as a reactive gas. After the first dry etching process is performed, the silicon oxide layer SR on the first peripheral electrode 108 and the second peripheral electrode 109 is maintained.

[0097] 14 shows the element substrate 10 after the first mask removal step. The first mask removal step is performed after the first dry etching step. In the first mask removal step, the first mask Mk1 formed on the silicon oxide layer SR is removed.

[0098] 15 shows the element substrate 10 after the second mask formation step. The second mask formation step is performed after the first mask removal step. In the second mask formation step, a second mask Mk2 is formed on the silicon oxide layer SR and the element substrate 10. The second mask Mk2 is formed on the silicon oxide layer SR and the element substrate 10 by applying a resist material onto the silicon oxide layer SR and the element substrate 10, followed by exposure and development. The second mask Mk2 on the silicon oxide layer SR is formed into a hemispherical shape by surface tension when the resist material is heated and melted.

[0099] FIG. 16 shows the element substrate 10 after the second dry etching process. The second dry etching process is performed after the second mask formation process. The dry etching used in the second dry etching process is, for example, RIE, similar to the dry etching used in the first dry etching process. In the second dry etching process, the silicon oxide layer SR and the second mask Mk are etched. In the second dry etching process, the etching is stopped before the height of the second mask Mk2 on the pixel electrode 15 reaches the height of the pixel electrode 15. When the second dry etching process is performed, minute irregularities are formed on the side surface of the silicon oxide layer SR.

[0100] 17 shows the element substrate 10 after the second mask removal step. The second mask removal step is performed after the second dry etching step. By performing the second mask removal step, the element substrate 10 including the first concave-convex members 111 and the second concave-convex members 115 is formed. The element substrate 10 shown in FIG. 17 is the element substrate 10 used in the third liquid crystal device 100c.

[0101] 17 is bonded between the first peripheral electrode 108 and the second peripheral electrode 109. The side surface of the first uneven member 111 is composed of a first uneven surface 112. The side surface of the second uneven member 115 is composed of a second uneven surface 116. The first uneven surface 112 and the second uneven surface 116 are formed in a second dry etching process.

[0102] 17, the upper surfaces of the first concave-convex member 111 and the second concave-convex member 115 are smooth surfaces. The upper surfaces of the first concave-convex member 111 and the second concave-convex member 115 are protected by the second mask Mk2 and are therefore smooth surfaces.

[0103] 10 to 17 show the manufacturing process for forming the first concave-convex member 111 and the second concave-convex member 115 of the third liquid crystal device 100c. The shapes of the first concave-convex member 111 and the second concave-convex member 115 can be appropriately formed by adjusting the conditions for forming the silicon oxide layer SR, the conditions for forming the first mask Mk, etc.

[0104] FIG. 18 shows an example of the schematic configuration of the liquid crystal device 100. FIG. 18 shows the schematic configuration of a fourth liquid crystal device 100d, which is an example of the liquid crystal device 100. FIG. 18 shows an example of the schematic configuration of the peripheral region S. FIG. 18 shows the JJ cross section shown in FIG. 4 in a plan view from the -Y direction. FIG. 18 shows a part of the display region E and the peripheral region S. A plurality of pixel electrodes 15 are arranged in the display region E. In the peripheral region S, a sealing material 60, a first peripheral electrode 108, a second peripheral electrode 109, a first concave-convex member 111, and a second concave-convex member 115 are arranged.

[0105] The first uneven member 111 of the fourth liquid crystal device 100d is formed on the first peripheral electrode 108. The first uneven member 111 covers the entire first peripheral electrode 108. The first uneven member 111 is arranged along the first peripheral electrode 108. By having the first uneven member 111 cover the first peripheral electrode 108, it becomes difficult for ionic impurities Im attracted to the first peripheral electrode 108 to move, and it is possible to prevent the ionic impurities Im from moving toward the display region E.

[0106] The upper surface of the first uneven member 111 of the fourth liquid crystal device 100d is composed of a first uneven upper surface 113. The upper surface of the first uneven member 111 is the surface of the first uneven member 111 in the +Z direction. The upper surface of the first uneven member 111 is the surface that faces the counter substrate 20. The first uneven upper surface 113 is a surface that has fine unevenness, similar to the first uneven surface 112. The first uneven upper surface 113 is formed by dry etching the silicon oxide layer SR or by adjusting the film formation conditions for the silicon oxide layer SR. By providing the first uneven upper surface 113, it is possible to further prevent ionic impurities Im from migrating to the display region E.

[0107] The second uneven member 115 of the fourth liquid crystal device 100d is formed on the second peripheral electrode 109. The second uneven member 115 covers the entire second peripheral electrode 109. The second uneven member 115 is arranged along the second peripheral electrode 109. By having the second uneven member 115 cover the second peripheral electrode 109, it becomes difficult for ionic impurities Im attracted to the second peripheral electrode 109 to move, and it is possible to prevent the movement of ionic impurities Im to the display region E.

[0108] The upper surface of the second uneven member 115 of the fourth liquid crystal device 100d is composed of a second uneven upper surface 117. The upper surface of the second uneven member 115 is the surface of the second uneven member 115 in the +Z direction. The upper surface of the second uneven member 115 is the surface that faces the counter substrate 20. The second uneven upper surface 117 is a surface that has fine unevenness, similar to the second uneven surface 116. The second uneven upper surface 117 is formed by dry etching the silicon oxide layer SR or by adjusting the film formation conditions for the silicon oxide layer SR. By providing the second uneven upper surface 117, it is possible to further prevent the migration of ionic impurities Im into the display region E.

[0109] 18, the first concave-convex member 111 and the second concave-convex member 115 are spaced apart between the first peripheral electrode 108 and the second peripheral electrode 109, but this is not limiting. The first concave-convex member 111 and the second concave-convex member 115 may also be joined between the first peripheral electrode 108 and the second peripheral electrode 109.

[0110] 18, the upper surface of the first concave-convex member 111 is configured as the first concave-convex upper surface 113, and the upper surface of the second concave-convex member 115 is configured as the second concave-convex upper surface 117, but this is not limited to this. The upper surface of the first concave-convex member 111 does not have to be configured as the first concave-convex upper surface 113. Alternatively, the upper surface of the second concave-convex member 115 does not have to be configured as the second concave-convex upper surface 117. If at least one of the upper surfaces of the first concave-convex member 111 and the second concave-convex member 115 has the configuration shown in FIG. 18, it is possible to prevent ionic impurities Im from moving toward the display region E.

[0111] FIG. 19 shows an example of the schematic configuration of the liquid crystal device 100. FIG. 19 shows the schematic configuration of a fifth liquid crystal device 100e, which is an example of the liquid crystal device 100. FIG. 19 shows an example of the schematic configuration of the peripheral region S. FIG. 19 shows the JJ cross section shown in FIG. 4 in a plan view from the -Y direction. FIG. 19 shows a part of the display region E and the peripheral region S. A plurality of pixel electrodes 15 are arranged in the display region E. In the peripheral region S, a sealing material 60, a first peripheral electrode 108, a second peripheral electrode 109, a first concave-convex member 111, and a second concave-convex member 115 are arranged.

[0112] The first uneven member 111 of the fifth liquid crystal device 100e is formed on the first peripheral electrode 108. The first uneven member 111 covers the entire first peripheral electrode 108. The first uneven member 111 is arranged along the first peripheral electrode 108. By having the first uneven member 111 cover the first peripheral electrode 108, it becomes difficult for ionic impurities Im attracted to the first peripheral electrode 108 to move, and it is possible to prevent the ionic impurities Im from moving toward the display region E.

[0113] The top surface of the first concave-convex member 111 of the fifth liquid crystal device 100e has a first recessed portion 114. The first recessed portion 114 corresponds to an example of a recessed portion. As an example, the first recessed portion 114 is formed by performing a dry etching process on the top surface of the first concave-convex member 111. By providing the first recessed portion 114, the migration distance of the ionic impurities Im toward the display region E increases, and the migration of the ionic impurities Im toward the display region E can be further prevented.

[0114] The second uneven member 115 of the fifth liquid crystal device 100e is formed on the second peripheral electrode 109. The second uneven member 115 covers the entire second peripheral electrode 109. The second uneven member 115 is arranged along the second peripheral electrode 109. By having the second uneven member 115 cover the second peripheral electrode 109, it becomes difficult for ionic impurities Im attracted to the second peripheral electrode 109 to move, and it is possible to prevent the movement of ionic impurities Im to the display region E.

[0115] The upper surface of the second concave-convex member 115 of the fifth liquid crystal device 100e has a second recessed portion 118. The second recessed portion 118 corresponds to an example of a recessed portion. As an example, the second recessed portion 118 is formed by performing a dry etching process on the upper surface of the second concave-convex member 115. By providing the second recessed portion 118, the migration distance of the ionic impurities Im toward the display region E increases, and the migration of the ionic impurities Im toward the display region E can be further prevented.

[0116] 19, the first concave-convex member 111 and the second concave-convex member 115 are spaced apart between the first peripheral electrode 108 and the second peripheral electrode 109, but this is not limiting. The first concave-convex member 111 and the second concave-convex member 115 may also be joined between the first peripheral electrode 108 and the second peripheral electrode 109.

[0117] 19, the first concave-convex member 111 has the first recessed portion 114, and the second concave-convex member 115 has the second recessed portion 118, but this configuration is not limiting. When the first concave-convex member 111 has the first recessed portion 114, the second concave-convex member 115 does not have to have the second recessed portion 118. When the second concave-convex member 115 has the second recessed portion 118, the first concave-convex member 111 does not have to have the first recessed portion 114.

[0118] The first concave-convex member 111 preferably has a first recess 114 on its upper surface. By providing the first recessed portion 114, the distance that the ionic impurities Im move to the display region E increases, and the movement of the ionic impurities Im to the display region E can be more effectively prevented.

[0119] 20 shows a schematic configuration of a projection display device 1000. The projection display device 1000 corresponds to an example of an electronic device. As an example, the projection display device 1000 is a three-panel projector equipped with three liquid crystal devices 100. The projection display device 1000 includes an illumination device 1001, an illumination optical system 1002, a projection optical system 1003, and a control unit 1004.

[0120] The illumination device 1001 is a light source that emits light to the illumination optical system 1002. The illumination device 1001 has a lamp light source such as a halogen lamp, a xenon lamp, or an ultra-high pressure mercury lamp. The illumination device 1001 may also have a solid-state light source such as an LED (Light Emitting Diode) or a laser light source.

[0121] The illumination optical system 1002 separates the light emitted from the illumination device 1001 into red light RL, green light GL, and blue light BL. The illumination optical system 1002 supplies the red light RL, green light GL, and blue light BL to the liquid crystal devices 100 provided corresponding to each color light.

[0122] The liquid crystal device 100 modulates light supplied from an illumination optical system 1002. The liquid crystal device 100 includes any one of a first liquid crystal device 100a, a second liquid crystal device 100b, a third liquid crystal device 100c, a fourth liquid crystal device 100d, and a fifth liquid crystal device 100e. Each of the three liquid crystal devices 100 functions as a light modulation device that modulates one of the separated light beams, red light RL, green light GL, and blue light BL, in accordance with a display image. A first polarizing plate 210 is disposed on the light incident side of each liquid crystal device 100. A second polarizing plate 220 is disposed on the light exit side of each liquid crystal device 100. The first polarizing plate 210 and the second polarizing plate 220 disposed in the liquid crystal device 100 are disposed in a crossed Nicol configuration in which the transmission axes of the respective polarizing plates for transmitting light are orthogonal to each other. The liquid crystal device 100 emits light to a projection optical system 1003 via the second polarizing plate 220.

[0123] The projection optical system 1003 forms image light by combining the red light RL, green light GL, and blue light BL modulated by the liquid crystal devices 100. The projection optical system 1003 projects the image light onto a screen SC.

[0124] The control unit 1004 is a controller that controls each unit of the projection display device 1000. The control unit 1004 is, for example, a processor having a CPU (Central Processing Unit). The control unit 1004 is composed of one or more processors. The control unit 1004 may have semiconductor memory such as a ROM (Read Only Memory) or a RAM (Random Access Memory). The semiconductor memory functions as a work area for the control unit 1004. The control unit 1004 controls each liquid crystal device 100 to modulate the red light RL, green light GL, and blue light BL supplied from the illumination optical system 1002 in accordance with the display image.

[0125] The projection display device 1000 is not limited to a three-panel projector. The projection display device 1000 may be a single-panel projector, a two-panel projector, or a projector equipped with four or more liquid crystal devices 100. Devices equipped with the liquid crystal device 100 may be smartphones, PDAs (Personal Digital Assistants), cameras, televisions, car navigation systems, personal computers, displays, electronic paper, calculators, videophones, and devices equipped with POS (Point of Sale), printers, scanners, copiers, video players, or touch panels. Devices equipped with the liquid crystal device 100 correspond to examples of electronic devices.

[0126] The projection display device 1000 preferably includes any one of a first liquid crystal device 100a, a second liquid crystal device 100b, a third liquid crystal device 100c, a fourth liquid crystal device 100d, and a fifth liquid crystal device 100e. It is possible to provide a projection display device 1000 that can suppress the deterioration of display quality caused by ionic impurities Im and maintain the display quality. [Explanation of symbols]

[0127] 3...scanning line, 6...data line, 8...capacitor line, 10...element substrate, 10s...element substrate base, 15...pixel electrode, 16...capacitor element, 18...first alignment film, 18a...first evaporated film, 18b...second evaporated film, 20...counter substrate, 20s...counter substrate base, 21...common electrode, 22...second alignment film, 22a...third evaporated film, 22b...fourth evaporated film, 24...parting portion, 25...insulating layer, 30...transistor, 50...liquid crystal layer, 50a...liquid crystal, 60...sealing material, 100...liquid crystal device, 100a...first liquid crystal device, 100b...second liquid crystal device, 100c...third liquid crystal device, 100d...fourth liquid crystal device, 100e...fifth liquid crystal device, 101...data line driving circuit, 104...external connection terminal element, 106...vertical conducting portion, 108...first peripheral electrode, 109...second peripheral electrode, 111...first uneven member, 112...first uneven surface, 113...first uneven upper surface, 114...first recessed portion, 115...second uneven member, 116...second uneven surface, 117...second uneven upper surface, 118...second recessed portion, 210...first polarizing plate, 220...second polarizing plate, 1000...projection type display device, 1001...illumination device, 1002...illumination optical system, 1003...projection optical system, 1004...controller, BL...blue light, E...display area, GL...green light, Im...ionic impurities, L...incident light, Mk1...first mask, Mk2...second mask, P...pixel, RL...red light, S...peripheral area, SR...silicon oxide layer

Claims

1. an electro-optic layer having pixel areas; a first electrode disposed outside the pixel region; a second electrode disposed outside the pixel region and having a potential different from that of the first electrode applied thereto; an uneven member disposed between the first electrode and the second electrode in a plan view; Equipped with Electro-optical device.

2. The first electrode, the second electrode, and the uneven member are each arranged along a first direction. The electro-optical device according to claim 1 .

3. a height of the concave-convex member based on a placement surface on which the first electrode and the second electrode are placed is higher than a first electrode height of the first electrode based on the placement surface and a second electrode height of the second electrode based on the placement surface; The electro-optical device according to claim 1 .

4. The side surface of the uneven member is composed of an uneven surface. The electro-optical device according to claim 1 .

5. The uneven member has a recessed portion on the upper surface. The electro-optical device according to claim 1 .

6. The uneven member is made of silicon oxide. The electro-optical device according to claim 1 .

7. an electro-optic layer having pixel areas; a first electrode disposed outside the pixel region; a second electrode disposed outside the pixel region and having a potential different from that of the first electrode applied thereto; an uneven member covering at least one of the first electrode and the second electrode; Equipped with Electro-optical device.

8. An electronic device comprising the electro-optical device according to claim 1 .

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