Wafer, semiconductor device, and method of manufacturing wafer

Abstract

To provide a wafer capable of improving characteristics, a semiconductor device, and a method of manufacturing the wafer.SOLUTION: According to an embodiment, a wafer includes a substrate, a first layer including Alx1Ga1 and x1N (0 ≤ x1 <1), and a second layer including Alx2Ga1 and x2N (x1 <x2 <1). The first semiconductor layer is between the base body and the second semiconductor layer. The second semiconductor layer includes a first region, a second region, a third region, and a fourth region. The first region is between the first semiconductor layer and the third region. The second region is between the first region and the third region. The fourth region is between the first semiconductor layer and the first region. The 4Al composition ratio of the fourth region increases in the orientation from the first region toward the second region. The second 2Al portion composition ratio in the second region is lower than the third 3Al portion composition ratio in the third region. The first side 1Al composition ratio in the first region is higher than the second side 2Al composition ratio.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a wafer, a semiconductor device, and a method for manufacturing a wafer. [Background technology]

[0002] For example, improvements in the characteristics of semiconductor devices based on nitride semiconductors are desired. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6812322 Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE INVENTION Embodiments of the present invention provide a wafer, a semiconductor device, and a method for manufacturing a wafer that can improve characteristics. [Means for solving the problem]

[0005] According to an embodiment of the present invention, the wafer comprises a substrate and an Al x1 Ga 1-x1 a first semiconductor layer containing N (0≦x1<1) and Al x2 Ga 1-x2It includes a second semiconductor layer containing N(x1 < x2 < 1). The first semiconductor layer is between the substrate and the second semiconductor layer in a first direction from the substrate to the second semiconductor layer. The second semiconductor layer includes a first region, a second region, a third region, and a fourth region. The first region is between the first semiconductor layer and the third region. The second region is between the first region and the third region. The fourth region is between the first semiconductor layer and the first region. The fourth Al composition ratio in the fourth region increases in a direction from the first semiconductor layer to the first region. The second Al composition ratio in the second region is lower than the third Al composition ratio in the third region. The first Al composition ratio in the first region is higher than the second Al composition ratio.

Brief Description of the Drawings

[0006] [Figure 1] Figure 1 is a schematic cross-sectional view illustrating a wafer according to the first embodiment. [Figure 2] Figure 2 is a graph illustrating a wafer according to the first embodiment. [Figure 3] Figure 3 is a graph illustrating a wafer. [Figure 4] Figure 4 is a graph illustrating a wafer. [Figure 5] Figure 5 is a graph illustrating a wafer. [Figure 6] Figure 6 is a graph illustrating the characteristics of a wafer. [Figure 7] Figures 7(a) to 7(d) are graphs illustrating the characteristics of a wafer. [Figure 8] Figure 8 is a schematic cross-sectional view illustrating a wafer according to the first embodiment. [Figure 9] Figure 9 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment. [Figure 10] Figure 10 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment. [Figure 11] Figures 11(a) and 11(b) are schematic diagrams illustrating a method for manufacturing a wafer according to the third embodiment.

Best Mode for Carrying Out the Invention

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as the actual ones. Even when representing the same part, the dimensions and ratios may be represented differently in the drawings. In the specification of the present application and each figure, the same reference numerals are given to the same elements as those described above with respect to the previously shown figures, and the detailed description will be omitted as appropriate.

[0008] (First Embodiment) FIG. 1 is a schematic cross-sectional view illustrating a wafer according to the first embodiment. FIG. 2 is a graph illustrating a wafer according to the first embodiment. As shown in FIG. 1, the wafer 210 according to the embodiment includes a substrate 60, a first semiconductor layer 10, and a second semiconductor layer 20.

[0009] The first semiconductor layer 10 contains Al x1 Ga 1-x1 N (0 ≦ x1 < 1). For example, the composition ratio x1 may be 0 or more and 0.13 or less. The first semiconductor layer 10 may be a GaN layer.

[0010] The second semiconductor layer 20 contains Al x2 Ga 1-x2 N (x1 < x2 < 1). The second semiconductor layer 20 may be an AlGaN layer. As will be described later, the second semiconductor layer 20 may vary along the thickness direction. The average Al composition ratio x2 in the second semiconductor layer 20 may, for example, exceed 0.13 and be less than 0.5.

[0011] The first semiconductor layer 10 is between the substrate 60 and the second semiconductor layer 20 in the first direction D1 from the substrate 60 to the second semiconductor layer 20. The first semiconductor layer 10 and the second semiconductor layer 20 are included in the semiconductor member 10M.

[0012] The first direction D1 is the Z-axis direction. A direction perpendicular to the Z-axis direction is the X-axis direction. A direction perpendicular to the Z-axis direction and the X-axis direction is the Y-axis direction. The base 60, the first semiconductor layer 10, and the second semiconductor layer 20 are each layered along the XY plane.

[0013] The second semiconductor layer 20 includes a first region 21, a second region 22, a third region 23, and a fourth region 24. The first region 21 is located between the first semiconductor layer 10 and the third region 23. The second region 22 is located between the first region 21 and the third region 23. The fourth region 24 is located between the first semiconductor layer 10 and the first region 21.

[0014] 2 illustrates an example of an EDX (Energy Dispersive X-ray Spectroscopy) analysis result of a first sample SPL1 corresponding to a wafer 210 according to the embodiment. In FIG. 2, the horizontal axis represents the position pZ in the Z-axis direction. The vertical axis represents the Al concentration C(Al). The Al concentration C(Al) corresponds to the Al composition ratio.

[0015] 2, the fourth Al composition ratio C4 in the fourth region 24 increases in the direction from the first semiconductor layer 10 to the first region 21. The second Al composition ratio C2 in the second region 22 is lower than the third Al composition ratio C3 in the third region 23. The first Al composition ratio C1 in the first region 21 is higher than the second Al composition ratio C2.

[0016] For example, it is preferable that the Al composition ratio changes moderately sharply between the first semiconductor layer 10, which has a low Al composition ratio, and the second semiconductor layer 20, which has a high Al composition ratio. This allows, for example, an appropriate amount of carriers to be generated. In a semiconductor device using the wafer 210, high mobility can be obtained. Here, if the composition ratio changes too sharply, there is a possibility that the continuity of crystallinity may be adversely affected due to differences in lattice length, etc.

[0017] For example, the third region 23 is a region where the Al composition ratio is substantially constant. In the embodiment, the profile of the Al composition ratio in the region between the first semiconductor layer 10 and the third region 23 is appropriately controlled. This allows the Al composition ratio in the region between the first semiconductor layer 10 and the second semiconductor layer 20 to change appropriately sharply.

[0018] In the wafer 210, a first region 21 in which the Al composition ratio is locally high is provided. This results in a steep change. Furthermore, a second region 22 in which the Al composition ratio is locally low is provided. This prevents the first Al composition ratio C1 in the first region 21 in which the Al composition ratio is locally high from becoming excessively high. For example, even in a situation in which the Al concentration at the position corresponding to the first region 21 becomes excessively high, excess Al can move into the second region 22 by diffusion or the like. As a result, the first Al composition ratio C1 in the first region 21 is unlikely to become excessively high. The adverse effects of an excessively steep change can be suppressed.

[0019] Furthermore, as will be described later, it has been found that an excessively high first Al composition ratio C1 in the first region 21 increases the electrical resistance between the first semiconductor layer 10 and the second semiconductor layer 20 (for example, the third region 23). By providing the second region 22, in which the Al composition ratio is locally low, an excessively high first Al composition ratio C1 can be suppressed, and low electrical resistance can be maintained.

[0020] The wafer 210 according to the embodiment can provide, for example, high mobility, high crystallinity, and, for example, low electrical resistance. According to the embodiment, it is possible to provide a wafer and a semiconductor device capable of improving characteristics.

[0021] In the first sample SPL1, the electron mobility was 2047 cm 2 / Vs. The electrical resistance (contact resistance) is 0.563 Ωmm. High electron mobility and low contact resistance are obtained.

[0022] 2, for example, the Al composition ratio in the third region 23 may be substantially constant in the Z-axis direction (first direction D1). The Al composition ratio in the third region 23 may vary in the Z-axis direction due to nonuniformity in the sample or characteristics of the analysis method. The third Al composition ratio C3 in the third region 23 may be the average value of the Al composition ratio in the first direction D1 in the third region 23. In FIG. 2, the average value of the Al composition ratio in the first direction D1 in the third region 23 is indicated by a dashed line as the third Al composition ratio C3. The Al composition ratio in the third region 23 may vary within a range of ±10% of the average value.

[0023] In the embodiment, for example, a region where an Al composition ratio less than 0.9 times the third Al composition ratio C3 (average value) is obtained may correspond to the second region 22. For example, the second Al composition ratio C2 is less than 0.9 times the third Al composition ratio C3 (average value).

[0024] In the embodiment, for example, a region where an Al composition ratio of 0.9 times or more the third Al composition ratio C3 (average value) is obtained may correspond to the first region 21. For example, the first Al composition ratio C1 is 0.9 times or more the third Al composition ratio C3 (average value). The first Al composition ratio C1 may be 2 times or less the third Al composition ratio C3 (average value). The first Al composition ratio C1 may be 1.2 times or less the third Al composition ratio C3 (average value).

[0025] For example, the fourth region 24 may correspond to a region in which the Al composition ratio varies from 0.1 to 0.9 times the third Al composition ratio C3 (average value). For example, the fourth Al composition ratio C4 may vary between 0.1 times the third Al composition ratio C3 (average value) and 0.9 times the third Al composition ratio.

[0026] The first region 21 contacts the fourth region 24 and the second region 22. The second region 22 contacts the first region 21 and the third region 23. Due to the above definition, a part of the second semiconductor layer 20 may be present between the fourth region 24 and the first semiconductor layer 10. In this part of the second semiconductor layer 20, the Al composition ratio changes between 0.1 times the third Al composition ratio C3 (average value) and the Al composition ratio in the first semiconductor layer 10. The second semiconductor layer 20 may contact the first semiconductor layer 10.

[0027] 1, the first thickness t1 of the first region 21 in the first direction D1 may be thinner than the third thickness t3 of the third region 23 in the first direction D1. The second thickness t2 of the second region 22 in the first direction D1 may be thinner than the third thickness t3.

[0028] The fourth thickness t4 of the fourth region 24 in the first direction D1 may be equal to or less than the sum of the first thickness t1 and the second thickness t2, resulting in a steep change in Al.

[0029] The fourth thickness t4 may be, for example, 2.5 nm or less. The first thickness t1 may be, for example, 1 nm or more and 2 nm or less. The second thickness t2 may be, for example, 0.5 nm or more and 2 nm or less. The third thickness t3 may be, for example, 5 nm or more and 50 nm or less.

[0030] The first Al composition ratio C1 may be, for example, 0.16 or more and 0.48 or less, the second Al composition ratio C2 may be, for example, 0.14 or more and 0.2 or less, and the third Al composition ratio C3 may be, for example, 0.16 or more and 0.3 or less.

[0031] 3 to 5 are graphs illustrating wafers. FIG. 3 corresponds to the second sample SPL2. FIG. 4 corresponds to the third sample SPL3. FIG. 5 corresponds to the fourth sample SPL4. These samples correspond to reference examples. The horizontal axis of these figures is the position pZ in the Z-axis direction. The vertical axis is the Al concentration C(Al).

[0032] As shown in FIG. 3, the second sample SPL2 includes a first region 21, a second region 22, a third region 23, and a fourth region 24. In the second sample SPL2, the first thickness t1 of the first region 21 is approximately 0.3 nm. The fourth thickness t4 of the fourth region 24 is approximately 3 nm, and the Al concentration C(Al) changes gradually. In the second sample SPL2, the electron mobility is 1555 cm 2 / Vs. The electrical resistance (contact resistance) is 0.645 Ωmm. The second sample SPL2 has a lower electron mobility and a higher contact resistance than the first sample SPL1.

[0033] As shown in FIG. 4, the third sample SPL3 does not have the second region 22. The Al concentration C(Al) changes gradually. In the third sample SPL3, the electron mobility is 1687 cm 2 / Vs. The electrical resistance (contact resistance) is 0.651 Ωmm. The third sample SPL3 has a lower electron mobility and a higher contact resistance than the first sample SPL1.

[0034] As shown in FIG. 5, the fourth sample SPL4 does not have the second region 22. The Al concentration C(Al) changes abruptly. In the fourth sample SPL4, the first Al composition ratio C1 is excessively high. In the fourth sample SPL4, the electron mobility is 2223 cm 2 / Vs. The electrical resistance (contact resistance) is 2.303 Ωmm. In the fourth sample SPL4, the electron mobility is higher than that of the first sample SPL1, but the contact resistance is very high. The very high contact resistance is thought to be due to the excessively high first Al composition ratio C1.

[0035] FIG. 6 is a graph illustrating the characteristics of the wafer. Figure 6 shows the characteristics of the first sample SPL1, second sample SPL2, third sample SPL3, and fourth sample SPL4. The horizontal axis of Figure 6 represents the first Al composition ratio C1. The left vertical axis represents the contact resistance Rc. The right horizontal axis represents the electron mobility μ.

[0036] As shown in Figure 6, as the first Al composition ratio C1 increases, the electron mobility μ increases. In the region where the first Al composition ratio C1 is 0.48 or less, as the first Al composition ratio C1 increases, the contact resistance Rc decreases slightly. When the first Al composition ratio C1 is 0.5 or more, the contact resistance Rc increases significantly.

[0037] 7(a) to 7(d) are graphs illustrating the characteristics of the wafer. These figures correspond to the first sample SPL1, the second sample SPL2, the third sample SPL3, and the fourth sample SPL4, respectively. The horizontal axis of these figures represents the lattice spacing Lz in the Z-axis direction (first direction D1). The vertical axis represents the position pZ in the Z-axis direction. The lattice spacing Lz is derived based on information about the atomic positions obtained from a TEM (transmission electron microscope) image of the sample.

[0038] As shown in FIG. 7(a), in the first sample SPL1, the first lattice spacing L21 in the first direction D1 in the first region 21 is approximately 0.254 nm.

[0039] As shown in FIG. 7(b), in the second sample SPL2, the first lattice spacing L21 is approximately 0.2568 nm.

[0040] As shown in FIG. 7(c), in the third sample SPL3, the first lattice spacing L21 is approximately 0.2566 nm.

[0041] As shown in FIG. 7(d), in the fourth sample SPL4, the first lattice spacing L21 is approximately 0.253 nm.

[0042] In the embodiment, the first lattice spacing L21 in the first direction D1 in the first region 21 is preferably 0.254 nm or more and 0.256 nm or less, thereby achieving high electron mobility and low contact resistance.

[0043] FIG. 8 is a schematic cross-sectional view illustrating the wafer according to the first embodiment. As shown in FIG. 8, the wafer 211 according to the embodiment includes a nitride member 60S. The configuration of the wafer 211 may be the same as that of the wafer 210.

[0044] The nitride member 60S is provided between the substrate 60 and the first semiconductor layer 10. The nitride member 60S is Al z1 Ga 1-z1 a first nitride layer 61 containing N (0 < z1 ≦ 1), and Al z2 Ga 1-z2 a second nitride layer 62 containing N (0 < z2 < z1). The first nitride layer 61 is between the substrate 60 and the first semiconductor layer 10. The second nitride layer 62 is between the first nitride layer 61 and the first semiconductor layer 10.

[0045] The substrate 60 may be, for example, a silicon substrate or the like. The substrate 60 may be a GaN substrate, a SiC substrate, or the like. The first nitride layer 61 may be, for example, an AlN layer. The second nitride layer 62 may be, for example, an AlGaN layer. These nitride layers may be, for example, at least a part of the buffer layer.

[0046] The nitride member 60S may further include a laminate 63 containing Al, Ga, and N. The laminate 63 is between the second nitride layer 62 and the first semiconductor layer 10. The laminate 63 includes a plurality of first nitride films 63a and a plurality of second nitride films 63b. One of the plurality of first nitride films 63a is between one of the plurality of second nitride films 63b and another one of the plurality of second nitride films 63b. One of the plurality of second nitride films 63b is between one of the plurality of first nitride films 63a and another one of the plurality of first nitride films 63a. The composition ratio of Al in the plurality of first nitride films 63a is different from the composition ratio of Al in the plurality of second nitride films 63b. The laminate 63 may be, for example, a superlattice layer.

[0047] (Second Embodiment) FIG. 9 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment. As shown in FIG. 9, the semiconductor device 110 according to the embodiment includes a wafer according to the first embodiment (for example, a wafer 210), a first electrode 51, a second electrode 52, and a third electrode 53.

[0048] A second direction D2 from the first electrode 51 to the second electrode 52 intersects with the first direction D1. The second direction D2 may be, for example, the X-axis direction. The position of the third electrode 53 in the second direction D2 is between the position of the first electrode 51 in the second direction D2 and the position of the second electrode 52 in the second direction D2.

[0049] The second semiconductor layer 20 includes a first semiconductor portion 20a and a second semiconductor portion 20b. The direction from the first semiconductor portion 20a to the second semiconductor portion 20b is along the second direction D2. The first electrode 51 is electrically connected to the first semiconductor portion 20a. The second electrode 52 is electrically connected to the second semiconductor portion 20b.

[0050] The current flowing between the first electrode 51 and the second electrode 52 is controlled by the potential of the third electrode 53. The potential of the third electrode 53 may be, for example, a potential based on the potential of the first electrode 51. The first electrode 51 functions as, for example, a source electrode. The second electrode 52 functions as a drain electrode. The third electrode 53 functions as a gate electrode. The semiconductor device 110 is, for example, a transistor.

[0051] The first semiconductor layer 10 includes a region facing the second semiconductor layer 20. A carrier region is formed in this region. The carrier region is, for example, a two-dimensional electron gas. The semiconductor device 110 is, for example, a HEMT (High Electron Mobility Transistor).

[0052] In the semiconductor device 110, high electron mobility and low contact resistance are obtained, for example, low on-resistance is obtained.

[0053] 9, in this example, at least a portion of the third electrode 53 is provided between the first semiconductor portion 20a and the second semiconductor portion 20b in the second direction D2. The third electrode 53 is, for example, a recessed gate electrode. For example, a normally-off characteristic is obtained. At least a portion of the third electrode 53 may be provided between a portion of the first semiconductor layer 10 and another portion of the first semiconductor layer 10 in the second direction D2.

[0054] For example, the first semiconductor layer 10 includes a first partial region 10a, a second partial region 10b, a third partial region 10c, a fourth partial region 10d, and a fifth partial region 10e. The direction from the first partial region 10a to the first electrode 51 is along the first direction D1. The direction from the second partial region 10b to the second electrode 52 is along the first direction D1. The direction from the third partial region 10c to the third electrode 53 is along the first direction D1.

[0055] The position of the fourth partial region 10d in the second direction D2 is between the position of the first partial region 10a in the second direction D2 and the position of the third partial region 10c in the second direction D2. The position of the fifth partial region 10e in the second direction D2 is between the position of the third partial region 10c in the second direction D2 and the position of the second partial region 10b in the second direction D2.

[0056] The direction from the fourth partial region 10d to the first semiconductor portion 20a is along the first direction D1. The direction from the fifth partial region 10e to the second semiconductor portion 20b is along the first direction D1. In this example, a portion of the third electrode 53 is located between the fourth partial region 10d and the fifth partial region 10e in the second direction D2. A high threshold voltage is obtained. For example, stable normally-off operation is obtained.

[0057] 9, the semiconductor device 110 may further include a first insulating member 41. The first insulating member 41 includes a first insulating portion 41p, which is provided between the third electrode 53 and the semiconductor member 10M. The first insulating portion 41p functions as, for example, a gate insulating film.

[0058] 9, the semiconductor member 10M may further include an intermediate nitride layer 15. The intermediate nitride layer 15 is, for example, a GaN layer. The carbon concentration in the intermediate nitride layer 15 is higher than the carbon concentration in the first semiconductor layer 10. The intermediate nitride layer 15 is provided as needed, and may be omitted.

[0059] FIG. 10 is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment. 10 , the semiconductor device 111 according to the embodiment includes the wafer (e.g., wafer 210) according to the first embodiment, a first electrode 51, a second electrode 52, and a third electrode 53. In the semiconductor device 111, the third electrode 53 does not overlap with the second semiconductor layer 20 in the second direction D2. Except for this, the configuration of the semiconductor device 111 may be similar to that of the semiconductor device 110.

[0060] For example, normally-on operation can be obtained from the semiconductor device 111. In the semiconductor device 111, the first insulating member 41 may be omitted. For example, the semiconductor device 111 may be used as a high-frequency switching element.

[0061] (Third embodiment) The third embodiment relates to a method for manufacturing a wafer. 11(a) and 11(b) are schematic views illustrating the wafer manufacturing method according to the third embodiment. In these figures, the horizontal axis represents time tm, the vertical axis in Fig. 11(a) represents the supply rate A0 of the first source gas containing Al, and the vertical axis in Fig. 11(b) represents the supply rate G0 of the second source gas containing Ga.

[0062] As shown in FIG. 11(a), a first process OP1 is performed. In the first process OP1, Al x1 Ga 1-x1 A first process OP1 is performed on a first semiconductor layer 10 containing N (0≦x1<1) using a first source gas containing Al. In the first process OP1, the first source gas is supplied at a first supply amount A1. In the first process OP1, a third source gas containing N may be supplied, and a heat treatment may be performed.

[0063] As shown in FIG. 11(b), in the first process OP1, the supply amount G0 of the second source gas may be small. In the first process OP1, the second source gas may not be supplied. By the first process OP1, for example, at least a part of the fourth region 24 and the first region 21 may be formed.

[0064] As shown in FIG. 11(a), after the first process OP1, the second process OP2 is performed. In the second process OP2, the first source gas is not used. Or, the second supply amount A2 of the first source gas in the second process OP2 is smaller than the first supply amount A1. In the second process OP2, a third source gas containing N is supplied, and a heat treatment may be performed.

[0065] As shown in FIG. 11(b), in the second process OP2, the supply amount G0 of the second source gas may be small. In the second process OP2, the second source gas may not be supplied. By the second process OP2, for example, the second region 22 is formed.

[0066] As shown in FIG. 11(a), after the second process OP2, the third process OP3 is performed. In the third process OP3, a process using the first source gas and the second source gas containing Ga is performed. Thereby, a part of the second semiconductor layer 20 containing Al x2 Ga 1-x2 N (x1 <x2 <1) is formed. For example, the third region 23 may be formed by the third process OP3.

[0067] The third supply amount A3 of the first source gas in the third process OP3 may be larger than the first supply amount A1. It is easy to obtain a uniform third region 23.

[0068] According to the method for manufacturing a wafer according to the embodiment, the second region 22 having a locally low Al composition ratio can be stably formed. According to the embodiment, a method for manufacturing a wafer capable of improving characteristics is provided.

[0069] In an embodiment, information regarding the shape of the nitride region, etc. can be obtained, for example, from an electron microscope image or the like. Information regarding the composition and elemental concentration can be obtained, for example, by EDX (Energy Dispersive X-ray Spectroscopy), or SIMS (Secondary Ion Mass Spectrometry), or the like. Information regarding the composition may be obtained, for example, by inverse lattice space mapping or the like.

[0070] The embodiment may include the following technical solutions. (Technical solution 1) A substrate, Al x1 Ga 1-x1 A first semiconductor layer containing N(0≦x1<1), Al x2 Ga 1-x2 A second semiconductor layer containing N(x1<x2<1), Comprising, The first semiconductor layer is between the substrate and the second semiconductor layer in a first direction from the substrate to the second semiconductor layer, The second semiconductor layer includes a first region, a second region, a third region, and a fourth region, The first region is between the first semiconductor layer and the third region, The second region is between the first region and the third region, The fourth region is between the first semiconductor layer and the first region, The fourth Al composition ratio in the fourth region increases in the direction from the first semiconductor layer to the first region, <X The second Al composition ratio in the second region is lower than the third Al composition ratio in the third region, The first Al composition ratio in the first region is higher than the second Al composition ratio, wafer.

[0071] (Technical solution 2) The third Al composition ratio is the average value in the first direction of the composition ratio of Al in the third region, The second Al composition ratio is less than 0.9 times the third Al composition ratio, A wafer according to Technical Scheme 1, wherein the first Al composition ratio is 0.9 times or more the third Al composition ratio.

[0072] (Technical proposal 3) A wafer according to Technical Scheme 2, wherein the first Al composition ratio is not more than twice the third Al composition ratio.

[0073] (Technical proposal 4) A wafer according to Technical Scheme 2, wherein the first Al composition ratio is 1.2 times or less the third Al composition ratio.

[0074] (Technical proposal 5) The wafer according to Technical Scheme 2, wherein the fourth Al composition ratio varies between 0.1 times the third Al composition ratio and 0.9 times the third Al composition ratio.

[0075] (Technical proposal 6) a first thickness of the first region in the first direction is smaller than a third thickness of the third region in the first direction; 6. The wafer according to any one of Technical Schemes 1 to 5, wherein the second thickness of the second region in the first direction is thinner than the third thickness.

[0076] (Technical proposal 7) A wafer according to Technical Proposal 6, wherein a fourth thickness in the first direction of the fourth region is equal to or less than the sum of the first thickness and the second thickness.

[0077] (Technical proposal 8) A wafer according to Technical Proposal 7, wherein the fourth thickness is 2.5 nm or less.

[0078] (Technical proposal 9) the first thickness is equal to or greater than 1 nm and equal to or less than 2 nm; 9. The wafer according to any one of Technical Schemes 6 to 8, wherein the second thickness is 0.5 nm or more and 2 nm or less.

[0079] (Technical proposal 10) the first region is in contact with the fourth region and the second region, The second region is a wafer according to any one of Technical Solutions 1 to 9, which is in contact with the first region and the third region.

[0080] (Technical Solution 11) The first Al composition ratio is 0.16 or more and 0.48 or less, and the wafer is according to any one of Technical Solutions 1 to 10.

[0081] (Technical Solution 12) The second Al composition ratio is 0.14 or more and 0.2 or less, and the wafer is according to Technical Solution 11.

[0082] (Technical Solution 13) The third Al composition ratio is 0.16 or more and 0.3 or less, and the wafer is according to Technical Solution 12.

[0083] (Technical Solution 14) In the first region, the first lattice plane spacing in the first direction is 0.254 nm or more and 0.256 nm or less, and the wafer is according to any one of Technical Solutions 1 to 13.

[0084] (Technical Solution 15) The wafer further includes a nitride member provided between the substrate and the first semiconductor layer, The nitride member is Al z1 Ga 1-z1 a first nitride layer containing N (0 < z1 ≤ 1), Al z2 Ga 1-z2 a second nitride layer containing N (0 < z2 < z1), and includes The first nitride layer is between the substrate and the first semiconductor layer, The second nitride layer is between the first nitride layer and the first semiconductor layer, The wafer is according to any one of Technical Solutions 1 to 14.

[0085] (Technical Solution 16) The nitride member further includes a laminate containing Al, Ga, and N, the stack is between the second nitride layer and the first semiconductor layer; the stack includes a plurality of first nitride films and a plurality of second nitride films; one of the plurality of first nitride films is between one of the plurality of second nitride films and another of the plurality of second nitride films; the one of the plurality of second nitride films is between the one of the plurality of first nitride films and another one of the plurality of first nitride films; A wafer according to Technical Solution 15, wherein the Al composition ratio in the plurality of first nitride films is different from the Al composition ratio in the plurality of second nitride films.

[0086] (Technical proposal 17) A wafer according to any one of technical proposals 1 to 16; A first electrode; A second electrode; A third electrode; Equipped with a second direction from the first electrode to the second electrode intersects with the first direction; a position of the third electrode in the second direction is between a position of the first electrode in the second direction and a position of the second electrode in the second direction; the second semiconductor layer includes a first semiconductor portion and a second semiconductor portion; a direction from the first semiconductor portion to the second semiconductor portion is along the second direction; the first electrode is electrically connected to the first semiconductor portion; The second electrode is electrically connected to the second semiconductor portion.

[0087] (Technical proposal 18) The semiconductor device described in Technical Proposal 17, wherein at least a portion of the third electrode is located between the first semiconductor portion and the second semiconductor portion in the second direction.

[0088] (Technical proposal 19) Al x1 Ga 1-x1A first treatment is performed on a first semiconductor layer containing N(0≦x1<1) using a first source gas containing Al. In the first treatment, the first source gas is supplied at a first supply amount. After the first treatment, a second treatment is performed. In the second treatment, the first source gas is not used, or the second supply amount of the first source gas in the second treatment is smaller than the first supply amount. After the second treatment, a third treatment is performed using the first source gas and a second source gas containing Ga to form a part of a second semiconductor layer containing Al x2 Ga 1-x2 N(x1<x2<1), a method for manufacturing a wafer.

[0089] (Technical proposal 20) The method for manufacturing a wafer according to Technical Proposal 19, wherein the third supply amount of the first source gas in the third treatment is larger than the first supply amount.

[0090] According to an embodiment, it is possible to provide a wafer, a semiconductor device, and a method for manufacturing a wafer capable of improving characteristics.

[0091] In the present specification, the state of "electrically connected" includes a state in which a plurality of conductors are physically in contact and an electric current flows between these plurality of conductors. The state of "electrically connected" includes a state in which another conductor is inserted between a plurality of conductors and an electric current flows between these plurality of conductors.

[0092] As described above, the embodiments of the present invention have been described with reference to specific examples. However, the present invention is not limited to these specific examples. For example, regarding the specific configurations of each element such as a substrate, a semiconductor layer, and an electrode included in a wafer or a semiconductor device, the present invention can be similarly implemented by appropriately selecting from the range known to those skilled in the art, and as long as the same effects can be obtained, it is included in the scope of the present invention. <​​​

[0094] In addition, all wafers, semiconductor devices, and wafer manufacturing methods that can be implemented by a person skilled in the art by making appropriate design modifications based on the wafers, semiconductor devices, and wafer manufacturing methods described above as embodiments of the present invention also fall within the scope of the present invention, as long as they include the gist of the present invention.

[0095] In addition, within the scope of the concept of the present invention, a person skilled in the art may come up with various modifications and alterations, and these modifications and alterations are also considered to fall within the scope of the present invention.

[0096] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0097] 10, 20: first and second semiconductor layers, 10M: semiconductor member, 10a-10e: first to fifth partial regions, 15: intermediate nitride layer, 20a, 20b: first and second semiconductor portions, 21-24: first to fourth regions, 41: first insulating member, 41p: first insulating portion, 51-53: first to third electrodes, 60: base, 60S: nitride member, 61, 62: first and second nitride layers, 63: stacked body, 63a, 63b: first and second nitride films, 110, 111: semiconductor device, 210, 211: wafer, A0: supply amount, A1-A3: first to third supply amounts, C(Al): concentration, C1-C4: first to fourth Al composition ratios, D1, D2: first and second directions, G0: supply amount, L21: first lattice spacing, Lz: lattice spacing, OP1 to OP3: first to third treatments, Rc: contact resistance, SPL1 to SPL4: first to fourth samples, pZ: position, t1 to t4: first to fourth thicknesses, tm: time, μ: electron mobility

Claims

1. a substrate; Al ｘ１ Ga １－ｘ１ a first semiconductor layer including N (0≦x1<1); Al ｘ２ Ga １－ｘ２ a second semiconductor layer including N (x1<x2<1); Equipped with the first semiconductor layer is located between the substrate and the second semiconductor layer in a first direction from the substrate to the second semiconductor layer; the second semiconductor layer includes a first region, a second region, a third region, and a fourth region; the first region is between the first semiconductor layer and the third region, the second region is between the first region and the third region, the fourth region is between the first semiconductor layer and the first region, a fourth Al composition ratio in the fourth region increases in a direction from the first semiconductor layer to the first region, a second Al composition ratio in the second region is lower than a third Al composition ratio in the third region; A wafer, wherein the first Al composition ratio in the first region is higher than the second Al composition ratio.

2. the third Al composition ratio is an average value of the Al composition ratio in the third region in the first direction, the second Al composition ratio is less than 0.9 times the third Al composition ratio, 2. The wafer according to claim 1, wherein the first Al composition ratio is 0.9 times or more the third Al composition ratio.

3. 3. The wafer according to claim 2, wherein the first Al composition ratio is equal to or less than twice the third Al composition ratio.

4. 3. The wafer according to claim 2, wherein the first Al composition ratio is 1.2 times or less than the third Al composition ratio.

5. 3. The wafer according to claim 2, wherein the fourth Al composition ratio varies between 0.1 times the third Al composition ratio and 0.9 times the third Al composition ratio.

6. a first thickness in the first direction of the first region is smaller than a third thickness in the first direction of the third region; The wafer according to claim 1 , wherein the second thickness in the first direction of the second region is thinner than the third thickness.

7. The wafer according to claim 6 , wherein a fourth thickness in the first direction of the fourth region is equal to or less than the sum of the first thickness and the second thickness.

8. 8. The wafer according to claim 1, wherein the first lattice spacing in the first direction in the first region is 0.254 nm or more and 0.256 nm or less.

9. The wafer according to claim 1; A first electrode; A second electrode; A third electrode; Equipped with a second direction from the first electrode to the second electrode intersects with the first direction; a position of the third electrode in the second direction is between a position of the first electrode in the second direction and a position of the second electrode in the second direction; the second semiconductor layer includes a first semiconductor portion and a second semiconductor portion; a direction from the first semiconductor portion to the second semiconductor portion is along the second direction; the first electrode is electrically connected to the first semiconductor portion; The second electrode is electrically connected to the second semiconductor portion.

10. Al ｘ１ Ga １－ｘ１ a first process is performed on a first semiconductor layer containing N (0≦x1<1) using a first source gas containing Al, and the first source gas is supplied at a first supply amount during the first process; a second process is performed after the first process, and the first source gas is not used in the second process, or a second supply amount of the first source gas in the second process is smaller than the first supply amount; After the second process, a third process is performed using the first source gas and a second source gas containing Ga to form Al ｘ２ Ga １－ｘ２ forming a portion of the second semiconductor layer containing N (x1<x2<1);

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