Memory system and control method

Abstract

To improve resistance to a burst error.SOLUTION: For each I of 1 or more and I or less, the memory controller generates Mi code words each including a parity having a size of Ni, and divides each of the parities included in the Mi code words into K partial parities, determination processing of determining K * A code words from Mi code words and K or less partial parities of the K * A code words is executed for Mi pieces of write information, a partial parity is selected from the K * A code words, Mi pieces of write information including the selected partial parity are generated, and continuous addresses of a nonvolatile memory are assigned to the K or less partial parities included in each of the Mi pieces of write information. The memory controller executes the determination processing so that the number of pieces of write information in which the sizes of the plurality of partial parities included therein match becomes larger.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a memory system and a control method. [Background technology]

[0002] In a memory system, in order to protect data stored in a memory such as a NAND flash memory, error correction coded data is stored in the memory. Therefore, when reading data stored in the memory, the error correction coded data (also called a received word) read from the memory is decoded to restore the data before being error correction coded.

[0003] Error-correcting codes can sometimes cause burst errors, where errors are concentrated in consecutive locations on the storage medium. To address this issue, memory systems have proposed various features to prevent errors from concentrating in a single codeword. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2021-034769 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the embodiments of the present invention is to provide a memory system and a control method that can further improve the resistance to burst errors. [Means for solving the problem]

[0006] The memory system of the embodiment includes a memory controller. The memory controller has a size of N for each i between 1 and I. i M each containing parity i Generate M codewords iEach parity in each codeword is divided into K partial parities, and M i For each written piece of information, M i A decision process is performed to determine K×A code words from the code words and K or less partial parities of the K×A code words, select partial parities from the K×A code words, and i Generate writing information, and i Contiguous addresses in the nonvolatile memory are assigned to the K or less partial parities included in each of the write information. The memory controller performs a determination process so that the number of write information pieces that contain the same size partial parities is larger. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram of a memory system according to an embodiment. [Figure 2] FIG. 2 is a block diagram of an encoding / decoding unit according to the embodiment. [Figure 3] FIG. 1 is a diagram for explaining a configuration example. [Figure 4] FIG. 10 is a diagram showing an example of a word to be processed. [Figure 5] FIG. 10 is a diagram showing an example of component code numbers included in words of each cycle. [Figure 6] FIG. 10 is a diagram showing an example of pseudocode. [Figure 7] FIG. 10 is a diagram showing the numbers and number of bits of component codes included in the words of each cycle. [Figure 8] FIG. 10 is a diagram for explaining a situation in which burst error resistance cannot be guaranteed. [Figure 9] FIG. 10 is a diagram showing examples of words generated by the configuration example. [Figure 10] FIG. 10 is a diagram showing another example of a word generated by the configuration example. [Figure 11] FIG. 10 is a diagram showing examples of generated words. [Figure 12] FIG. 10 is a diagram showing an example of pseudocode. [Figure 13] FIG. 10 is a diagram showing an example of a word generated in the embodiment. [Figure 14] FIG. 10 is a diagram showing an example of a word generated in the embodiment. [Figure 15] FIG. 10 is a diagram showing an example of a word generated in the embodiment. [Figure 16] FIG. 10 is a diagram showing an example of a situation in which burst error resistance cannot be guaranteed. [Figure 17] FIG. 10 is a diagram showing examples of generated words. [Figure 18] 10 is a flowchart illustrating an example of encoding processing according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A memory system according to an embodiment will be described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments.

[0009] (First embodiment) Fig. 1 is a block diagram showing a schematic configuration example of a memory system according to the first embodiment. As shown in Fig. 1, the memory system 1 includes a memory controller 10 and a nonvolatile memory 20. The memory system 1 can be connected to a host 30, and Fig. 1 shows the memory system 1 connected to the host 30. The host 30 may be, for example, an electronic device such as a personal computer or a mobile terminal.

[0010] The nonvolatile memory 20 is a nonvolatile memory that stores data nonvolatilely, such as a NAND memory. In the following description, a case where a NAND memory is used as the nonvolatile memory 20 will be exemplified, but it is also possible to use storage devices other than a NAND memory, such as a three-dimensional structure flash memory, a ReRAM (Resistance Random Access Memory), or an FeRAM (Ferroelectric Random Access Memory), as the nonvolatile memory 20. Furthermore, it is not essential that the nonvolatile memory 20 be a semiconductor memory, and this embodiment can also be applied to various storage media other than semiconductor memories.

[0011] The memory system 1 may be a memory card or the like in which the memory controller 10 and the nonvolatile memory 20 are configured as one package, or may be an SSD (Solid State Drive) or the like.

[0012] The memory controller 10 controls writing to the nonvolatile memory 20 in accordance with a write request from the host 30. The memory controller 10 also controls reading from the nonvolatile memory 20 in accordance with a read request from the host 30. The memory controller 10 includes a host I / F (host interface) 15, a memory I / F (memory interface) 13, a control unit 11, an encoding / decoding unit (codec) 14, and a data buffer 12. The host I / F 15, the memory I / F 13, the control unit 11, the encoding / decoding unit 14, and the data buffer 12 are interconnected by an internal bus 16. Some or all of the operations of the components of the memory controller 10 may be realized by a CPU (Central Processing Unit) executing firmware, or may be realized by hardware.

[0013] The host I / F 15 is a circuit that performs processing in accordance with the interface standard with the host 30 and outputs commands received from the host 30, user data to be written, etc. to the internal bus 16. The host I / F 15 also transmits user data that has been read and restored from the nonvolatile memory 20, responses from the control unit 11, etc. to the host 30.

[0014] The memory I / F 13 is a circuit that performs a write process to the nonvolatile memory 20 based on an instruction from the control unit 11. The memory I / F 13 also performs a read process from the nonvolatile memory 20 based on an instruction from the control unit 11.

[0015] The control unit 11 performs overall control of each component of the memory system 1. When the control unit 11 receives an instruction from the host 30 via the host I / F 15, it performs control in accordance with the instruction. For example, the control unit 11 instructs the memory I / F 13 to write user data and parity to the nonvolatile memory 20 in accordance with the instruction from the host 30. The control unit 11 also instructs the memory I / F 13 to read user data and parity from the nonvolatile memory 20 in accordance with the instruction from the host 30.

[0016] Furthermore, when the control unit 11 receives a write request for user data from the host 30, it accumulates the user data in the data buffer 12 and determines a storage area (memory area) for the user data in the nonvolatile memory 20. That is, the control unit 11 manages the write destination of the user data. The correspondence between the logical address of the user data received from the host 30 and the physical address indicating the storage area on the nonvolatile memory 20 where the user data is stored is stored as an address conversion table.

[0017] Furthermore, when the control unit 11 receives a read request from the host 30, it converts the logical address specified by the read request into a physical address using the address conversion table described above, and instructs the memory I / F 13 to read from the physical address.

[0018] In NAND memory, data is generally written and read in units of data called pages, and erased in units of data called blocks. In this embodiment, a plurality of memory cells connected to the same word line are called a memory cell group. If the memory cells are single-level cells (SLC), one memory cell group corresponds to one page. If the memory cells are multi-level cells (MLC), one memory cell group corresponds to multiple pages. Each memory cell is connected to both a word line and a bit line. Therefore, each memory cell can be identified by an address that identifies the word line and an address that identifies the bit line.

[0019] The data buffer 12 temporarily stores user data received by the memory controller 10 from the host 30 before storing the data in the nonvolatile memory 20. The data buffer 12 also temporarily stores user data read from the nonvolatile memory 20 before transmitting the data to the host 30. The data buffer 12 may be implemented using general-purpose memory such as an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory).

[0020] User data transmitted from the host 30 is transferred to the internal bus 16 and temporarily stored in the data buffer 12. The encoding / decoding unit 14 encodes the user data to generate code words. The encoding / decoding unit 14 also decodes received words, which are data read from the non-volatile memory 20, to restore the user data. Therefore, the encoding / decoding unit 14 includes an encoder 17 and a decoder 18. Note that the data encoded by the encoding / decoding unit 14 may include control data used inside the memory controller 10 in addition to the user data.

[0021] Next, the write process of this embodiment will be described. When writing user data to the nonvolatile memory 20, the control unit 11 instructs the encoder 17 to encode the user data. At that time, the control unit 11 determines a storage location (storage address) of the codeword in the nonvolatile memory 20, and also instructs the memory I / F 13 about the determined storage location.

[0022] The encoder 17 generates code words by encoding the user data in the data buffer 12 based on instructions from the control unit 11. Examples of encoding methods that can be used include encoding methods using algebraic codes such as BCH (Bose-Chaudhuri-Hocquenghem) codes and RS (Reed-Solomon) codes, as well as encoding methods (such as product codes) that use these codes as row- and column-oriented component codes. The memory I / F 13 controls the storage of code words in memory locations in the nonvolatile memory 20 instructed by the control unit 11.

[0023] Next, a description will be given of the processing performed when reading data from the nonvolatile memory 20 in this embodiment. When reading data from the nonvolatile memory 20, the control unit 11 specifies an address on the nonvolatile memory 20 and instructs the memory I / F 13 to read. The control unit 11 also instructs the decoder 18 to start decoding. In accordance with the instruction from the control unit 11, the memory I / F 13 reads data from the specified address in the nonvolatile memory 20 and inputs the read data to the decoder 18 as a received word. The decoder 18 decodes the received word, which is the data read from the nonvolatile memory 20.

[0024] Next, the error correction code (codeword) used in this embodiment will be described. In this embodiment, the encoder 17 generates a multidimensional error correction code. The error correction code to which this embodiment can be applied is not limited to a multidimensional error correction code. Here, a multidimensional error correction code refers to an error correction code in which at least one symbol, which is a constituent unit of the error correction code, is multiply protected by a plurality of smaller component codes. Furthermore, one symbol is composed of, for example, one bit (an element of a binary field) or an alphabet element of a finite field other than a binary field. For ease of explanation, the following description will be given taking as an example a binary error correction code in which one symbol is composed of one bit. In the explanation, there may be places where the terms symbol and bit are used interchangeably, but both mean the same thing.

[0025] An example of a multidimensional error correcting code is a product code. A product code has a structure in which each information symbol, which is a constituent unit of user data, is protected by a Hamming code including parity symbols of a predetermined parity length in both the row and column directions. That is, in a product code, all symbols are doubly protected by component codes in the row direction (referred to as dimension 1) and the column direction (referred to as dimension 2). Note that the multidimensional error correcting code is not limited to this, and may be, for example, a generalized low density parity check code (LDPC code). In general multidimensional error correcting codes, including generalized LDPC codes, the degree of protection may differ for each symbol, and component codes cannot be grouped into dimension 1 and dimension 2, but the present technology can be applied to such code configurations.

[0026] For simplicity, the following describes an example using a two-dimensional error-correcting code (product code) in which each symbol is protected by two component codes that can be grouped into dimension 1 and dimension 2. Each component code for each dimension includes one or more component codes determined for that dimension. Hereinafter, component codes corresponding to each dimension and including one or more component codes may be referred to as a component code group. For example, the component code group for dimension 1 includes p1 component codes, and the component code group for dimension 2 includes p2 component codes. Applicable error-correcting codes are not limited to this, and may also be a P-dimensional error-correcting code in which at least one symbol constituting the code is protected by P component code groups (P is an integer equal to or greater than 2). When expressed in terms of the number of component codes included in each component code group, a P-dimensional error-correcting code is protected by Q component codes (Q is the sum of pi (1≦i≦P), P is an integer equal to or greater than 2, and pi is the number of component codes in the i-th dimension).

[0027] Next, a configuration example of the encoding / decoding unit 14 that encodes and decodes a product code will be described. Fig. 2 is a block diagram showing an example of a detailed functional configuration of the encoding / decoding unit 14 of the first embodiment. As shown in Fig. 2, the encoding / decoding unit 14 includes a parity memory 121, a correspondence storage unit 122, a word register 123, an address calculation unit 101, and a selection unit 102 in addition to an encoder 17 and a decoder 18.

[0028] The encoder 17 generates a codeword, which is a product code, by performing error correction encoding on the user data received from the host. The encoder 17 generates a parity of the user data for each of the multiple component codes that make up the product code.

[0029] For example, the encoder 17 may generate a vector of size N for each integer i between 1 and I (I is an integer greater than or equal to 1). i (N i M each containing a parity where i pieces (M i In this embodiment, a case where I is 1 will be described. That is, in this embodiment, a case where the parity size N1 of a plurality of component codes is the same will be described. Note that an example where I is 2 or more and component codes with different parity lengths will be described in the third embodiment.

[0030] Hereinafter, the size of the parity may be referred to as the parity length. The total number of component codes having a parity length of N1 is represented as M1 (M1 is an integer equal to or greater than 2). The total number M1 corresponds to the number p1 of component codes in dimension 1 or the number p2 of component codes in dimension 2. When the parities for dimension 1 and dimension 2 are written together to nonvolatile memory 20, the total number M1 may be the sum of the number p1 of component codes in dimension 1 and the number p2 of component codes in dimension 2.

[0031] The parity memory 121 is a memory for storing parity for each of a plurality of component codes generated by the encoder 17. The parity memory 121 stores, for example, the parity for one component code for each address.

[0032] The address calculation unit 101 calculates the address of the parity memory 121 that stores the parity of each component code.

[0033] The word register 123 is a register for storing words. A word corresponds to write information, which is a unit of writing to the nonvolatile memory 20. In this embodiment, one of a plurality of partial parities obtained by dividing the parity into K pieces (K is an integer of 2 or more) is selected from each of a plurality of component codes, and a word is generated so as to include the selected partial parity.

[0034] The correspondence storage unit 122 stores correspondence information for generating words. The correspondence information is, for example, information that defines, for each of M1 words, K×A code words (where A is an integer equal to or greater than 1) and one or more partial parities to be included in the word. The following mainly describes an example in which A is 1.

[0035] The selection unit 102 selects partial parities using the correspondence information and performs a process of generating words. For example, the selection unit 102 divides each of the parities included in the M1 code words into K partial parities. Each of the K partial parities has a size common to the M1 code words.

[0036] The selection unit 102 selects K or less partial parities to be used to generate the x-th word (x-th word) from among the M1 words in accordance with the correspondence information. The selection unit 102 generates the x-th word so as to include the selected partial parities. After the M1-th word (M1-th word) is generated, the process returns to the first and is repeated. In other words, word generation using the correspondence information is performed in units of M1 words. Details of the word generation process using the correspondence information will be described later.

[0037] The encoding / decoding unit 14 assigns consecutive addresses in the nonvolatile memory 20 to the K or less partial parities included in each of the M1 words. The nonvolatile memory 20 stores the M iMemorize the words.

[0038] Next, examples of measures against burst errors will be described. First, a configuration example E1 of measures against burst errors will be described. Fig. 3 is a diagram for explaining the configuration example E1.

[0039] 3 shows an example of a product code in which the number p2 of column-oriented component codes 301 is 52 and the number p1 of row-oriented component codes 302 is 48. The column-oriented component codes 301 include parity 311. The row-oriented component codes 302 include parity 312. In this embodiment, the parities 311 and 312 are to be given burst error resistance. Burst error resistance for user data is realized by a separate function.

[0040] Furthermore, for example, the control unit 11 can be configured to have a function of limiting burst errors to occur only in bit units of a specific size (for example, in units of 4 bits) from the beginning of the address. In this embodiment, the control unit 11 is assumed to have a function of limiting burst error occurrence to 4-bit units. Therefore, below, we will explain measures against burst errors that are 4 bits in size and occur at addresses 4n, 4n+1, 4n+2, and 4n+3 (n is an integer equal to or greater than 0).

[0041] In the following, the column-wise parity 311 will be described as an example, but the same procedure can be applied to the row-wise parity 312. In configuration example E1, the parity length of the parity of each component code is 32 bits. The size of word 321 of parity 311 is also 32 bits. That is, word 321 is generated so as to include 8-bit partial parity selected from each of the four component codes (component codes of columns 0 to 3). The component code number corresponds to the column position, for example.

[0042] The addresses (bit positions) of the bits included in word 321 are assigned so that they are not consecutive within the same component code. This makes it possible to configure so that even if a 4-bit burst error occurs, which is the same length as the number of component codes (4) that make up word 321, no errors of two or more bits will occur in one component code. For example, a 4-bit burst error that occurs in bit group 331 stored in bit positions 4 to 7 is distributed one bit at a time to four component codes.

[0043] Although the above is an example in which the number of component codes constituting word 321 and the bit length of the burst error are 4 (K=4), the same discussion applies even if other values ​​are used.

[0044] 3 shows an example of a word 321 processed in the first cycle (hereinafter, cycle C0). In each cycle, different component codes are selected, and a word is generated that includes 8 bits of partial parity selected from each of the selected component codes. In cycle C0, the 32-bit word 321 is stored in bit positions (addresses) 0 to 31.

[0045] 4 is a diagram further illustrating an example of word 321b processed in the cycle following cycle C0 (hereinafter referred to as cycle C1). In cycle C1, the component code in column 4 (component code number 4) is selected instead of the component code in column 0 (component code number 0) selected in cycle C0. In cycle C1, the 32-bit word 321b is stored in bit positions (addresses) 32 to 63.

[0046] FIG. 5 is a diagram showing an example of the numbers of component codes included in the words of each cycle. FIG. 5 shows an example of the numbers of four component codes included in seven words corresponding to seven cycles. The parity of each component code is divided into four (K=4) partial parities, and each of the four partial parities is included in four mutually different words. In other words, the partial parities obtained by dividing the parity of each component code are output in any four cycles. In configuration example E1, the parity of each component code, totaling 32 bits, is output in 8-bit increments over four cycles.

[0047] For example, the four partial parities corresponding to the component code numbered 0 are included in the words numbered 0, 4, 5, and 6, and are therefore output in the 0th, 4th, 5th, and 6th cycles. Figure 5 shows an example in which the number of divisions is 4 (K=4), but the number of divisions may be a value other than 4.

[0048] If the number of component codes is seven, all partial parities of the seven component codes (numbered 0 to 6) are output in seven cycles as shown in Fig. 5. The number of component codes is not limited to seven and may be any other value. Whatever the value, all partial parities included in each component code are output in the same number of cycles as the number of divisions.

[0049] In the configuration example E1, a method (algorithm) for assigning component codes to each word (cycle) as shown in Fig. 5 will be described. In the configuration example E1, a method (hereinafter referred to as method Al-1) for obtaining the following output using the following input and constraints on the input is applied. input: The number of component codes that make up the word, K (K=4 in the example in Figure 5) The number of component codes M (in the example of Figure 5, M=7, and the component code numbers are 0 to 6) Parity length N of component code (N=32 in configuration example E1) Input constraints: N%K must be 0 output: The component code number selected for each index j in each word (word numbers are 0, 1, 2, ...)

[0050] The index j is a value indicating the position of the partial parity that constitutes the word, and takes a value from 0 to K-1 (if K=4, j=0 to 3). In the example of Figure 5, for word number 3, the index j and the component code numbers correspond as follows: j=0: Component code number = 4 j=1: component code number = 5 j=2: Component code number = 6 j=3: Component code number = 3

[0051] 6 is a diagram showing an example of pseudocode 601 for realizing method Al-1. Note that Fig. 6 shows an example in the case where K=4.

[0052] B represents the number of the component code to be output for each word. Since K=4, the initial value of B is set by the four numbers in ascending order in the first line.

[0053] "next_cmp" on the third line represents the number of the component code to be selected next. "next_j" on the fourth line represents the index j to which the next component code will be assigned. "W" on the fifth line represents the number of words. W=M, and the number of words is equal to the number M of component codes.

[0054] In line 9, index j is selected in ascending order. In line 10, the component code numbers are selected in ascending order. Exceptionally, the component codes with small numbers 0, 1, and 2 are also selected for words with large numbers (4, 5, and 6 in the example in Figure 5).

[0055] Using the method Al-1 shown in FIG. 6, the selection unit 102 selects in order the component codes for which parity is to be output in each cycle.

[0056] FIG. 7 is a diagram showing the number and number of bits of the component codes included in the word of each cycle. FIG. 7 corresponds to FIG. 5 in which the number of bits of the partial parity selected from each component code is added. In configuration example E1, the parity length of each component code is fixed at 32 bits, and the partial parity obtained by dividing the 32-bit parity into four is all 8 bits. Therefore, for all words, the word contains four partial parities, and the number of bits of each partial parity is 8 bits.

[0057] The information shown in FIG. 7 can be interpreted as corresponding information. That is, the information in FIG. 7 corresponds to correspondence information that defines, for each of seven (M1=7) words, four (K=4) code words (component codes) and one or more (four in configuration example E1) partial parities to be included in the word. The correspondence information may be calculated in advance and stored in the correspondence storage unit 122. In this case, the selection unit 102 reads the correspondence information stored in the correspondence storage unit 122 and performs a determination process to determine the partial parities to be included in each word using the read correspondence information. The determination process is a process of determining K×A code words from M1 code words for each of M1 words and determining K or less (K=4 in configuration example E1) partial parities from each of the selected K×A code words.

[0058] The selection unit 102 may generate correspondence information for each encoding process. For example, the selection unit 102 may execute a process of generating correspondence information before a process of generating words after receiving a write instruction from the control unit 11. In this case, the correspondence storage unit 122 may not be provided.

[0059] Here, an example of a decoding process when a burst error countermeasure such as that in the configuration example E1 is adopted will be described.

[0060] During decoding, words are obtained in ascending order of numbers by reading data from addresses (bit positions) in nonvolatile memory 20 in order from the smallest value. For example, data in word number 0 is written in addresses 0 to 31 in nonvolatile memory 20. Therefore, word number 0 is obtained by reading 32 bits of data in order from address 0, which has the smallest value.

[0061] Similarly, the data in word number 1 is written to addresses 32 to 61, and the data in word number 2 is written to addresses 62 to 95. Therefore, by further reading 32 bits of data in order starting from address 0, which has the smallest value, words number 1 and number 2 can be obtained.

[0062] For each word obtained, by referring to the correspondence information, the number of the component code for which the bit in the data of the word is a partial parity can be obtained for each bit constituting the data of the word. That is, for each component code, the parity data can be obtained from the data in the word. The decoder 18 performs a decoding process on each component code obtained in this way.

[0063] As described above, configuration example E1 is an example of a burst error countermeasure when the parity length is fixed at 32 bits. Therefore, even if configuration example E1 is applied to a parity length other than 32 bits, burst error resistance may not be guaranteed.

[0064] 8 is a diagram illustrating a situation in which burst error tolerance cannot be guaranteed. For example, suppose that the parity length of each component code is 21 bits, and the number of parity divisions K is 4. Also, for each component code, the 21-bit parity is selected in four cycles in the order of 6 bits, 6 bits, 6 bits, and 3 bits.

[0065] In this configuration, for example, in word number 3, the partial parity of component codes numbered 4, 5, and 6 is 6 bits each, but the partial parity of component code number 3 is 3 bits. Due to this mismatch in the number of bits, a situation may arise in which four consecutive addresses (bit positions) in non-volatile memory 20 cannot be assigned to four component codes. In the example of FIG. 8, of a 4-bit address group 801 corresponding to addresses 84 to 87, addresses 85 and 87 are assigned to component code number 5. Therefore, when a 4-bit burst error corresponding to addresses 84 to 87 occurs, the configuration is not such that two or more errors do not occur for one component code, and burst error resistance is not guaranteed.

[0066] Therefore, in configuration example E2 of this embodiment, configuration example E1 is improved so that burst error resistance can be obtained even when the parity length adjustment unit is other than 32 bits. For example, in configuration example E2, the algorithm for determining the bit position is expanded to accommodate parity lengths other than 32-bit units.

[0067] In the configuration example E2, the selection unit 102 executes the determination process so as to increase the number of words that include a plurality of partial parities with the same size.

[0068] FIG. 9 is a diagram showing an example of a word generated by configuration example E2. FIG. 9 is a diagram showing the component code numbers and the number of bits included in the word of each cycle. In configuration example E2, the selection unit 102 makes the parity lengths obtained from multiple component codes to generate a word as uniform as possible. For example, to unify the size of each partial parity of word number 3 to 3, the four partial parities of component codes 4, 5, 6, and 3 have the following sizes (bits) in the order of selection: ·Component code 4:6,6,3,6 ·Component code 5:6,3,6,6 ·Component code 6:3,6,6,6 ·Component code 3:6,6,6,3

[0069] The bit positions in the nonvolatile memory 20 of the word numbered 3 (third word) are 72 to 83 (12 bits in total). As shown on the right side of Fig. 9, a 3-bit address is assigned to each of the four component codes. Therefore, when a 4-bit burst error occurs, an error of 2 or more bits does not occur for one component code, and burst error resistance is guaranteed.

[0070] Even in the configuration example E2, the sizes of the partial parities included in some words may not match. In the example of Fig. 9, the final word 901 (word numbered 6) has a partial parity size of 3 or 6, and the sizes of the partial parities do not match.

[0071] Configuration example E2 can be applied to any division method and parity length as long as the "number of divisions" = "period of component code switching." Also, when the "number of component codes" % "number of divisions" = 0, the sizes of the multiple partial parities included in all words are the same. Therefore, burst error resistance is guaranteed for all words.

[0072] Fig. 10 is a diagram showing another example of a word generated by configuration example E2. Fig. 10 shows an example in which the number of component codes is 8, the number of divisions is 4, and the "number of component codes" % "number of divisions" = 0. Therefore, even in the final word 1001, for example, the size of the multiple partial parities included is 3, which is the same, ensuring burst error resistance.

[0073] When the number of component codes % "number of divisions" ≠ 0, burst error resistance decreases in some words (for example, near the final word). Figure 9 shows an example where the number of component codes is 7, the number of divisions is 4, and the number of component codes % "number of divisions" ≠ 0. Therefore, as described above, the sizes of multiple partial parities in the final word 901 do not match, and burst error resistance is not guaranteed.

[0074] Figures 9 and 10 are examples of dividing 21-bit parity into four partial parities of 6 bits, 6 bits, 6 bits, and 3 bits. The parity lengths of the four partial parities are not limited to this, and it can be generalized to the case of dividing into four partial parities of a bits, b bits, c bits, and d bits.

[0075] Figure 11 is a diagram showing an example of a word generated in such a generalized case. The left word group 1101 shows an example of each word when the number of component codes is 8. In this case, since the number of component codes % "the number of divisions" = 0, burst error tolerance is guaranteed for all words including, for example, the last word 1111.

[0076] The right word group 1102 shows an example of each word when the number of component codes is 7. In this case, since the number of component codes % "the number of divisions" ≠ 0, the parity lengths of the partial parities may not match in the word group 1112 including, for example, three words from the last word. That is, burst error tolerance may not be guaranteed in the word group 1112. Incidentally, if the values of a, b, c, and d are made to match as much as possible, the number of words with matching parity lengths can be increased.

[0077] In this embodiment, for example, words can be generated as follows. ·Among M1 words, the words from the first to the m1-th (m1 is an integer satisfying 1 < m1 ≤ M1) have the same size of a plurality of partial parities included.

[0078] For example, in the word group 1101 of Figure 11, m1 = M1 = 8, that is, in all words from the first (number 0) to the eighth (number 7), the sizes of the partial parities are the same. In the word group 1102, m1 = 4, that is, in the words from the first (number 0) to the fourth (number 3), the sizes of the partial parities are the same. Incidentally, for the words from the fifth (= m1 + 1)-th to the eighth (= M1)-th, at least some of the sizes of the plurality of partial parities included do not match.

[0079] In configuration example E2, a method (algorithm) for assigning component codes to each word (cycle) as shown in Fig. 11 will be described. In configuration example E2, a method (hereinafter referred to as method Al-2) for obtaining the following output using the following input and constraints on the input is applied. input: The number of component codes that make up a word, K (K=4 in the example in Figure 11) Number of component codes M Parity length N of component code Parity division method: n0, n1, , nK-1 (in the example of Figure 11, n0=a, n1=b, n2=c, n3=d) Input constraints: n0+n1++nK-1=N output: Output Out1: The component code number selected for each index j in each word (word numbers are 0, 1, 2, ...) Output Out2: Parity length of the partial parity of the component code selected for each index j in each word (word numbers are 0, 1, 2, ...)

[0080] In the example of FIG. 11, for word number 5 of word group 1112, the index j and the parity length of the partial parity of the component code correspond as follows: j=0: Parity length = c j=1: Parity length=b j=2: Parity length=b j=3: Parity length=c

[0081] The method for determining the output Out1 is similar to the method Al-1 of the configuration example E1 (for example, the pseudo code 601 in FIG. 6), and therefore the description thereof will be omitted.

[0082] Fig. 12 is a diagram showing an example of pseudocode 1201 for realizing the process of obtaining output Out2 in method Al-2. Note that Fig. 12 shows an example in the case where K=4 and M (the number of component codes)=7.

[0083] L represents the parity length of the partial parity of the component codes output for each word. In the first line, the initial value of L is set by the first parity length (a) for all four component codes.

[0084] "ns" on the second line is an array that indicates how to divide the component code. For example, the parity length of each of the four partial parities is set in ns. The index of the array ns is 0 to 3.

[0085] "ps" on the third line is an array that indicates the index of the next array ns to be used for each component code. The initial value of the array ps is set on the third line. For example, for component code number 6, ps[6]=3. Therefore, for component code number 6, the parity length of the next partial parity is ns[3]=d.

[0086] In the fourth line, the initial value of L corresponding to word number 0, [a,a,a,a], is output.

[0087] In lines 6 to 12, L is determined for words numbered 1 and onwards, and the determined L is output. B in lines 8 and 9 represents the output Out1 (the number of the component code) required for index j.

[0088] By using technique Al-2 including the processing shown in FIG. 12, the selector 102 determines the parity length of the partial parity to be selected from the component code in each cycle.

[0089] In method Al-2, one or more words starting from the highest numbered word may have a mismatch in the parity length of the partial parity, as shown in the example of Fig. 11 (word group 1112). The position of the word with a mismatch in the parity length of the partial parity is not limited to this, and may be any position.

[0090] For example, a method (hereinafter referred to as method Al-2b) may be used in which one or more words with the smallest number value are words whose partial parity parity lengths do not match. Method Al-2b may be, for example, a method in which the ascending word numbers obtained by method Al-2 are replaced with descending numbers.

[0091] So far, we have explained an example where A is 1. If A is 2 or more, the above procedure is applied by replacing one component code with a component code set containing A component codes. For example, if A=4, the component code set contains four component codes. In this case, each word is generated to contain multiple partial parities of 4 x 4 x 6 bits or 4 x 4 x 3 bits. This results in 4 x 4 = 16 bits of burst error resistance.

[0092] (Second embodiment) In the second embodiment, the method of dividing the parity of the component codes is limited, thereby ensuring burst error resistance for all words including, for example, the final word.

[0093] In this embodiment, the difference in size between the K partial parities is equal to or less than 1. For example, the selection unit 102 in this embodiment divides the parity of the component code so that the difference in parity length between the K partial parities is equal to or less than 1. When K=4 and the parity length of the component code is 21, the selection unit 102 divides the parity of the component code into three 5-bit partial parities and one 6-bit partial parity.

[0094] 13 and 14 are diagrams showing examples of words generated in this embodiment. FIG. 13 shows an example where K=4, the parity length of the component codes is 21, and the number of component codes is 7. The final word (word number 6) includes one 5-bit partial parity and three 6-bit partial parities. The final word is assigned to a consecutive 21-bit address as shown on the right side of FIG. 13.

[0095] Figure 14 shows an example where K=4, the parity length of the component codes is 22, and the number of component codes is 7. The last word (word number 6) includes two 5-bit partial parities and two 6-bit partial parities. The last word is assigned to a consecutive 20-bit address as shown on the right side of Figure 14.

[0096] In FIG. 13 and FIG. 14, an address is represented by the offset (bit offset) of a bit position within the word.

[0097] In this embodiment, even in the last word, the difference in the number of bits is within 1, so a situation does not occur in which some of four consecutive addresses (bit positions) in the nonvolatile memory 20 are assigned to the same component code. In other words, it is possible to configure all words so that the burst error resistance is not reduced.

[0098] (Third embodiment) In the third embodiment, an example will be described in which I is 2 or more, that is, component codes with different parity lengths are generated. In the following, an example will be described in which I=2, but the same procedure can also be applied in the case in which I is 3 or more.

[0099] As a use case of this embodiment, for example, the following use case is assumed. A fixed size (for example, 368 bits) is given as the parity area. The parity area is a storage area for storing parity, such as the parity memory 121. The parity area size may be a multiple of 4 or a power of 2. It is desirable to appropriately set the number of component codes for each of the two parity lengths (for example, 21 bits and 22 bits) so that the parity area is used as much as possible. · The parity of the component codes provides burst error resistance.

[0100] In order to accommodate the use cases described above, in this embodiment, the numbers of component codes and parity lengths of a plurality of parity lengths are set, for example, as follows:

[0101] There are two parity lengths, 21 bits and 22 bits, the parity division number K is 4, and the size of the parity area is 368 bits. A parity area is assigned to each component code so that the number of component codes of each of the two parity lengths is four or more. For example, of the 368-bit parity area, a 21 x 4 bit area and a 22 x 4 bit area are assigned to the component code with a parity length of 21 bits and the component code with a parity length of 22 bits, respectively.

[0102] The remaining parity area is 196 (= 368 - (21 × 4 + 22 × 4)) bits. Component codes with a parity length of 21 bits and component codes with a parity length of 22 bits are assigned so that this remaining parity area is used up as much as possible. As shown below, by using two component codes with a parity length of 21 bits and seven component codes with a parity length of 22 bits, it is possible to use up all 196 bits. 196=21×2+22×7

[0103] By appropriately setting the parity lengths of multiple component codes (for example, by setting the difference in parity length to 1), the size of the area to be used can be adjusted in 1-bit increments. Therefore, unless the parity area size is extremely small, it is possible to allocate the parity area so that it is fully used.

[0104] The component codes of the two parity lengths may be any combination of component codes. For example, when I=2, the M1 codewords (component codes) may be BCH codes, and the M2 codewords (component codes) may be extended BCH codes. The extended BCH code is a code in which the size of the M1 codewords is increased by adding a bit representing the exclusive OR (XOR) of all bits contained in the M1 codewords.

[0105] The procedure of this embodiment will be further explained. When I=2, the encoder 17 generates a matrix of size N i M each containing parity i codewords are generated. In the following, an example where N1=21, M1=7, and N2=22 will be mainly described. N1, M1, and N2 are not limited to these values. Furthermore, the value of M2 is not particularly limited, but may be the same value as M1, 7, or a value different from M1.

[0106] In this embodiment, the correspondence storage unit 122 stores two pieces of correspondence information corresponding to i=1 and i=2, respectively. i This is information that defines, for each word, K×A code words and one or more partial parities to be included in the word.

[0107] In this embodiment, the selection unit 102 selects M i Each parity included in the codewords is divided into K partial parities. Each of the K partial parities is i The size is common to all codewords. i The selection unit 102 selects K or less partial parities to be used to generate the x-th word from among the words. The selection unit 102 generates the x-th word so as to include the selected partial parities.

[0108] Thus, in this embodiment, for each i, words are generated using the procedure of the first or second embodiment. Figure 15 is a diagram showing examples of words generated in this embodiment. Word group 1501 and word group 1502 show examples of words corresponding to i=1 and i=2, respectively.

[0109] Note that word group 1501 includes words generated by applying the procedure of the second embodiment to component codes with a parity length of 21 bits, and word group 1502 includes words generated by applying the procedure of the second embodiment to component codes with a parity length of 22 bits.

[0110] In the example of Figure 15, word group 1501 including words numbered 0 to 6 is generated, and then word group 1502 including words numbered 7 and onwards is generated. The order of the parity lengths of the component codes from which the word groups are generated is not limited to this and may be in any order. For example, after a word group for a component code with a parity length of 22 bits is generated, a word group for a component code with a parity length of 21 bits may be generated. Word groups for component codes with the same parity length may be generated consecutively.

[0111] 15, a burst error that occurred in the last word (word numbered 6) of word group 1501 is included in the component code numbered 7 contained in the first word (word numbered 7) of the next word group 1502. In other words, the 4-bit burst error 1510 is distributed across all different component codes.

[0112] 15, the above-mentioned method A1-2 is applied to both word group 1501 and word group 1502, that is, the method in which the parity lengths of the partial parities may not match for one or more words with the highest number values. In this application method, burst error resistance may not be guaranteed for subsequently generated words.

[0113] An example of a situation in which burst error tolerance cannot be guaranteed will be described using Figure 16. Note that a 4-bit burst error starts from the position where the remainder when the total bit offset is divided by 4 is 0. The total bit offset represents the bit offset counted from the first word (word numbered 0).

[0114] The first half of Fig. 16 corresponds to the component code and bit offset determined for, for example, word number 6 in word group 1501 in Fig. 15. For ease of explanation, Fig. 16 shows the bit offset counted from word number 6.

[0115] In the first half, 4-bit burst errors start at bit offsets 0, 4, 8, 12, 16, and 20. Burst errors 1601 to 1606 represent burst errors starting from each of these starting positions. In the first half, the burst errors are evenly distributed among the different component codes.

[0116] The latter half corresponds to, for example, the component code and bit offset determined for word number 7 in word group 1502 in Fig. 15. In the latter half, burst error resistance may not be obtained due to the influence of rows that include bits with no data in the former half.

[0117] In the example in the second half of Figure 16, a 4-bit burst error starts at bit offsets 24, 28, 32, etc. Therefore, of the 4-bit burst error 1611 starting at bit offset 24, for example, the 2-bit errors corresponding to bit offsets 24 and 27 are distributed to the component code numbered 8. In this way, the distribution of the burst error to the component codes becomes uneven, and burst error resistance may not be guaranteed.

[0118] To avoid such a situation, the method applied when generating successive word groups may be changed. For example, the above method Al-2 may be applied to the first word group (hereinafter also referred to as the first half) and the above method Al-2b may be applied to the next word group (hereinafter also referred to as the second half).

[0119] 17 shows an example of words generated when this method is used. Word group 1701 and word group 1702 include words generated by applying method Al-2 to component codes with a parity length of 22 bits. This method also makes it possible to configure the latter half of the code so that burst errors 1711 to 1715 are evenly distributed among multiple different component codes.

[0120] The application method of FIG. 17 corresponds to the following word generation method. ·I is 2. · Among the M1 words, the sizes of the multiple partial parities included in the words from the 1st to the m1th (m1 is an integer satisfying 1 < m1 < M1) are the same (in the example of FIG. 17, m1 = 6). · Among the M1 words, the sizes of at least some of the multiple partial parities included in the words from the (m1 + 1)th to the M1th are different. · Among the M2 words, the sizes of at least some of the multiple partial parities included in the words from the 1st to the m2th (m2 is an integer satisfying 1 ≤ m2 < M2) are different (in the example of FIG. 17, m2 = 1). · Among the M2 words, the sizes of the multiple partial parities included in the words from the (m2 + 1)th to the M2th are the same.

[0121] Next, the flow of the encoding process by the memory system 1 of the present embodiment will be described. FIG. 18 is a flowchart showing an example of the encoding process of the present embodiment.

[0122] When the encoder 17 is instructed by the control unit 11 to encode user data, for example, it acquires corresponding information from the corresponding storage unit 122 (step S101). The encoder 17 generates the parity of the user data and stores it in the parity memory 121 (step S102).

[0123] The selection unit 102 selects K component codes corresponding to the initial values according to the corresponding information (step S103). This process corresponds to, for example, the first line of the pseudo code 601.

[0124] The selection unit 102 acquires partial parities from the parities of the selected K component codes according to the corresponding information, and generates a word including the acquired multiple partial parities (step S104). The selection unit 102 stores the generated word in the word register 123 (step S105). The word stored in the word register 123 is further stored at the address for writing the next word in the non-volatile memory 20.

[0125] The encoder 17 determines whether all parities have been output (step S106). If all parities have not been output (step S106: No), the selector 102 replaces one of the selected component codes with the next component code according to the correspondence information (step S107), and returns to step S104 to repeat the process.

[0126] If all parities have been output (step S106: Yes), the encoder 17 ends the encoding process.

[0127] As described above, according to the embodiment, burst error resistance can be obtained even for parity with a parity length adjustment unit other than 32 bits, which means that burst error resistance can be further improved.

[0128] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0129] 1. Memory System 10 Memory Controller 11 Control section 12 Data Buffers 13 Memory I / F 14 Encoding / Decoding Unit 15 Host I / F 16 Internal Bus 17 Encoder 18 Decoder 20 Non-volatile memory 30 hosts 101 Address calculation unit 102 Selection section 121 Parity Memory 122 Corresponding memory unit 123 word registers

Claims

1. By performing error correction coding on the user data received from the host, for each integer i between 1 and I (I is an integer greater than or equal to 1), the size is N ｉ (N ｉ is an integer of 2 or more) ｉ pieces (M ｉ is an integer equal to or greater than 2), M ｉ The parities included in the code words are respectively expressed as M ｉ K partial parities (K is an integer of 2 or more) having a size common to the codewords; M is the unit of writing to the nonvolatile memory ｉ For each piece of written information, M ｉ selecting K×A code words (A is an integer equal to or greater than 1) from the code words, and performing a determination process to determine K or less partial parities from each of the selected K×A code words; K or less partial parities are selected from the determined K×A code words, and M each including the selected K or less partial parities is selected. ｉ generating the pieces of writing information; M ｉ assigning consecutive addresses in the nonvolatile memory to the K or less partial parities included in each of the write information; A memory controller; Based on the assigned address, ｉ a nonvolatile memory that stores the write information; Equipped with The memory controller performing the determination process so that the number of pieces of write information that include the plurality of partial parities that match in size is larger; Memory system.

2. The difference between the sizes of the K partial parities is 1 or less.

10. The memory system of claim 1.

3. M ｉ The codewords are product codes, 10. The memory system of claim 1.

4. I is 2, M １ The codewords are Bose-Chandhuri-Hocquenghem (BCH) codes, M ２ The codewords are extended BCH codes, 10. The memory system of claim 1.

5. I is 1, M １ Among the pieces of written information, the first to m １ th (m １ is 1 < m １ ≦M １ the write information includes a plurality of partial parities whose sizes are equal to each other, up to an integer satisfying the formula:

10. The memory system of claim 1.

6. I is 2, M １ Among the pieces of written information, the first to m １ th (m １ is 1 < m １ <M １ The write information includes a plurality of partial parities whose sizes are the same, and １ +1st to M １ the write information up to the first write information includes a plurality of partial parities whose sizes at least part of the partial parities are inconsistent, M ２ Among the pieces of written information, the first to m ２ th (m ２ is 1≦m ２ <M ２ The write information up to m (an integer satisfying the condition m) includes a plurality of partial parities whose sizes at least part of the included partial parities are inconsistent, and ２ +1st to M ２ the write information up to the first write information includes a plurality of partial parities whose sizes match each other, 10. The memory system of claim 1.

7. The memory controller M ｉ performing the determination process using correspondence information that defines, for each of the write information, the K×A code words and one or more partial parities to be included in the write information; 10. The memory system of claim 1.

8. A control method for controlling a nonvolatile memory, comprising: By performing error correction coding on the user data received from the host, for each integer i between 1 and I (I is an integer greater than or equal to 1), the size is N ｉ (N ｉ is an integer of 2 or more) ｉ pieces (M ｉ is an integer equal to or greater than 2), M ｉ The parities included in the code words are respectively expressed as M ｉ K partial parities (K is an integer of 2 or more) having a size common to the codewords; M is the unit of writing to the nonvolatile memory ｉ For each piece of written information, M ｉ selecting K×A code words (A is an integer equal to or greater than 1) from the code words, and performing a determination process to determine K or less partial parities from each of the selected K×A code words; K or less partial parities are selected from the determined K×A code words, and M each including the selected K or less partial parities is selected. ｉ generating the pieces of writing information; M ｉ assigning consecutive addresses in the nonvolatile memory to the K or less partial parities included in each of the write information; Based on the assigned address, ｉ storing the write information in a nonvolatile memory; This includes: the determination process is performed so that the number of pieces of write information that include the plurality of partial parities with the same size is larger. Control method.

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