Method for evaluating printed wiring board

Abstract

To evaluate not only the reliability of a route in a printed wiring board but also the reliability of a joining member existing between a mounted electronic component and the printed wiring board.SOLUTION: A method for evaluating a printed wiring board having a build-up portion including a plurality of resin insulating layers and conductor layers includes forming a joining member on a conductor layer on an uppermost surface of the printed wiring board, mounting a dummy component including a substrate and a conductor layer formed on an entire surface of the substrate on the printed wiring board in a state where the conductor layer and the joining member are connected to each other, and measuring a resistance of a path connected by the conductor layer of the dummy component to evaluate reliability of the path.SELECTED DRAWING: Figure 1C

Description

[Technical Field]

[0001] The present invention relates to a method for evaluating a printed wiring board for examining the reliability of a printed wiring board on which mounted components such as IC chips are mounted. [Background technology]

[0002] Conventionally, as a technique for evaluating the reliability of paths in a printed wiring board, a method for inspecting a printed wiring board is known, for example, from Patent Document 1. Fig. 3 is a diagram for explaining one embodiment of the conventional method for inspecting a printed wiring board disclosed in Patent Document 1.

[0003] 3, CS is a core substrate having, for example, a first surface CS1 on the upper side and a second surface CS2 on the lower side in the figure. BU1 is a first buildup section formed on the first surface CS1 of the core substrate CS and including a plurality of first insulating layers 52 and a plurality of first conductor layers 53 that are alternately stacked. BU2 is a second buildup section formed on the second surface CS2 of the core substrate CS and including a plurality of second insulating layers 62 and a plurality of second conductor layers 63 that are alternately stacked.

[0004] In the inspection method disclosed in Patent Document 1, in order to evaluate the reliability of the paths of stacked vias in a printed wiring board 51, paths to be evaluated (for example, R51 and R52 in FIG. 3) are short-circuited by connecting wiring 54 across the uppermost first conductor layer 53 of both. Then, a dummy substrate 55 simulating an electronic component to be actually mounted is mounted on the uppermost first conductor layer 53 via a bonding member 56, and a heat cycle test is performed on the printed wiring board 51. Before and after the heat cycle test, the resistance of the path R51 to be evaluated is found by measuring the resistance between P51 and P52 on the lowermost second conductor layer 63, and the resistance of the path R52 to be evaluated is found by measuring the resistance between P53 and P54 on the lowermost second conductor layer 63, and the reliability of the paths is evaluated based on the changes in the found resistance values. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2022-119300 Summary of the Invention [Problem to be solved by the invention]

[0006] The inspection method disclosed in Patent Document 1 performs reliability inspection using a dummy substrate 55 that does not have wiring, so there is no need to mount actual electronic components. However, the dummy substrate 55 is made of, for example, a glass substrate and does not have any special functions. Therefore, while it is possible to evaluate the reliability of the paths within the printed wiring board 51 to be evaluated, it is not possible to evaluate the reliability of the joining members 56 that connect the printed wiring board 51 and the electronic components. [Means for solving the problem]

[0007] The method for evaluating a printed wiring board of the present invention is a method for evaluating a printed wiring board having a build-up portion consisting of multiple resin insulating layers and conductor layers, and includes forming a bonding member on the conductor layer on the top surface of the printed wiring board, mounting a dummy component consisting of a substrate and a conductor layer formed over one entire surface of the substrate on the printed wiring board with the conductor layer and the bonding member connected, and measuring the resistance of the path connected by the conductor layer of the dummy component to evaluate the reliability of the path. [Brief explanation of the drawings]

[0008] [Figure 1A] 1 is a diagram for explaining an embodiment of a method for evaluating a printed wiring board according to the present invention. [Figure 1B] 1 is a diagram for explaining an embodiment of a method for evaluating a printed wiring board according to the present invention. [Figure 1C] 1 is a diagram for explaining an embodiment of a method for evaluating a printed wiring board according to the present invention. [Figure 1D] 1 is a diagram for explaining an embodiment of a method for evaluating a printed wiring board according to the present invention. [Figure 2] 10A and 10B are diagrams for explaining another embodiment of the method for evaluating a printed wiring board of the present invention. [Figure 3] 1A and 1B are diagrams for explaining an embodiment of a conventional method for inspecting a printed wiring board. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of a printed wiring board according to the present invention will be described with reference to the drawings. In the example shown in Figures 1A to 1D and 2, the dimensions of each component, particularly the height dimension, are shown as dimensions different from the actual dimensions in order to better understand the features of the present invention.

[0010] <One embodiment of the method for evaluating a printed wiring board of the present invention> FIG. 1A is a diagram illustrating one embodiment of a printed wiring board evaluation method of the present invention. In the printed wiring board evaluation method of the present invention, first, an evaluation printed wiring board 1, an example of which is shown in FIG. 1A, is prepared. In the evaluation printed wiring board 1 shown in FIG. 1A, CS is a core substrate having, for example, a first surface CS1 on the upper side and a second surface CS2 on the lower side in the figure. BU1 is a first buildup section formed on the first surface CS1 of the core substrate CS and including a plurality of first insulating layers 2 and a plurality of first conductor layers 3 that are alternately stacked. BU2 is a second buildup section formed on the second surface CS2 of the core substrate CS and including a plurality of second insulating layers 12 and a plurality of second conductor layers 13 that are alternately stacked.

[0011] 1B is a diagram illustrating one embodiment of the printed wiring board evaluation method of the present invention. In the printed wiring board evaluation method of the present invention, next, as shown in FIG. 1B, bonding members 4 are formed on the first conductor layer 3 on the uppermost surface of the printed wiring board 1. The bonding members 4 are formed separately on the first conductor layer 3. For example, bumps can be used as the bonding members 4, and they can be formed according to a conventionally known method for manufacturing solder bumps.

[0012] 1C is a diagram illustrating one embodiment of the printed wiring board evaluation method of the present invention. In the printed wiring board evaluation method of the present invention, as shown in FIG. 1C, a dummy component 23 is prepared, which is composed of a substrate 21 and a conductor layer 22 formed on one entire surface of the substrate 21. A silicon substrate or a glass substrate with a low thermal expansion coefficient is preferably used as the substrate 21 so as to simulate the thermal expansion coefficient of the electronic component to be actually mounted. Furthermore, a metal such as copper is preferably used as the conductor layer 22 so as to simulate the thermal expansion coefficient of the electronic component to be actually mounted.

[0013] 1C, the method for evaluating a printed wiring board of the present invention further includes mounting a dummy component 23 on printed wiring board 1 with its conductor layer 22 connected to bonding member 4 of printed wiring board 1. By mounting this dummy component 23 on bonding member 4 of printed wiring board 1, lands P1 to P4 formed of second conductor layer 13 on the bottom surface of printed wiring board 1 are electrically connected to one another via conductor layer 22 of dummy component 23, stacked vias in first buildup section BU1, vias in core substrate CS, and stacked vias in second buildup section BU2.

[0014] 1D is a diagram illustrating one embodiment of the method for evaluating a printed wiring board of the present invention. Next, in the method for evaluating a printed wiring board of the present invention, as shown in FIG. 1D, the evaluation of path R1 can be performed by measuring the resistance value between lands P1 and P2, and the evaluation of path R2 can be performed by measuring the resistance value between lands P3 and P4.

[0015] Specifically, a printed wiring board can be evaluated by subjecting a printed wiring board 1 mounted with dummy components 23 shown in FIG. 1C to a heat cycle test, followed by a continuity test to measure the resistance values ​​of each path R1 and R2 before and after the test. One example of a heat cycle test is to repeat 1,000 cycles of leaving the board at -65°C for 3 minutes and then at 130°C for 3 minutes. By measuring the resistance values ​​of each path before and after the heat cycle test, it is possible to evaluate the paths for open circuits and cracks.

[0016] <Another embodiment of the method for evaluating a printed wiring board according to the present invention> FIG. 2 is a diagram illustrating another embodiment of the printed wiring board evaluation method of the present invention. In the example shown in FIG. 2, instead of the printed wiring board 1 in which a first buildup layer BU1 and a second buildup layer BU2 are formed above and below a core substrate CS as shown in FIGS. 1A to 1D, a printed wiring board 41 is used that does not use a core substrate and is formed only with a single buildup layer BU1. In the printed wiring board evaluation method of the present invention shown in FIG. 2, similar to the printed wiring board evaluation method of the present invention shown in FIGS. 1A to 1D, a dummy component 23 consisting of a substrate 21 and a conductor layer 22 formed over one entire surface thereof is mounted on the first conductor layer on the top surface of the printed wiring board 41 via a bonding member 4. As a result, even if the paths R11 and R12 are not formed linearly but are bent along the way as shown in FIG. 2, the printed wiring board evaluation method of the present invention can be performed in the same manner as the embodiment shown in FIGS. 1A to 1D.

[0017] According to the above-described method for evaluating a printed wiring board of the present invention, by mounting a dummy component 23 consisting of a substrate 21 and a conductor layer 22 formed on one entire surface of the substrate 21 on the first conductor layer on the top surface of the printed wiring board via a bonding member 4, it is possible to evaluate not only the reliability of the paths within the printed wiring board but also the reliability of the bonding member 4 that exists between the mounted electronic component and the printed wiring board. Therefore, it is possible to evaluate the reliability of not only the paths within the printed wiring board but also the reliability of the bonding member 4 that bonds the mounted component. [Explanation of symbols]

[0018] 1, 41 Printed wiring board 2 First insulating layer 3 First conductor layer 4 Joint materials 12 Second insulating layer 13 Second conductor layer 21 PCB 22 Conductor layer 23 Dummy parts BU1 First build-up section BU2 Second build-up section CS core board CS1 1st page CS2 2nd page P1~P4 Land R1, R2, R11, R12 route

Claims

1. A method for evaluating a printed wiring board having a build-up portion made up of a plurality of resin insulating layers and conductor layers, comprising: forming a bonding member on the conductor layer on the top surface of the printed wiring board; Mounting a dummy component, which is made up of a substrate and a conductor layer formed on one entire surface of the substrate, on the printed wiring board in a state in which the conductor layer is connected to the bonding member; and measuring the resistance of a path connected by the conductor layer of the dummy component to evaluate the reliability of the path.

2. 2. The method for evaluating a printed wiring board according to claim 1, wherein the substrate of the dummy component is made of a silicon substrate or a glass substrate.

3. 3. The method for evaluating a printed wiring board according to claim 1, wherein the conductor layer of the dummy component is made of a metal such as copper.

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