Semiconductor device and power supply device

Abstract

To achieve fail-safe when an external terminal is short-circuited.SOLUTION: The control circuit 30 changes the voltage Vout in accordance with the first voltage Verr applied to the internal node n1, the current / voltage conversion device 40 connected between the external node COMP and the internal node n1, and the current generation circuit 50 causes the first current I1 to flow through the current / voltage conversion device 40 such that the second voltage Vcomp applied to the external node COMP matches a predetermined third voltage Vref1. n1.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a power supply device. [Background technology]

[0002] Some semiconductor devices have a terminal that can increase output power as the terminal voltage decreases, known as a low-active terminal. Other semiconductor devices have a terminal that can increase output power as the terminal voltage increases, known as a high-active terminal. For example, the phase compensation terminal of a typical power supply control IC (integrated circuit) is often a low-active terminal.

[0003] As an example of the related prior art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-164394

[0005] [overview] In conventional semiconductor devices, there is room for further consideration of measures to prevent short circuits between the low active terminal and the high active terminal.

[0006] For example, a semiconductor device according to the present disclosure includes an external terminal, an internal node, a control circuit configured to change an output depending on a first voltage applied to the internal node, a current / voltage conversion element connected between the external terminal and the internal node, and a current generating circuit configured to pass a first current through the current / voltage conversion element so as to match a second voltage applied to the external terminal with a predetermined third voltage. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing the overall configuration of a power supply device. [Figure 2] FIG. 2 is a diagram showing the overall configuration of the semiconductor device. [Figure 3] FIG. 3 is a diagram showing a comparative example of a semiconductor device. [Figure 4] FIG. 4 is a diagram showing the behavior of the comparative example when a ground fault occurs at an external terminal. [Figure 5] FIG. 5 is a diagram showing a first embodiment of a semiconductor device. [Figure 6] FIG. 6 is a diagram showing the behavior when a ground fault occurs at an external terminal in the first embodiment. [Figure 7] FIG. 7 is a diagram showing how the output current becomes excessive in the first embodiment. [Figure 8] FIG. 8 is a diagram showing a second embodiment of the semiconductor device. [Figure 9] FIG. 9 is a diagram showing how the output current is suppressed in the second embodiment. [Figure 10] FIG. 10 is a diagram showing a third embodiment of the semiconductor device.

[0008] [Detailed explanation] <Power supply> Figure 1 shows the overall configuration of power supply device A. In this example configuration, power supply device A is a switching power supply, a so-called DC (direct current) / DC converter, that steps down a DC input voltage Vin to generate a DC output voltage Vout. Power supply device A can be installed in a variety of applications, such as vehicles and industrial machinery.

[0009] Referring to this figure, the power supply device A includes a semiconductor device 1 and various discrete components, such as capacitors C1 to C4, an inductor L1, and resistors R1 to R3.

[0010] The semiconductor device 1 is a power supply control device, a so-called power supply control integrated circuit (IC), that can be the main controller of the power supply device A. The semiconductor device 1 has a plurality of external terminals, such as a bootstrap terminal BST, a phase compensation terminal COMP, a feedback terminal FB, a ground terminal PGND, a switch terminal SW, and an input terminal VIN, as means for establishing electrical connection with the outside of the device. Note that the semiconductor device 1 may also have external terminals other than those mentioned above.

[0011] The input terminal VIN is connected to a terminal to which an input voltage Vin is applied. A capacitor C1 is connected between the input terminal VIN and a ground terminal. The ground terminal PGND is connected to the ground terminal.

[0012] A first end of the capacitor C3 is connected to the bootstrap terminal BST. A second end of the capacitor C3 and a first end of the inductor L1 are connected to the switch terminal SW. A second end of the inductor L1 and a first end of each of the resistor R1 and the capacitor C2 are connected to the application terminal of the output voltage Vout. A second end of the resistor R1 and a first end of the resistor R2 are connected to the feedback terminal FB. A second end of each of the resistor R2 and the capacitor C2 are connected to the ground terminal.

[0013] Capacitor C3 functions as part of a bootstrap circuit that generates a bootstrap voltage Vbst that is higher than the switch voltage Vsw applied to the switch terminal SW. Inductor L1 and capacitor C2 function as part of a rectifying / smoothing circuit that rectifies and smoothes the pulsed switch voltage Vsw to generate the output voltage Vout. Resistors R1 and R2 function as a voltage divider circuit that divides the output voltage Vout to generate a feedback voltage Vfb (=Vout×R2 / (R1+R2)).

[0014] A first terminal of the resistor R3 is connected to the phase compensation terminal COMP. A second terminal of the resistor R3 is connected to a first terminal of the capacitor C4. A second terminal of the capacitor C4 is connected to the ground terminal. The resistor R3 and the capacitor C4 function as a phase compensation circuit for preventing oscillation of an amplifier 21 (described in detail later) built into the semiconductor device 1.

[0015] <Semiconductor device (overall configuration)> 2 is a diagram showing the overall configuration of the semiconductor device 1. The semiconductor device 1 of this configuration example includes an output circuit 10 and a feedback control circuit 20.

[0016] The output circuit 10, together with an external inductor L1 and capacitor C2, generates an output voltage Vout from an input voltage Vin. Referring to the figure, the output circuit 10 includes transistors 11 and 12. The transistors 11 and 12 may be N-channel transistors.

[0017] The drain of the transistor 11 is connected to the input terminal VIN. The source of the transistor 11 is connected to the switch terminal SW. The gate of the transistor 11 is connected to an application terminal of the upper gate drive signal G1. The transistor 11 is turned on when the upper gate drive signal G1 is at a high level (Vbst). The transistor 11 is turned off when the upper gate drive signal G1 is at a low level (Vsw). The transistor 11 functions as an upper switch element that forms a half-bridge output stage.

[0018] The drain of the transistor 12 is connected to the switch terminal SW. The source of the transistor 12 is connected to the ground terminal PGND. The gate of the transistor 12 is connected to an application terminal of the low-side gate drive signal G2. The transistor 12 is turned on when the low-side gate drive signal G2 is at a high level (Vreg). The transistor 12 is turned off when the low-side gate drive signal G2 is at a low level (PGND). The transistor 12 functions as a low-side switch element that forms a half-bridge output stage.

[0019] The feedback control circuit 20 controls the output circuit 10 so that the feedback voltage Vfb, which corresponds to the output voltage Vout, matches a predetermined reference voltage Vref.

[0020] Referring to this figure, the feedback control circuit 20 includes amplifiers 21 and 22, a soft start circuit 23, a ramp voltage generating circuit 24, a comparator 25, a controller 26, a driver 27, a current sensor 28, a capacitor C5, a diode D1, a transistor M1, and a resistor R4.

[0021] The amplifier 21 is an error amplifier that generates an error voltage Verr corresponding to the difference between a feedback voltage Vfb input from a feedback terminal FB to its non-inverting input terminal (+) and the lower of a reference voltage Vref input to its first inverting input terminal (-) and a soft-start voltage Vss input to its second inverting input terminal (-). The error voltage Verr decreases when the feedback voltage Vfb is lower than the reference voltage Vref or the soft-start voltage Vss. On the other hand, the error voltage Verr increases when the feedback voltage Vfb is higher than the reference voltage Vref or the soft-start voltage Vss. The output node of the amplifier 21 is connected to a phase compensation terminal COMP as an internal node n1. The amplifier 21 may be a transconductance amplifier, a so-called gm amplifier, that generates a current signal flowing through the phase compensation terminal COMP.

[0022] The amplifier 22 generates a control voltage Vc corresponding to the difference between the error voltage Verr input to its inverting input terminal (-) and the sense voltage Vcs input to its non-inverting input terminal (+). The control voltage Vc increases when the error voltage Verr is lower than the sense voltage Vcs, and decreases when the error voltage Verr is higher than the sense voltage Vcs. A resistor R4 and a capacitor C5 for phase compensation may be connected between the output node of the amplifier 22 and the ground terminal. The amplifier 22 may be a transconductance amplifier, a so-called gm amplifier, that generates a current signal flowing through the resistor R4 and the capacitor C5.

[0023] The soft start circuit 23 generates a soft start voltage Vss that rises gently at a predetermined slope when the semiconductor device 1 is started up. The soft start voltage Vss can be adjusted so that it exceeds the reference voltage Vref when a soft start time Tss has elapsed since the soft start voltage Vss started to rise.

[0024] The ramp voltage generating circuit 24 generates a ramp voltage Vr having a triangular or sawtooth waveform that repeatedly rises and falls in synchronization with a clock signal CK. The clock signal CK may be a square wave signal that is pulse-driven with a predetermined switching period Tsw.

[0025] The comparator 25 generates a duty signal S0 by comparing, for example, a control voltage Vc input to a non-inverting input terminal (+) with a ramp voltage Vr input to an inverting input terminal (-). The duty signal S0 goes high when the control voltage Vc is higher than the ramp voltage Vr. On the other hand, the duty signal S0 goes low when the control voltage Vc is lower than the ramp voltage Vr.

[0026] The controller 26 generates the upper control signal S1 and the lower control signal S2 in response to the clock signal CK and the duty signal S0. For example, the controller 26 may generate the upper control signal S1 and the lower control signal S2 so as to turn on the transistor 11 and turn off the transistor 12 at the timing when a pulse is generated in the clock signal CK. Alternatively, the controller 26 may generate the upper control signal S1 and the lower control signal S2 so as to turn off the transistor 11 and turn on the transistor 12 at the timing when the duty signal S0 falls from high to low, that is, at the timing when the ramp voltage Vr exceeds the control voltage Vc. In this way, the controller 26 may generate the upper control signal S1 and the lower control signal S2 using the clock signal CK as the on-timing determining signal and the duty signal S0 as the off-timing determining signal.

[0027] The driver 27 drives the output circuit 10 by generating an upper gate drive signal G1 and a lower gate drive signal G2 in response to an upper control signal S1 and a lower control signal S2. For example, the driver 27 sets the upper gate drive signal G1 to a high level (Vbst) when the upper control signal S1 is at a high level (Vreg), and sets the upper gate drive signal G1 to a low level (Vsw) when the upper control signal S1 is at a low level (GND). Furthermore, the driver 27 sets the lower gate drive signal G2 to a high level (Vreg) when the lower control signal S2 is at a high level (Vreg), and sets the lower gate drive signal G2 to a low level (PGND) when the lower control signal S2 is at a low level (GND).

[0028] The bootstrap voltage Vbst applied to the bootstrap terminal BST is generated by a diode D1, a transistor M1, and an external capacitor C3. The transistor M1 may be a P-channel type. The diode D1 may be the body diode of the transistor M1. The anode of the diode D1 and the drain of the transistor M1 are connected to a terminal to which a constant voltage Vreg is applied. The cathode of the diode D1 and the source of the transistor M1 are connected to the bootstrap terminal BST.

[0029] For example, when transistor 11 is off and transistor 12 is on, i.e., when switch voltage Vsw is low (PGND), transistor M1 is turned on. At this time, the constant voltage Vreg is charged across capacitor C3. Therefore, the bootstrap voltage Vbst becomes a voltage value (=PGND+Vreg) that is higher than switch voltage Vsw by the constant voltage Vreg.

[0030] On the other hand, when the transistor 11 is on and the transistor 12 is off, i.e., when the switch voltage Vsw is at a high level (Vin), the transistor M1 is turned off. At this time, the voltage across the capacitor C3 is maintained at approximately the constant voltage Vreg due to the law of conservation of charge. Therefore, the bootstrap voltage Vbst is a voltage value (=Vin+Vreg) that is higher than the switch voltage Vsw by the constant voltage Vreg.

[0031] The current sensor 28 generates a sense voltage Vcs according to the output current I flowing through the output circuit 10. For example, the current sensor 28 may detect the output current I flowing through the transistor 12. If a voltage mode control method is adopted instead of a current mode control method as the topology of the feedback control circuit 20, the amplifier 22 and the current sensor 28 may be omitted, and the error voltage Verr may be directly input to the non-inverting input terminal (+) of the comparator 25.

[0032] <Semiconductor device (comparison example)> 3 is a diagram showing a comparative example (i.e., a configuration example to be compared with the embodiments described later) of the semiconductor device 1. In this diagram, the peripheral circuits of the phase compensation terminal COMP, specifically, amplifiers 21 and 22 and a duty control circuit 30, are depicted as essential parts of the semiconductor device 1.

[0033] The duty control circuit 30 depicted downstream of the amplifier 22 can be understood as a circuit block that combines the aforementioned output circuit 10 (including the external inductor L1 and capacitor C2) and part of the feedback control circuit 20 (the controller 26 and the driver 27).

[0034] The duty control circuit 30 controls the on-duty Don of the output circuit 10 so that the output voltage Vout increases as the error voltage Verr applied to the phase compensation terminal COMP and, by extension, the internal node n1 decreases. Therefore, the phase compensation terminal COMP can be understood as a terminal that can increase the output voltage Vout as the terminal voltage decreases, a so-called low active terminal. The on-duty Don can be defined, for example, as the ratio of the on-period Ton of the transistor 11 to the switching period Tsw (Don=Ton / Tsw).

[0035] In the semiconductor device 1 of this comparative example, the phase compensation terminal COMP is directly connected to the internal node n1 to which the error voltage Verr is applied. Therefore, if a ground fault occurs at the phase compensation terminal COMP, the output voltage Vout may rise uncontrollably. Note that a ground fault in this specification can be understood as a short circuit to the ground terminal or an equivalent low-potential terminal.

[0036] 4 is a diagram showing the behavior of the semiconductor device 1 of this comparative example when a ground fault occurs at the phase compensation terminal COMP. The upper part of the diagram depicts the error voltage Verr, and the lower part of the diagram depicts the output voltage Vout.

[0037] As shown in the figure, when a ground fault occurs at the phase compensation terminal COMP, the error voltage Verr drops to 0 V. Therefore, the duty control circuit 30 raises the on-duty Don of the output circuit 10 to its maximum. As a result, the output feedback control for matching the output voltage Vout with the target value Vtarget no longer works, and the output voltage Vout rises to close to the input voltage Vin. When this uncontrollable state occurs, it becomes difficult to ensure the safety of downstream circuits that receive the output voltage Vout.

[0038] In view of the above considerations, a first embodiment capable of realizing a fail-safe in the event of a ground fault at the phase compensation terminal COMP will be proposed below.

[0039] <Semiconductor Device (First Embodiment)> 5 is a diagram showing a first embodiment of the semiconductor device 1. The semiconductor device 1 of this embodiment is based on the above-mentioned comparative example (FIG. 3) and further includes a current / voltage conversion element 40 and a current generation circuit 50.

[0040] The current / voltage conversion element 40 is connected between the phase compensation terminal COMP and the internal node n1. The current / voltage conversion element 40 may be, for example, a resistor element having a resistance value R.

[0041] The current generating circuit 50 causes a current I1 to flow through the current / voltage conversion element 40 so that the terminal voltage Vcomp applied to the phase compensation terminal COMP matches a predetermined reference voltage Vref1. Referring to the figure, the current generating circuit 50 includes a transistor 51 and an amplifier 52. The transistor 51 may be an N-channel type.

[0042] The transistor 51 is provided on a path through which the current I1 flows. Specifically, the drain of the transistor 51 is connected to the application terminal of the constant voltage Vreg. The source of the transistor 51 is connected to the internal node n1. Therefore, the current I1 can flow from the application terminal of the constant voltage Vreg to the internal node n1 via the transistor 51, and further flow from the internal node n1 to the phase compensation terminal COMP via the current / voltage conversion element 40.

[0043] The amplifier 52 drives the gate of the transistor 51 so that the terminal voltage Vcomp input to the inverting input terminal (-) from the phase compensation terminal COMP matches the reference voltage Vref1 input to the non-inverting input terminal (+). Therefore, when the terminal voltage Vcomp is lower than the reference voltage Vref1, a current I1 having a magnitude corresponding to the difference between the terminal voltage Vcomp and the reference voltage Vref1 (=Vref1-Vcomp) flows through the transistor 51. On the other hand, when the terminal voltage Vcomp is higher than the reference voltage Vref1, the transistor 51 is turned off, and the path through which the current I1 flows is blocked.

[0044] 6 is a diagram showing the behavior of the semiconductor device 1 of the first embodiment when a ground fault occurs at the phase compensation terminal COMP. The upper part of the diagram depicts the terminal voltage Vcomp (solid line) and the error voltage Verr (dashed line). The lower part of the diagram depicts the output voltage Vout.

[0045] When a ground fault occurs at the phase compensation terminal COMP, the terminal voltage Vcomp drops to 0V, as in the case of FIG. 4. At this time, the current generating circuit 50 generates a current I1 in an attempt to raise the terminal voltage Vcomp to the reference voltage Vref1. This causes a potential difference ΔV (=I1×R) to occur between both ends of the current / voltage conversion element 40. In other words, a potential difference ΔV is created between the error voltage Verr and the terminal voltage Vcomp. Therefore, even if the terminal voltage Vcomp is stuck at 0V, the error voltage Verr will not follow the terminal voltage Vcomp and will not drop. As a result, the output voltage Vout can be maintained in a controllable state.

[0046] For example, as shown in the figure, the potential difference ΔV between the error voltage Verr and the terminal voltage Vcomp may be set to be equal to or greater than the equilibrium value Verr0 of the error voltage Verr. The equilibrium value Verr0 can be understood as the error voltage Verr obtained when the output voltage Vout matches the target value Vtarget. With this setting, the error voltage Verr becomes higher than the equilibrium value Verr0 when a ground fault occurs at the phase compensation terminal COMP. Therefore, the output voltage Vout is reduced from the target value Vtarget, thereby improving the safety of downstream circuits that receive the output voltage Vout.

[0047] 7 is a diagram showing how the output current I becomes excessive when a ground fault occurs at the phase compensation terminal COMP in the semiconductor device 1 of the first embodiment. The upper part of the diagram depicts the terminal voltage Vcomp (solid line) and the error voltage Verr (dashed line). The middle part of the diagram depicts the output voltage Vout. The lower part of the diagram depicts the output current I. The direction of the output current I from the switch terminal SW toward the transistor 12 is defined as the positive direction.

[0048] As shown in the figure, in the ground fault protection operation of the phase compensation terminal COMP, the output voltage Vout is reduced, causing the output current I to fluctuate sharply. As a result, there is a risk that the output current I may exceed the allowable upper limit of the semiconductor device 1.

[0049] In view of the above considerations, a second embodiment will be proposed below that can suppress the output current I that accompanies the ground fault protection operation of the phase compensation terminal COMP.

[0050] <Semiconductor Device (Second Embodiment)> 8 is a diagram showing a second embodiment of the semiconductor device 1. The semiconductor device 1 of this embodiment is based on the first embodiment (FIG. 5) described above, with modifications made to the configuration and operation of the current generating circuit 50.

[0051] The current generating circuit 50 adjusts the driving capability of the amplifier 52 so that the terminal voltage Vcomp matches a predetermined reference voltage Vref2. For example, the current generating circuit 50 further includes a transistor 53 and an amplifier 54 in addition to the transistor 51 and amplifier 52 described above.

[0052] The transistor 53 is provided on a path through which a current I2 flows to adjust the driving capability of the amplifier 52. For example, the driving capability of the amplifier 52 decreases as the current I2 increases, and increases as the current I2 decreases. In other words, the current I1 is reduced as the current I2 increases.

[0053] The amplifier 54 drives the gate of the transistor 53 so that the error voltage Verr input from the internal node n1 to the inverting input terminal (-) matches the reference voltage Vref2 input to the non-inverting input terminal (+). Therefore, when the error voltage Verr is higher than the reference voltage Vref2, a current I2 having a magnitude corresponding to the difference between the error voltage Verr and the reference voltage Vref2 (=Verr-Vref2) flows through the transistor 53. On the other hand, when the error voltage Verr is lower than the reference voltage Vref2, the transistor 53 is turned off, and the path through which the current I2 flows is blocked.

[0054] 9 is a diagram showing how the output current I is suppressed when a ground fault occurs at the phase compensation terminal COMP in the semiconductor device 1 of the second embodiment. The upper part of the diagram depicts the terminal voltage Vcomp (solid line) and the error voltage Verr (dashed line). The middle part of the diagram depicts the output voltage Vout. The lower part of the diagram depicts the output current I. The direction of the output current I from the switch terminal SW toward the transistor 12 is defined as the positive direction.

[0055] As shown in the figure, the addition of the transistor 53 and the amplifier 54 prevents the error voltage Verr from increasing beyond the reference voltage Vref2. As a result, an upper limit is set for the output current I, making it difficult for the output current I to exceed the allowable upper limit of the semiconductor device 1.

[0056] <Semiconductor Device (Third Embodiment)> 10 is a diagram showing a third embodiment of the semiconductor device 1. The semiconductor device 1 of the third embodiment includes an external terminal 61, an internal node 62, a control circuit 63, a current / voltage conversion element 64, and a current generation circuit 65.

[0057] The external terminal 61 can be understood as a so-called high-active terminal, which can increase the output OUT as the terminal voltage V2 increases. The internal node 62 is a node to which a node voltage V1 is applied. The control circuit 63 increases the output OUT as the node voltage V1 increases. The current / voltage conversion element 64 is connected between the external terminal 61 and the internal node 62. The current generation circuit 65 causes a current I1 to flow through the current / voltage conversion element 64 so that the terminal voltage V2 applied to the external terminal 61 matches a predetermined reference voltage V3. Referring to this diagram, the current generation circuit 65 causes a current I1 to flow from the external terminal 61 through the current / voltage conversion element 64 toward the internal node 62.

[0058] With this configuration, when a short circuit to power occurs at the external terminal 61, a potential difference ΔV is generated between the node voltage V1 and the terminal voltage V2. Therefore, even if the terminal voltage V2 is stuck at the power supply voltage Vcc, the node voltage V1 will not rise following the terminal voltage V2. As a result, the output OUT can be maintained in a controllable state. In this specification, a short circuit to power can be understood as a short circuit to a power supply terminal or an equivalent high potential terminal.

[0059] <Additional Notes> With the semiconductor device according to the present disclosure, a fail-safe can be realized when an external terminal is shorted, for example, when a low active terminal is shorted to ground and when a high active terminal is shorted to power.

[0060] [Appendix 1] External terminals (COMP, 61) and An internal node (n1, 62) and a control circuit (30, 63) configured to vary an output (Vout, OUT) in response to a first voltage (Verr, V1) applied to the internal node (n1, 62); a current / voltage conversion element (40, 64) connected between the external terminal (COMP, 61) and the internal node (n1, 62); a current generating circuit (50, 65) configured to cause a first current (I1) to flow through the current / voltage converting element (40, 64) so ​​as to make a second voltage (Vcomp, V2) applied to the external terminal (COMP) coincide with a predetermined third voltage (Vref1, V3); A semiconductor device (1) comprising:

[0061] [Appendix 2] the control circuit (30) increases the output (Vout) as the first voltage (Verr) decreases, The semiconductor device (1) according to Appendix 1, wherein the current generating circuit (50) flows the first current (I1) in a direction from the internal node (n1) through the current / voltage conversion element (40) toward the external terminal (COMP).

[0062] [Appendix 3] the control circuit (63) increases the output (OUT) as the first voltage (V1) increases, The semiconductor device (1) according to appendix 1, wherein the current generating circuit (65) flows the first current (I1) in a direction from the external terminal (61) through the current / voltage conversion element (64) toward the internal node (62).

[0063] [Appendix 4] The current generating circuit (50) a first transistor (51) provided on a path through which the first current (I1) flows; a first amplifier (52) configured to drive the first transistor (51) so as to match the second voltage (Vcomp) and the third voltage (Vref1); The semiconductor device (1) according to any one of appendices 1 to 3, comprising:

[0064] [Appendix 5] The semiconductor device (1) described in Appendix 4, wherein the current generating circuit (50) adjusts the driving capability of the first amplifier (52) so as to match the second voltage (Vcomp) with a predetermined fourth voltage (Vref2).

[0065] [Appendix 6] The current generating circuit (50) a second transistor (53) provided on a path through which a second current (I2) flows for adjusting the driving capability of the first amplifier (52); a second amplifier (54) configured to drive the second transistor (53) so as to match the second voltage (Vcomp) and the fourth voltage (Vref2); The semiconductor device (1) according to appendix 5, further comprising:

[0066] [Appendix 7] an output circuit (10, L1, C2) configured to generate an output voltage (Vout) from an input voltage (Vin); a feedback control circuit (20) configured to control the output circuit (10) so that a feedback voltage (Vfb) corresponding to the output voltage (Vout) matches a predetermined reference voltage (Vref); Equipped with 7. The semiconductor device (1) according to any one of appendices 1 to 6, wherein the control circuit (30) is a part of the output circuit (10) and the feedback control circuit (20).

[0067] [Appendix 8] The feedback control circuit (20) includes an error amplifier (21) configured to generate an error voltage (Verr) corresponding to a difference between the feedback voltage (Vfb) and the reference voltage (Vref), The semiconductor device (1) according to Appendix 7, wherein the internal node (n1) is an output node of the error amplifier (21), the first voltage (Verr) is the error voltage (Verr), and the external terminal (COMP) is a phase compensation terminal (COMP) of the error amplifier (21).

[0068] [Appendix 9] The feedback control circuit (20) a ramp voltage generating circuit (24) configured to generate a ramp voltage (Vr); a comparator (25) configured to compare the error voltage (Verr) or a control voltage (Vc) corresponding thereto with the lamp voltage (Vr) to generate a duty signal (S0); a controller (26) configured to generate control signals (S1, S2) in response to the duty signal (S0); a driver (27) configured to drive the output circuit (10) in response to the control signals (S1, S2); 9. The semiconductor device (1) according to claim 8, comprising:

[0069] [Appendix 10] A power supply device (A) comprising the semiconductor device (1) according to any one of appendices 7 to 9.

[0070] <Other> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. Furthermore, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0071] 1. Semiconductor device 10 Output circuit 11, 12 Transistors 20 Feedback control circuit 21, 22 Amplifier 23 Soft start circuit 24 Lamp voltage generation circuit 25 Comparator 26 Controller 27 Drivers 28 Current Sensor 30 Duty control circuit 40 Current / Voltage Conversion Element 50 Current generation circuit 51, 53 Transistors 52, 54 amplifier 61 External terminal 62 internal nodes 63 Control circuit 64 Current / Voltage Conversion Element 65 Current generation circuit A Power supply BST Bootstrap terminal C1~C4, C5 capacitors COMP Phase compensation terminal D1 Diode FB Feedback terminal L1 inductor M1 transistor n1 internal node PGND Ground terminal R1~R3, R4 resistance SW Switch terminal VIN input terminal

Claims

1. An external terminal, an internal node; a control circuit configured to vary an output in response to a first voltage applied to the internal node; a current / voltage conversion element connected between the external terminal and the internal node; a current generating circuit configured to cause a first current to flow through the current / voltage conversion element so that the second voltage applied to the external terminal matches a predetermined third voltage; A semiconductor device comprising:

2. the control circuit increases the output as the first voltage decreases; 2. The semiconductor device according to claim 1, wherein said current generating circuit causes said first current to flow in a direction from said internal node through said current / voltage conversion element toward said external terminal.

3. the control circuit increases the output as the first voltage increases, 2. The semiconductor device according to claim 1, wherein said current generating circuit causes said first current to flow in a direction from said external terminal through said current / voltage conversion element toward said internal node.

4. The current generating circuit includes: a first transistor provided on a path through which the first current flows; a first amplifier configured to drive the first transistor to match the second voltage and the third voltage; The semiconductor device according to claim 1 , comprising:

5. 5. The semiconductor device according to claim 4, wherein said current generating circuit adjusts the driving capability of said first amplifier so that said second voltage coincides with a predetermined fourth voltage.

6. The current generating circuit includes: a second transistor provided on a path through which a second current flows for adjusting the driving capability of the first amplifier; a second amplifier configured to drive the second transistor to match the second voltage and the fourth voltage; The semiconductor device according to claim 5 , further comprising:

7. an output circuit configured to generate an output voltage from an input voltage; a feedback control circuit configured to control the output circuit so that a feedback voltage corresponding to the output voltage matches a predetermined reference voltage; Equipped with 7. The semiconductor device according to claim 1, wherein said control circuit is a part of said output circuit and said feedback control circuit.

8. the feedback control circuit includes an error amplifier configured to generate an error voltage according to a difference between the feedback voltage and the reference voltage; 8. The semiconductor device according to claim 7, wherein said internal node is an output node of said error amplifier, said first voltage is said error voltage, and said external terminal is a phase compensation terminal of said error amplifier.

9. The feedback control circuit a ramp voltage generating circuit configured to generate a ramp voltage; a comparator configured to compare the error voltage or a control voltage corresponding thereto with the ramp voltage to generate a duty signal; a controller configured to generate a control signal in response to the duty signal; a driver configured to drive the output circuit in response to the control signal; The semiconductor device according to claim 8 , comprising:

10. A power supply device comprising the semiconductor device according to claim 7.

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