Method for manufacturing semiconductor substrate, semiconductor substrate, method for manufacturing semiconductor device, and semiconductor device

Abstract

To improve manufacturing efficiency of a semiconductor device.SOLUTION: A method of manufacturing a semiconductor substrate includes preparing an active layer-containing substrate including a growth substrate having a seed portion and a non-seed portion, a semiconductor portion extending from the seed portion to above the non-seed portion, and a laminated body located above the semiconductor portion and including an active layer, and forming an insulating film in contact with a side surface of the laminated body, wherein the side surface of the insulating film has a region in which a distance from the laminated body in a direction along an upper surface of the semiconductor portion increases upward.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor substrate. [Background technology]

[0002] Patent Document 1 describes a technique relating to a method for incorporating a vertical (vertical) micro LED device into a light-emitting device such as a display. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2018-522585 Summary of the Invention [Problem to be solved by the invention]

[0004] There is a need to improve the manufacturing efficiency of semiconductor devices. [Means for solving the problem]

[0005] A method for manufacturing a semiconductor substrate in one aspect of the present disclosure includes the steps of preparing an active layer-containing substrate including a growth substrate having a seed portion and a non-seed portion, a semiconductor portion extending from the seed portion above the non-seed portion, and a stack located above the semiconductor portion and including an active layer, and forming an insulating film in contact with a side surface of the stack, the side surface of the insulating film having a region in which the distance from the stack in a direction along the top surface of the semiconductor portion increases upward. [Effects of the Invention]

[0006] According to one aspect of the present invention, it is possible to easily improve the manufacturing efficiency of semiconductor devices. [Brief explanation of the drawings]

[0007] [Figure 1]1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. [Figure 2] 1 is a flowchart illustrating an example of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. [Figure 3] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 4] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 5] 1 is a flowchart illustrating an example of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 6] 1 is a schematic diagram illustrating a configuration of a semiconductor substrate manufacturing apparatus according to an embodiment of the present disclosure. [Figure 7] 1 is a schematic diagram illustrating a configuration of a semiconductor device manufacturing apparatus according to an embodiment of the present disclosure. [Figure 8] 1 is a perspective view showing an active layer-containing substrate used in an example of a method for manufacturing a semiconductor substrate in Example 1. FIG. [Figure 9] 1 is a perspective view showing an example of a method for manufacturing a semiconductor substrate in Example 1. FIG. [Figure 10] 1 is a perspective view showing an example of a method for manufacturing a semiconductor substrate in Example 1. FIG. [Figure 11] 1 is a plan view showing a configuration of a semiconductor substrate in Example 1. FIG. [Figure 12] 12 is a cross-sectional view taken along line XII-XII shown in FIG. 11. [Figure 13] 13 is a cross-sectional view taken along line XIII-XIII shown in FIG. 11. [Figure 14] 14 is a cross-sectional view taken along line XIV-XIV shown in FIG. [Figure 15] 12 is a cross-sectional view taken along line XV-XV shown in FIG. [Figure 16] 1A to 1C are plan views showing an example of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 17] 17 is a cross-sectional view taken along line XVII-XVII shown in FIG. 16. [Figure 18]17 is a cross-sectional view taken along line XVIII-XVIII shown in FIG. 16. [Figure 19] 3A to 3C are cross-sectional views showing an example of a method for manufacturing a semiconductor substrate in a configuration example of the first embodiment. [Figure 20] 1 is a plan view showing an example of a semiconductor substrate in a configuration example of a first embodiment. [Figure 21] 1 is a plan view showing an example of a semiconductor substrate in a configuration example of a first embodiment. [Figure 22] FIG. 2 is a cross-sectional view showing an example of the configuration of a laminate. [Figure 23] 1 is a cross-sectional view showing an example of a semiconductor substrate in a configuration example of a first embodiment. [Figure 24] 10A to 10C are cross-sectional views showing an example of a method for manufacturing a semiconductor substrate in Example 2. [Figure 25] 10A to 10C are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 26] 10A to 10C are cross-sectional views showing an example of a method for manufacturing a semiconductor device having a configuration example in Example 2. [Figure 27] 10A to 10C are cross-sectional views showing an example of a method for manufacturing a semiconductor substrate in Example 3. DETAILED DESCRIPTION OF THE INVENTION

[0008] First, to facilitate understanding of a method for manufacturing a semiconductor substrate according to one embodiment of the present disclosure, a summary of the findings of the present disclosure will be given.

[0009] [Summary of findings of the present disclosure] Conventionally, in the manufacturing process of a semiconductor device (display, etc.) incorporating a vertical (perpendicular) LED (Light Emitting Diode) element, for example, the following steps are carried out.

[0010] The LED element may be manufactured on a growth substrate, or may be manufactured on a temporary substrate after a multilayer film formed on the growth substrate is transferred to the temporary substrate, and the LED element is then transferred from the growth substrate or temporary substrate to a mounting substrate such as a wiring board.

[0011] For example, the anode of a vertical LED element (hereinafter referred to as a vertical LED element) is bonded to an anode pad on a mounting substrate, and the vertical LED element is transferred to the mounting substrate. The vertical LED element on the mounting substrate is then covered with an insulator (e.g., an organic film). The insulator is patterned to expose the cathode (or n-type layer) of the vertical LED element and the cathode pad on the mounting substrate. A conductive film (e.g., ITO) is then formed, allowing electrical conduction between the cathode (or n-type layer) of the vertical LED element and the cathode pad located on the mounting substrate.

[0012] The manufacturing process described above includes a step in the process after transferring the vertical LED element to the mounting substrate, which makes it difficult to rework (i.e., to correct the defect in the defective product) if a defect occurs. Specifically, if a defect occurs in the process of patterning the insulator or depositing the conductive film, it may be difficult to return the semi-finished product to a normal state. As a result, the LED element and mounting substrate incorporated in the semi-finished product may have to be discarded, resulting in significant losses.

[0013] In reality, in the series of manufacturing processes for semiconductor devices, different implementers (typically companies) may carry out different manufacturing steps, and there is a demand for reducing the possibility of defects occurring in downstream steps. Solving this problem would be of great technological and industrial significance.

[0014] The present inventors conducted extensive research and came up with a new idea, leading to the present disclosure. According to one aspect of the present disclosure, for example, for vertical LED elements manufactured on a growth substrate, an insulating film is formed in contact with the side surfaces of the vertical LED element before the element is transferred to a mounting substrate. The vertical LED element is then transferred to the mounting substrate together with the insulating film. This method can be realized, for example, by applying the semiconductor substrate technology developed by the present inventors. This reduces the number of steps in the processing after the vertical LED element is transferred to the mounting substrate, and facilitates a reduction in the possibility of defects. As a result, the risk of losses can be effectively reduced. Therefore, the manufacturing efficiency of semiconductor devices can be easily improved.

[0015] [Embodiment] Fig. 1 is a cross-sectional view showing an example of a method for manufacturing a semiconductor substrate, and Fig. 2 is a flowchart showing an example of a method for manufacturing a semiconductor substrate.

[0016] 1 and 2, the method for manufacturing a semiconductor substrate 10 includes a step S10 of preparing an active-layer-containing substrate AK including a growth substrate TS having a seed portion SA and a non-seed portion (growth-inhibiting portion) DA, a semiconductor portion 8 extending from the seed portion SA above the non-seed portion DA, and a stacked body LB located above the semiconductor portion 8 and including an active layer (active portion) 9K, and a step S20 of forming an insulating film ZF in contact with a side surface LBS of the stacked body LB. The side surface of the insulating film ZF has a region RA in which the distance from the stacked body LB in a direction along the top surface 8T of the semiconductor portion 8 increases (becomes larger) upward. The insulating film ZF has a first portion ZP1 in which the thickness in the direction along the top surface 8T of the semiconductor portion 8 increases upward, and the region RA may be included in the first portion ZP1. In other words, the insulating film ZF includes a first side surface P1S located on the opposite side to the side on which the laminated body LB is located, and the first side surface P1S may include a portion (region RA) in which the distance from the laminated body LB in the direction along the upper surface 8T of the semiconductor part 8 increases upward.

[0017] The distance from the laminate LB may be the distance from the side surface LBS of the laminate LB in a direction along the top surface 8T, or it may be the distance from the axis identified in a direction along the top surface 8T, based on the axis of rotational symmetry (or central axis) of the laminate LB along the stacking direction of the laminate LB.

[0018] The active layer-containing substrate AK may be prepared by a known method. The active layer-containing substrate AK is not limited to the example shown in FIG. 1 , etc. Furthermore, the laminate LB included in the active layer-containing substrate AK may be prepared by a known method. The specific structure and manufacturing method of the laminate LB are not particularly limited.

[0019] In the following description, the direction from the semiconductor portion 8 to the stacked body LB is defined as the upward direction. In a semiconductor device obtained from the semiconductor substrate 10, the stacked body LB may be located below the semiconductor portion 8 (in the direction of gravity).

[0020] In one embodiment, the growth substrate TS may have a base substrate BS and a mask pattern 6 located above the base substrate BS. The mask pattern 6 may include openings K that overlap the seed portions SA and mask portions 5 that function as non-seed portions DA. Specifically, the surface (upper surface) of the mask portions 5 may serve as a growth suppression region for the non-seed portions DA. The mask portions 5 may include at least one of silicon nitride and silicon oxide. The growth substrate TS may also be called a template substrate.

[0021] Viewing an object from a line of sight parallel to the normal direction of the growth substrate TS or the mounting substrate MS (see FIG. 4, described below) (including perspective views) may be referred to as a "planar view." In the planar view, the seed portion SA and the non-seed portion DA may be aligned in a first direction (X-axis direction), and the opening K may have a longitudinal shape extending in a second direction (Y-axis direction) perpendicular to the first direction. The thickness direction of the semiconductor portion 8 is defined as the third direction (Z1-axis direction). "Two components overlap in a planar view" may mean that "at least a portion of one component overlaps the other component in a planar view viewed in the normal direction of the growth substrate TS or the mounting substrate MS." Two components may overlap in a planar view when one component is located above or below the other component.

[0022] With regard to the insulating film ZF, the thickness in the direction along the top surface 8T of the semiconductor portion 8 may be, for example, the length (width) in the first direction when viewed in a cross section perpendicular to the second direction. The insulating film ZF can also be referred to as an insulating wall portion or an inclined wall portion that contacts the side surface LBS of the laminated body LB. The region RA can also be referred to as an overhang region that overhangs the growth substrate TS in the direction along the top surface 8T (including the first and second directions).

[0023] The semiconductor portion 8 may contain a nitride semiconductor as a main component. In this specification, the main component refers to the component (molecule, single atom) of the material that has the largest content (number of moles) (when the material contains only one component, that component). The nitride semiconductor may be, for example, Al x Ga y In z N (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1). Specific examples of nitride semiconductors include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). GaN-based semiconductors are semiconductors containing gallium atoms (Ga) and nitrogen atoms (N). Typical examples of GaN-based semiconductors include GaN, AlGaN, AlGaInN, and InGaN. Nitride semiconductors may be doped (for example, n-type containing donors) or undoped.

[0024] The first direction (X-axis direction) may be parallel to the a-axis direction (<11-20> direction) of the semiconductor portion 8 that is a nitride semiconductor crystal. The second direction (Y-axis direction) may be parallel to the m-axis direction (<1-100> direction) of the semiconductor portion 8 that is a nitride semiconductor crystal. The third direction (Z1-axis direction) that is perpendicular to the first and second directions may be parallel to the c-axis direction (<1-100> direction) of the semiconductor portion 8 that is a nitride semiconductor crystal. <0001> direction).

[0025] The semiconductor portion 8 may include a ridge portion R, a base portion B located on the ridge portion R, and a wing portion F connected to the base portion B. In one embodiment, the wing portion F may not be in contact with the growth substrate TS. In one embodiment, a gap JD may be located between the wing portion F and the growth substrate TS. The ridge portion R may be a portion grown from the seed portion SA exposed below the opening K of the mask pattern 6 to a position above the upper surface of the mask portion 5. The semiconductor portion 8 may be formed, for example, by further growing the semiconductor layer using an ELO (Epitaxial Lateral Overgrowth) method starting from the ridge portion R, and then removing a portion of the formed semiconductor layer by etching or the like.

[0026] Of the semiconductor portion 8, the wing portion F located above the mask portion 5 becomes a low-defect portion having a lower threading dislocation density than the base portion B located above the opening K. The threading dislocation density of the wing portion F may be 1 / 5 or less, 1 / 10 or less, or 1 / 100 or less of the threading dislocation density of the base portion B. The threading dislocation density of the wing portion F is 5×10 6 [pcs / cm 2 The laminate LB may be located above the wing portion F.

[0027] In this embodiment, the active layer-containing substrate AK may include a mask portion 5 located between the wing portion F and the growth substrate TS. The semiconductor substrate 10 may include a mask portion 5 located between the wing portion F and the growth substrate TS. The wing portion F may be separated from the mask portion 5 and located above the gap JD. The gap JD may be a space surrounded (defined three-dimensionally with a portion open) by the growth substrate TS, the ridge portion R, and the wing portion F. The wing portion F may include a tether portion T connected to the base portion B and a main body portion H connected to the tether portion T. The tether portion T has a length in the Y-axis direction that is shorter than that of the main body portion H (see FIGS. 7, 9, etc.). The semiconductor portion 8 may be formed by a known method. In one embodiment, the semiconductor portion 8 may not have the ridge portion R or the tether portion T.

[0028] The laminate LB may have the structure of a vertical LED element. The active layer 9K of the laminate LB may overlap the wing portion F in a planar view. The laminate LB may include, for example, an anode EA (electrode) in contact with the contact layer 9C located above the active layer 9K. The anode EA overlaps the active layer 9K in a planar view. The laminate LB may also include a protective film PF that forms the side surface LBS of the laminate LB. The protective film PF may cover the end face of the active layer 9K. The protective film PF may cover the periphery of the laminate LB except for the contact portion between the contact layer 9C and the anode EA.

[0029] As shown in FIG. 1, the insulating film ZF may be formed, for example, as follows. First, an insulator (e.g., an organic film) ZM is applied to the entire surface of the active layer-containing substrate AK (in other words, the entire surface of the growth substrate TS). The semiconductor portion 8 and the stacked body LB may be covered with the insulator ZM. Next, the insulator ZM is patterned. In one example, the insulator ZM may be a negative resist. In this case, after a portion of the negative resist is subjected to pattern exposure (patterning exposure), the unexposed portion can be dissolved and removed using a developer. This allows the insulating film ZF to be formed based on the exposed portion of the insulator ZM.

[0030] The semiconductor substrate 10 includes a growth substrate TS having a seed portion SA and a non-seed portion DA, a semiconductor portion 8 extending from the seed portion SA above the non-seed portion DA, a stacked body LB located above the semiconductor portion 8 and including an active layer 9K and an anode EA (electrode), and an insulating film ZF in contact with a side surface of the stacked body LB, the side surface of the insulating film ZF having a region RA whose distance from the stacked body LB in a direction along the top surface 8T of the semiconductor portion 8 increases upward. In the semiconductor substrate 10, the insulating film ZF has a first portion ZP1 whose thickness in the direction along the top surface 8T of the semiconductor portion 8 increases upward, and the region RA may be included in the first portion ZP1.

[0031] With respect to the semiconductor substrate 10, an inverse taper and a forward taper can be defined with respect to the growth substrate TS. Specifically, with respect to the semiconductor substrate 10, an inverse taper means that the width in the first direction (X-axis direction) or the second direction (Y-axis direction) increases upward (toward the positive direction of the Z1 axis), i.e., as the substrate moves away from the growth substrate TS. With respect to the semiconductor substrate 10, a forward taper means that the width in the first direction (X-axis direction) or the second direction (Y-axis direction) decreases upward (toward the positive direction of the Z1 axis). Furthermore, with respect to the semiconductor substrate 10, an overhanging shape means that the substrate protrudes beyond other components as it moves upward (toward the positive direction of the Z1 axis).

[0032] In the example shown in FIG. 1, the first portion ZP1 includes a first side surface P1S located farther from the base portion B in the first direction (X-axis direction). The first side surface P1S may be an overhanging reverse tapered surface. The region RA may be included in the first side surface P1S, which is a reverse tapered surface. The insulating film ZF may cover the side surface of the laminated body LB. The first portion ZP1 of the insulating film ZF may cover the side surface of the laminated body LB. The insulating film ZF may have a second portion ZP2 that rises up onto the laminated body LB.

[0033] A semiconductor device 20 can be manufactured using the semiconductor substrate 10. Figures 3 and 4 are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 5 is a flowchart showing an example of a method for manufacturing a semiconductor device. For convenience of illustration, Figure 3 shows the semiconductor substrate 10 upside down from the state shown in Figure 1, and Figure 4 schematically shows a cross-sectional view in which the positions of the stacked body LB and the semiconductor portion 8 are shifted in the X-axis direction.

[0034] 3 to 5, a method for manufacturing a semiconductor device 20 according to an embodiment of the present disclosure includes a step S30 of preparing a semiconductor substrate 10 and a mounting substrate MS, and a step S40 of mounting a laminated body LB so that the anode (electrode) EA is in contact with the mounting substrate MS and separating the semiconductor portion 8 and the growth substrate TS. While the example shown in FIG. 3 illustrates a case in which two laminated bodies LB are simultaneously transferred to the mounting substrate MS, for example, the semiconductor substrate 10 may include a plurality of laminated bodies LB, and some of the plurality of laminated bodies LB may be selectively transferred to the mounting substrate MS. The specific configuration of the mounting substrate MS is not particularly limited.

[0035] In this specification, the XY-Z1 axis and the XY-Z2 axis may be used interchangeably depending on the subject of the description. The Z2 axis is inverted in direction from the Z1 axis shown in Figure 1 and the like, and the direction from the mounting substrate MS toward the laminate LB is the positive direction of the Z2 axis.

[0036] The mounting substrate MS may include a conductive first pad (anode pad) P1. In the example shown in Fig. 3, for example, the anode EA of the laminate LB is bonded to the first pad P1 of the mounting substrate MS. Then, for example, the mounting substrate MS is pressed against the semiconductor substrate 10 (in other words, the growth substrate TS), thereby breaking the tether portion T. This transfers the laminate LB and the semiconductor portion 8 to the mounting substrate MS.

[0037] The semiconductor portion 8 transferred to the mounting substrate MS may include a main body portion H and a part of the tether portion T. The semiconductor portion 8 may have a fracture surface FS formed by breaking the tether portion T at an end portion in the X-axis direction. For ease of explanation, hereinafter, the set of the laminate LB, the semiconductor portion 8, and the insulating film ZF separated from the growth substrate TS and positioned on the mounting substrate MS may be referred to as the light emitting element body 15.

[0038] As shown in FIGS. 3 and 4, the mounting substrate MS includes a conductive second pad (cathode pad) P2. As shown in FIGS. 4 and 5, in the manufacturing method of the semiconductor device 20, after step S40, a step S50 of forming a conductive film CF in contact with the semiconductor portion 8, the first portion ZP1, and the second pad P2 is further performed. As a result, the back surface 8B of the semiconductor portion 8 having n-type conductivity (the surface facing the gap JD in the semiconductor substrate 10) is electrically connected to the second pad P2 via the conductive film CF. When the semiconductor portion 8 is a nitride semiconductor portion, the back surface 8B may be a nitrogen-polarity surface. The conductive film CF may be, for example, ITO (indium tin oxide) and may be formed by sputtering or the like.

[0039] With respect to the semiconductor device 20, a reverse taper and a forward taper can be defined with reference to the mounting substrate MS. As described above, since the light emitting element 15 is inverted upside down during transfer, the reverse taper and forward taper of the semiconductor device 20 are oriented in the opposite direction to those of the semiconductor substrate 10. Specifically, with respect to the semiconductor device 20, a reverse taper means that the width in the first direction (X-axis direction) or the second direction (Y-axis direction) increases toward the positive direction of the Z2 axis, i.e., as the device moves away from the mounting substrate MS. With respect to the semiconductor device 20, a forward taper means that the width in the first direction (X-axis direction) or the second direction (Y-axis direction) decreases toward the positive direction of the Z2 axis.

[0040] According to the manufacturing method of the semiconductor substrate 10 in one embodiment of the present disclosure, the insulating film ZF is formed before the laminate LB is transferred to the mounting substrate MS. This reduces the number of steps in the processing after transfer to the mounting substrate MS. The insulating film ZF also includes the first portion ZP1. This allows the following to be said about the light emitting element body 15 on the mounting substrate MS.

[0041] That is, since the first side surface P1S of the insulating film ZF is an inversely tapered surface on the growth substrate TS, it can be formed on the mounting substrate MS with a shape in which the thickness decreases in the positive direction of the Z2 axis (a forward tapered shape). Forming the conductive film CF along the forwardly tapered first side surface P1S on the mounting substrate MS facilitates continuous formation of the conductive film CF from the back surface 8B of the semiconductor portion 8 to the second pad P2. Therefore, using the semiconductor substrate 10 effectively reduces the risk of loss in processing after transferring the stacked body LB to the mounting substrate MS. This facilitates improving the manufacturing efficiency of the semiconductor device 20. Other advantages of the present disclosure will be described in the examples below.

[0042] In the example shown in FIGS. 3 and 4, the semiconductor substrate 10 may have a portion on the side surface LBS of the laminate LB where the insulating film ZF is not formed (is not in contact with) the insulating film ZF. The semiconductor device 20 may have a region (separated region) A1 where the surface of the mounting substrate MS and the back surface 8B of the semiconductor portion 8 are not connected by the conductive film CF. That is, in a cross-sectional view, the semiconductor device 20 may have the conductive film CF separated at the end position of the semiconductor portion 8 having the fracture surface FS. Even in this case, the conductive film CF can electrically connect the back surface 8B and the second pad P2. A structural example will be described in more detail in the examples below.

[0043] In the manufacturing method of the semiconductor substrate 10 according to one embodiment of the present disclosure, the specific method for forming the insulating film ZF is not particularly limited. The insulating film ZF may be formed using a known method. The position, shape, etc. of the insulating film ZF may be designed and adjusted as appropriate. For example, the insulating film ZF can be formed in various modes depending on the positional relationship between the light emitting element body 15 and the second pad P2 on the mounting substrate MS, the specific configuration of the semiconductor substrate 10, etc. The specific configuration of the semiconductor substrate 10, etc., is not necessarily limited to the configuration described in the examples below, and various modifications are possible within the scope of the gist of the present disclosure.

[0044] Fig. 6 is a schematic diagram showing the configuration of a semiconductor substrate manufacturing apparatus according to an embodiment of the present disclosure. As shown in Fig. 6, a semiconductor substrate manufacturing apparatus 50 includes an apparatus M10 that performs step S10 of Fig. 2, an apparatus M20 that performs step S20 of Fig. 2, and an apparatus M1 that controls the apparatuses M10 and M20. The apparatus M10 may include an MOCVD apparatus, and the apparatus M20 may include a photolithography apparatus.

[0045] Fig. 7 is a schematic diagram showing the configuration of a semiconductor device manufacturing apparatus according to an embodiment of the present disclosure. As shown in Fig. 7, semiconductor device manufacturing apparatus 60 includes apparatus M30 that performs step S30 of Fig. 5, apparatus M40 that performs step S40 of Fig. 5, and apparatus M2 that controls apparatuses M30 and M40. Semiconductor device manufacturing apparatus 60 may also include apparatus M50 that performs step S50 of Fig. 5. In this case, apparatus M2 controls apparatus M50. Apparatus M50 may include a sputtering apparatus.

[0046] Example 1 FIG. 8 is a perspective view showing an active layer-containing substrate used in an example of the method for manufacturing a semiconductor substrate in Example 1. In the perspective views such as FIG. 8, for convenience of illustration and explanation, a part of the base B in the semiconductor portion 8 is shown with a dotted line and is shown transparently. In addition, in FIG. 8 and other figures, for convenience of illustration, the configuration of the laminated body LB is shown in a simplified manner. As described above, the laminated body LB may include a protective film PF that forms the side surface LBS, and the protective film PF is not shown in FIG. 8 and other figures. In addition, the side surface LBS of the laminated body LB may be an inclined surface or may have a step. The shape of the ridge portion R of the semiconductor portion 8 is also shown in a simplified manner.

[0047] As shown in FIG. 8 , the base substrate BS of the growth substrate TS may include a main substrate 1 and an underlayer (underlayer) 4 located on the main substrate 1. The surface of the underlayer 4 that overlaps with the opening K of the mask pattern 6 can be used as a seed portion SA. The main substrate 1 may be a heterogeneous substrate having a lattice constant different from that of the semiconductor portion 8. The main substrate 1 may include a semiconductor (e.g., silicon, silicon carbide), or may not include a semiconductor. Examples of the main substrate 1 that includes a semiconductor include a silicon substrate or a silicon carbide substrate (4H—SiC, 6H—SiC substrate). Examples of the main substrate 1 that does not include a semiconductor include a sapphire substrate. The main substrate 1 may be, for example, a nitride substrate (e.g., GaN, AlN substrate), an ScMgAlO substrate, or the like. The main substrate 1 may be a free-standing substrate (wafer). In Example 1, the semiconductor portion 8 may be a nitride semiconductor portion, and the growth substrate TS may include a silicon substrate.

[0048] The semiconductor substrate means a substrate including a nitride semiconductor, and the base substrate BS may include a semiconductor other than a nitride semiconductor (for example, a silicon-based semiconductor, silicon carbide, or gallium oxide) or a non-semiconductor (sapphire).

[0049] The base portion 4 may be, for example, a seed layer made of a nitride semiconductor (such as a GaN-based semiconductor or AlN). The base portion 4 may be a seed layer or a buffer layer, or may have a multi-layer structure including a seed layer and a buffer layer. The base portion 4 may include a buffer layer (such as AlN) located on the main substrate 1 side and a seed layer (such as a GaN-based semiconductor) located on the mask portion 5 side, or the buffer layer may be a multi-layer structure (such as an Al layer and an AlN layer). The growth substrate TS may have a structure that allows the semiconductor portion 8 to be grown thereon, and the specific structure is not particularly limited, and known structures may be applied as appropriate.

[0050] In Example 1, the active layer-containing substrate AK has wing portions F of the semiconductor portion 8 separated from the surface of the mask portion 5, and a gap JD is formed between the wing portions F and the mask portion 5. This reduces internal stress in the wing portions F, making it easier to reduce warpage of the active layer-containing substrate AK. In Example 1, the semiconductor portion 8 has tether portions T between the base portion B and the main body portion H. The tether portions T can be formed, for example, by growing the base portion B and the wing portions F using the ridge portion R as a base point using the ELO method, and then removing a portion of the semiconductor portion 8. In FIG. 8, the portion of the base portion B indicated by the dotted line may or may not be removed when forming the tether portions T (it may be present in the active layer-containing substrate AK).

[0051] In the active layer-containing substrate AK, the semiconductor portion 8 has the tether portion T and the gap JD, thereby reducing the contact area between the semiconductor portion 8 and the growth substrate TS. As a result, the wing portion F can ensure the width of the main body portion H while reducing internal stress. Furthermore, when the laminate LB is transferred to the mounting substrate MS as described above, the tether portion T can be broken, making it easier to separate the wing portion F.

[0052] In FIG. 8 , the active layer 9K included in the laminate LB is indicated by multiple dashed lines. The laminate LB may be located above the main body portion H of the semiconductor portion 8. The laminate LB may be formed by stacking various layers including the active layer 9K on the wing portions F before forming the tether portions T of the semiconductor portion 8. Alternatively, the laminate LB may be formed by stacking various layers including the active layer 9K on the main body portion H after forming the tether portions T of the semiconductor portion 8. The anode EA of the laminate LB overlaps with the active layer 9K in a planar view. Hereinafter, in the active-layer-containing substrate AK, the space facing the laminate LB may be referred to as a void VS.

[0053] The laminate LB may have any known structure for vertical LEDs and may be formed by, for example, MOCVD. The laminate LB may have, for example, a laminate structure of an n-GaN layer, an active layer 9K, and a p-GaN layer. The active layer 9K has an MQW (multi-quantum well) structure and includes, for example, an InGaN layer or a GaN layer. The MQW structure of the active layer 9K may have, for example, a 5- to 6-period structure of InGaN / GaN. The contact layer 9C in contact with the anode EA may be, for example, a p-GaN layer.

[0054] The protective film PF (see FIG. 1, etc.) constituting the side surface LBS of the laminate LB includes an insulating material. The protective film PF may include, for example, silicon nitride, silicon oxide, aluminum oxide, etc. The anode EA may be formed of a transparent conductive material that is optically transparent to the wavelength of light emitted from the active layer 9K. Examples of the transparent conductive material that can be used include known materials such as indium tin oxide (including crystalline ITO, amorphous ITO, and Sn-doped In2O3).

[0055] Fig. 9 is a perspective view showing an example of a method for manufacturing a semiconductor substrate in Example 1. For convenience of illustration, in Fig. 9, the insulator ZM is shown with semitransparent hatching.

[0056] As shown in FIG. 9, first, an insulator ZM is applied onto an active layer-containing substrate AK. As the insulator ZM, for example, an alkaline development type negative photoresist (hereinafter simply referred to as "negative resist") can be used. In Example 1, a negative type TLOR-N001PM (manufactured by Tokyo Ohka Kogyo Co., Ltd.) was used as the insulator ZM. However, the insulator ZM is not limited to this, and any material known as a negative resist can be appropriately selected and used. Therefore, a detailed description of the specific components of the insulator ZM will be omitted.

[0057] Next, a photomask PM having a predetermined exposure pattern PT is prepared, and the photomask PM is aligned above the active layer-containing substrate AK. Light L is then irradiated onto the insulator ZM through the photomask PM. This results in a pattern exposure of a portion of the insulator ZM based on the exposure pattern PT of the photomask PM. In the example shown in FIG. 9 , the exposure pattern PT, in a plan view in the aligned state, includes a first light-shielding portion SP1 overlapping the anode EA, a second light-shielding portion SP2 overlapping the tether portion T, and a third light-shielding portion SP3 located between and connected to the first light-shielding portion SP1 and the second light-shielding portion SP2. The exposure pattern PT also includes a hollow light-transmitting region TA, which is the rectangular region excluding the first light-shielding portion SP1, the second light-shielding portion SP2, and the third light-shielding portion SP3.

[0058] 9, the first light-shielding portion SP1 may be, for example, square-shaped. The second light-shielding portion SP2 may be, for example, rectangular-shaped with the second direction (Y-axis direction) as its longitudinal direction. The first light-shielding portion SP1, the third light-shielding portion SP3, and the second light-shielding portion SP2 may be aligned in the first direction (X-axis direction), and the lengths in the second direction (Y-axis direction) may be greatest in the order of the third light-shielding portion SP3, the first light-shielding portion SP1, and the second light-shielding portion SP2.

[0059] 10 is a perspective view showing an example of a method for manufacturing a semiconductor substrate in Example 1. The portions of the insulator ZM that are pattern-exposed by light L are referred to as exposed portions EP. In FIG. 10, the exposed portions EP are shown with semitransparent hatching that is separate from the non-exposed portions of the insulator ZM.

[0060] When the insulator ZM is a negative resist, the exposed portion EP has lower solubility in the developer PD than the non-exposed portion. As shown in FIG. 10, the non-exposed portion of the insulator ZM can be dissolved and removed using the developer PD, thereby forming the insulating film ZF based on the exposed portion EP. The insulating film ZF includes a resist material. The components of the developer PD may be selected appropriately depending on the material of the insulator ZM.

[0061] In one embodiment of the method for manufacturing a semiconductor substrate according to the present disclosure, a negative resist (insulator ZM) placed in a gap VS facing the laminate LB is subjected to pattern exposure, and then the unexposed portions of the negative resist (portions other than the exposed portions EP) are removed to form an insulating film ZF.

[0062] 9 and 10, the semiconductor substrate 10 has a first non-formed portion NF1 formed corresponding to the first light-shielding portion SP1, a second non-formed portion NF2 formed corresponding to the second light-shielding portion SP2, and a third non-formed portion NF3 formed corresponding to the third light-shielding portion SP3. The first non-formed portion NF1, the second non-formed portion NF2, and the third non-formed portion NF3 are each a portion where the insulating film ZF is not formed (i.e., a portion of the unexposed portion of the insulator ZM). In the first embodiment, the insulating film ZF does not cover a portion of the periphery of the stacked body LB in a plan view, and may not cover a portion of the periphery of the semiconductor portion 8.

[0063] In the first embodiment, the first non-forming portion NF1 may be located on the laminate LB, overlap with the anode EA in a plan view, and be a recess recessed toward the laminate LB in the third direction (Z1-axis direction). The second non-forming portion NF2 may be located on the base B side and be a recess recessed toward the laminate LB in the first direction (X-axis direction). The second non-forming portion NF2 may have a length in the second direction (Y-axis direction) longer than the first non-forming portion NF1. In the second non-forming portion NF2, parts of the main body portion H and the tether portion T may be exposed. The third non-forming portion NF3 may be located on the semiconductor portion 8 and the laminate LB between the first non-forming portion NF1 and the second non-forming portion NF2, and may have a length in the second direction (Y-axis direction) shorter than that of the first non-forming portion NF1. In the third non-forming portion NF3, parts of the semiconductor portion 8 and the laminate LB may be exposed.

[0064] The insulating film ZF may have a protruding portion TP located between the first non-forming portion NF1 and the second non-forming portion NF2 in plan view and protruding in the second direction (Y-axis direction). Having the protruding portion TP can facilitate improving stability when transferring the laminate LB to the mounting substrate MS. In one embodiment, in the semiconductor substrate 10, the two insulating films ZF located on both sides of the base B in the first direction (X-axis direction) may have the same shape. In other words, the two insulating films ZF may have shapes that are symmetrical (mirror symmetric, 180° rotational symmetric) with respect to the base B. In this case, it is possible to simplify the conditions for transferring multiple laminates LB to the mounting substrate MS.

[0065] The insulating film ZF may not have the protruding portion TP. In one embodiment, in the semiconductor substrate 10, the first non-forming portion NF1, the third non-forming portion NF3, and the second non-forming portion NF2 may have the same width in the second direction (Y-axis direction).

[0066] Here, the insulator ZM can also flow into the gap JD below the wing portion F (see FIGS. 1 and 9, etc.). In the example shown in FIGS. 9 and 10, the presence of an unexposed portion in the insulator ZM formed by the second light-shielding portion SP2 of the photomask PM causes the semiconductor substrate 10 to have a second non-formed portion NF2. This prevents the formation of an exposed portion EP in the gap JD1 below the tether portion T. As a result, an injection path IC for the developer PD into the gap JD can be secured. This makes it easier to remove the insulator ZM located in the gap JD by the developer PD.

[0067] As described above, in the method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure, the wing portion F includes the tether portion T adjacent to the base portion B, and the insulating film ZF does not need to be in contact with the tether portion T. Furthermore, in the method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure, the void JD1 located below the tether portion T may be used as an injection path IC for the developer PD when forming the insulating film ZF.

[0068] FIG. 11 is a plan view showing the configuration of a semiconductor substrate in Example 1. FIG. 12 is a cross-sectional view including line XII-XII shown in FIG. 11. FIG. 13 is a cross-sectional view including line XIII-XIII shown in FIG. 11. FIG. 14 is a cross-sectional view including line XIV-XIV shown in FIG. 11. FIG. 15 is a cross-sectional view including line XV-XV shown in FIG. 11. In FIG. 11, the insulating film ZF is shown with semi-transparent hatching. Furthermore, each layer such as the active layer 9K in the laminate LB is schematically shown by dashed lines in a planar perspective view.

[0069] 11 to 15, in one embodiment of the present disclosure, the first portion ZP1 of the insulating film ZF may have a first side surface P1S that is an overhanging reverse tapered surface. The region RA may be included in the first side surface P1S that is a reverse tapered surface. As described above, the exposed portion EP that is the basis of the insulating film ZF is formed by irradiating light L through a photomask PM. The side surface of the exposed portion EP can be made to have an inclined shape (reverse tapered shape) corresponding to the optical path of the light L that passes through the light-transmitting region TA of the photomask PM and is irradiated onto the insulator ZM.

[0070] In one embodiment, the first portion ZP1 of the insulating film ZF may have a shape (overhanging shape) that protrudes with respect to the stack LB or the upper surface of the growth substrate TS (the surface of the mask portion 5 in the first embodiment). The upper surface of the insulating film ZF in the third direction (Z1 axis direction) is the top surface ZFT, and the lower surface is the bottom surface ZFB. For example, the insulating film ZF may have an obtuse angle θ1 formed between the first side surface P1S and the bottom surface ZFB. For example, the insulating film ZF may have an angle θ1 that is greater than 90° and equal to or less than 170°.

[0071] Hereinafter, the surface of the protective film PF located on the upper side (positive side of the Z1 axis) of the laminate LB will be referred to as the first upper surface LBT1, and the surface of the anode EA will be referred to as the second upper surface LBT2. When there is no need to distinguish between the first upper surface LBT1 and the second upper surface LBT2, they may be collectively referred to as the upper surface LBT.

[0072] In one embodiment of the present disclosure, the first portion ZP1 may cover the side surface LBS of the laminate LB. In a cross-sectional view, the first portion ZP1 may cover the side surface LBS from the lower end to the upper end (the boundary with the first top surface LBT1) of the side surface LBS. In the first embodiment, the entire side surface LBS around the laminate LB except for a portion where the third non-forming portion NF3 is located may be covered by the insulating film ZF.

[0073] In one embodiment of the present disclosure, the insulating film ZF may have a second portion ZP2 located on the upper surface LBT (first upper surface LBT1) of the laminate LB. The second portion ZP2 may have a shape that protrudes with respect to (the first upper surface LBT1 of) the laminate LB. The second portion ZP2 includes a second side surface P2S located closer to the base B in the first direction (X-axis direction). The second side surface P2S may be an overhanging, inversely tapered surface. The second portion ZP2 may not overlap with the anode EA in a planar view. In one embodiment of the present disclosure, the laminate LB may include an electrode (anode EA), and at least a portion of the electrode may not be in contact with the insulating film ZF.

[0074] In one embodiment of the present disclosure, the insulating film ZF may be in contact with the end face 8ES of the semiconductor portion 8. Such an insulating film ZF can be formed by adjusting the shape of the exposure pattern PT of the photomask PM in step S20 so that the insulator ZM in contact with the end face 8ES is exposed.

[0075] In one embodiment of the present disclosure, the insulating film ZF may have a third portion ZP3 located between the end 8E of the semiconductor portion 8 and the growth substrate TS. The end 8E may be, for example, the end of the semiconductor portion 8 in the first direction (X-axis direction), and in Example 1, it may be the end farther from the base portion B. Alternatively, the end 8E may be the end of the semiconductor portion 8 in the second direction (Y-axis direction). The third portion ZP3 may have a shape that protrudes from the growth substrate TS (the upper surface of the mask portion 5 thereof). The third portion ZP3 includes a third side surface P3S facing the gap JD. The third side surface P3S may be an overhanging, inversely tapered surface. The insulating film ZF as described above can be formed in step S20 by adjusting the shape of the exposure pattern PT of the photomask PM, etc., so that the optical path of the light L passes through the end 8E, and by using an emission wavelength that is transparent to the semiconductor portion 8, etc.

[0076] The third portion ZP3 may be in contact with the growth substrate TS. In other words, the bottom surface ZFB of the insulating film ZF may be in contact with the growth substrate TS. This can facilitate improving the stability of the semiconductor substrate 10 during storage or transportation. Even when the width of the tether portion T is relatively narrow, the possibility of the tether portion T accidentally breaking due to an impact or the like can be easily reduced. Furthermore, in step S40, the risk of the light emitting element 15 accidentally falling off when being transferred to the mounting substrate MS can be reduced. This is because the above configuration can reduce the load acting on the tether portion T when an external force is applied to the tether portion T due to a process such as cleaning.

[0077] As shown in FIGS. 10 and 15, the semiconductor substrate 10 has a gap JD1 below the tether portion T where the insulating film ZF is not formed. In FIG. 15, the portion of the semiconductor portion 8 connected to the tether portion T is indicated by a dashed line. Using the gap JD1 as an injection path IC for the developer PD facilitates removal of the insulator ZM that has infiltrated into the gap JD. If the insulator ZM remains in the gap JD, it may be difficult to peel the light-emitting element 15 from the growth substrate TS when transferring the light-emitting element 15 to the mounting substrate MS, and contamination of the rear surface 8B may occur. Therefore, for example, before transferring the light-emitting element 15 to the mounting substrate MS, the mask portion 5 may be removed using a hydrogen fluoride (HF) solution to facilitate removal of the insulator ZM in the gap JD. Furthermore, after transferring the light-emitting element 15 to the mounting substrate MS, residual insulator ZM adhering to the rear surface 8B may be removed by chemical cleaning or ashing using O2, Ar gas, or the like.

[0078] In one embodiment of the semiconductor substrate 10, the side surface LBS of the laminate LB may be a forward tapered surface. Furthermore, in the laminate LB, the upper surface (top surface ZFT) of the insulating film ZF may be located higher than the surface (second top surface LBT2) of the anode EA. If the protrusion height of the second top surface LBT2 from the first top surface LBT1 is H1 and the protrusion height of the top surface ZFT from the first top surface LBT1 is H2, the protrusion height H2 may be greater than the protrusion height H1.

[0079] Fig. 16 is a plan view showing an example of a method for manufacturing a semiconductor device in Example 1. In Fig. 16, the conductive film CF is shown with semitransparent hatching. Fig. 17 is a cross-sectional view including line XVII-XVII shown in Fig. 16. Fig. 18 is a cross-sectional view including line XVIII-XVIII shown in Fig. 16.

[0080] 16 to 18 show the state after the light emitting element 15 has been transferred from the growth substrate TS to the mounting substrate MS. Before the conductive film CF is formed, a part of the back surface 8B of the semiconductor portion 8 and the bottom surface ZFB of the insulating film ZF are positioned above in the third direction (Z2-axis direction) on the mounting substrate MS. The semiconductor substrate 10 has the second non-formation portion NF2 (see FIG. 10), which makes it easier to break the tether portion T when transferring the light emitting element 15. This makes it easier to transfer the light emitting element 15 from the growth substrate TS to the mounting substrate MS. The light emitting element 15 transferred onto the mounting substrate MS may have a fracture surface FS on the tether portion T of the semiconductor portion 8.

[0081] 16 to 18, in Example 1, the light emitting element 15 and the second pad P2 may be aligned in the second direction (Y-axis direction). The area of ​​the bottom surface ZFB shown in Fig. 16 may be smaller than the area of ​​the top surface ZFT of the insulating film ZF shown in Fig. 11. This can be understood from the above explanation.

[0082] By forming a conductive film CF in contact with the back surface 8B of the semiconductor portion 8, the insulating film ZF, and the second pad P2, it is possible to electrically connect the back surface 8B and the second pad P2 through the conductive film CF. In a manufacturing method for a semiconductor device 20 according to an embodiment of the present disclosure, the semiconductor portion 8 may be a nitride semiconductor portion, and the back surface 8B may be a nitrogen-polar surface. The conductive film CF may be in contact with the nitrogen-polar surface (back surface 8B) of the nitride semiconductor portion (semiconductor portion 8). The insulating film ZF may be disposed on the nitrogen-polar surface (back surface 8B). The semiconductor device 20 may include a mounting substrate MS including a conductive second pad P2, the semiconductor portion 8 (nitride semiconductor portion), and a conductive film CF located below the semiconductor portion 8 and in contact with the stacked body LB mounted on the mounting substrate MS, the back surface 8B (nitrogen-polar surface) of the semiconductor portion 8 (nitride semiconductor portion), and the second pad P2.

[0083] In addition, in the manufacturing method of the semiconductor device 20 according to an embodiment of the present disclosure, the electrode may be an anode EA, and the first pad P1 may be a cathode pad. The conductive film CF may be light-transmitting. In the first embodiment, the conductive film CF may be formed to contact the back surface 8B, the surface of the insulating film ZF, the upper surface MST of the mounting substrate MS, and the second pad P2. In the light-emitting element body 15 located on the mounting substrate MS, the insulating film ZF has a forward tapered shape. Specifically, the first side surface P1S and the third side surface P3S may have forward tapered surfaces. As described above, the insulating film ZF may have an obtuse angle θ1 formed between the first side surface P1S and the bottom surface ZFB. Furthermore, the insulating film ZF may have an obtuse angle θ3 formed between the third side surface P3S of the third portion ZP3 and the bottom surface ZFB. The insulating film ZF may have an angle θ3 equal to or substantially equal to the angle θ1. The term "substantially equal" allows for an error of about 1° that occurs during the manufacturing process, etc. The bottom surface ZFB may have a planar or substantially planar shape along the first direction (X-axis direction).

[0084] The above configuration makes it easy to form the conductive film CF continuously from the back surface 8B to the second pad P2. This allows for good connection between the light emitting element body 15 and the second pad P2. Furthermore, since the insulating film ZF is located between the first pad P1 and the second pad P2 on the mounting substrate MS, the possibility of a short circuit occurring between the first pad P1 and the second pad P2 can be effectively reduced.

[0085] In Example 1, the side surface LBS of the laminate LB may have a forward tapered shape on the growth substrate TS, and in this case, the side surface LBS has an inverse tapered shape on the mounting substrate MS. This can effectively improve the light extraction efficiency from the light emitting element 15. In one example of the present disclosure, the insulating film ZF reduces the influence of the shape of the laminate LB, and good connection between the light emitting element 15 and the second pad P2 can be achieved.

[0086] Furthermore, in one embodiment of the present disclosure, a conductive film CF is formed between the light emitting element body 15 and the second pad P2, contacting the upper surface MST of the mounting substrate MS. This increases the contact area (area) between the conductive film CF and the mounting substrate MS. As a result, the possibility of the conductive film CF peeling off from the mounting substrate MS can be effectively reduced.

[0087] In a method for manufacturing a semiconductor device 20 according to an embodiment of the present disclosure, a gap (internal gap, space) IS may be located between the insulating film ZF and the anode EA. When the semiconductor device 20 is in use, the insulating film ZF expands and contracts due to temperature fluctuations. By providing the gap IS, the semiconductor device 20 can prevent stress caused by the expansion and contraction of the insulating film ZF from being transmitted to the anode EA and the first pad P1. This effectively improves the reliability of the bond between the anode EA and the first pad P1.

[0088] The protrusion height H3 of the upper surface of the first pad P1 in the third direction (Z2-axis direction) relative to the upper surface MST of the mounting substrate MS located around the first pad P1, particularly the upper surface MST of the portion in contact with the top surface ZFT of the insulating film ZF. In one embodiment of the present disclosure, the protrusion height H2 of the second portion ZP2 may be greater than the sum of the protrusion height H1 of the anode EA and the protrusion height H3 of the first pad P1.

[0089] According to the above configuration, when the light emitting element 15 is transferred from the growth substrate TS to the mounting substrate MS, the light emitting element 15 is pressed against the mounting substrate MS, which makes it difficult for a gap to occur between the top surface ZFT and the upper surface MST of the mounting substrate MS. Even if a gap does occur, the size of the gap can be made as small as possible.

[0090] In one embodiment of the present disclosure, the protrusion height H2 may be greater than the sum of the protrusion height H1 and the protrusion height H3 by, for example, 1 μm or more. The protrusion height H2 may be smaller than the sum of the protrusion height H1 and the protrusion height H3 plus 3 μm. In one embodiment of the present disclosure, the anode EA of the laminate LB may be bonded to the first pad P1 via a bonding material such as solder. The bonding material such as solder may have a thickness of, for example, 1 to 3 μm.

[0091] The insulating film ZF may have a second side surface P2S of the second portion ZP2 having a forward tapered shape on the mounting substrate MS. The insulating film ZF may have an acute angle θ2 formed between the second side surface P2S and the top surface ZFT. The insulating film ZF may have an angle θ2 smaller than 90° and equal to or greater than 10°. The insulating film ZF may have an acute angle θ4 formed between the first side surface P1S and the top surface ZFT. The insulating film ZF may have an angle θ4 equal to or substantially equal to the angle θ2. This configuration reduces the possibility of a cut portion (discontinuous portion) occurring in the conductive film CF from the corner CP located at the intersection of the first side surface P1S and the top surface ZFT to the upper surface MST of the mounting substrate MS.

[0092] The corners CP may have, for example, a curved or polygonal shape. In this case, the shape of the corners CP may be formed by performing reflow after transferring the light emitting element 15 to the mounting substrate MS. This reduces the possibility of cuts (discontinuities) occurring in the conductive film CF at the corners CP. Alternatively, the thickness of the conductive film CF may be increased to reduce the possibility of cuts (discontinuities) occurring in the conductive film CF at the corners CP.

[0093] 17, the conductive film CF may have a discontinuous region (separated region) A1 at an end of the semiconductor portion 8 (e.g., tether portion T). The conductive film CF formed in a portion other than region A1 enables electrical connection between the light emitting element 15 and the second pad P2. In the semiconductor device 20, the upper surface of the tether portion T in the third direction (Z2-axis direction) may be covered with the conductive film CF, and the lower surface may be exposed. This may improve the heat dissipation of the light emitting element 15.

[0094] (Configuration example) (a) GaN-based semiconductors have the property of high absorbance of i-line (wavelength 365 nm). Therefore, for example, the light L may be i-line, and the insulator ZM may be a negative resist made of a material that can be patterned by i-line. In this case, the light L is less likely to reach the back surface 8B of the semiconductor portion 8 during pattern exposure. As a result, it is possible to make it less likely that an exposed portion EP will be generated on the back surface 8B side (in other words, the position of the void JD).

[0095] 19 is a cross-sectional view showing an example of a method for manufacturing a semiconductor substrate in one configuration example of Example 1. As shown in FIG. 19, the insulating film ZF of the semiconductor substrate 10 may not have the third portion ZP3. In this case, the insulator ZM in the gap JD can be easily removed. The insulating film ZF may be in contact with the end surface 8ES. This makes it easier to continuously form the conductive film CF in contact with the semiconductor portion 8 (rear surface 8B), the first portion ZP1, and the second pad P2 after transferring the light emitting element body 15 to the mounting substrate MS.

[0096] FIG. 20 is a plan view showing an example of a semiconductor substrate in one configuration example of the first embodiment. As shown in FIG. 20, the semiconductor substrate 10 may not have the third non-forming portion NF3, and the side surface LBS of the laminated body LB may be covered over the entire periphery with the insulating film ZF. By adjusting the wavelength of the light L and the material of the insulator ZM to make it difficult for the light L to reach the back surface 8B of the semiconductor portion 8, it is possible to make it difficult for an exposed portion EP to be generated in the gap JD. This makes it easier to ensure an injection path IC for the developer PD into the gap JD.

[0097] Fig. 21 is a plan view showing an example of a semiconductor substrate in one configuration example of Example 1. As shown in Fig. 21, the semiconductor substrate 10 does not have to have the second non-formation portion NF2 and the third non-formation portion NF3, but may have a fourth non-formation portion NF4 extending from the first non-formation portion NF1 in the second direction (Y-axis direction). In this case, an injection path IC for the developer PD can be provided between the back surface 8B of the semiconductor portion 8 and the growth substrate TS at the position of the fourth non-formation portion NF4.

[0098] In the manufacturing method of a semiconductor substrate according to one embodiment, the exposed portion EP may be formed so as to ensure an injection path IC for the developer PD into the gap JD, and the shape of the exposed portion EP may be adjusted as appropriate. For example, the fourth non-formation portion NF4 may be positioned so as to extend from the first non-formation portion NF1 in a direction away from the base portion B in the first direction (X-axis direction). The specific position and shape of the fourth non-formation portion NF4 are not particularly limited.

[0099] (b) By changing the exposure pattern PT of the photomask PM, it is possible to change the shape, position, etc. of the insulating film ZF on the semiconductor substrate 10. The exposure pattern PT may be any pattern that can be used to form the insulating film ZF by pattern exposure on the insulator ZM. The specific shape, etc. of the exposure pattern PT is not particularly limited.

[0100] (c) In Example 1, an example was described in which a negative resist was used as the insulator ZM, but in one aspect of the present disclosure, a positive resist may be used as the insulator ZM. In this case, the insulating film ZF may be formed by appropriately adjusting the optical path of the light L and pattern-exposing the positive resist.

[0101] (d) Fig. 22 is a cross-sectional view showing an example of the configuration of a laminate LB. As shown in the diagram indicated by reference numeral 2201 in Fig. 22, the laminate LB may have, for example, an n-type semiconductor layer 9N having a donor, an active layer 9K, a p-type semiconductor layer 9P having an acceptor, and a p-type contact layer 9C laminated in this order. The n-type semiconductor layer 9N may be a part of the wing portion F of the semiconductor portion 8 formed by the ELO method, or may be a regrowth layer formed on the wing portion F.

[0102] The specific configuration of the active layer 9K may be appropriately designed according to the desired emission wavelength and is not particularly limited. The n-type semiconductor layer 9N, the active layer 9K, and the p-type semiconductor layer 9P may each contain a GaN-based semiconductor. The laminate LB may include an anode EA in contact with the p-type contact layer 9C, and may have a blocking layer between the active layer 9K and the p-type semiconductor layer 9P.

[0103] As shown in the diagram indicated by reference numeral 2202 in FIG. 22, the laminate LB may have a transparent electrode layer TE located above the p-type semiconductor layer 9P. The transparent electrode layer TE may be made of, for example, ITO. The laminate LB may have an electrode plating portion PE in contact with the transparent electrode layer TE. The electrode plating portion PE may be a so-called UBM (Under Bump Metal).

[0104] When the laminate LB has an electrode plated portion PE, the description of the anode EA in this specification can be understood by replacing the anode EA with the electrode plated portion PE.

[0105] FIG. 23 is a cross-sectional view showing an example of a semiconductor substrate in one configuration example of Example 1. In a laminate LB having an electrode plating portion PE, the protruding height H1 of the second upper surface LBT2 of the electrode plating portion PE relative to the first upper surface LBT1 of the protective film PF may be the same as or approximately the same as the protruding height H2 of the top surface ZFT of the insulating film ZF. The electrode plating portion PE facilitates increasing the flatness of the second upper surface LBT2. When mounting a light emitting element body 15 including a laminate LB having an electrode plating portion PE on a mounting substrate MS, the first pad P1 of the mounting substrate MS may be bonded to the electrode plating portion PE by surface activation bonding. In this case, the first pad P1 and the electrode plating portion PE may be bonded by intermolecular forces without using a bonding material such as solder.

[0106] In Example 1, an example is shown in which the side surface LBS of the laminate LB has an inclined shape, but this is not limiting. The side surface LBS of the laminate LB may have a vertical shape along the third direction (Z1-axis direction). Furthermore, the side surface LBS of the laminate LB may have a stepped shape.

[0107] After the laminate LB is transferred to the mounting substrate MS, the light emitting element 15 is used as a micro LED. The light emitting element 15 may have an element size (chip size) of approximately 100 μm or less. The light emitting element 15 may have a distance from the back surface 8B of the semiconductor portion 8 to the second top surface LBT2 (element thickness in the third direction) of 10 μm or less.

[0108] The laminate LB is not limited to the above-mentioned configuration example, and any known configuration can be applied.

[0109] (e) In FIG. 1 and other figures, an example has been described in which the growth substrate TS has a mask pattern 6, but the present invention is not limited to this, and the growth substrate TS may have a non-seed portion DA formed by modifying (surface modifying) the base material. The growth substrate TS may not have a mask portion 5. Alternatively, the growth substrate TS may have a mask pattern 6, and a space may be formed below the back surface 8B of the semiconductor portion 8 by removing the mask portion 5. In this case, the space may be a gap JD in the active layer-containing substrate AK.

[0110] (f) As described above, the semiconductor portion 8 in the active layer-containing substrate AK can be formed by a known method. For example, International Publication Nos. 2024 / 084630 and 2024 / 084634 can be referenced for methods of forming the wing portion F so as to have the gap JD.

[0111] Furthermore, the tether portion T can be formed in various shapes. For example, International Publication No. 2024 / 122644 and the like can be referenced for configuration examples of the tether portion T. For example, the two tether portions T located on both sides of the base portion B in the first direction (X-axis direction) may have the same shape. For example, the two tether portions T located on both sides of the base portion B may be positioned along the first direction (X-axis direction). For example, the tether portion T may be positioned along the first direction (X-axis direction). The shape of the insulating film ZF (e.g., the shape of the exposure pattern PT) may be appropriately set to correspond to the shape of the tether portion T, and methods for manufacturing a semiconductor substrate 10 having tether portions T and insulating films ZF of such various shapes are also included within the technical scope of the invention according to the present disclosure.

[0112] Example 2 24 is a cross-sectional view showing an example of a method for manufacturing a semiconductor substrate in Example 2. As shown in FIG. 24, in the method for manufacturing a semiconductor substrate in Example 2, first, an active layer-containing substrate AK is prepared, and then an insulator ZM is applied to cover a laminate LB on a growth substrate TS. The insulator ZM may be, for example, an organic film. Heating may be performed after the application of the insulator ZM. The insulator ZM may be formed by a sputtering method, a CVD (Chemical Vapor Deposition) method, vapor deposition, or the like.

[0113] Next, the insulator ZM located above the laminate LB is removed by CMP (Chemical Mechanical Polishing), wet etching, dry etching, or the like. This allows the insulating film ZF to be formed in contact with the side surface LBS of the laminate LB. Then, an electrode can be formed on the laminate LB. While FIG. 24 shows an example in which the electrode is an anode EA, the aforementioned electrode plating portion PE may also be formed on the laminate LB.

[0114] The first portion ZP1 of the insulating film ZF may cover the end face 8ES of the semiconductor portion 8. In the second embodiment, the surface of the first portion ZP1 may include a curved surface. The insulating film ZF may have a first side surface P1S of the first portion ZP1 that is a curved surface. The insulating film ZF may not have the second portion ZP2 or the third portion ZP3.

[0115] Fig. 25 is a cross-sectional view showing an example of a manufacturing method for a semiconductor device in Example 2. As shown in Fig. 25, the stacked body LB is junction-down mounted on a mounting substrate MS. In the example shown in Fig. 25, the mounting substrate MS may have a dug portion MS1, and a first pad P1 is located within the dug portion MS1.

[0116] Then, the anode EA of the laminate LB is bonded to the first pad P1, thereby breaking the ridge portion R. Because the first pad P1 is located within the recessed portion MS1, the light emitting element 15 including the laminate LB and the insulating film ZF can be transferred to the mounting substrate MS so that the top surface ZFT of the insulating film ZF is in contact with the upper surface MST of the mounting substrate MS. Thereafter, a conductive film CF is formed in contact with the back surface 8B of the semiconductor portion 8, the first portion ZP1, and the second pad P2. This electrically connects the back surface 8B and the second pad P2 via the conductive film CF. The semiconductor device 20 may have a gap IS within the recessed portion MS1.

[0117] In one embodiment, for example, when the anode EA of the laminate LB is joined to the first pad P1 via solder, the volume of the space in the dug portion MS1 ​​excluding the first pad P1 may be larger than the volume of the solder. The depth and width of the dug portion MS1 ​​may be set appropriately.

[0118] The distance in the third direction between the surface of the first pad P1 and the upper surface MST of the mounting board MS may be smaller than the sum of the solder thickness and the protrusion height H1, and may be, for example, 3 μm or less.

[0119] FIG. 26 is a cross-sectional view showing an example of a manufacturing method for a semiconductor device of one configuration example in Example 2. As shown in FIG. 26, the anode EA of the laminate LB is bonded to the first pad P1, and the ridge portion R is broken, thereby transferring the light emitting element 15 including the laminate LB and the insulating film ZF to the mounting substrate MS. Next, reflow is performed, causing the softened insulating film ZF to sag. This allows the top surface ZFT of the insulating film ZF to abut against the upper surface MST of the mounting substrate MS. Thereafter, a conductive film CF is formed in contact with the back surface 8B of the semiconductor portion 8, the first portion ZP1, and the second pad P2. This electrically connects the back surface 8B and the second pad P2 via the conductive film CF.

[0120] In one configuration example of the second embodiment, as described above, the electrode plated portion PE may be formed on the laminated body LB, and in this case, the electrode plated portion PE and the first pad P1 may be surface activated bonded to each other.

[0121] Example 3 27 is a cross-sectional view showing an example of a method for manufacturing a semiconductor substrate in Example 3. As shown in FIG. 27, when the laminate LB has an electrode plating portion PE, for example, an insulator ZM is applied, and then a resin body RS is applied onto the growth substrate TS. The resin body RS may be, for example, a soluble resin. Then, the resin body RS and the insulator ZM are polished to the surface level of the electrode plating portion PE, for example, by CMP.

[0122] Next, the resin body RS is washed away using a solvent, thereby manufacturing the semiconductor substrate 10. Thereafter, as in Example 2, the electrode plating portion PE is bonded to the first pad P1 of the mounting substrate MS, and the ridge portion R is broken, thereby transferring the light emitting element body 15 including the laminate LB and the insulating film ZF to the mounting substrate MS.

[0123] [Additional notes] The invention according to the present disclosure has been described above based on various drawings and examples. However, the invention according to the present disclosure is not limited to the above-described embodiments and examples. In other words, the invention according to the present disclosure can be modified in various ways within the scope of the present disclosure, and embodiments obtained by appropriately combining the technical means disclosed in different embodiments and examples are also included in the technical scope of the invention according to the present disclosure. In other words, it should be noted that a person skilled in the art can easily make various modifications or corrections based on the present disclosure. It should also be noted that these modifications or corrections are included in the scope of the present disclosure.

[0124] 〔summary〕 A method for manufacturing a semiconductor substrate in aspect 1 of the present disclosure includes the steps of preparing an active layer-containing substrate including a growth substrate having a seed portion and a non-seed portion, a semiconductor portion extending from the seed portion above the non-seed portion, and a stack located above the semiconductor portion and including an active layer, and forming an insulating film in contact with a side surface of the stack, the side surface of the insulating film having a region where the distance from the stack in a direction along the top surface of the semiconductor portion increases upward.

[0125] In a method for manufacturing a semiconductor substrate in aspect 2 of the present disclosure, in aspect 1, the insulating film has a first portion in which the thickness along the top surface of the semiconductor portion increases upward, and the region is included in the first portion.

[0126] A third aspect of the present disclosure provides the method for manufacturing a semiconductor substrate according to the second aspect, wherein the first portion has an overhanging reverse tapered surface, and the region is included in the reverse tapered surface.

[0127] A fourth aspect of the present disclosure relates to the method for manufacturing a semiconductor substrate in the second or third aspect, wherein the first portion covers a side surface of the stack.

[0128] A fifth aspect of the present disclosure relates to the method for manufacturing a semiconductor substrate according to any one of the second to fourth aspects, wherein the insulating film has a second portion located on the upper surface of the stack.

[0129] A sixth aspect of the present disclosure relates to the method for manufacturing a semiconductor substrate according to any one of the first to fifth aspects, wherein the side surface of the stacked body is a forward tapered surface.

[0130] A seventh aspect of the present disclosure relates to the method for manufacturing a semiconductor substrate according to any one of the first to sixth aspects, wherein the stack includes a protective film that forms a side surface of the stack, and the protective film covers an end face of the active layer.

[0131] A method for manufacturing a semiconductor substrate according to an eighth aspect of the present disclosure is any one of the first to seventh aspects, wherein the stack includes an electrode, and at least a portion of the electrode is not in contact with the insulating film.

[0132] A ninth aspect of the present disclosure relates to the method for manufacturing a semiconductor substrate according to any one of the first to eighth aspects, wherein the insulating film is in contact with an end face of the semiconductor portion.

[0133] The method for manufacturing a semiconductor substrate in aspect 10 of the present disclosure is, in any one of aspects 1 to 9, a method for forming the insulating film by pattern-exposing a negative resist placed in a gap facing the laminate and then removing the unexposed portions of the negative resist.

[0134] A method for manufacturing a semiconductor substrate in aspect 11 of the present disclosure is any one of aspects 1 to 10, wherein the semiconductor portion includes a ridge portion, a base portion located on the ridge portion, and a wing portion connected to the base, and a gap is located between the wing portion and the growth substrate.

[0135] A twelfth aspect of the present disclosure provides the method for manufacturing a semiconductor substrate according to the eleventh aspect, wherein the stack is located above the wing portion.

[0136] A thirteenth aspect of the present disclosure provides the method for manufacturing a semiconductor substrate according to any one of the first to twelfth aspects, wherein the stack includes an electrode, and an upper surface of the insulating film is located above a surface of the electrode.

[0137] The method for manufacturing a semiconductor substrate in aspect 14 of the present disclosure is any one of aspects 11, 12, and 13 (citing aspect 11 or 12), in which the insulating film has a third portion located between the end of the semiconductor portion and the growth substrate.

[0138] The method for manufacturing a semiconductor substrate in aspect 15 of the present disclosure is any one of aspects 11, 12, and 13 (citing aspect 11 or 12), and aspect 14, wherein the wing portion includes a tether portion adjacent to the base portion, and the insulating film does not contact the tether portion.

[0139] The method for manufacturing a semiconductor substrate according to a sixteenth aspect of the present disclosure is the same as in the fifteenth aspect, except that a gap located below the tether portion is used as a path for injecting a developer when forming the insulating film.

[0140] A seventeenth aspect of the present disclosure relates to the method for manufacturing a semiconductor substrate according to any one of the second to sixteenth aspects (referring to the second aspect), in which the first portion covers an end face of the semiconductor portion.

[0141] The semiconductor substrate in aspect 18 of the present disclosure comprises a growth substrate having a seed portion and a non-seed portion, a semiconductor portion extending from the seed portion above the non-seed portion, a stack located above the semiconductor portion and including an active layer and an electrode, and an insulating film in contact with a side surface of the stack, the side surface of the insulating film having a region where the distance from the stack in a direction along the top surface of the semiconductor portion increases upward.

[0142] In aspect 19 of the present disclosure, the semiconductor substrate is the same as aspect 18, wherein the insulating film has a first portion in which the thickness along the top surface of the semiconductor portion increases upward, and the region is included in the first portion.

[0143] A semiconductor substrate according to a twentieth aspect of the present disclosure is the same as that according to the nineteenth aspect, wherein the first portion has an overhanging reverse tapered surface, and the region is included in the first portion.

[0144] In a twenty-first aspect of the present disclosure, the semiconductor substrate is the nineteenth or twentyth aspect, wherein the first portion covers a side surface of the stack.

[0145] A semiconductor substrate according to a twenty-second aspect of the present disclosure is any one of the nineteenth to twenty-first aspects, wherein the insulating film has a second portion extending over the stack.

[0146] A method for manufacturing a semiconductor device in aspect 23 of the present disclosure includes the steps of preparing a semiconductor substrate and a mounting substrate in any one of aspects 19 to 22, mounting the laminate so that the electrodes are in contact with the mounting substrate, and separating the semiconductor portion and the growth substrate.

[0147] A method for manufacturing a semiconductor device according to a twenty-fourth aspect of the present disclosure is the twenty-third aspect, wherein the mounting substrate includes a conductive pad, and further includes a step of forming a conductive film in contact with the semiconductor portion, the first portion, and the pad.

[0148] A twenty-fifth aspect of the present disclosure provides the method for manufacturing a semiconductor device according to the twenty-fourth aspect, wherein the semiconductor portion is a nitride semiconductor portion, and the conductive film is in contact with a nitrogen-polar face of the nitride semiconductor portion.

[0149] A twenty-sixth aspect of the present disclosure provides the method for manufacturing a semiconductor device according to the twenty-fourth or twenty-fifth aspect, wherein a gap is located between the insulating film and the electrode.

[0150] A twenty-seventh aspect of the present disclosure relates to the method for manufacturing a semiconductor device according to the twenty-fifth or twenty-sixth aspect (which cites the twenty-fifth aspect), and further relates to the method for manufacturing a semiconductor device according to the twenty-fifth aspect (which cites the twenty-fifth aspect), wherein the insulating film is raised on the nitrogen polarity face.

[0151] A twenty-eighth aspect of the present disclosure relates to the method for manufacturing a semiconductor device according to any one of the twenty-fourth to twenty-seventh aspects, wherein the conductive film has a region that is discontinuous at an end of the semiconductor portion.

[0152] A semiconductor device according to a twenty-ninth aspect of the present disclosure comprises a mounting substrate including a conductive pad, a nitride semiconductor portion, a stack located below the nitride semiconductor portion and mounted on the mounting substrate, and a conductive film in contact with the nitrogen-polar surface of the nitride semiconductor portion and the pad. [Explanation of symbols]

[0153] 1 Main board 5 Mask section 6 Mask Pattern 8. Semiconductor Department 9K active layer 10. Semiconductor substrate 15 Light-emitting element 20 Semiconductor Devices B base BS base board DA non-seed part EA anode F wing section H Main body JD void PF protective film P1S 1st side R ridge part SA Seed Department T tether part TS growth substrate ZF insulating film ZP1 1st part

Claims

1. The method includes the steps of preparing an active layer-containing substrate including a growth substrate having a seed portion and a non-seed portion, a semiconductor portion extending from the seed portion above the non-seed portion, and a stacked body including an active layer and positioned above the semiconductor portion, and forming an insulating film in contact with a side surface of the stacked body, A method for manufacturing a semiconductor substrate, wherein the side surface of the insulating film has a region in which the distance from the stack in a direction along the top surface of the semiconductor portion increases upward.

2. the insulating film has a first portion whose thickness in a direction along the top surface of the semiconductor portion increases upward; The method for manufacturing a semiconductor substrate according to claim 1 , wherein the region is included in the first portion.

3. the first portion has an overhanging reverse tapered surface, The method for manufacturing a semiconductor substrate according to claim 2 , wherein the region is included in the reverse tapered surface.

4. The method for manufacturing a semiconductor substrate according to claim 2 , wherein the first portion covers a side surface of the stack.

5. The method for manufacturing a semiconductor substrate according to claim 2 , wherein the insulating film has a second portion located on the upper surface of the stack.

6. The method for manufacturing a semiconductor substrate according to claim 1 , wherein the side surface of the stacked body is a forward tapered surface.

7. the laminate includes a protective film that forms a side surface thereof, The method for manufacturing a semiconductor substrate according to claim 1 , wherein the protective film covers an end face of the active layer.

8. the laminate includes an electrode; The method for manufacturing a semiconductor substrate according to claim 1 , wherein at least a portion of the electrode is not in contact with the insulating film.

9. The method for manufacturing a semiconductor substrate according to claim 1 , wherein the insulating film contacts an end face of the semiconductor portion.

10. The method for manufacturing a semiconductor substrate according to claim 1 , wherein the insulating film is formed by pattern-exposing a negative resist disposed in the gap facing the laminate and then removing an unexposed portion of the negative resist.

11. the semiconductor portion includes a ridge portion, a base portion located on the ridge portion, and a wing portion connected to the base portion; The method for manufacturing a semiconductor substrate according to claim 1 , wherein a gap is located between the wing portion and the growth substrate.

12. The method for manufacturing a semiconductor substrate according to claim 11 , wherein the stacked body is located above the wing portion.

13. the laminate includes an electrode; The method for manufacturing a semiconductor substrate according to claim 1 , wherein an upper surface of said insulating film is located above a surface of said electrode.

14. The method for manufacturing a semiconductor substrate according to claim 11 , wherein the insulating film has a third portion located between an end of the semiconductor portion and the growth substrate.

15. the wing portion includes a tether portion adjacent the base portion; The method for manufacturing a semiconductor substrate according to claim 11 , wherein the insulating film does not contact the tether portion.

16. The method for manufacturing a semiconductor substrate according to claim 15 , wherein a gap located below the tether portion is used as a path for injecting a developer when the insulating film is formed.

17. The method for manufacturing a semiconductor substrate according to claim 2 , wherein the first portion covers an end face of the semiconductor portion.

18. a growth substrate having a seed portion and a non-seed portion; a semiconductor portion extending from the seed portion above the non-seed portion; a stacked body located above the semiconductor portion and including an active layer and an electrode; and an insulating film in contact with a side surface of the stacked body; A semiconductor substrate, wherein the side surface of the insulating film has a region in which the distance from the stacked body in a direction along the top surface of the semiconductor portion increases upward.

19. the insulating film has a first portion whose thickness in a direction along the top surface of the semiconductor portion increases upward; The semiconductor substrate according to claim 18 , wherein the region is included in the first portion.

20. the first portion has an overhanging reverse tapered surface, The semiconductor substrate according to claim 19 , wherein the region is included in the first portion.

21. The semiconductor substrate according to claim 19 , wherein the first portion covers a side surface of the stack.

22. The semiconductor substrate according to claim 19 , wherein the insulating film has a second portion extending over the stack.

23. a step of preparing the semiconductor substrate and the mounting substrate according to claim 19; mounting the laminate so that the electrodes are in contact with the mounting substrate, and separating the semiconductor portion and the growth substrate.

24. the mounting substrate includes a conductive pad; The method for manufacturing a semiconductor device according to claim 23, further comprising forming a conductive film in contact with the semiconductor portion, the first portion, and the pad.

25. the semiconductor portion is a nitride semiconductor portion, The method for manufacturing a semiconductor device according to claim 24 , wherein the conductive film is in contact with a nitrogen-polar face of the nitride semiconductor portion.

26. The method for manufacturing a semiconductor device according to claim 24 , wherein a gap is located between the insulating film and the electrode.

27. 26. The method for manufacturing a semiconductor device according to claim 25, wherein the insulating film is elevated on the nitrogen polarity face.

28. 25. The method for manufacturing a semiconductor device according to claim 24, wherein the conductive film has a region that is discontinuous at an end of the semiconductor portion.

29. a mounting substrate including conductive pads; a nitride semiconductor portion; a stacked body located below the nitride semiconductor portion and mounted on the mounting substrate; a conductive film in contact with the nitrogen-polarity face of the nitride semiconductor portion and the pad.

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