Gate signal generation device

Abstract

To provide a gate signal generation device that generates a gate signal capable of further reducing ringing.SOLUTION: A switching interval S1 in which a gate waveform 200 representing a change of the gate signal changes from a pre-control voltage to a post-control voltage, a maintaining interval S1 following the switching interval S2 and maintaining the post-control voltage, an intermediate voltage start interval S2 following the maintaining interval S3 and changing from the post-control voltage to an intermediate voltage which is a voltage between the pre-control voltage and the post-control voltage, and an interval following the intermediate voltage start interval S3, and an intermediate voltage end interval S4 in which the voltage changes from the intermediate voltage to the post-control voltage at a plurality of types of voltage changing speeds including at least a speed higher than zero and lower than the maximum changing speed.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present invention relates to a gate signal generating device, and more particularly to a gate signal generating device that can suppress the occurrence of ringing. [Background technology]

[0002] Non-Patent Document 1 discloses a gate waveform that can reduce ringing. The gate waveform disclosed in Non-Patent Document 1 drops from 20V to 0V, and then after a certain time has passed, rises in a pulsed manner to an intermediate voltage lower than 20V. After maintaining the intermediate voltage for a while, it drops again in a pulsed manner to 0V. The contents of the prior art documents are incorporated by reference as explanations of the technical elements in this specification. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Junichi Ito, "Development of noise-free USPM with ultra-high-speed digital control and its application technology", p. 20, [online], Japan Science and Technology Agency, [Retrieved July 16, 2024], Internet < URL: https: / / www.jst.go.jp / sip / dl / p08 / 2022annual_report_ioe04.pdf > Summary of the Invention [Problem to be solved by the invention]

[0004] Ringing can be reduced by the gate waveform disclosed in Non-Patent Document 1. However, further reduction of ringing is desired.

[0005] The present disclosure has been made based on this situation, and an object of the present disclosure is to provide a gate signal generating device that generates a gate signal that can further reduce ringing. [Means for solving the problem]

[0006] The above object is achieved by the combination of features recited in the independent claims, and the subclaims define further advantageous specific examples. The reference numerals in parentheses in the claims correspond to specific aspects described in the following embodiments as one aspect, and do not limit the technical scope of the disclosure.

[0007] One disclosure to achieve the above objective is: A gate signal generating device that generates a gate signal to be input to a gate terminal of a switching element (20) having a gate terminal, The gate waveform (100, 200, 300, 400) that represents the change in the gate signal is A switching section (S1) in which the voltage before control changes to the voltage after control; A maintenance section (S2) following the switching section, in which the voltage is maintained after control; an intermediate voltage start section (S3) following the sustain section, in which the voltage changes from the post-control voltage to an intermediate voltage between the pre-control voltage and the post-control voltage; and an intermediate voltage end section (S4) following the intermediate voltage start section, in which the voltage change rate changes from the intermediate voltage to the controlled voltage at a plurality of voltage change rates including at least a rate faster than zero and slower than the maximum change rate. A gate signal generating device that generates a gate signal.

[0008] The gate signal generated by this gate signal generator changes from a pre-control voltage to a post-control voltage in the switching section, and also changes from the post-control voltage to an intermediate voltage in the intermediate voltage start section. Ringing occurring in the switching element due to the gate waveform in the intermediate voltage start section can at least partially cancel out ringing occurring in the switching element due to the gate waveform in the switching section.

[0009] In addition, the gate waveform in the intermediate voltage end section changes from the intermediate voltage to the controlled voltage at multiple voltage change rates, including at least a rate faster than zero and slower than the maximum change rate. Therefore, ringing in the switching element is suppressed by the gate waveform in the intermediate voltage end section compared to when the voltage changes from the intermediate voltage to the controlled voltage at the maximum change rate. Therefore, this gate signal generator can further reduce ringing in the switching element. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing the configuration of a gate signal generating device. [Figure 2] FIG. 10 is a diagram showing an example of a gate waveform. [Figure 3] FIG. 10 is a diagram showing waveforms of a second comparative example and changes in the drain-source voltage Vds. [Figure 4] 10A and 10B are diagrams showing changes in gate waveforms and drain-source voltage Vds in an embodiment. [Figure 5] A diagram showing the circuit configuration set up for the simulation. [Figure 6] FIG. 10 is a diagram showing a simulation result of the first comparative example. [Figure 7] FIG. 10 is a diagram showing a simulation result of a second comparative example. [Figure 8] FIG. 10 is a diagram showing a simulation result of the first embodiment. [Figure 9] FIG. 4 is a diagram for explaining gate waveforms in the first embodiment. [Figure 10] FIG. 4 is a diagram showing the relationship between frequency and amplitude spectrum in the first comparative example, the second comparative example, and the first embodiment. [Figure 11] FIG. 10 is a diagram showing the results of switching using the gate waveform of the second embodiment. [Figure 12] FIG. 10 is a diagram for explaining gate waveforms in the second embodiment. [Figure 13] FIG. 10 is a diagram showing the results of switching using the gate waveform of the third embodiment. [Figure 14] FIG. 10 is a diagram for explaining gate waveforms in the third embodiment. [Figure 15]FIG. 10 is a diagram showing the relationship between frequency and amplitude spectrum in the first, second, and third embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, an embodiment will be described with reference to the drawings. FIG. 1 is a diagram showing the configuration of a gate signal generating device 10. The gate signal generating device 10 is a device that generates a gate signal to be input to a gate terminal of a switching element 20 having a gate terminal. FIG. 1 shows an n-channel MOSFET as the switching element 20. However, the switching element 20 is not limited to an n-channel MOSFET. The switching element 20 may be a p-channel MOSFET or an IGBT.

[0012] The gate signal generating device 10 includes a controller 11, a gate driver IC 12, and a resistor 13. The controller 11 inputs an instruction signal to the gate driver IC 12 to generate a gate signal. The gate driver IC 12 generates a gate signal by amplifying the instruction signal input from the controller 11. The gate signal generated by the controller 11 passes through the resistor 13 and is input to the gate terminal of the switching element 20. The gate signal generating device 10 shown in FIG. 1 is an example. The gate signal generating device 10 may be configured to generate the gate signals described below.

[0013] [Gate waveform concept] A waveform showing a time change of a gate signal generated by the gate signal generating device 10 is referred to as a gate waveform. FIG. 2 shows a gate waveform 100 as a gate waveform of an embodiment. The gate waveform 100 is a waveform when an n-channel MOSFET is turned from on to off. The gate waveform 100 includes a switching section S1, a sustain section S2, an intermediate voltage start section S3, and an intermediate voltage end section S4.

[0014] The switching section S1 is a section in which the voltage changes from a pre-control voltage to a post-control voltage. In the case of the gate waveform 100, the pre-control voltage is the voltage that turns on the switching element 20, for example, 5V. 5V can also be referred to as a high-level voltage. Time t0 is the start time of the switching section S1. The start time of the switching section S1 can also be referred to as the start time of switching control that changes the on / off state of the switching element 20. The post-control voltage is the voltage after the intermediate voltage end section S4 ends, for example, 0V. 0V can also be referred to as a low-level voltage. In Figure 2, time t1 is the end time of the switching section S1.

[0015] In the gate waveform 100, the voltage change rate in the switching section S1 is the maximum change rate. The maximum change rate refers to the voltage change rate of the gate signal output by the gate driver IC12 when the controller 11 inputs a step-like instruction signal that changes from high to low or from low to high to the gate driver IC12. Even if the controller 11 inputs a step-like instruction signal to the gate driver IC12, it is not possible to change the voltage generated by the gate driver IC12 to 0 V in zero time, which is why the switching section S1 occurs.

[0016] The sustain section S2 is a section following the switching section S1, in which the post-control voltage is maintained. In FIG. 2, the sustain section S2 extends from time t1 to time t2. The intermediate voltage start section S3 is a section following the sustain section S2, in which the post-control voltage changes to an intermediate voltage, which is a voltage between the pre-control voltage and the post-control voltage. In FIG. 2, the intermediate voltage start section S3 extends from time t2 to time t3. The intermediate voltage refers to the voltage that is closest to the pre-control voltage after the sustain section S2. The intermediate voltage in the gate waveform 100 is the highest voltage that becomes after the voltage becomes 0V in the sustain section S2. The level of the intermediate voltage will be described later.

[0017] The intermediate voltage end section S4 is a section following the intermediate voltage start section S3, in which the voltage changes from the intermediate voltage to the controlled voltage at multiple voltage change rates that are at least faster than zero and slower than the maximum change rate. In Figure 2, the intermediate voltage end section S4 runs from time t3 to time t7.

[0018] The intermediate voltage end section S4 of the gate waveform 100 changes to the controlled voltage at four different voltage change rates. Specifically, the intermediate voltage end section S4 of the gate waveform 100 includes multiple sections (hereinafter, "subsections") with different voltage change rates. The subsection from time t3 to t4 is the first subsection, the subsection from time t4 to t5 is the second subsection, the subsection from time t5 to t6 is the third subsection, and the subsection from time t6 to t7 is the fourth subsection.

[0019] The third subsection from time t5 to time t6 is a section where the voltage change rate is zero. There is voltage change in the remaining subsections. That is, the voltage change rate in the remaining subsections is faster than zero. Also, the voltage change rate in the remaining subsections is slower than the voltage change rate in the switching section S1. That is, the voltage change rate in the remaining subsections is slower than the maximum change rate.

[0020] The reason why the gate waveform 100 is a waveform including four sections will be explained using FIGS. 3 and 4. Note that FIGS. 3 and 4 are both conceptual graphs. FIG. 3 shows one comparative example, the second comparative example described below. In FIG. 3, the upper part is the gate waveform Wc of the second comparative example (hereinafter referred to as the second comparative example waveform). The lower part is the waveform of the drain-source voltage Vds of the switching element 20 (hereinafter referred to as the DS waveform) when the second comparative example waveform Wc is input to the gate terminal of the switching element 20. The middle part is the waveform in the lower part separated into its components. In other words, the waveform in the lower part can be said to be a combination of the waveforms in the middle part.

[0021] In the second comparative example waveform Wc, the lengths of the switching section S1 and the sustaining section S2 are the same as those of the switching section S1 and the sustaining section S2 of the gate waveform 100. The voltage change rate in the intermediate voltage start section S3 of the second comparative example waveform Wc is the same as that in the intermediate voltage start section S3 of the gate waveform 100. However, the intermediate voltage is a value slightly lower than that of the gate waveform 100. In the intermediate voltage end section S4 of the second comparative example waveform Wc, the voltage is maintained at the intermediate voltage for a certain period of time and then changes to 0 V at the maximum change rate. In the intermediate voltage end section S4, the section in which the intermediate voltage is maintained is designated S4-1, and the section in which the voltage changes to 0 V at the maximum change rate is designated S4-2.

[0022] In the middle waveform, V(S1), V(S3), and V(S4-2) conceptually represent the changes in the drain-source voltage Vds caused by the voltage changes in sections S1, S3, and S4-2 of the second comparative example waveform Wc, respectively.

[0023] The waveform in the bottom row can be thought of as the sum of the waveforms in the middle row. Ringing occurs in the waveform in the bottom row. The reason for the ringing in the waveform in the bottom row is presumably because the waveform of V(S3) does not sufficiently cancel out the waveform of V(S1), and because the waveform of V(S4-2) increases the ringing.

[0024] Next, Fig. 4 will be described. In Fig. 4, the upper part is the gate waveform 100 described in Fig. 2, and the lower part is the D-S waveform when the gate waveform 100 is input to the gate terminal of the switching element 20. The middle part is the waveform in the lower part separated into its components.

[0025] At time t11, the voltage of the gate waveform 100 falls below the threshold voltage of the switching element 20. This causes the drain-source voltage Vds to start rising. As in FIG. 3, V(S1) in the middle section conceptually shows the D-S waveform generated by the voltage change in the switching section S1 of the gate waveform 100. In the intermediate voltage start section S3, the gate voltage rises again to the intermediate voltage, resulting in the waveform V(S3) shown in the middle section. The start time of the intermediate voltage start section S3 is set so that the peak occurrence time of the waveform V(S3) overlaps with the peak occurrence time of V(S1).

[0026] The waveform of V(S3) shown in the middle of Figure 3 becomes larger as the intermediate voltage increases. If V(S3) is increased, V(S3) can cancel out V(S1). However, in the second comparative example waveform Wc, the voltage changes from the intermediate voltage at the maximum rate of change in section S4-2. If the intermediate voltage is increased, the waveform of V(S4-2) becomes larger, which may increase ringing. Therefore, the intermediate voltage cannot be increased in the second comparative example waveform Wc.

[0027] On the other hand, in the gate waveform 100, the voltage decreases at a rate slower than the maximum rate of change during the intermediate voltage end section S4. This suppresses fluctuations in the drain-source voltage Vds due to voltage changes during the intermediate voltage end section S4. Therefore, the middle section of FIG. 4 does not show fluctuations in the drain-source voltage due to the gate waveform 100 during the intermediate voltage end section S4. Because fluctuations in the drain-source voltage Vds due to the gate waveform 100 during the intermediate voltage end section S4 are unlikely to occur, the intermediate voltage can be set to a level that generates V(S3) that can cancel out V(S1).

[0028] The start time of the intermediate voltage start section S3 is determined so that the peak of V(S3), which can cancel out V(S1), overlaps with the peak of V(S1). The voltage change rate during the intermediate voltage start section S3 may be the maximum change rate, but it does not necessarily have to be the maximum change rate. A slower voltage change rate generates more heat. However, the voltage change rate during the intermediate voltage start section S3 may be slowed down within an acceptable range for the amount of heat generated. The start time of the intermediate voltage start section S3 is determined based on the value of the intermediate voltage and the voltage change rate.

[0029] As shown in the middle of Fig. 4, in the gate waveform 100, V(S3) can cancel out V(S1), and fluctuations in the drain-source voltage Vds caused by the gate waveform 100 in the intermediate voltage end section S4 are suppressed. Therefore, as shown in the bottom of Fig. 4, ringing in the drain-source voltage Vds is sufficiently suppressed.

[0030] [Simulation Results] So far, we have conceptually explained how ringing can be suppressed by inputting the waveform to the gate terminal of switching element 20 as gate waveform 100 shown in Fig. 4. Next, we will explain how ringing can be suppressed using simulation results.

[0031] Figure 5 shows the circuit configuration set up for the simulation. In Figure 5, the source terminal of the switching element 20 is connected to ground and the negative terminal of the power supply 30, the drain terminal is connected to an ammeter 31, and the gate terminal is connected to one end of a resistor 13. A resistor 32 and a coil 33 are connected in series between the ammeter 31 and the positive terminal of the power supply 30. A gate waveform generator 34 generates a gate waveform and has the functions of the controller 11 and the gate driver IC 12.

[0032] The simulation results shown in FIG. 6 are for the first comparative example. The gate waveform used in the first comparative example is a waveform that includes only the switching section S1 of the gate waveform 100. As shown in FIG. 6, when the gate waveform of the first comparative example is used, large ringing occurs. The simulation results shown in FIG. 7 are for the second comparative example. It can be seen that when the second comparative example waveform Wc is used, ringing is suppressed more than in the inter-DS waveform of FIG. 6.

[0033] 8 is a simulation result obtained by switching the switching element 20 using the gate waveform 200 according to the first embodiment. The gate waveform 200 is derived by using the gradient method to minimize ringing by making the voltage change rate in the intermediate voltage end section S4 variable.

[0034] The gate waveform 200 is also shown in FIG. 9. As shown in FIG. 9, the gate waveform 200 also includes a switching section S1, a sustaining section S2, an intermediate voltage start section S3, and an intermediate voltage end section S4. The voltage change rate in the switching section S1 of the gate waveform 200 is the same as that in the switching section S1 of the gate waveform 100. The intermediate voltage of the gate waveform 200 is also the same as that in the gate waveform 100. The intermediate voltage end section S4 of the gate waveform 200 includes a first subsection S4-1, a second subsection S4-2, and a third subsection S4-3. The first subsection S4-1 of the gate waveform 200 is a section immediately after the intermediate voltage is reached, in which the voltage gradually decreases. The second subsection S4-2 of the gate waveform 200 is a section in which there is no voltage change. The third subsection S4-3 of the gate waveform 200 is a section in which the voltage decreases at the maximum change rate. As shown in FIG. 8, when the gate waveform 200 is used, ringing is further suppressed than when the second comparative example waveform Wc is used.

[0035] Fig. 10 shows the relationship between frequency and amplitude spectrum when using the gate waveforms of the first comparative example, the second comparative example, and the first embodiment. As shown in Fig. 10, the second comparative example has reduced high-frequency noise more than the first comparative example, and the first embodiment has reduced high-frequency noise even more than the second comparative example. The first embodiment has reduced high-frequency noise by up to 90% (approximately 20 dB) compared to the second comparative example.

[0036] Heat generation was also confirmed in the simulation. Table 1 summarizes the simulation results for peak voltage, heat generation, and high-frequency noise. In the first embodiment, the peak voltage was reduced by 3% compared to the second comparative example, and the high-frequency noise was also reduced compared to the second comparative example. Note that the heat generation in the first embodiment was slightly higher than in the second comparative example.

[0037] [Table 1] [Another simulation result] Next, another simulation result is shown. The simulation result shown in FIG. 11 is the result of switching the switching element 20 using a gate waveform 300 according to a second embodiment. The gate waveform 300 is also shown in FIG. 12. As shown in FIG. 12, the gate waveform 300 also comprises a switching interval S1, a sustain interval S2, an intermediate voltage start interval S3, and an intermediate voltage end interval S4. The voltage change rate in the switching interval S1 of the gate waveform 300 is the same as that in the switching interval S1 of the gate waveform 100. Furthermore, the intermediate voltage of the gate waveform 300 is the same as that of the gate waveform 100.

[0038] The intermediate voltage end section S4 of the gate waveform 300 also includes a first subsection S4-1, a second subsection S4-2, and a third subsection S4-3. The first subsection S4-1 of the gate waveform 300 is a section immediately after the intermediate voltage is reached, in which the voltage gradually decreases. The voltage change rate in the first subsection S4-1 of the gate waveform 300 is the same as the voltage change rate in the first subsection S4-1 of the gate waveform 200. However, the first subsection S4-1 of the gate waveform 300 is longer than the first subsection S4-1 of the gate waveform 200. Therefore, the voltage in the second subsection S4-2 of the gate waveform 300 is lower than the voltage in the second subsection S4-2 of the gate waveform 200. The second subsection S4-2 of the gate waveform 300 is a section in which there is no voltage change. The second subsection S4-2 of the gate waveform 300 is longer than the second subsection S4-2 of the gate waveform 200. The third subsection S4-3 of the gate waveform 300 is the section where the voltage changes at the maximum rate of change down to 0 V. The gate waveform 300 is derived by using the gradient method to minimize ringing while fixing the rate of voltage change in this third subsection S4-3.

[0039] The simulation results shown in Figure 13 are the results of switching the switching element 20 using a gate waveform 400 according to the third embodiment. The gate waveform 400 is also shown in Figure 14. As shown in Figure 14, the gate waveform 400 also comprises a switching section S1, a sustaining section S2, an intermediate voltage start section S3, and an intermediate voltage end section S4. The voltage change rate in the switching section S1 of the gate waveform 400 is the same as that in the switching section S1 of the gate waveform 100. The intermediate voltage of the gate waveform 400 is 2.0 V, which is slightly lower than the intermediate voltage of the gate waveform 100.

[0040] The intermediate voltage end section S4 of the gate waveform 400 includes a first subsection S4-1 and a second subsection S4-2. The first subsection S4-1 of the gate waveform 400 is a section immediately after the voltage reaches the intermediate voltage and is an intermediate voltage maintenance section in which the voltage is maintained at the intermediate voltage. In the second subsection S4-2 of the gate waveform 400, the voltage changes from the intermediate voltage to 0 V at a voltage change rate significantly slower than the maximum change rate.

[0041] FIG. 15 shows the relationship between frequency and amplitude spectrum when using the gate waveforms of the first, second, and third examples. As shown in FIG. 15, the first and third examples reduce high-frequency noise to the same extent. The second example is less effective at reducing high-frequency noise than the first and third examples. However, the second example also reduces high-frequency noise more than the second comparative example shown in FIG. 10.

[0042] Table 2 summarizes the simulation results to date.

[0043] [Table 2] The first embodiment is able to lower the peak voltage and also effectively reduce high-frequency noise. The second embodiment is inferior to the first embodiment in reducing high-frequency noise, but has the same peak voltage as the first embodiment. The third embodiment has a slightly higher peak voltage than the first and second embodiments. However, the peak voltage of the third embodiment is lower than the first and second comparative examples. Furthermore, the third embodiment is able to reduce high-frequency noise to the same level as the first embodiment.

[0044] [Summary of implementation] The gate waveforms 100, 200, 300, and 400 generated by the gate signal generating device 10 not only change from a pre-control voltage of 5V to a post-control voltage of 0V in the switching section S1, but also change from 0V to an intermediate voltage in the intermediate voltage start section S3. The ringing occurring in the switching element 20 in the gate waveforms 100, 200, 300, and 400 in the intermediate voltage start section S3 can at least partially cancel out the ringing occurring in the switching section S1.

[0045] Additionally, the gate waveforms 100, 200, 300, and 400 in the intermediate voltage end section S4 change from the intermediate voltage to 0 V at multiple voltage change rates, including at least a rate faster than zero and slower than the maximum change rate. For example, the gate waveform 100 changes from the intermediate voltage to 0 V at four different voltage change rates in the intermediate voltage end section S4. The gate waveforms 200 and 300 change from the intermediate voltage to 0 V at three different voltage change rates in the intermediate voltage end section S4. The gate waveform 400 changes from the intermediate voltage to 0 V at two different voltage change rates in the intermediate voltage end section S4.

[0046] Therefore, compared to when the voltage changes from the intermediate voltage to 0 V at the maximum change rate, ringing occurring in the switching element 20 is suppressed in the gate waveforms 100, 200, 300, and 400 in the intermediate voltage end section S4. Therefore, according to this gate signal generating device 10, ringing occurring in the switching element 20 can be further suppressed.

[0047] Furthermore, the voltage change rate of the gate waveforms 100, 200, and 300 in the first subinterval S4-1, which is the interval immediately following the intermediate voltage start interval S3, is faster than zero and slower than the maximum change rate. This increases the intermediate voltage, and the gate waveforms 100, 200, and 300 in the intermediate voltage start interval S3 can more effectively cancel out the ringing that occurs in the switching interval S1. As a result, the peak voltage can be reduced.

[0048] Furthermore, in the gate waveforms 200 and 300, in addition to the voltage change rate in the first subsection S4-1 as described above, the voltage change rate in the final section where the voltage changes to the post-controlled voltage in the intermediate voltage end section S4 is the maximum change rate. This allows the peak voltage to be lowered, as shown in the first and second examples in Table 2. Furthermore, the control can be terminated earlier than when the voltage change rate in the final section where the voltage changes to the post-controlled voltage is slower than the maximum change rate.

[0049] The second comparative example waveform Wc also has the same maximum voltage change rate in the final section where the voltage changes to the post-control voltage. Nevertheless, as the simulation results show, the peak voltages of the gate waveforms 200 and 300 are lower. The reason why the peak voltages of the gate waveforms 200 and 300 are lower is considered as follows.

[0050] The voltage change rate in the first subinterval S4-1 is faster than zero and slower than the maximum change rate, allowing the intermediate voltage to be increased. Increasing the intermediate voltage allows the initial one or more oscillations in the drain-source voltage Vds caused by the switching interval S1 to be canceled out by the fluctuations in the drain-source voltage Vds caused by the intermediate voltage start interval S3. However, subsequent fluctuations in the drain-source voltage Vds may be greater due to the fluctuations in the drain-source voltage Vds caused by the gate waveforms 200 and 300 in the intermediate voltage start interval S3. It is estimated that the fluctuations in the drain-source voltage Vds caused by the intermediate voltage start interval S3 are canceled out by the fluctuations in the drain-source voltage Vds caused by the gate waveforms 200 and 300 in the intermediate voltage start interval S3 in the final interval where the drain-source voltage Vds changes to the post-control voltage in the intermediate voltage end interval S4.

[0051] The intermediate voltage end section S4 of the gate waveform 400 comprises a first subsection S4-1 immediately following the intermediate voltage start section S3, in which the voltage does not change, and a subsequent second subsection in which the voltage change rate is faster than zero and slower than the maximum change rate.

[0052] Even in this way, the peak voltage can be reduced more than in the first and second comparative examples, as shown in Table 2 for the third embodiment. Also, high frequency noise can be reduced to the same extent as in the first embodiment.

[0053] Although the embodiments have been described above, the disclosed technology is not limited to the above-described embodiments, and the following modifications are also included in the scope of the disclosure. Furthermore, various modifications other than those described below can be made without departing from the spirit of the invention.

[0054] For example, the above-described embodiment is a gate waveform when the switching element 20 is turned from on to off. However, the above-described technique can also be applied when the switching element 20 is turned from off to on. When the switching element 20 is turned from off to on, the pre-control voltage is 0 V and the post-control voltage is, for example, 5 V.

[0055] In the above-described embodiment, the voltage change rate in the intermediate voltage end section S4 was four for gate waveform 100, three for gate waveforms 200 and 300, and two for gate waveform 400. In terms of the number of times the voltage change rate changes in the intermediate voltage end section S4, these are three, two, and one, respectively. However, the voltage change rate in the intermediate voltage end section S4 may be five or more times, or the number of times the voltage change rate changes may be four or more times. [Explanation of symbols]

[0056] 20...switching element, 100...gate waveform, 200...gate waveform, 300...gate waveform, 400...gate waveform, S1...switching section, S2...sustaining section, S3...intermediate voltage starting section, S4...intermediate voltage ending section

Claims

1. A gate signal generating device for generating a gate signal to be input to a gate terminal of a switching element (20) having a gate terminal, A gate waveform (100, 200, 300, 400) representing the change in the gate signal is A switching section (S1) in which the voltage changes from a pre-control voltage to a post-control voltage; a sustaining section (S2) following the switching section, in which the post-control voltage is maintained; an intermediate voltage start section (S3) following the sustain section, in which the post-control voltage is changed to an intermediate voltage between the pre-control voltage and the post-control voltage; an intermediate voltage end section (S4) following the intermediate voltage start section, in which the voltage change rate changes from the intermediate voltage to the controlled voltage at a plurality of voltage change rates including at least a rate faster than zero and slower than a maximum change rate; a gate signal generating device that generates the gate signal;

2. In the intermediate voltage end section of the gate waveform (100, 200, 300), the voltage change rate in the section immediately following the intermediate voltage start section is faster than zero and slower than the maximum change rate.

2. The gate signal generating device according to claim 1.

3. In the intermediate voltage end section of the gate waveform (200, 300), the voltage change rate in the last section where the voltage changes to the controlled voltage is the maximum change rate.

3. The gate signal generating device according to claim 2.

4. The intermediate voltage end section of the gate waveform (400) is an intermediate voltage maintaining section immediately following the intermediate voltage starting section, in which the voltage does not change; a section following the intermediate voltage maintaining section, in which the voltage change rate is faster than zero and slower than the maximum change rate; 2. The gate signal generating device according to claim 1.

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