Decoding device

Abstract

To provide a decoding device capable of reducing a circuit area.SOLUTION: A cutout circuit of a decoding device calculates a first code length of a first symbol. The cutout circuit calculates a second code length of a second symbol. The extraction circuit determines first context information corresponding to a third symbol. The extraction circuit determines second context information corresponding to a fourth symbol. The extraction circuit stores the first context information and first boundary position information. The extraction circuit stores the second context information and second boundary position information. The cutout circuit acquires third context information and third boundary position information corresponding to a plurality of fifth symbols following the third symbol. The cutout circuit acquires fourth context information and fourth boundary position information corresponding to a sixth symbol following the fourth symbol.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] SUMMARY OF THE INVENTION Embodiments of the present invention relate to a data compression circuit and a memory system. [Background technology]

[0002] A memory system is known that reduces the size of data received from a host by losslessly compressing the data. When transmitting data to the host, the memory system decompresses the compressed data, decodes the data, and transmits the decoded data to the host.

[0003] A decoding device that performs this data decoding has a high throughput if it can decode a large amount of data per unit time. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent Application Publication No. 2021 / 0250043 [Patent Document 2] US Patent Application Publication No. 2019 / 0044534 [Patent Document 3] US Patent Application Publication No. 2020 / 0145020 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a decoding device that can reduce the circuit area. [Means for solving the problem]

[0006] According to an embodiment, a decoding device decodes input first data. The decoding device includes an extraction circuit and a decoding circuit. The extraction circuit extracts one or more symbols from the first data. The decoding circuit performs a decoding process on the one or more symbols. The extraction circuit includes a first code length calculation circuit, a second code length calculation circuit, a first decision circuit, a second decision circuit, a first register, a second register, a first update circuit, a second update circuit, and an output circuit. The first code length calculation circuit calculates code lengths of multiple first symbols when the first symbols are considered to be coded using a first coding scheme, with each bit included in a first bit string consisting of multiple bits included in a cut-out range of the first data as a starting position. The second code length calculation circuit calculates second code lengths of multiple second symbols when the second symbols are considered to be coded using a second coding scheme, with each bit included in the first bit string as a starting position. The first decision circuit determines first context information indicating whether a third symbol following each of the plurality of first symbols is encoded using the first encoding scheme or the second encoding scheme. The second decision circuit determines second context information indicating whether a fourth symbol following each of the plurality of second symbols is encoded using the first encoding scheme or the second encoding scheme. The first register stores the first context information and first boundary information that is determined based on the first code length and indicates the position of the first bit of the third symbol. The second register stores the second context information and second boundary position information that is determined based on the second code length and indicates the position of the first bit of the fourth symbol. The first update circuit obtains third context information corresponding to a fifth symbol following each of the third symbols and third boundary position information that indicates the first bit of the fifth symbol based on the first context information and the first boundary position information stored in the first register, and stores them in the first register.The second update circuit stores, in the second register, fourth context information corresponding to a sixth symbol following each of the fourth symbols and fourth boundary position information indicating the first bit of the sixth symbol, based on the second context information and the second boundary position information stored in the second register. The extraction circuit further includes an output circuit that extracts one or more symbols from the bit string in the extraction range, based on the plurality of pieces of context information and the plurality of pieces of boundary position information stored in the first register and the second register, and outputs the extracted symbols to the decoding circuit. The decoding circuit performs the decoding process on each of the extracted one or more symbols. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a block diagram showing an example of the configuration of an information processing system including a memory system including a decoding device according to an embodiment. [Figure 2] 3A and 3B are diagrams for explaining data compression processing and data decompression processing executed by a decoding device and an encoding device according to an embodiment. [Figure 3] FIG. 1 is a diagram showing an example of dictionary-based coding in a memory system including a decoding device according to an embodiment. [Figure 4] FIG. 2 is a diagram showing an example of a compressed stream in a memory system including a decoding device according to an embodiment. [Figure 5] 1A and 1B are diagrams showing examples of match symbols in a memory system including a decoding device according to an embodiment. [Figure 6] 1 is a diagram showing a Huffman tree used in entropy coding in a memory system including a decoding device according to an embodiment. [Figure 7] FIG. 2 is a block diagram showing an example of the configuration of a clipping circuit included in the decoding device according to the embodiment. [Figure 8] FIG. 10 is a diagram showing an extraction process for extracting a plurality of symbols from a compressed stream in a comparative example. [Figure 9]FIG. 10 is a diagram for explaining a detailed configuration example of a cutting circuit in a comparative example. [Figure 10] 10A and 10B are diagrams showing 2N-symbol-ahead boundary position information and output bit strings generated by extraction processing in a comparative example. [Figure 11] FIG. 2 is a diagram for explaining a detailed configuration example of a cutout circuit included in the decoding device according to the embodiment. [Figure 12] 10A and 10B are diagrams showing 2N-symbol-ahead boundary position information and an output bit string generated by the extraction process executed in the decoding device according to the embodiment. [Figure 13] 10 is a flowchart showing the procedure of a code length calculation process in the extraction process executed in the decoding device according to the embodiment. [Figure 14] 10 is a flowchart showing the procedure of boundary update processing in the cutout processing executed in the decoding device according to the embodiment. [Figure 15] 10 is a flowchart showing an output bitstream output process of the extraction process executed by the decoding device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an embodiment will be described with reference to the drawings. 1 is a block diagram showing an example configuration of an information processing system 1 including a memory system 3 including a decoding device 46 according to an embodiment. The memory system 3 including the decoding device 46 according to an embodiment is, for example, a solid state device (SSD). The memory system 3 may be any of various types of storage devices such as a hard disk drive (HDD), a universal serial bus (USB) memory, a memory card, an optical disk device, etc. The memory system 3 is capable of communicating with a host 2.

[0009] The information processing system 1 includes a host device (host) 2 and a memory system 3. The host 2 and the memory system 3 can be connected via a bus 7.

[0010] The host 2 is an information processing device. The host 2 is, for example, a personal computer, a server computer, or a mobile terminal. The host 2 accesses the memory system 3. Specifically, the host 2 sends a write command to the memory system 3, which is a command requesting that data be written to the nonvolatile memory. The host 2 sends a read command to the memory system 3, which is a command requesting that data be read from the nonvolatile memory.

[0011] The memory system 3 is, for example, a semiconductor storage device that includes a nonvolatile memory and is configured to write data to and read data from the nonvolatile memory. The semiconductor storage device is, for example, an SSD. The nonvolatile memory included in the memory system 3 is, for example, a NAND flash memory 5.

[0012] The memory system 3 can be used as storage for the host 2. The memory system 3 may be built into the host 2, or may be connected to the host 2 via a cable or a network.

[0013] Communication between the memory system 3 and the host 2 is carried out via a bus 7. The bus 7 is primarily used for transmitting data and input / output commands (I / O commands) from the host 2 to the memory system 3, and for transmitting data and responses from the memory system 3 to the host 2. An I / O command is a command for writing or reading data from a nonvolatile memory. Examples of I / O commands include a write command, which is a command for requesting that data be written to the nonvolatile memory, and a read command, which is a command for requesting that data be read from the nonvolatile memory.

[0014] The interface for connecting the memory system 3 and the host 2 is SCSI, Serial Attached SCSI (SAS), ATA (AT Attachment), Serial ATA (SATA), PCI Express TM (PCIe TM ), Ethernet TM , Fiber channel, NVM Express TM (NVMe TM ) and other standards.

[0015] Next, we will explain the internal configuration of the memory system 3. The memory system 3 includes a memory controller (controller) 4 and a NAND flash memory 5. The memory system 3 may further include a dynamic random access memory (DRAM) 6.

[0016] The controller 4 is a memory controller that controls the NAND flash memory 5 and the DRAM 6. The controller 4 is, for example, a control circuit such as a system-on-a-chip (SoC). The controller 4 is electrically connected to each of the NAND flash memory 5 and the DRAM 6. The controller 4 processes various commands received from the host 2. The controller 4 writes data to the NAND flash memory 5 by processing a write command. The controller 4 reads data from the NAND flash memory 5 by processing a read command. The controller 4 may have a built-in static random access memory (SRAM) or a DRAM. In this case, the DRAM 6 external to the controller 4 may not be provided.

[0017] The controller 4 functions as, for example, a flash translation layer (FTL) configured to perform data management and block management of the NAND flash memory 5. The data management performed by the FTL includes management of mapping information indicating the correspondence between each logical address and each physical address of the NAND flash memory 5. The block management includes management of bad blocks, wear leveling, and garbage collection.

[0018] The logical address is used by the host 2 to address a storage area in the memory system 3. The logical address is, for example, a logical block address (LBA).

[0019] The management of the mapping between each logical address and each physical address is performed using, for example, a logical-physical address conversion table. The controller 4 uses the logical-physical address conversion table to manage the mapping between each logical address and each physical address in specific management size units. A physical address corresponding to a certain logical address indicates a physical storage location in the NAND flash memory 5 where user data of this logical address is written. The logical-physical address conversion table may be loaded from the NAND flash memory 5 to the DRAM 6 when the memory system 3 is started up.

[0020] Data can be written to one page only once per P / E cycle. Therefore, the controller 4 writes user data to be updated corresponding to a certain logical address to a different physical storage location, rather than to the physical storage location where the previous user data corresponding to this logical address is stored. The controller 4 then invalidates the previous user data by updating the logical-physical address translation table so as to associate this logical address with this different physical storage location.

[0021] The controller 4 is also communicatively connected to the DRAM 6. The controller 4 writes data to the DRAM 6 and reads data from the DRAM 6.

[0022] The NAND flash memory 5 is a non-volatile memory. The NAND flash memory 5 is, for example, a flash memory with a three-dimensional structure. The NAND flash memory 5 includes a plurality of memory cells arranged in a matrix. The NAND flash memory 5 includes a plurality of blocks BLK0 to BLKm-1. Each of the blocks BLK0 to BLKm-1 is a unit of a data erase operation for erasing data. The data erase operation is also called an erase operation or simply an erase operation. Each of the blocks BLK0 to BLKm-1 is also called a physical block, a flash block, or a memory block.

[0023] Each of the blocks BLK0 to BLKm-1 includes multiple pages (here, pages P0 to Pn-1). Each page includes multiple memory cells connected to the same word line. Each of the pages P0 to Pn-1 is a unit of data write and read operations.

[0024] The DRAM 6 is a volatile memory. A part of the storage area of ​​the DRAM 6 is used, for example, to temporarily store information used to manage the memory system 3. Another part of the storage area of ​​the DRAM 6 can be used to temporarily store write data received from the host 2 or read data read from the NAND flash memory 5.

[0025] Next, we will explain an example of the internal configuration of the controller 4. The controller 4 includes a host interface (host I / F) 41, a CPU 42, a NAND interface (NAND I / F) 43, a DRAM interface (DRAM I / F) 44, an encoding device 45, and a decoding device 46. These components are connected via an internal bus 40.

[0026] The host interface 41 is an interface circuit that executes communication with the host 2. For example, the host interface 41 receives I / O commands and data from the host 2. The host interface 41 also transmits data and responses to the host 2.

[0027] The CPU 42 is a processor. The CPU 42 controls the host interface 41, the NAND interface 43, the DRAM interface 44, the encoding device 45, and the decoding device 46. The CPU 42 loads a control program (firmware) stored in the NAND flash memory 5 or a ROM (not shown) into the DRAM 6 or a RAM (not shown) in the controller 4. The CPU 42 performs various processes by executing this control program (firmware).

[0028] The NAND interface 43 is an interface circuit that executes access to the NAND flash memory 5. When the NAND flash memory 5 is composed of multiple NAND flash dies, the NAND interface 43 may be connected to each of these multiple NAND flash memory dies via multiple channels. By driving multiple NAND flash dies in parallel, it is possible to broaden the bandwidth of access to the entire NAND flash memory 5.

[0029] The DRAM interface 44 is an interface circuit that executes access to the DRAM 6. The DRAM interface 44 stores data in the DRAM 6 and reads data stored in the DRAM 6.

[0030] The encoding device 45 compresses data to be written to the NAND flash memory 5. The encoding device 45 compresses, for example, write data associated with a write command received from the host 2. The encoding device 45 compresses the write data using a lossless compression algorithm. Hereinafter, data obtained by compressing the write data will be referred to as a compressed stream. An example of a lossless compression algorithm is a combination of dictionary coding and entropy coding (referred to as Deflate). Hereinafter, it is assumed that Deflate is used as the lossless compression algorithm. Dictionary coding converts previously occurring data among the write data compressed into the compressed stream into code words that refer to the previously occurring data. Entropy coding converts the code length based on the frequency of occurrence of each code word in the write data.

[0031] The compressed stream has a smaller size than the write data before compression. The larger the size of the write data compressed at one time by the encoding device 45, the smaller the ratio of the size of the compressed data to the size of the write data. In other words, the larger the size of the write data compressed at one time, the more efficiently the encoding device 45 can compress the write data. This is because the larger the size of the write data compressed at one time, the greater the amount of information that can be referenced in the compression process of the write data.

[0032] The decoding device 46 is a device that generates uncompressed data by decompressing a compressed stream. The decoding device 46 decompresses the compressed stream read from the NAND flash memory 5, for example, based on a read command received from the host 2. For example, this compressed stream is generated using Deflate. When decoding data on this compressed stream, the decoding device 46 performs a combination of entropy decoding and dictionary decoding. In this way, the decoding device 46 generates uncompressed data from the compressed stream.

[0033] Next, the encoding process and the decoding process will be described. Fig. 2 is a diagram for explaining the encoding process executed by the encoding device 45 and the decoding process executed by the decoding device 46.

[0034] Here, it is assumed that the encoding process executed by the encoding device 45 is Deflate. In this case, the encoding process includes dictionary-based encoding and entropy encoding. The encoding device 45 includes a dictionary-based encoding circuit 451 and an entropy encoding circuit 452.

[0035] The dictionary-based coding circuit 451 performs dictionary-based coding on the input data (uncompressed data) input to the encoding device 45.

[0036] Dictionary coding is a coding method that converts data to be compressed into a match distance and a match length using a dictionary buffer that stores previously input data. Dictionary coding is also called dictionary compression. Examples of dictionary coding that can be used include LZ77 and LZSS.

[0037] If data matching the data to be compressed is present in the dictionary buffer, the dictionary coding circuit 451 searches the dictionary buffer to obtain previously occurring data that at least partially matches the data to be compressed, and obtains a match distance and a match length. The dictionary coding circuit 451 then replaces the data to be compressed with the match distance and the match length, and outputs the results of dictionary coding. The match distance is the distance from the location in the dictionary buffer where the data to be compressed is stored to the location where the previously occurring data is stored. The match length is the length of the portion that matches between the previously occurring data and the data to be compressed. The dictionary coding circuit 451 can compress the data by converting the data to be compressed into a match distance and a match length. The data portion generated by this compression is referred to as a match symbol. In this embodiment, the match length and match distance included in the match symbol may each be treated as a single symbol. These symbols may be referred to as a match length symbol and a match distance symbol, respectively.

[0038] On the other hand, if there is no data matching the data to be compressed in the dictionary buffer, the dictionary-based coding circuit 451 outputs the data to be compressed as is as a result of dictionary-based coding. This data portion is called a literal symbol, or a literal.

[0039] The entropy coding circuit 452 further performs entropy coding on the input data that has been coded by dictionary coding.

[0040] In entropy coding, the code length of input data is converted according to the frequency of occurrence of the data. That is, the entropy coding circuit 452 assigns codes of different code lengths to data portions in the input data based on the differences in the frequency of occurrence of the data portions. The entropy coding circuit 452 assigns short code lengths to data portions with high frequency of occurrence and long code lengths to data portions with low frequency of occurrence, thereby reducing the overall amount of code required.

[0041] The entropy coding circuit 452 uses, for example, Huffman coding as the entropy coding. When Huffman coding is used, the entropy coding circuit 452 may perform static Huffman coding, which performs coding using a pre-constructed code tree, or may perform dynamic Huffman coding, which changes the code tree depending on the data to be Huffman coded. Other entropy coding methods, such as arithmetic coding, may also be used.

[0042] In the encoding process of the encoding device 45, first, the dictionary coding circuit 451 performs dictionary coding on the input uncompressed data. Then, the entropy coding circuit 452 performs entropy coding on the result of the dictionary coding. In this way, the encoding device 45 generates a compressed stream. The generated compressed data is written to, for example, the NAND flash memory 5.

[0043] The decoding device 46 performs extraction processing, entropy decoding processing, and dictionary decoding processing on the data read from the NAND flash memory 5. The decoding device 46 includes an extraction circuit 461 and a decoding circuit 462.

[0044] The extraction circuit 461 is a circuit that extracts one or more symbols from a compressed stream. The extraction circuit 461 selects a bit string of an extraction range from the compressed stream read from the NAND flash memory 5. The extraction circuit 461 acquires boundary position information for each of the one or more symbols included in the selected bit string. The boundary position information is information that indicates the start bit position of each symbol in the selected bit string. The extraction circuit 461 outputs the bit string of the extraction range, whose start bit position has been identified based on the acquired boundary position information, to the decoding circuit 462.

[0045] The decoding circuit 462 performs entropy decoding and dictionary decoding on each of the one or more symbols extracted by the extraction circuit 461. The decoding circuit 462 includes an entropy decoding circuit 4621 and a dictionary decoding circuit 4622.

[0046] The entropy decoding circuit 4621 and the dictionary decoding circuit 4622 are realized by at least one of, for example, a register, a memory, an adder, a comparator, a selector, and other computing units. The register is realized by, for example, a sequential circuit such as a flip-flop. The memory is realized by, for example, a storage element such as an SRAM or a DRAM. The adder, comparator, selector, and other computing units are realized by, for example, a combinational logic circuit.

[0047] The entropy decoding circuit 4621 performs entropy decoding on the input data (the extracted bit string). In the entropy decoding, the data portion included in the compressed stream is expanded based on the information used in the entropy encoding. The entropy decoding circuit 4621 sends the results of the entropy decoding to the dictionary-based decoding circuit 4622.

[0048] The dictionary decoding circuit 4622 performs dictionary decoding on the input data that has undergone entropy decoding. The dictionary decoding circuit 4622 converts the match length symbols and match distance symbols of the input data into uncompressed data. As a result, the dictionary decoding circuit 4622 outputs the uncompressed data. In dictionary decoding, match symbols are replaced with match lengths and match distances based on previously occurring data portions. Therefore, when decoding a match symbol, a conventional dictionary decoding circuit cannot determine the start position of the match symbol unless at least the immediately preceding match symbol is decoded. Therefore, sequential decoding is required for each symbol. In contrast, the dictionary decoding circuit 4622 of this embodiment can determine the start position of each symbol based on the boundary position information of each symbol in the input data output to the extraction circuit 461. As a result, the dictionary decoding circuit 4622 does not need to sequentially decode each symbol.

[0049] In the decoding process of the decoding device 46, the extraction circuit 461 first outputs a bit string including one or more symbols from the compressed stream. Then, the entropy decoding circuit 4621 performs entropy decoding on each of the one or more symbols included in the output bit string. The dictionary decoding circuit 4622 performs dictionary decoding on the result of the entropy decoding. As a result, the decoding device 46 generates uncompressed data.

[0050] Next, a specific example of dictionary-based coding will be described. Fig. 3 is a diagram showing an example of dictionary-based coding. In the example shown in Fig. 3, a previously input data string "...cacabc" is stored in the dictionary buffer. The currently input data string is "caba".

[0051] In this case, the first two characters of the current input data string "caba" match those of the data string "ca" stored in the dictionary buffer six positions before the position where the current input data string "caba" is stored. Also, the first three characters of the current input data string "caba" match those of the data string "cab" stored in the dictionary buffer four positions before the position where the current input data string "caba" is stored.

[0052] In dictionary encoding, the current input data string "caba" is converted into a match distance and match length that refer relatively to a longer matching data string in the dictionary buffer.

[0053] Therefore, the current input data string "caba" is converted into a match distance of "4" and a match length of "3" that relatively reference the data string "cab" in the dictionary buffer. The match distance of "4" indicates the relative distance from the location in the dictionary buffer where the current input data string "caba" is stored to the location where the data string "cab" is stored. The match length of "3" indicates the length of the portion that matches between the current input data string "caba" and the data string "cab". Therefore, when dictionary-based encoding is performed on the current input data string "caba", the dictionary-based encoding circuit 451 outputs, for example, (4, 3) indicating the pair of match distance and match length.

[0054] Next, a compressed stream that has been subjected to dictionary coding will be described below. Fig. 4 shows an example of the compressed stream.

[0055] The compressed stream 71 includes a plurality of symbols, including a literal symbol 711 and a match symbol 712.

[0056] The literal symbol 711 is a symbol that does not match any data string stored in the dictionary buffer. The literal symbol may also be referred to as a dictionary mismatch symbol. The literal symbol 711 is made up of a prefix. The prefix is ​​a variable-length code.

[0057] The match symbol 712 is a symbol that matches a data string stored in the dictionary buffer. The match symbol may also be referred to as a dictionary match symbol. An example of the configuration of the match symbol 712 will be described with reference to FIG. 5. FIG. 5 is a diagram showing an example of the configuration of the match symbol 712. The match symbol 712 includes a match length symbol and a match distance symbol.

[0058] The match length symbol is a symbol corresponding to the match length. The match length symbol is composed of a prefix and an extra bit.

[0059] The match distance symbol is a symbol corresponding to the match distance. The match distance symbol is composed of a prefix and an extra bit.

[0060] The method for calculating the code length differs depending on the type of the corresponding symbol. More specifically, the code length of a literal symbol is the length of the prefix. The code lengths of both the match length symbol and the match distance symbol are calculated by adding the length of the prefix and the length of the extra bit.

[0061] Here, the length of the prefix will be explained.

[0062] Fig. 6 shows an example of a Huffman tree 81 representing prefixes assigned to literal symbols and prefixes assigned to match length symbols. The prefixes assigned to literal symbols and prefixes assigned to match length symbols are expressed in a common Huffman tree 81. In Fig. 6, the prefixes of the literal symbols and match length symbols are expressed in a Huffman tree 81, but the prefixes of match distance symbols are also expressed in a Huffman tree. Here, a case where the prefix of the match length symbol is used will be described with reference to Fig. 6.

[0063] Each leaf node 82 of the Huffman tree 81 corresponds to either a literal symbol or a match length symbol that appears in the compressed stream 71. The depth of each leaf node 82 starting from the root node 810 of the Huffman tree 81 (i.e., the number of nodes traversed from the root node 810 to the leaf node 82) corresponds to the length of the prefix assigned to the corresponding symbol.

[0064] To generate the Huffman tree 81, first, a new node is generated by bundling the two leaf nodes 82 with the fewest number of leaf nodes 82. The number of nodes corresponding to the generated node is the sum of the numbers of the two leaf nodes 82 that are bundled together.

[0065] Next, a new node is generated by bundling the two leaf nodes 82 or nodes with the fewest numbers among the other leaf nodes 82 and the generated node. The number corresponding to the generated node is the sum of the numbers corresponding to the bundled leaf nodes 82 or nodes.

[0066] This process is repeated to generate a root node 810, which is the starting point, thereby completing the Huffman tree 81. At each node of the Huffman tree 81, a value of 0 or 1 is assigned to each branch. In the root node 810 of FIG. 6, a value of 0 is assigned to the left branch and a value of 1 is assigned to the right branch. This provides a bit string that uniquely identifies each leaf node 82.

[0067] For example, leaf node 821 corresponds to a literal symbol. A prefix "00" is assigned to the literal symbol corresponding to leaf node 821. The length of this prefix is ​​2.

[0068] For example, the leaf node 822 corresponds to the match length symbol. The prefix "1011" is assigned to the match length symbol corresponding to the leaf node 822. The length of this prefix is ​​four.

[0069] As such, prefixes are variable-length codes obtained by entropy coding. Therefore, the larger the number of prefixes, i.e., the more frequently a symbol appears, the shorter the corresponding prefix length. Conversely, the smaller the number of prefixes, i.e., the less frequently a symbol appears, the longer the corresponding prefix length.

[0070] The ExtraBit is a code that can be included in a match symbol. Specifically, the ExtraBit is a code that can be added to a prefix included in a symbol corresponding to the match length and a symbol corresponding to the match distance. The length of the ExtraBit is determined based on the type of the corresponding match symbol.

[0071] Next, a description will be given of an example of the configuration of the extraction circuit 461. Fig. 7 is a block diagram showing an example of the configuration of the extraction circuit 461 included in the decoding device 46 according to the embodiment.

[0072] The extraction circuit 461 includes an input bit string register 4611, a code length calculation circuit 4612, a plurality of first registers 4613-0 . . . 4613-N, a plurality of second registers 4614-0 .

[0073] The input bit string register 4611, the code length calculation circuit 4612, the plurality of first registers 4613-0...4613-N, the plurality of second registers 4614-0...4614-N, the plurality of boundary update circuits 4615-1...4615-N, and the output bit string selection circuit 4616 are realized by at least one of registers, adders, comparators, selectors, and other operational units, for example. The registers are realized by sequential circuits such as flip-flops, for example. The adders, comparators, selectors, and other operational units are realized by combinational logic circuits, for example.

[0074] The input bit string register 4611 is a register that includes multiple storage locations. Each of the multiple storage locations stores one bit of data. A bit string within a cutout range from the compressed stream to be decoded that is input to the cutout circuit 461 is stored in the multiple storage locations of the input bit string register 4611. The cutout range is the size of the bit string cut out by the cutout circuit 461. The number of storage locations included in the input bit string register 4611 corresponds to the number of bits included in the cutout range.

[0075] The code length calculation circuit 4612 is a circuit that calculates the code lengths of symbols included in the extraction range. The code length calculation circuit 4612 calculates the code length of each symbol by assuming that each bit of the bit string stored in the input bit string register 4611 is the starting position. In addition, the code length calculation circuit 4612 calculates, for each symbol, a first code length when the symbol is considered to have been coded using a first coding method, and a second code length when the symbol is considered to have been coded using a second coding method.

[0076] The code length calculation circuit 4612 includes a first calculation circuit 46121 and a second calculation circuit 46122 .

[0077] The first calculation circuit 46121 calculates the code length assuming that the symbol starting at each bit is encoded using the first encoding method. The first encoding method is for encoding literal symbols or match length symbols. The first calculation circuit 46121 then generates boundary position information indicating the starting position of the symbol following each symbol based on the calculated code length. When calculating the boundary position information, the first calculation circuit 46121 determines whether the symbol is a literal symbol or a match length symbol. If the symbol is a literal symbol, the first calculation circuit 46121 stores, in the first register 4613-0, context information indicating that the symbol following the symbol is encoded using the first encoding method, together with the calculated boundary position information. If the symbol is a match length symbol, the first calculation circuit 46121 stores, in the first register 4613-0, context information indicating that the symbol following the symbol is encoded using the second encoding method, together with the calculated boundary position information. This is because the symbol following a literal is a literal symbol or a match length symbol, and the symbol following a match length symbol is a match distance symbol.

[0078] The second calculation circuit 46122 calculates the code length assuming that the symbol starting from each bit is encoded using the second encoding method. The second encoding method is encoding for match distance symbols. The second calculation circuit 46122 then generates boundary position information indicating the starting position of the symbol following each symbol based on the calculated code length. The second calculation circuit 46122 stores context information indicating that the symbol following that symbol is a symbol encoded using the first encoding method, together with the calculated boundary position information, in the second register 4614-0. This is because the symbol following the match distance symbol is predicted to be a literal symbol or a match length symbol, both of which are symbols encoded using the first encoding method.

[0079] The first registers 4613-0...4613-N are registers including multiple storage locations for storing boundary position information and context information when each bit in the input bit string is considered to be a start position and encoded using the first encoding method. Each of the multiple storage locations included in the first registers 4613-0...4613-N corresponds to each of the multiple bits included in the extraction range. Each of the multiple storage locations in the first register 4613-0 stores boundary position information indicating the start position of a symbol following a symbol that considers each bit in the input bit string as its start position, calculated by the first calculation circuit 46121, and context information corresponding to the subsequent symbol. Each of the multiple storage locations in the first register 4613-1 stores boundary position information indicating the start position of a symbol two symbols ahead of a symbol that considers each bit in the input bit string as its start position, and context information corresponding to that symbol, obtained by the first update circuit 46151-1 (described later). Each of the plurality of storage locations of the first register 4613-2 stores boundary position information indicating the start position of a symbol four symbols ahead of a symbol that regards each bit in the input bit string as a start position, which is acquired by a first update circuit 46151-2 described below, and context information corresponding to that symbol. Each of the plurality of storage locations of the first register 4613-N stores boundary position information indicating the start position of a symbol four symbols ahead of a symbol that regards each bit in the input bit string as a start position, which is acquired by a first update circuit 46151-2 described below. N Boundary position information indicating the start position of the symbol ahead and context information corresponding to that symbol are stored. Here, N corresponds to the number of times the boundary position information is repeatedly updated. N is, for example, an integer equal to or greater than 2.

[0080] The second registers 4614-0...4614-N are registers containing multiple memory locations for storing boundary position information and context information when it is assumed that the symbol, whose starting position is assumed to be a bit in the input bit sequence, uses the second encoding method. Each of the multiple memory locations included in the second registers 4614-0...4614-N corresponds to each of the multiple bits included in the extraction range. Each of the multiple memory locations in the second register 4614-0 stores boundary position information calculated by the second calculation circuit 46122, indicating the starting position of the symbol following the symbol whose starting position is assumed to be a bit in the input bit sequence, and context information corresponding to the following symbol. Each of the multiple memory locations in the second register 4614-1 stores boundary position information calculated by the second update circuit 46152-1 (described later), indicating the starting position of the symbol two symbols ahead of the symbol whose starting position is assumed to be a bit in the input bit sequence, and context information corresponding to that symbol. Each of the plurality of storage locations of the second register 4614-2 stores boundary position information indicating the start position of a symbol four symbols ahead for a symbol assuming each bit in the input bit string as its start position, calculated by a second update circuit 46152-2 (to be described later), and context information corresponding to that symbol. Each of the plurality of storage locations of the second register 4614-N stores boundary position information indicating the start position of a symbol four symbols ahead for a symbol assuming each bit in the input bit string as its start position, calculated by a second update circuit 46152-N (to be described later). N Boundary position information indicating the start position of the symbol ahead and context information corresponding to that symbol are stored.

[0081] The boundary update circuits 4615-1...4615-N are circuits that acquire the boundary position information and context information of the subsequent symbol based on the boundary position information and context information corresponding to each bit in the input bit string. The boundary update circuits 4615-1...4615-N each include a first update circuit 46151-1...46151-N and a second update circuit 46152-1...46152-N.

[0082] The first update circuits 46151-1...46151-N acquire the boundary position information and context information stored in the memory locations of the first registers 4613-0...4613-(N-1) or the second registers 4614-0...4614-(N-1) identified by the boundary position information and context information stored in the first registers 4613-0...4613-(N-1). The first update circuits 46151-1...46151-N then store the acquired boundary position information and context information in the first registers 4613-1...4613-N.

[0083] Specifically, the first update circuit 46151-1 identifies the boundary position information and context information to be stored in the first register 4613-1 based on the boundary position information and context information stored in the first register 4613-0. If the original context information indicates the first encoding method, the first update circuit 46151-1 acquires new boundary position information and context information from a storage location in the first register 4613-0 that corresponds to the original boundary position information. The first update circuit 46151-1 stores the acquired new boundary position information and context information in the first register 4613-1. On the other hand, if the original context information indicates the second encoding method, the first update circuit 46151-1 acquires the boundary position information and context information from a storage location in the second register 4614-1 that corresponds to the original boundary position information. The first update circuit 46151-1 stores the acquired boundary position information and context information in the first register 4613-2.

[0084] The second update circuits 46152-1...46152-N acquire the boundary position information and context information stored in the memory locations of the first registers 4613-0...4613-(N-1) or the second registers 4614-0...4614-(N-1) identified by the boundary position information and context information stored in the second registers 4614-0...4614-(N-1). The second update circuits 46152-1...46152-N then store the acquired boundary position information and context information in the second registers 4614-1...4614-N.

[0085] Specifically, the second update circuit 46152-1 identifies the boundary position information and context information to be stored in the second register 4614-1 based on the original boundary position information and context information stored in the second register 4614-0. If the original context information indicates the first encoding method, the second update circuit 46152-1 acquires new boundary position information and context information from a storage location in the first register 4613-0 that corresponds to the original boundary position information. The boundary update circuit 4615-1 stores the acquired boundary position information and context information in the second register 4614-1. If the original context information indicates the second encoding method, the second update circuit 46152-1 acquires the boundary position information and context information from a storage location in the second register 4614-1 that corresponds to the original boundary position information. The second update circuit 46152-1 stores the acquired boundary position information and context information in the second register 4614-2.

[0086] The output bit string selection circuit 4616 is a circuit 4616 that selects the bit string output by the extraction circuit 461. The output bit string selection circuit 4616 selects the two bit strings stored in the first register 4613-N or the second register 4614-N. N An output bitstream is selected based on the boundary position information and context information of the symbol destination, and the output bitstream may include at least one or more symbols.

[0087] Before describing the cutout processing by the cutout circuit 461 of the decoding device 46 according to the embodiment, the cutout processing in a comparative example will be described.

[0088] First, the extraction process for extracting one or more symbols from a compressed stream in a comparative example will be described. Fig. 8 is a diagram showing the extraction process for extracting a plurality of symbols from a compressed stream in a comparative example.

[0089] In the comparative example, 32 bits from bits #0 to #31 constitute the first partial bit string. Each bit of the first partial bit string is stored in the input bit string register. For the sake of explanation, FIG. 8 also shows some bits from #32 to #34. Here, bits #32 to #34 are referred to as the second partial bit string.

[0090] In Figure 8, in the input bit string, 0 is stored in bit #0, 1 in bit #1, 1 in bit #2, 1 in bit #3, 1 in bit #4, 0 in bit #5, 1 in bit #6, 1 in bit #7, 1 in bit #8, 0 in bit #9, 0 in bit #29, 1 in bit #30, and 1 in bit #31.

[0091] The code length calculation circuit calculates the code length by regarding each bit of the input bit string register as the start position. The code length calculation circuit calculates the code length by regarding each bit as the beginning of a symbol.

[0092] The code length calculation circuit calculates the boundary position one symbol ahead based on the calculated code length, and stores the calculated boundary position in a register.

[0093] As a result of the calculation, for example, the boundary position of one symbol ahead as viewed from bit #0 is 2, the boundary position of one symbol ahead as viewed from bit #1 is 5, the boundary position of one symbol ahead as viewed from bit #2 is 6, the boundary position of one symbol ahead as viewed from bit #3 is 6, the boundary position of one symbol ahead as viewed from bit #4 is 6, the boundary position of one symbol ahead as viewed from bit #5 is 7, the boundary position of one symbol ahead as viewed from bit #6 is 9, the boundary position of one symbol ahead as viewed from bit #7 is 9, the boundary position of one symbol ahead as viewed from bit #8 is 10, and the boundary position of one symbol ahead as viewed from bit #9 is 12. Furthermore, the boundary position of one symbol ahead as viewed from bit #29 is 31, the boundary position of one symbol ahead as viewed from bit #30 is 34, and the boundary position of one symbol ahead as viewed from bit #31 is 35.

[0094] The boundary update circuit uses the boundary position one symbol ahead to obtain the boundary position two symbols ahead, and updates the boundary position information using boundary position information stored in a memory location specified based on the boundary position information one symbol ahead.

[0095] The boundary position one symbol ahead from bit #0 is 2, and the boundary position one symbol ahead from bit #2 is 6. Therefore, the boundary position two symbols ahead from bit #0 is 6. As a result, boundary position information indicating 6 is stored in the memory position corresponding to bit #0. Furthermore, the boundary position one symbol ahead from bit #1 is 5, and the boundary position one symbol ahead from bit #5 is 7. Therefore, the boundary position two symbols ahead from bit #1 is 7. As a result, boundary position information indicating 7 is stored in the memory position corresponding to bit #1.

[0096] Furthermore, the boundary position one symbol ahead from bit #6 is 9, and the boundary position one symbol ahead from bit #9 is 12. Therefore, the boundary position two symbols ahead from bit #6 is 12. As a result, boundary position information indicating 12 is stored in the memory position corresponding to bit #6.

[0097] By performing this boundary update for each bit, boundary information two symbols ahead from each bit is stored in a register. However, if the one symbol ahead exceeds the range of the first partial bit string, no further updating is performed. For example, the boundary position one symbol ahead from bit #30 is 34, but bit #34 exceeds the first partial bit string and points to the second partial bit, so 34, the same value as the boundary information one symbol ahead of bit #30, is stored in the corresponding memory location as boundary information two symbols ahead of bit #30.

[0098] Next, the boundary update circuit uses the boundary position two symbols ahead to obtain the boundary position four symbols ahead, and updates the boundary position information using the boundary position information stored in the memory location identified based on the boundary position information two symbols ahead.

[0099] The boundary position two symbols ahead from bit #0 is 6, and the boundary position two symbols ahead from bit 6 is 12. Therefore, the boundary position four symbols ahead from bit #0 is 12. As a result, boundary position information indicating 12 is stored in the memory position corresponding to bit #0.

[0100] By performing such boundary updates for each bit, boundary information four symbols ahead from each bit is stored in a register.

[0101] When this boundary update is repeated N times, 2 N The boundary information of the symbol destination is stored in a register.

[0102] Next, a detailed configuration example of the extraction circuit including the code length calculation circuit and the boundary update circuit in the comparative example will be described. Fig. 9 is a diagram for explaining a detailed configuration example of the extraction circuit in the comparative example.

[0103] For simplicity, Fig. 9 shows a case where the extraction width is 4 bits. The code length calculation circuit #0 shown in Fig. 9 regards the first bit #0 of the input bit string as the beginning of the symbol and calculates the code length. The code length calculation circuit #0 includes a literal / match length code length calculation circuit, a shift circuit, a match distance code length calculation circuit, and an adder circuit.

[0104] The literal / match length code length calculation circuit calculates the code length of the literal symbol when the symbol type is a literal symbol. Also, when the symbol type is a match symbol, the literal / match length code length calculation circuit calculates only the code length of the part corresponding to the match length symbol.

[0105] If the symbol type is a match symbol, the shift circuit shifts the input bit string by the code length of the portion corresponding to the calculated match length symbol.

[0106] The Dist code length calculation circuit calculates the code length of the portion of the match symbols that corresponds to the match distance symbols.

[0107] Then, the adder circuit calculates the code length of the match symbol by adding together the code length of the match distance symbol calculated by the Dist code length calculation circuit and the code length of the match length symbol.

[0108] In this way, the code length calculation circuit #0 calculates the code length of the literal symbol or match symbol starting from bit #0. The code length calculation circuit also includes code length calculation circuits starting from other bits. That is, the code length calculation circuit includes a code length calculation circuit #0 corresponding to bit #0, a code length calculation circuit #1 corresponding to bit #1, a code length calculation circuit #2 corresponding to bit #2, and a code length calculation circuit #3 corresponding to bit #3.

[0109] Boundary update circuit #0 calculates boundary position information of the succeeding symbol from bit #0. Boundary update circuit #0 includes a multiplexer. The multiplexer of boundary update circuit #0 references boundary position information one symbol ahead and acquires boundary position information two symbols ahead. Boundary update circuit #0 outputs the acquired boundary position information two symbols ahead.

[0110] In this way, boundary update circuit #0 updates the boundary position information of the symbol following bit #0. The boundary update circuit also includes other boundary update circuits that update the boundary position information of the symbol following other bits. That is, the boundary update circuit further includes boundary update circuit #1 that updates the boundary position information of the symbol following bit #1, boundary update circuit #2 that updates the boundary position information of the symbol following bit #2, and boundary update circuit #3 that updates the boundary position information of the symbol following bit #3.

[0111] The output bit string output in the comparative example will be described. FIG. 10 shows the output bit string generated by the extraction process in the comparative example. NFIG. 10 is a diagram showing symbol destination boundary position information and an output bit string.

[0112] In Figure 10, the boundary update is performed for the Nth time. N The boundary position information of the symbol destination is shown.

[0113] Here, if the last bit of the output bit string output in the previous cycle is bit #0, the first bit of the bit string output this time will be bit #1. N The boundary position information of the symbol destination is 34. Therefore, the first bit of the bit string output in the next cycle is bit #34.

[0114] As a result, the bit string that is output this time is 33 bits from bit #1 to bit #33.

[0115] In the comparative example, the extraction circuit requires a shift circuit and an adder circuit, particularly in the code length calculation circuit, resulting in a large circuit size. Furthermore, the code length calculation circuit includes multiple circuits corresponding to each of the multiple bits included in the extraction range. Therefore, the impact of the increased circuit size is significant for the number of bits included in the extraction range. This section describes an embodiment in which the circuit size required for extracting a compressed stream is reduced.

[0116] FIG. 11 is a diagram for explaining a detailed configuration example of the extraction circuit 461 included in the decoding device 46 according to the embodiment.

[0117] Fig. 11 shows a case where the cutout width is 4 bits, as in Fig. 9. As in Fig. 9, this will be described focusing on the component corresponding to bit #0, but other components corresponding to other bits may have the same configuration as the component corresponding to bit #0. The code length calculation circuit #0 shown in Fig. 11 is a circuit that performs code length calculation by regarding the leading bit #0 of the input bit string as the beginning of the symbol.

[0118] The code length calculation circuit #0 includes a first calculation circuit 46121 and a second calculation circuit 46122.

[0119] The first calculation circuit 46121 calculates the code length assuming that the symbol starting from bit #0 uses the first encoding method. In other words, the first calculation circuit 46121 calculates the code length assuming that the symbol starting from bit #0 is a literal symbol or a match length symbol. The first calculation circuit 46121 includes a context determination circuit 461211 and a literal / match length code length calculation circuit 461212.

[0120] The context determination circuit 461211 is a circuit that determines context information for the symbol one symbol ahead. When the symbol being calculated is a literal symbol, the context determination circuit 461211 determines that the first encoding scheme is used for the symbol one symbol ahead. Furthermore, when the symbol being calculated is a match length symbol, the context determination circuit 461211 determines that the second encoding scheme is used for the symbol one symbol ahead. For example, when the first encoding scheme is used, the context determination circuit 461211 sets the context information to 0. Furthermore, when the second encoding scheme is used, the context determination circuit 461211 sets the context information to 1. This is based on the fact that the symbol following a literal symbol is a literal symbol or a match length symbol, and the symbol following a match length symbol is a match distance symbol.

[0121] The literal / match length code length calculation circuit 461212 is a circuit that calculates the code length assuming that the symbol starts with bit #0. At this time, the literal / match length code length calculation circuit 461212 calculates the code length assuming that the target symbol uses the first encoding method. The literal / match length code length calculation circuit 461212 calculates the code length assuming that the symbol starting with bit #0 is a literal symbol or a match length symbol.

[0122] The first calculation circuit 46121 generates one-symbol-ahead boundary position information based on the calculated code length. The first calculation circuit 46121 generates one-symbol-ahead boundary position information using the start position of this symbol and the code length of this symbol. The first calculation circuit 46121 stores the generated one-symbol-ahead boundary position information and context information in a memory location corresponding to bit #0 of the first register 4613-0.

[0123] The second calculation circuit 46122 calculates the code length assuming that the symbol starting from bit #0 uses the second coding method. In other words, the second calculation circuit 46122 calculates the code length assuming that the symbol starting from bit #0 is a match distance symbol. The second calculation circuit 46122 includes a context determination circuit 461221 and a match distance code length calculation circuit 461222.

[0124] The context determination circuit 461221 is a circuit that determines the context information of the symbol one symbol later. The context determination circuit 461221 determines that the symbol one symbol later uses the first encoding method. For example, the context determination circuit 461221 sets the context information to 0. This is because the symbol following the match distance symbol is either a literal symbol or a match length symbol. Both the literal symbol and the match length symbol are data encoded using the first encoding method.

[0125] The match distance code length calculation circuit 461222 is a circuit that calculates the code length. The match distance code length calculation circuit 461222 calculates the code length assuming that the symbol starting from bit #0 is a match distance symbol.

[0126] The second calculation circuit 46122 generates one-symbol-ahead boundary position information based on the calculated code length. The second calculation circuit 46122 generates one-symbol-ahead boundary position information using the start position of this symbol and the code length of this symbol. The second calculation circuit 46122 stores the generated one-symbol-ahead boundary position information and context information in a memory location corresponding to bit #0 of the second register 4614-0.

[0127] Similarly, for the other bits of the input bit string, context information and one-symbol-ahead boundary position information are generated, and this information is stored in the storage locations of first register 4613-0 and second register 4614-0.

[0128] The boundary update circuit 4615-1 is a circuit that acquires boundary position information two symbols ahead based on boundary position information one symbol ahead as viewed from each bit. The boundary update circuit 4615-1 includes a first update circuit 46151-1 or a second update circuit 46152-1.

[0129] The first update circuit 46151-1 obtains two-symbol-ahead boundary position information and context information to be stored in the first register 4613-1 based on the one-symbol-ahead boundary position information stored in the first register 4613-0. The first update circuit 46151-1 includes a context selection circuit 461511-1 and a multiplexer (MUX) 461512-1.

[0130] The context selection circuit 461511-1 is a circuit that selects the first register 4613-0 or the second register 4614-0 based on context information. The context selection circuit 461511-1 acquires context information corresponding to bit #0 from the first register 4613-0. If the acquired context information is 0, the context selection circuit 461511-1 selects the first register 4613-0. On the other hand, if the acquired context information is 1, the context selection circuit 461511-1 selects the second register 4614-0.

[0131] The multiplexer 461512-1 is a circuit that selects the storage location of the first register 4613-0 or the second register 4614-0 based on the one-symbol-ahead boundary position information. The multiplexer 461512-1 obtains context information and boundary position information from the storage location corresponding to the one-symbol-ahead boundary position information, among the registers selected by the context selection circuit 461511-1.

[0132] The first update circuit 46151-1 selects one storage location in the register using the context selection circuit 461511-1 and multiplexer 461512-1, and acquires two-symbol-ahead boundary position information and context information. The first update circuit 46151-1 then stores the acquired two-symbol-ahead boundary position information and context information in a storage location corresponding to bit #0 of the first register 4613-1.

[0133] The second update circuit 46152-1 obtains two-symbol-ahead boundary position information and context information to be stored in the second register 4614-1 based on the one-symbol-ahead boundary position information stored in the second register 4614-0. The second update circuit 46152-1 includes a context selection circuit 461521-1 and a multiplexer (MUX) 461522-1.

[0134] The context selection circuit 461521-1 is a circuit that selects the first register 4613-0 or the second register 4614-0 based on context information. The context selection circuit 461521-1 acquires context information corresponding to bit #0 from the second register 4614-0. If the acquired context information is 0, the context selection circuit 461521-1 selects the first register 4613-0. On the other hand, if the acquired context information is 1, the context selection circuit 461521-1 selects the second register 4614-0.

[0135] The multiplexer 461522-1 is a circuit that selects the storage location of the first register 4613-0 or the second register 4614-0 based on the one-symbol-ahead boundary position information. The multiplexer 461522-1 obtains context information and boundary position information from the storage location corresponding to the one-symbol-ahead boundary position information, among the registers selected by the context selection circuit 461521-1.

[0136] The second update circuit 46152-1 selects one storage location in the register using the context selection circuit 461521-1 and multiplexer 461522-1 to obtain two-symbol-ahead boundary position information and context information. The second update circuit 46152-1 then stores the obtained two-symbol-ahead boundary position information and context information in a storage location corresponding to bit #0 of the second register 4614-1.

[0137] Similarly, the boundary update circuit 4615-2 acquires four-symbol-ahead boundary position information and context information based on the two-symbol-ahead boundary position information and context information stored in the first register 4613-1 and the second register 4614-2. The boundary update circuit 4615-2 stores the acquired four-symbol-ahead boundary position information and context information in the first register 4613-2 and the second register 4614-2.

[0138] Then, the output bit string selection circuit 4616 selects an output bit string based on the four-symbol-ahead boundary position information and context information stored in the first register 4613-2 and the second register 4614-2.

[0139] The output bit string output by the output bit string selection circuit 4616 will now be described. FIG. 12 shows the two bit strings generated by the extraction process executed in the decoding device 46 according to the embodiment. N 12 is a diagram illustrating symbol-heading boundary position information and an output bit string, where the extraction width D is 32.

[0140] In Figure 12, two types of 2D boundary lines are obtained by the Nth boundary update. N The boundary position information and context information of the symbol destination are shown. N is an integer equal to or greater than 2. 2 corresponds to context 0. N The context information and boundary position information of the symbol destination are stored in, for example, the first register 4613-N. Specifically, the context information and boundary position information of the symbol destination are stored in the first register 4613-N. N The boundary position information of the symbol destination is 33, and the context information is 1. This corresponds to context 0, and the symbol starting from bit #1 is 2. N The boundary position information of the symbol destination is 33, and the context information is 1. This corresponds to context 0, and the symbol starting from bit #2 is 2. N The boundary position information of the symbol destination is 33, and the context information is 1.

[0141] Context 1, 2 N The context information and boundary position information of the symbol destination are stored in, for example, the second register 4614-N. Specifically, the context information and boundary position information of the symbol destination are stored in the second register 4614-N. N The boundary position information of the symbol destination is 34, and the context information is 1. Corresponding to context 1, the symbol starting from bit #1 is 2 N The boundary position information of the symbol destination is 34, and the context information is 0. Corresponding to context 1, the symbol starting from bit #2 is 2 N The boundary position information of the symbol destination is 34, and the context information is 0.

[0142] Here, assume that the context information corresponding to the first bit of the output bit string output in the previous cycle indicates 1, and the last bit is bit #0. In this case, the first bit of the bit string output this time will be bit #1, which corresponds to context 1. In other words, the bit string output this time is extracted from the extraction range starting from the bit following the last bit of the bit string output in the previous cycle.

[0143] In this case, the first two symbols are taken from bit #1 of context 1. N The boundary position information of the symbol destination is 34. As a result, the bit string output this time is 33 bits from bit #1 to bit #33 of context 1.

[0144] Furthermore, the context information of bit #1 of context 1 is 0. Therefore, the first bit of the bit string output in the next cycle is bit #34 of context 0.

[0145] Next, the code length calculation process will be described with reference to Fig. 13, which is a flowchart showing the procedure of the code length calculation process in the extraction process executed by the decoding device 46 according to the embodiment.

[0146] First, data is input to the extraction circuit 461 of the decoding device 46 (step S11). The input data is stored in the input bit string register 4611, for example.

[0147] The first calculation circuit 46121 of the code length calculation circuit 4612 regards each bit in the input bit string as a starting position, and calculates the code length of the symbol assuming a literal symbol or a match length symbol (step S12). That is, the first calculation circuit 46121 regards each bit as a starting position and calculates the code length assuming that it has been coded using the first coding method.

[0148] The context determination circuit 461211 of the first calculation circuit 46121 determines the context of the symbol immediately preceding for each bit (step S13). That is, the context determination circuit 461211 determines the context information of the symbol subsequent to the symbol whose code length was calculated in S12. If the symbol whose code length was calculated in S12 is a literal symbol, the context determination circuit 461211 determines the context information to be 0, which indicates that the subsequent symbol is a literal symbol or a match length symbol. On the other hand, if the symbol whose code length was calculated in S12 is a match length symbol, the context determination circuit 461211 determines the context information to be 1, which indicates that the subsequent symbol is a match distance symbol.

[0149] The first calculation circuit 46121 stores the context information determined in S13 and the boundary position information determined based on the code length calculated in S12 in the first register 4613-0 (step S14).

[0150] The second calculation circuit 46122 of the code length calculation circuit 4612 regards each bit in the input bit string as a starting position, and calculates the code length of the symbol by assuming a match distance symbol (step S15). That is, the second calculation circuit 46122 regards each bit as a starting position and calculates the code length by assuming that the bit string has been coded by the second coding method.

[0151] The context determination circuit 461221 of the second calculation circuit 46122 determines the context of the symbol immediately following for each bit (step S16). That is, the context determination circuit 461221 determines the context information of the symbol following the symbol whose code length was calculated in S15. The context determination circuit 461221 determines the context information to be 0, which indicates that the following symbol is a literal symbol or a match length symbol.

[0152] The second calculation circuit 46122 stores the context information determined in S16 and the boundary position information determined based on the code length calculated in S15 in the second register 4614-0 (step S17).

[0153] As a result, extraction circuit 461 calculates one-symbol-ahead boundary position information and context information assuming that the input bit string is encoded by the first encoding method, and one-symbol-ahead boundary position information and context information assuming that the input bit string is encoded by the second encoding method, with each bit in the extraction range of the input bit string as the starting position. Then, it stores the calculated boundary position information and context information in first register 4613-0 and second register 4614-0.

[0154] Next, the boundary update process of the cutout process will be described. Fig. 14 is a flowchart showing the procedure of the boundary update process of the cutout process executed in the decoding device 46 according to the embodiment.

[0155] The first update circuit 46151 of the boundary update circuit 4615 acquires context information and boundary position information from the first register 4613 (step S21). For example, each of the multiple first update circuits 46151 acquires context information and boundary position information corresponding to each of the multiple bits included in the cutout width from each of the multiple storage locations of the first register 4613.

[0156] The context selection circuit 461511 of the first update circuit 46151 selects a context based on the context information acquired in S21 (step S22).

[0157] The first update circuit 46151 acquires the context information and boundary position information stored in the storage location corresponding to the boundary position information acquired in S21 from among the registers corresponding to the context selected in S22 (step S23). If the context selected in S22 is context 0, the first update circuit 46151 acquires the context information and boundary position information from the first register 4613. If the context selected in S22 is context 1, the first update circuit 46151 acquires the context information and boundary position information from the second register 4614.

[0158] The first update circuit 46151 updates the first register 4613 with the context information and boundary position information acquired in S23 (step S24).

[0159] The second update circuit 46152 of the boundary update circuit 4615 acquires the context information and the boundary position information from the second register 4614 (step S25). For example, each of the second update circuits 46152 acquires the context information and the boundary position information corresponding to each of the multiple bits included in the cutout width from each of the multiple storage locations of the second register 4614.

[0160] The context selection circuit 461521 of the second update circuit 46152 selects a context based on the context information acquired in S25 (step S26).

[0161] The second update circuit 46152 acquires the context information and boundary position information stored in the storage location corresponding to the boundary position information acquired in S25 from the register corresponding to the context selected in S26 (step S27). If the context selected in S26 is context 0, the second update circuit 46152 acquires the context information and boundary position information from the first register 4613. If the context selected in S26 is context 1, the second update circuit 46152 acquires the context information and boundary position information from the second register 4614.

[0162] The second update circuit 46152 updates the second register 4614 with the context information and boundary position information acquired in S27 (step S28).

[0163] The steps from S21 to S24 and the steps from S25 to S28 may be performed in parallel.

[0164] The extraction circuit 461 repeats the procedure described in FIG. 14 to obtain boundary position information and context information of the symbol following each bit in the extraction range.

[0165] As a result, by executing the boundary update process, the extraction circuit 461 can update the boundary position information and context information from one symbol ahead, starting from the symbol that has each bit in the extraction range of the input bit string as the start position, to the boundary position information and context information from two symbols ahead. When the boundary update process is repeated N times, the extraction circuit 461 can update the boundary position information and context information from two symbols ahead based on the boundary position information and context information from one symbol ahead. N It is possible to obtain the boundary position information and context information of the symbol destination.

[0166] Next, the output bitstream output process of the segmentation process will be described below. Fig. 15 is a flowchart showing the output bitstream output process of the segmentation process executed by the decoding device 46 according to the embodiment.

[0167] First, the output bitstream selection circuit 4616 generates an output bitstream based on the context information and boundary position information stored in the first register 4613 and the second register 4614 (step S31).

[0168] The output bit string selection circuit 4616 outputs the output bit string generated in S31 (step S32).

[0169] As a result, the extraction circuit 461 generates an output bit string based on the boundary position information and context information generated by the code length calculation process and boundary update process.

[0170] The output bit string is decoded by, for example, the decoding circuit 462.

[0171] As described above, the extraction circuit 461 of the decoding device 46 according to the embodiment does not require a shift circuit or an adder circuit, and can extract two N The boundary position information and context information of the symbol destination can be obtained.

[0172] The code length calculation circuit 4612 in the extraction circuit 461 of the decoding device 46 according to this embodiment does not require a shift circuit or an adder circuit, as compared with the configuration example of the code length calculation circuit in the comparative example described with reference to Fig. 9. The code length calculation circuit 4612 has components corresponding to the number of bits included in the extraction range. Therefore, as the number of bits included in the extraction range increases, the code length calculation circuit 4612 according to this embodiment has a greater effect of reducing the circuit size compared to the code length calculation circuit in the comparative example.

[0173] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0174] 1...information processing system, 2...host, 3...memory system, 4...controller, 5...NAND flash memory, 6...DRAM, 7...bus, 40...internal bus, 41...host interface, 42...CPU, 43...NAND interface, 44...DRAM interface, 45...encoding device, 46...decoding device, 451...dictionary coding circuit, 452...entropy coding circuit, 461...extraction circuit, 462...decoding circuit, 4621...entropy decoding circuit, 4622...dictionary decoding circuit, 4611...input bit string register, 4612...code length calculation circuit, 4613...first register, 4614...second register, 4615...boundary update circuit, 4616...output bit string selection circuit, 46121...first calculation circuit, 46122...second calculation circuit, 46151...first update circuit, 46152...second update circuit.

Claims

1. A decoding device that decodes input first data, an extraction circuit for extracting one or more symbols from the first data; a decoding circuit for performing a decoding process on the one or more symbols; The extraction circuit a first code length calculation circuit that calculates first code lengths of a plurality of first symbols when each bit included in a first bit string constituted by a plurality of bits included in an extraction range of the first data is set as a starting position and the first symbols are considered to have been encoded by a first encoding method; a second code length calculation circuit that calculates second code lengths of a plurality of second symbols when each bit included in the first bit string is taken as a starting position and the second symbols are considered to have been encoded by a second encoding method; a first decision circuit that determines first context information indicating whether a plurality of third symbols following each of the plurality of first symbols are encoded by the first encoding scheme or the second encoding scheme; a second decision circuit that determines second context information indicating whether a plurality of fourth symbols following each of the plurality of second symbols are encoded by the first encoding scheme or the second encoding scheme; a first register that stores the first context information and first boundary position information that indicates leading bit positions of the third symbols and that is determined based on the first code lengths; a second register that stores the second context information and second boundary position information that indicates the first bit positions of the plurality of fourth symbols and that is determined based on the plurality of second code lengths; a first update circuit that acquires third context information corresponding to a plurality of fifth symbols subsequent to each of the plurality of third symbols and third boundary position information indicating a leading bit of each of the plurality of fifth symbols based on the first context information and the first boundary position information stored in the first register, and stores the acquired information in the first register; a second update circuit that acquires fourth context information corresponding to a plurality of sixth symbols following each of the plurality of fourth symbols and fourth boundary position information indicating a first bit of each of the plurality of sixth symbols based on the second context information and the second boundary position information stored in the second register, and stores the acquired information in the second register; the extraction circuit further includes an output circuit that extracts one or more symbols from the bit string in the extraction range based on a plurality of pieces of context information and a plurality of pieces of boundary position information stored in the first register and the second register, and outputs the extracted symbols to the decoding circuit; the decoding circuit is configured to perform the decoding process on each of the one or more extracted symbols. Decoding device.

2. the first update circuit acquires fifth context information corresponding to seventh symbols following each of the fifth symbols and fifth boundary position information indicating a first bit of the seventh symbols based on the third context information and the third boundary position information stored in the first register; the second update circuit acquires eighth boundary position information corresponding to an eighth symbol following each of the sixth symbols and sixth boundary position information indicating a first bit of the eighth symbol based on the fourth context information and the fourth boundary position information stored in the second register; The first update circuit extracts two symbols from the first symbol. Ｎ repeating the process of acquiring the boundary position information of the symbol destination until the boundary position information is acquired; The second update circuit calculates 2 from the second symbol. Ｎ repeating the process of acquiring the boundary position information of the symbol destination until the boundary position information is acquired; N is an integer of 2 or more.

2. The decoding device according to claim 1.

3. The first data is data encoded based on the Deflate standard, the first encoding method is an encoding method for a literal symbol or a match length symbol; the second encoding method is an encoding method for match distance symbols; 2. The decoding device according to claim 1.

4. The first determination circuit If the first symbol is a literal symbol, outputting the first context information corresponding to the first encoding scheme; If the first symbol is a match length symbol, output the first context information corresponding to the second encoding scheme; the second determination circuit is configured to output the second context information corresponding to the first encoding method.

4. The decoding device according to claim 3.

5. The extraction circuit After extracting the one or more symbols, and extracting one or more symbols from a second bit string formed of a plurality of bits included in the extraction range starting from a bit following a terminal bit of the one or more extracted symbols from the first data.

2. The decoding device according to claim 1.

6. The output circuit 2 Ｎ Based on the context information and boundary position information of the symbol destination, Determine the start bit position of the next extraction range, and determining whether the leading symbol of the next extraction range is encoded using the first encoding method or the second encoding method.

6. The decoding device according to claim 5.

7. the decoding process includes entropy decoding and dictionary decoding performed after the entropy decoding; 2. The decoding device according to claim 1.

8. 1. A memory system connectable to a host, comprising: a non-volatile memory; a memory controller including the decoding device of claim 1 and configured to read data from the non-volatile memory; The decoding device includes: The data read from the nonvolatile memory is input as the first data, The memory controller and transmitting the data decoded by the decoding device to the host. Memory system.

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