Silicon carbide epitaxial substrate, silicon carbide semiconductor device, and method for manufacturing silicon carbide semiconductor device

Abstract

To provide a silicon carbide epitaxial substrate, a silicon carbide semiconductor device, and a method of manufacturing the silicon carbide semiconductor device, capable of improving the yield of the silicon carbide semiconductor device.SOLUTION: The silicon carbide epitaxial substrate includes a silicon carbide substrate and a silicon carbide epitaxial layer on the silicon carbide substrate. The silicon carbide epitaxial layer includes a main surface. The main surface is formed by an outer peripheral region within a 5mm portion from an outer peripheral edge and a central region surrounded by the outer peripheral region. In the central region, the maximum value of the increase rate of the impurity concentration in the <1-100> direction is smaller than the maximum value of the increase rate of the impurity concentration in the <11-20> direction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a silicon carbide epitaxial substrate, a silicon carbide semiconductor device, and a method for manufacturing a silicon carbide semiconductor device. [Background technology]

[0002] Japanese Patent Application Laid-Open No. 2017-145150 (Patent Document 1) describes a method for manufacturing a silicon carbide epitaxial substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-145150 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present disclosure is to provide a silicon carbide epitaxial substrate, a silicon carbide semiconductor device, and a method for manufacturing a silicon carbide semiconductor device that are capable of improving the yield of silicon carbide semiconductor devices. [Means for solving the problem]

[0005] A silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide substrate and a silicon carbide epitaxial layer on the silicon carbide substrate. The silicon carbide epitaxial layer includes a main surface. The main surface is formed by a peripheral region within 5 mm from the outer edge and a central region surrounded by the peripheral region. In the central region, the maximum rate of increase of the impurity concentration in the <1-100> direction is smaller than the maximum rate of increase of the impurity concentration in the <11-20> direction. [Effects of the Invention]

[0006] According to the present disclosure, it is possible to provide a silicon carbide epitaxial substrate, a silicon carbide semiconductor device, and a method for manufacturing a silicon carbide semiconductor device that are capable of improving the yield of silicon carbide semiconductor devices. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view schematically illustrating the configuration of a silicon carbide epitaxial substrate according to the first embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. [Figure 3] FIG. 3 is a schematic diagram showing the relationship between the position on the second line and the impurity concentration in the central region. [Figure 4] FIG. 4 is a schematic diagram showing the relationship between the position on the first line and the impurity concentration in the central region. [Figure 5] FIG. 5 is a plan view schematically illustrating the configuration of a silicon carbide epitaxial substrate according to the second embodiment. [Figure 6] FIG. 6 is a cross-sectional view schematically illustrating the configuration of an apparatus for manufacturing a silicon carbide epitaxial substrate according to this embodiment. [Figure 7] FIG. 7 is a schematic plan view showing the shape of the holder. [Figure 8] FIG. 8 is a cross-sectional view schematically illustrating the configuration of a silicon carbide epitaxial substrate. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a step of forming a body region. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a step of forming a source region. [Figure 11] FIG. 11 is a cross-sectional view schematically illustrating a step of forming a trench in the first main surface. [Figure 12] FIG. 12 is a cross-sectional view showing a process of forming a gate insulating film. [Figure 13] FIG. 13 is a cross-sectional view showing a process of forming a gate electrode and an interlayer insulating film. [Figure 14] FIG. 14 is a cross-sectional view schematically showing the configuration of the silicon carbide semiconductor device in accordance with this embodiment. [Figure 15] FIG. 15 is a schematic plan view showing the shape of a chip of the silicon carbide semiconductor device according to this embodiment. [Figure 16] FIG. 16 is a diagram showing an arrangement of rectangular chips in the case where the longitudinal direction of the chips is parallel to the first direction. [Figure 17] FIG. 17 is a diagram showing an arrangement of rectangular chips in the case where the short side direction of the chips is parallel to the first direction. [Figure 18] FIG. 18 is a plan view schematically illustrating the configuration of a holder used in a method for manufacturing a silicon carbide epitaxial substrate according to a comparative example. [Figure 19] FIG. 19 is a graph showing the relationship between the nitrogen concentration and the measurement position in the silicon carbide epitaxial substrate of Sample 1. As shown in FIG. [Figure 20] FIG. 20 is a graph showing the relationship between the nitrogen concentration and the measurement position in the silicon carbide epitaxial substrate of Sample 2. As shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0008] [Summary of the embodiments of the present disclosure] First, an overview of the embodiments of the present disclosure will be described. In the crystallographic descriptions in this specification, individual orientations are represented by [ ], collective orientations by < >, individual planes by ( ), and collective planes by {}. A negative crystallographic index is usually represented by placing a "-" (bar) above the number, but in this specification, a negative crystallographic index is represented by placing a negative sign before the number.

[0009] (1) A silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide substrate and a silicon carbide epitaxial layer on the silicon carbide substrate. The silicon carbide epitaxial layer includes a main surface. The main surface is formed by a peripheral region within 5 mm from the outer edge and a central region surrounded by the peripheral region. In the central region, the maximum rate of increase of the impurity concentration in the <1-100> direction is smaller than the maximum rate of increase of the impurity concentration in the <11-20> direction.

[0010] (2) In the silicon carbide epitaxial substrate according to (1) above, the maximum rate of increase in the impurity concentration in the <1-100> direction in the central region is 3% cm -1 It may be less than.

[0011] (3) In the silicon carbide epitaxial substrate according to (1) or (2), the maximum rate of increase of the impurity concentration in the <11-20> direction in the central region is 3% cm -1 It may be more than that.

[0012] (4) A silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide substrate and a silicon carbide epitaxial layer on the silicon carbide substrate. The silicon carbide epitaxial substrate has an orientation flat or a notch. The silicon carbide epitaxial layer includes a main surface. The main surface is formed by a peripheral region within 5 mm from the outer periphery and a central region surrounded by the peripheral region. When viewed in a direction from the silicon carbide epitaxial layer toward the silicon carbide substrate, the direction from the center of the main surface toward the orientation flat or the notch is defined as a first direction, and the direction perpendicular to the first direction is defined as a second direction, in the central region, the maximum rate of increase in impurity concentration in the first direction is smaller than the maximum rate of increase in impurity concentration in the second direction.

[0013] (5) In the silicon carbide epitaxial substrate according to (4), the maximum rate of increase of the impurity concentration in the first direction in the central region is 3% cm -1 It may be less than.

[0014] (6) In the silicon carbide epitaxial substrate according to (4) or (5), the maximum rate of increase of the impurity concentration in the second direction in the central region is 3% cm -1 It may be more than that.

[0015] (7) In the silicon carbide epitaxial substrate according to (6) above, the maximum rate of increase of the impurity concentration in the second direction in the central region is 1.5% cm -1 It may be more than that.

[0016] (8) In the silicon carbide epitaxial substrate according to (4) or (5), a line parallel to the second direction and passing through the center when viewed in a direction from the silicon carbide epitaxial layer toward the silicon carbide substrate may intersect with each of the first position and the second position. Each of the first position and the second position may be located on a boundary line between the peripheral region and the central region. The maximum value of the rate of increase of the impurity concentration in the first region between the center and the first position may be greater than the maximum value of the rate of increase of the impurity concentration in the second region between the center and the second position.

[0017] (9) In the silicon carbide epitaxial substrate according to (8), the maximum rate of increase of the impurity concentration in the first region is 3% cm -1 It may be more than that.

[0018] (10) In the silicon carbide epitaxial substrate according to (8), the maximum rate of increase of the impurity concentration in the second region is 3% cm -1 It may be less than.

[0019] (11) In the silicon carbide epitaxial substrate according to (8) above, the impurity concentration may be an n-type impurity concentration.

[0020] (12) A method for manufacturing a silicon carbide semiconductor device according to the present disclosure includes the steps of preparing a silicon carbide epitaxial substrate according to any one of (1), (2), (4), and (5) above, and forming an electrode on the silicon carbide epitaxial substrate.

[0021] (13) A silicon carbide semiconductor device according to the present disclosure includes a silicon carbide substrate, a silicon carbide epitaxial layer, and an electrode. The silicon carbide epitaxial layer is on the silicon carbide substrate. The electrode is on the silicon carbide epitaxial layer. In a primary surface of the silicon carbide epitaxial layer, a maximum rate of increase in impurity concentration in a <1-100> direction is smaller than a maximum rate of increase in impurity concentration in a <11-20> direction.

[0022] (14) In the silicon carbide semiconductor device according to (13), the maximum rate of increase of the impurity concentration in the <1-100> direction on the main surface is 3% cm -1 It may be less than.

[0023] (15) In the silicon carbide semiconductor device according to (13) or (14), the maximum rate of increase of the impurity concentration in the <11-20> direction on the main surface is 3% cm -1 It may be more than that.

[0024] (16) In the silicon carbide semiconductor device according to (13) or (14), the impurity concentration may be an n-type impurity concentration.

[0025] [Details of the embodiments of the present disclosure] Hereinafter, the details of the embodiments of the present disclosure will be described. In the following description, the same or corresponding elements will be denoted by the same reference numerals, and the same description thereof will not be repeated.

[0026] (First embodiment) FIG. 1 is a plan view schematically showing the configuration of a silicon carbide epitaxial substrate 100 according to the first embodiment. FIG. 2 is a cross-sectional view schematically showing the configuration along line II-II in FIG. 1. As shown in FIGS. 1 and 2, the silicon carbide epitaxial substrate 100 according to this embodiment has a silicon carbide substrate 10 and a silicon carbide epitaxial layer 20. The silicon carbide epitaxial layer 20 is on the silicon carbide substrate 10. The silicon carbide epitaxial layer 20 is in contact with the silicon carbide substrate 10. The silicon carbide epitaxial layer 20 has a first main surface 1.

[0027] Silicon carbide epitaxial layer 20 forms a front surface (first main surface 1) of silicon carbide epitaxial substrate 100. Silicon carbide substrate 10 forms a back surface (second main surface 2) of silicon carbide epitaxial substrate 100.

[0028] 1, silicon carbide epitaxial substrate 100 has outer peripheral edge 5. Outer peripheral edge 5 is continuous with first main surface 1. Outer peripheral edge 5 has, for example, orientation flat 3 and arc-shaped portion 4.

[0029] 1 , when viewed in a direction from silicon carbide epitaxial layer 20 toward silicon carbide substrate 10, a direction from center A5 of first main surface 1 toward orientation flat 3 is defined as first direction 101, and a direction perpendicular to first direction 101 is defined as second direction 102. Orientation flat 3 extends along second direction 102. When viewed in a direction from silicon carbide epitaxial layer 20 toward silicon carbide substrate 10, first main surface 1 extends along each of first direction 101 and second direction 102.

[0030] 1, the orientation flat 3 is linear when viewed in a direction from the silicon carbide epitaxial layer 20 toward the silicon carbide substrate 10. The arc-shaped portion 4 is continuous with the orientation flat 3. The arc-shaped portion 4 is arc-shaped.

[0031] The first direction 101 is, for example, the <1-100> direction. The first direction 101 may be, for example, the [1-100] direction. The first direction 101 may be, for example, a direction obtained by projecting the <1-100> direction onto the first main surface 1. From another perspective, the first direction 101 may be, for example, a direction including a <1-100> direction component.

[0032] The second direction 102 is, for example, the <11-20> direction. The second direction 102 may be, for example, the [11-20] direction. The second direction 102 may be a direction obtained by projecting the <11-20> direction onto the first main surface 1. From another perspective, the first direction 101 may be, for example, a direction including a <11-20> direction component.

[0033] The first main surface 1 may be a surface inclined with respect to the {0001} plane. When the first main surface 1 is inclined with respect to the {0001} plane, the inclination angle (off angle) with respect to the {0001} plane is, for example, 2° or more and 6° or less. When the first main surface 1 is inclined with respect to the {0001} plane, the inclination direction (off direction) of the first main surface 1 is, for example, the <11-20> direction. From another perspective, the second direction 102 may be the off direction of the first main surface 1.

[0034] As shown in FIG. 1, the maximum diameter W1 of the first main surface 1 is, for example, 100 mm (4 inches). The maximum diameter W1 may be 125 mm (5 inches) or more, or 150 mm (6 inches) or more. There is no particular upper limit to the maximum diameter W1. The maximum diameter W1 may be, for example, 200 mm (8 inches) or less. The maximum diameter W1 is the maximum distance between any two points on the outer circumferential edge 5.

[0035] In this specification, 4 inches refers to 100 mm or 101.6 mm (4 inches x 25.4 mm / inch). 6 inches refers to 150 mm or 152.4 mm (6 inches x 25.4 mm / inch). 8 inches refers to 200 mm or 203.2 mm (8 inches x 25.4 mm / inch).

[0036] The polytype of the silicon carbide constituting silicon carbide substrate 10 is, for example, 4H. Similarly, the polytype of the silicon carbide constituting silicon carbide epitaxial layer 20 is, for example, 4H. As shown in Fig. 2 , third direction 103 is a direction from silicon carbide epitaxial layer 20 toward silicon carbide substrate 10. Third direction 103 is perpendicular to each of first direction 101 and second direction 102.

[0037] As shown in FIG. 2 , silicon carbide epitaxial layer 20 has buffer layer 11 and drift layer 14. Buffer layer 11 is on silicon carbide substrate 10. Buffer layer 11 is continuous with silicon carbide substrate 10. Drift layer 14 is on buffer layer 11. Drift layer 14 is continuous with buffer layer 11. Drift layer 14 constitutes first main surface 1. In third direction 103, buffer layer 11 is located between silicon carbide substrate 10 and drift layer 14.

[0038] The silicon carbide substrate 10 contains nitrogen (N) as an n-type impurity. The conductivity type of the silicon carbide substrate 10 is n-type. The silicon carbide epitaxial layer 20 contains nitrogen as an n-type impurity. The conductivity type of the silicon carbide epitaxial layer 20 is n-type. Specifically, the buffer layer 11 and the drift layer 14 each contain nitrogen as an n-type impurity. The impurity concentration of the buffer layer 11 is higher than the impurity concentration of the drift layer 14. The conductivity type of the buffer layer 11 and the drift layer 14 is n-type. The impurity concentration is an n-type impurity concentration. The n-type impurity may be phosphorus (P).

[0039] As shown in FIG. 1 , silicon carbide epitaxial substrate 100 has an orientation flat 3. First main surface 1 is formed by a peripheral region 7 and a central region 8. When viewed in a direction from silicon carbide epitaxial layer 20 toward silicon carbide substrate 10, peripheral region 7 is a region within 5 mm from outer periphery 5. Central region 8 is surrounded by peripheral region 7. Central region 8 is continuous with peripheral region 7.

[0040] When viewed in a direction from silicon carbide epitaxial layer 20 toward silicon carbide substrate 10, a line that is parallel to second direction 102 and passes through center A5 of first main surface 1 is defined as second line C2. Second line C2 intersects with first position A1 and second position A2. First position A1 and second position A2 are each located on the boundary line between peripheral region 7 and central region 8. First position A1 is located in second direction 102 with respect to center A5 of first main surface 1. Second position A2 is located opposite first position A1 with respect to center A5 of first main surface 1. Center A5 of first main surface 1 is located between first position A1 and second position A2.

[0041] When viewed in a direction from silicon carbide epitaxial layer 20 toward silicon carbide substrate 10, a line that is parallel to first direction 101 and passes through center A5 of first main surface 1 is defined as first line C1. First line C1 intersects with the boundary line between peripheral region 7 and central region 8 at third position A3 and fourth position A4. Third position A3 is located between orientation flat 3 and center A5. Fourth position A4 is located opposite third position A3 with respect to center A5 of first main surface 1. Center A5 of first main surface 1 is located between third position A3 and fourth position A4.

[0042] 3 is a schematic diagram showing the relationship between the position on the second line C2 and the impurity concentration in the central region 8. The impurity concentration at the first position A1 is a first impurity concentration B1. The impurity concentration at the second position A2 is a second impurity concentration B2. As shown in FIG. 3, the first impurity concentration B1 is higher than the second impurity concentration B2.

[0043] In the central region 8, the maximum rate of increase of the impurity concentration in the second direction 102 is, for example, 3% cm -1 In the central region 8, the maximum rate of increase in the impurity concentration in the second direction 102 is 2% cm -1 It may be more than 1.5% cm -1 It may be more than 1% cm -1 In the central region 8, the maximum rate of increase in the impurity concentration in the second direction 102 is 10% cm -1May be less than 5% cm -1 It may be the following:

[0044] The rate of increase in impurity concentration is calculated by dividing the absolute value of the difference in impurity concentration between two adjacent measurement points by the average value of the impurity concentrations at the two adjacent measurement points, and then dividing that value by the distance between the two adjacent measurement points. The distance between the two measurement points is 1.4 cm. As shown in FIG. 3 , for example, if the absolute value of the difference between the impurity concentration at the first position A1 and the impurity concentration at the sixth position A6 is E, and the distance between the first position A1 and the sixth position A6 is D, the rate of increase in impurity concentration is calculated by dividing E by the average value of B1 and B6, and then dividing that value by D. Here, the impurity concentration at the sixth position A6 is the sixth impurity concentration B6. E is the absolute value of the difference between the first impurity concentration B1 and the sixth impurity concentration B6.

[0045] 1 and 3, the central region 8 has a first region R1 and a second region R2. The first region R1 is a region located between the center A5 of the first main surface 1 and a first position A1. The second region R2 is a region located between the center A5 of the first main surface 1 and a second position A2. The maximum rate of increase in the impurity concentration in the first region R1 is greater than the maximum rate of increase in the impurity concentration in the second region R2.

[0046] The maximum rate of increase in the impurity concentration in the first region R1 is, for example, 3% cm -1 The maximum rate of increase in the impurity concentration in the first region R1 is 2% cm -1 It may be more than 1.5% cm -1 It may be more than 1% cm -1 The maximum rate of increase in the impurity concentration in the first region R1 may be 10% cm -1 May be less than 5% cm -1 It may be the following:

[0047] The maximum rate of increase in the impurity concentration in the second region R2 is, for example, 3% cm -1The maximum rate of increase of the impurity concentration in the second region R2 may be less than 2% cm -1 May be less than 1.5% cm -1 It may be the following:

[0048] 4 is a schematic diagram showing the relationship between the position on the first line C1 and the impurity concentration in the central region 8. The impurity concentration at the third position A3 is a third impurity concentration B3. The impurity concentration at the fourth position A4 is a fourth impurity concentration B4. The impurity concentration at the center A5 of the first main surface 1 is a fifth impurity concentration B5. When viewed in the third direction 103, the center A5 of the first main surface 1 is located at the intersection of the first line C1 and the second line C2 (see FIG. 1).

[0049] 4, the third impurity concentration B3 may be higher than the fifth impurity concentration B5. The fourth impurity concentration B4 may be higher than the fifth impurity concentration B5. The fourth impurity concentration B4 may be higher than the third impurity concentration B3, may be the same as the third impurity concentration B3, or may be lower than the third impurity concentration B3. The first impurity concentration B1 is higher than the fifth impurity concentration B5 (see FIG. 3).

[0050] 3 and 4, in the central region 8, the maximum value of the rate of increase of the impurity concentration in the first direction 101 is smaller than the maximum value of the rate of increase of the impurity concentration in the second direction 102. In the central region 8, the maximum value of the rate of increase of the impurity concentration in the first direction 101 is 3% cm -1 In the central region 8, the maximum rate of increase of the impurity concentration in the first direction 101 may be less than 2.5% cm -1 May be less than 2% cm -1 It may be the following:

[0051] 1 and 4, the central region 8 has a third region R3 and a fourth region R4. The third region R3 is a region located between the center A5 of the first main surface 1 and the third position A3. The fourth region R4 is a region located between the center A5 of the first main surface 1 and the fourth position A4. The maximum value of the rate of increase of the impurity concentration in the fourth region R4 may be greater than the maximum value of the rate of increase of the impurity concentration in the third region R3, may be the same as the maximum value of the rate of increase of the impurity concentration in the third region R3, or may be smaller than the maximum value of the rate of increase of the impurity concentration in the third region R3.

[0052] Next, a method for measuring the impurity concentration will be described. The impurity concentration in each of the above regions is measured using, for example, a mercury probe type C (Capacitance)-V (Voltage) measuring device. As the mercury probe type CV measuring device, for example, a CV measuring device (model number: CVmap92A) manufactured by Four Dimensions can be used. The mercury probe is brought into contact with the first main surface 1 to measure the carrier concentration of silicon carbide epitaxial layer 20 on first main surface 1. The measured carrier concentration is taken as the impurity concentration. The measuring diameter of the mercury probe is approximately 1.2 mm. The measuring speed is approximately 1 minute per point. The measuring interval of the mercury probe is 1.4 cm.

[0053] (Second embodiment) Next, the configuration of silicon carbide epitaxial substrate 100 according to the second embodiment will be described. Silicon carbide epitaxial substrate 100 according to the second embodiment differs from silicon carbide epitaxial substrate 100 according to the first embodiment mainly in that it has a notch instead of an orientation flat, but otherwise is substantially the same as silicon carbide epitaxial substrate 100 according to the first embodiment. The following description will focus on the configuration that differs from silicon carbide epitaxial substrate 100 according to the first embodiment.

[0054] Fig. 5 is a plan view schematically illustrating the configuration of a silicon carbide epitaxial substrate 100 according to the second embodiment. As shown in Fig. 5, a notch 9 is provided in silicon carbide epitaxial substrate 100. Specifically, outer peripheral edge 5 of silicon carbide epitaxial substrate 100 has notch 9 and an arc-shaped portion 4.

[0055] 5, when viewed in a direction from silicon carbide epitaxial layer 20 toward silicon carbide substrate 10, the direction from center A5 of first main surface 1 toward notch 9 is defined as first direction 101, and the direction perpendicular to first direction 101 is defined as second direction 102. Notch 9 has, for example, a curved shape. Arc-shaped portion 4 is continuous with notch 9. When viewed in a direction from silicon carbide epitaxial layer 20 toward silicon carbide substrate 10, notch 9 is recessed from outer circumferential edge 5 toward center A5 of first main surface 1.

[0056] (Silicon carbide epitaxial substrate manufacturing equipment) Fig. 6 is a cross-sectional view schematically illustrating the configuration of an apparatus for manufacturing silicon carbide epitaxial substrate 100 according to this embodiment. As shown in Fig. 6, the apparatus for manufacturing silicon carbide epitaxial substrate 100 is, for example, a hot-wall horizontal CVD (Chemical Vapor Deposition) apparatus. Manufacturing apparatus 250 for silicon carbide epitaxial substrate 100 mainly includes chamber 201, gas supply unit 235, control unit 245, heating element 203, quartz tube 204, a heat insulating material (not shown), and an induction heating coil (not shown).

[0057] The heating element 203 has, for example, a cylindrical shape, and defines a chamber 201 therein. The heating element 203 is made of, for example, graphite. The heating element 203 is provided inside a quartz tube 204. A heat insulating material surrounds the outer periphery of the heating element 203. The induction heating coil is wound around, for example, the outer periphery of the quartz tube 204. The induction heating coil is configured so that an alternating current can be supplied to it from an external power source (not shown). This causes the heating element 203 to be induction heated. As a result, the chamber 201 is heated by the heating element 203.

[0058] Chamber 201 is formed by being surrounded by inner wall surface 205 of heating element 203. Chamber 201 is provided with holder 210 that holds silicon carbide substrate 10. Holder 210 is made of, for example, silicon carbide. Silicon carbide substrate 10 is placed on holder 210. Holder 210 is placed on stage 206. Stage 206 is rotatably supported by rotation shaft 209. When stage 206 rotates, holder 210 rotates.

[0059] Manufacturing apparatus 250 for silicon carbide epitaxial substrate 100 further includes gas inlet 207 and gas outlet 208. Gas outlet 208 is connected to an exhaust pump (not shown). Arrows in FIG. 6 indicate the flow of gas. Gas is introduced into chamber 201 from gas inlet 207 and exhausted from gas exhaust outlet 208. The pressure inside chamber 201 is adjusted by balancing the amount of gas supplied and the amount of gas exhausted.

[0060] The gas supply unit 235 is configured to be able to supply a mixed gas containing a source gas, a dopant gas, and a carrier gas to the chamber 201. Specifically, the gas supply unit 235 includes, for example, a first gas supply unit 231, a second gas supply unit 232, a third gas supply unit 233, and a fourth gas supply unit 234.

[0061] The first gas supply unit 231 is configured to be able to supply a first gas containing, for example, carbon atoms. The first gas supply unit 231 is, for example, a gas cylinder filled with the first gas. The first gas is, for example, propane (C3H8) gas. The first gas may also be, for example, methane (CH4) gas, ethane (C2H6) gas, acetylene (C2H2) gas, etc.

[0062] The second gas supply unit 232 is configured to be able to supply a second gas containing, for example, silane gas. The second gas supply unit 232 is, for example, a gas cylinder filled with the second gas. The second gas is, for example, silane (SiH4) gas. The second gas may be a mixed gas of silane gas and a gas other than silane.

[0063] The third gas supply unit 233 is configured to be able to supply a third gas containing, for example, ammonia gas. The third gas supply unit 233 is, for example, a gas cylinder filled with the third gas. The third gas is a doping gas containing N (nitrogen atoms). Ammonia gas is more susceptible to thermal decomposition than nitrogen gas, which has a triple bond. The third gas may be nitrogen gas.

[0064] The fourth gas supply unit 234 is configured to be able to supply a fourth gas (carrier gas) such as hydrogen, etc. The fourth gas supply unit 234 is, for example, a gas cylinder filled with hydrogen.

[0065] The control unit 245 is configured to be able to control the flow rate of the mixed gas supplied from the gas supply unit 235 to the chamber 201. Specifically, the control unit 245 may include a first gas flow rate control unit 241, a second gas flow rate control unit 242, a third gas flow rate control unit 243, and a fourth gas flow rate control unit 244. Each control unit may be, for example, an MFC (Mass Flow Controller). The control unit 245 is disposed between the gas supply unit 235 and the gas inlet 207. In other words, the control unit 245 is disposed in a flow path connecting the gas supply unit 235 and the gas inlet 207.

[0066] (Method for manufacturing silicon carbide epitaxial substrate) Next, a method for manufacturing silicon carbide epitaxial substrate 100 in accordance with this embodiment will be described.

[0067] First, a silicon carbide substrate 10 is prepared. A silicon carbide single crystal of polytype 4H is manufactured by, for example, sublimation. Next, the silicon carbide single crystal is sliced ​​by, for example, a wire saw, to prepare the silicon carbide substrate 10. The silicon carbide substrate 10 contains an n-type impurity such as nitrogen. The conductivity type of the silicon carbide substrate 10 is, for example, n-type. Next, the silicon carbide substrate 10 is mechanically polished. Next, the silicon carbide substrate 10 is subjected to chemical mechanical polishing.

[0068] Next, a silicon carbide epitaxial layer 20 is formed on the silicon carbide substrate 10. Specifically, first, the silicon carbide substrate 10 is placed on a holder. FIG. 7 is a plan view schematic diagram showing the shape of the holder. As shown in FIG. 7, three substrate placement grooves 32 are formed on the surface of the holder 210. Each of the three substrate placement grooves 32 has a groove side surface 31 and a groove bottom surface 30. The groove side surface 31 has a first side surface portion 31a and a second side surface portion 31b.

[0069] 7, in a plan view, first side surface portion 31a is arc-shaped, and second side surface portion 31b is linear. When silicon carbide substrate 10 is placed in substrate placement groove 32, orientation flat 3 faces second side surface portion 31b. In a plan view, second side surface portion 31b is arranged so as to be substantially parallel to a line passing through the center of substrate placement groove 32 and the center of holder 210. As described above, silicon carbide substrate 10 is placed in substrate placement groove 32 provided in holder 210.

[0070] Next, a silicon carbide epitaxial layer 20 is formed on the silicon carbide substrate 10. Specifically, the silicon carbide epitaxial layer 20 is formed by epitaxial growth using a CVD (Chemical Vapor Deposition) method. In the epitaxial growth, for example, silane (SiH4) and propane (C3H8) are used as source gases, and hydrogen (H2) is used as a carrier gas. The epitaxial growth temperature is, for example, about 1400°C or higher and 1750°C or lower. In the epitaxial growth, for example, ammonia gas is used as a dopant gas. As a result, nitrogen atoms are introduced into the silicon carbide epitaxial layer 20.

[0071] Specifically, first, a carrier gas is introduced into the chamber 201. The flow rate of the carrier gas is, for example, 100 slm. Next, ammonia gas is introduced into the chamber 201. Ammonia gas, silane, and propane are introduced into the chamber 201. The flow rate of the ammonia gas is, for example, 1.5 sccm. The flow rate of the silane is, for example, 46 sccm. The flow rate of the propane gas is, for example, 29 sccm. The pressure inside the chamber 201 is, for example, 2 kPa or more and 6 kPa or less.

[0072] FIG. 8 is a cross-sectional schematic diagram showing the configuration of a silicon carbide epitaxial substrate 100. As shown in FIG. 8, the silicon carbide epitaxial substrate 100 has a silicon carbide substrate 10 and a silicon carbide epitaxial layer 20. The silicon carbide epitaxial layer 20 has a buffer layer 11 and a drift layer 14. The buffer layer 11 is provided on a third main surface 15. The drift layer 14 is provided on the buffer layer 11. Each of the buffer layer 11 and the drift layer 14 contains an n-type impurity such as nitrogen. The impurity concentration of the buffer layer 11 may be higher than the impurity concentration of the drift layer 14.

[0073] (Method for manufacturing silicon carbide semiconductor device) Next, a method for manufacturing silicon carbide semiconductor device 300 according to this embodiment will be described.

[0074] First, a silicon carbide epitaxial substrate 100 according to this embodiment is prepared (see FIG. 8). Next, a step of forming a body region is performed. FIG. 9 is a cross-sectional view schematically showing the step of forming a body region. Specifically, p-type impurities such as aluminum are ion-implanted into drift layer 14 of silicon carbide epitaxial layer 20. This forms body region 113 having p-type conductivity. Body region 113 has a thickness of, for example, 0.9 μm.

[0075] Next, a step of forming a source region is performed. FIG. 10 is a cross-sectional view showing the step of forming the source region. Specifically, n-type impurities such as phosphorus are ion-implanted into the body region 113. This forms a source region 114 having n-type conductivity. The thickness of the source region 114 is, for example, 0.4 μm. The concentration of the n-type impurities contained in the source region 114 may be higher than the concentration of the p-type impurities contained in the body region 113.

[0076] Next, a p-type impurity such as aluminum is ion-implanted into the source region 114 to form a contact region 118. The contact region 118 is formed to penetrate the source region 114 and the body region 113 and to be in contact with the third layer 13. The concentration of the p-type impurity contained in the contact region 118 may be higher than the concentration of the n-type impurity contained in the source region 114.

[0077] Next, activation annealing is performed to activate the implanted impurities. The temperature of the activation annealing is, for example, about 1700° C. The activation annealing time is, for example, about 30 minutes. The atmosphere of the activation annealing is, for example, an Ar atmosphere.

[0078] Next, a step of forming trenches in the first main surface 1 is performed. FIG. 11 is a cross-sectional view showing the step of forming trenches in the first main surface 1. As shown in FIG. 11, a mask 117 having openings is formed on the first main surface 1 including the source region 114 and the contact region 118. The source region 114, the body region 113, and a portion of the drift layer 14 are removed by etching using the mask 117. As an etching method, for example, reactive ion etching, particularly inductively coupled plasma reactive ion etching, can be used. Specifically, for example, inductively coupled plasma reactive ion etching using SF or a mixed gas of SF and O as a reactive gas can be used. As a result of the etching, recesses are formed in the first main surface 1.

[0079] Next, thermal etching is performed on the recesses. Thermal etching can be performed, for example, by heating the first main surface 1 with the mask 117 formed thereon in an atmosphere containing a reactive gas having at least one type of halogen atom. The at least one type of halogen atom includes at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere includes, for example, Cl2, BCl3, SF6, or CF4. For example, thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as the reactive gas, with the heat treatment temperature set to, for example, 700°C or higher and 1000°C or lower. The reactive gas may contain a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas. Examples of the carrier gas that can be used include nitrogen gas, argon gas, and helium gas.

[0080] 11 , trenches 106 are formed in the first main surface 1 by thermal etching. The trenches 106 are defined by side surfaces 123 and a bottom surface 124. The side surfaces 123 are formed by the source region 114, the body region 113, and the drift layer 14. The bottom surface 124 is formed by the drift layer 14. Next, the mask 117 is removed from the first main surface 1.

[0081] Next, a step of forming a gate insulating film is performed. Fig. 12 is a cross-sectional view schematically illustrating the step of forming a gate insulating film. Specifically, silicon carbide epitaxial substrate 100 having trench 106 formed in first main surface 1 is heated in an oxygen-containing atmosphere at a temperature of, for example, 1300°C or higher and 1400°C or lower. This forms gate insulating film 115 that is in contact with drift layer 14 at bottom surface 124, in contact with drift layer 14, body region 113, and source region 114 at side surface 123, and in contact with source region 114 and contact region 118 at first main surface 1.

[0082] Next, a step of forming a gate electrode is performed. Fig. 13 is a cross-sectional view showing a step of forming a gate electrode and an interlayer insulating film. The gate electrode 127 is formed inside the trench 106 so as to contact the gate insulating film 115. The gate electrode 127 is disposed inside the trench 106 and is formed on the gate insulating film 115 so as to face each of the side surface 123 and the bottom surface 124 of the trench 106. The gate electrode 127 is formed, for example, by an LPCVD (Low Pressure Chemical Vapor Deposition) method.

[0083] Next, an interlayer insulating film 126 is formed. The interlayer insulating film 126 is formed so as to cover the gate electrode 127 and to be in contact with the gate insulating film 115. The interlayer insulating film 126 is formed by, for example, chemical vapor deposition. The interlayer insulating film 126 is made of, for example, a material containing silicon dioxide. Next, the interlayer insulating film 126 and the gate insulating film 115 are partially etched so as to form openings over the source region 114 and the contact region 118. As a result, the contact region 118 and the source region 114 are exposed from the gate insulating film 115.

[0084] Next, a step of forming a source electrode is performed. The source electrode 116 is formed so as to contact each of the source region 114 and the contact region 118. The source electrode 116 is formed by, for example, a sputtering method. The source electrode 116 is made of, for example, a material containing Ti, Al, and Si.

[0085] Next, alloying annealing is performed. Specifically, the source electrode 116 in contact with each of the source region 114 and the contact region 118 is maintained at a temperature of 900°C or higher and 1100°C or lower for about 5 minutes. This causes at least a portion of the source electrode 116 to be silicided. This forms the source electrode 116 in ohmic contact with the source region 114.

[0086] Next, the source wiring 119 is formed. The source wiring 119 is electrically connected to the source electrode 116. The source wiring 119 is formed so as to cover the source electrode 116 and the interlayer insulating film 126.

[0087] Next, the step of forming the drain electrode 120 is carried out. First, the silicon carbide substrate 10 is polished on the second main surface 2. Next, the drain electrode 120 is formed. The drain electrode 120 is formed so as to be in contact with the silicon carbide substrate 10 on the second main surface 2. In this manner, the silicon carbide semiconductor device 300 according to this embodiment is manufactured.

[0088] (Silicon carbide semiconductor device) Next, the configuration of a silicon carbide semiconductor device 300 according to this embodiment will be described. FIG. 14 is a cross-sectional schematic diagram showing the configuration of the silicon carbide semiconductor device 300 according to this embodiment. As shown in FIG. 14, the silicon carbide semiconductor device 300 according to this embodiment mainly includes a silicon carbide epitaxial substrate 100, a gate insulating film 115, a gate electrode 127, a source electrode 116, a drain electrode 120, a source wiring 119, and an interlayer insulating film 126. The silicon carbide epitaxial substrate 100 includes a silicon carbide substrate 10, a silicon carbide epitaxial layer 20, a first main surface 1, and a second main surface 2. The silicon carbide epitaxial layer 20 includes a buffer layer 11, a drift layer 14, a body region 113, a source region 114, and a contact region 118.

[0089] The body region 113 is formed on the drift layer 14. The body region 113 is in contact with the drift layer 14. The body region 113 contains p-type impurities such as aluminum. The body region 113 has p-type conductivity. The source region 114 is formed on the body region 113. The source region 114 contains n-type impurities such as phosphorus. The source region 114 has n-type conductivity. The concentration of the n-type impurities contained in the source region 114 may be higher than the concentration of the p-type impurities contained in the body region 113.

[0090] The contact region 118 penetrates the source region 114 and the body region 113. The contact region 118 is in contact with each of the source region 114, the body region 113, and the third layer 13. The contact region 118 contains p-type impurities such as aluminum. The concentration of the p-type impurities contained in the contact region 118 may be higher than the concentration of the n-type impurities contained in the source region 114.

[0091] A trench 106 is provided in the first main surface 1. The trench 106 is defined by a side surface 123 and a bottom surface 124. The side surface 123 is formed by the source region 114, the body region 113, and the drift layer 14. The bottom surface 124 is formed by the drift layer 14.

[0092] The gate insulating film 115 is in contact with the drift layer 14 at its bottom surface 124, and is in contact with each of the drift layer 14, the body region 113, and the source region 114 at its side surface 123. The gate electrode 127 is disposed on the gate insulating film 115. The gate electrode 127 is in contact with the gate insulating film 115 inside the trench 106. The gate electrode 127 faces each of the side surface 123 and the bottom surface 124 of the trench 106.

[0093] The interlayer insulating film 126 covers the gate electrode 127. The interlayer insulating film 126 is in contact with the gate insulating film 115. The interlayer insulating film 126 is made of a material containing, for example, silicon dioxide. The source electrode 116 is in contact with each of the source region 114 and the contact region 118. The source electrode 116 is made of a material containing, for example, Ti, Al, and Si. The source wiring 119 is in contact with the source electrode 116. The source wiring 119 is electrically connected to the source electrode 116. The source wiring 119 covers the source electrode 116 and the interlayer insulating film 126. The drain electrode 120 is in contact with the silicon carbide substrate 10 on the second main surface 2.

[0094] Fig. 15 is a plan view schematically showing the shape of a chip of silicon carbide semiconductor device 300 according to this embodiment. As shown in Fig. 15, chip 55 of silicon carbide semiconductor device 300 has, for example, a rectangular shape when viewed in a direction perpendicular to first main surface 1. The longitudinal direction of chip 55 is aligned with first direction 101. The lateral direction of chip 55 is aligned with second direction 102.

[0095] On the first main surface 1, the maximum rate of increase of the impurity concentration in the first direction 101 is, for example, 3% cm -1 On the first main surface 1, the maximum rate of increase of the impurity concentration in the first direction 101 is 2.5% cm -1 May be less than 2% cm -1 It may be the following:

[0096] On the first main surface 1, the maximum rate of increase of the impurity concentration in the second direction 102 is, for example, 3% cm -1 On the first main surface 1, the maximum rate of increase in the impurity concentration in the second direction 102 is 2% cm -1 It may be more than 1.5% cm -1 It may be more than 1% cm -1 On the first main surface 1, the maximum rate of increase in the impurity concentration in the second direction 102 is 10% cm -1 May be less than 5% cm -1 It may be the following:

[0097] The rate of increase in impurity concentration is calculated by dividing the absolute value of the difference in impurity concentration between two adjacent measurement points by the average value of the impurity concentrations at the two adjacent measurement points, and then dividing this value by the distance between the two adjacent measurement points. In silicon carbide semiconductor device 300, the distance between measurement points is 1.4 mm. The impurity concentration is measured by SIMS (Secondary Ion Mass Spectrometry) analysis.

[0098] In the above embodiment, the silicon carbide semiconductor device 300 is a MOSFET, but the silicon carbide semiconductor device 300 is not limited to a MOSFET. The silicon carbide semiconductor device 300 may be, for example, an IGBT (Insulated Gate Bipolar Transistor) or the like.

[0099] Next, the effects of silicon carbide epitaxial substrate 100, silicon carbide semiconductor device 300, and method for manufacturing silicon carbide semiconductor device 300 according to this embodiment will be described.

[0100] Silicon carbide semiconductor device 300 is formed by patterning silicon carbide epitaxial substrate 100. The chip shape of silicon carbide semiconductor device 300 is square or rectangular. It is desirable that the impurity concentration distribution in silicon carbide epitaxial substrate 100 has high in-plane uniformity.

[0101] When a current flows through an electronic circuit, heat is generated in the electronic circuit according to the current and electrical resistance. In the silicon carbide semiconductor device 300, heat is generated during ON operation according to the ON current and ON resistance. If the impurity concentration distribution within the chip of the silicon carbide semiconductor device 300 becomes large, the current becomes large locally in the region with a high impurity concentration. As a result, the region becomes locally hot, causing the chip to become defective. This reduces the yield of the silicon carbide semiconductor device 300.

[0102] The inventors investigated the in-plane distribution of the impurity concentration in silicon carbide epitaxial substrate 100 and found that the impurity concentration increases sharply from center A5 of first main surface 1 toward the direction in which the orientation flat is located (i.e., first direction 101 or <1-100> direction). In this case, the distribution of the impurity concentration in first direction 101 is greater than the distribution of the impurity concentration in second direction 102. When the longitudinal direction of rectangular chip 55 is parallel to first direction 101, the distribution of the impurity concentration within chip 55 is greater than when the lateral direction of rectangular chip 55 is parallel to first direction 101.

[0103] After extensive investigation, the inventors have focused on making the distribution of impurity concentration in second direction 102 perpendicular to first direction 101 greater than the distribution of impurity concentration in first direction 101. This makes it possible to reduce the distribution of impurity concentration in the longitudinal direction of chip 55 of silicon carbide semiconductor device 300. As a result, the yield of silicon carbide semiconductor device 300 can be improved.

[0104] In silicon carbide epitaxial substrate 100 according to the present embodiment, the maximum value of the rate of increase of the impurity concentration in the <1-100> direction is smaller than the maximum value of the rate of increase of the impurity concentration in the <11-20> direction in central region 8. This enables the yield of silicon carbide semiconductor device 300 to be improved when the longitudinal direction of chip 55 is along the <1-100> direction.

[0105] In silicon carbide epitaxial substrate 100 according to the present embodiment, in central region 8, the maximum value of the rate of increase of the impurity concentration in first direction 101 is smaller than the maximum value of the rate of increase of the impurity concentration in second direction 102. This enables the yield of silicon carbide semiconductor device 300 to be improved when the longitudinal direction of chip 55 is aligned with first direction 101.

[0106] Fig. 16 is a diagram showing an arrangement of rectangular chips 55 when the longitudinal direction of the chips is parallel to first direction 101. As shown in Fig. 16, on first main surface 1 of silicon carbide epitaxial substrate 100, multiple chips 55 are arranged along each of first direction 101 and second direction 102. When viewed in a direction perpendicular to first main surface 1, the length of chip 55 in first direction 101 is greater than the length of chip 55 in second direction 102.

[0107] 17 is a diagram showing an arrangement of rectangular chips 55 in the case where the short side direction of the chips is parallel to a first direction 101. As shown in Fig. 17, when viewed in a direction perpendicular to the first main surface 1, the length of the chips 55 in the first direction 101 is smaller than the length of the chips in the second direction 102.

[0108] Bar-shaped stacking faults 56 may occur in silicon carbide epitaxial substrate 100. Bar-shaped stacking faults 56 extend in the <1-100> direction (i.e., first direction 101). As shown in FIG. 16 , when bar-shaped stacking faults 56 are formed in rectangular chips 55 whose longitudinal directions are parallel to first direction 101, three chips 55 become defective. On the other hand, as shown in FIG. 17 , when bar-shaped stacking faults 56 are formed in rectangular chips 55 whose lateral directions are parallel to first direction 101, four chips 55 become defective. In other words, when the longitudinal direction of rectangular chips 55 is parallel to first direction 101, the defect rate of chips 55 can be reduced compared to when the lateral direction of chips 55 is parallel to first direction 101. As a result, the yield of silicon carbide semiconductor devices 300 can be improved. [Example]

[0109] (Sample preparation) Silicon carbide epitaxial substrates 100 according to Samples 1 and 2 were prepared. Silicon carbide epitaxial substrate 100 according to Sample 1 is a comparative example. Silicon carbide epitaxial substrate 100 according to Sample 2 is an example.

[0110] FIG. 18 is a plan view schematically illustrating the configuration of a holder 210 used in a comparative example method for manufacturing a silicon carbide epitaxial substrate 100. As shown in FIG. 18, three substrate placement grooves 32 are formed in the surface of holder 210. Each of the three substrate placement grooves 32 has a groove side surface 31 and a groove bottom surface 30. Groove side surface 31 has a first side surface portion 31a and a second side surface portion 31b. In a plan view, first side surface portion 31a is arc-shaped, and second side surface portion 31b is linear. When silicon carbide substrate 10 is placed in substrate placement groove 32, orientation flat 3 faces second side surface portion 31b.

[0111] 18, in holder 210 used in the method for manufacturing silicon carbide epitaxial substrate 100 of the comparative example, second side surface portion 31b is arranged so as to be substantially perpendicular to a line passing through the center of substrate placement groove 32 and the center of holder 210. On the other hand, in holder 210 used in the method for manufacturing silicon carbide epitaxial substrate 100 of the example, second side surface portion 31b is arranged so as to be substantially parallel to a line passing through the center of substrate placement groove 32 and the center of holder 210 (see FIG. 7).

[0112] (Evaluation method) FIG. 19 is a diagram showing the relationship between the nitrogen concentration and the measurement position in silicon carbide epitaxial substrate 100 of Sample 1. FIG. 20 is a diagram showing the relationship between the nitrogen concentration and the measurement position in silicon carbide epitaxial substrate 100 of Sample 2. The nitrogen concentration on first main surface 1 was measured using a CV measurement device (model number: CVmap92A) manufactured by Four Dimensions. The measurement diameter of the mercury probe was approximately 1.2 mm. The measurement speed was approximately 1 minute per point. The measurement interval of the mercury probe was 1.4 cm.

[0113] In Figures 19 and 20, the value of "□" indicates the nitrogen concentration at a measurement position arranged along the direction from the second position A2 to the first position A1. The first position A1 is at 70 mm. The second position A2 is at -70 mm. The value of "◇" indicates the nitrogen concentration at a measurement position arranged along the direction from the third position A3 to the fourth position A4. The third position A3 is at -64 mm. The fourth position A4 is at 70 mm. The value of "△" indicates the nitrogen concentration at a measurement position arranged along a direction that bisects the angle between the direction of the value of "□" and the direction of the value of "◇". The value of "X" indicates the nitrogen concentration at a measurement position arranged along a direction perpendicular to the direction of the value of "△". The center A5 of the first main surface 1 is at 0 mm.

[0114] (Evaluation results) 19, the nitrogen concentration was generally constant in the direction from the second position A2 to the first position A1. In the direction from the center A5 of the first main surface 1 to the third position A3, the nitrogen concentration significantly increased with increasing distance from the third position A3. In the direction from the center A5 of the first main surface 1 to the fourth position A4, the nitrogen concentration was generally constant.

[0115] 20, the nitrogen concentration was generally constant in the direction from the center A5 of the first main surface 1 toward the second position A2. In the direction from the center A5 of the first main surface 1 toward the first position A1, the nitrogen concentration significantly increased as the distance to the first position A1 increased. In the direction from the first main surface 1 toward the third position A3, the nitrogen concentration slightly increased as the distance to the third position A3 increased. In the direction from the first main surface 1 toward the fourth position A4, the nitrogen concentration slightly increased as the distance to the fourth position A4 increased.

[0116] The embodiments and examples disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present invention is defined by the claims rather than the above-described embodiments and examples, and it is intended to include any modifications within the scope of the claims that are equivalent to the claims. [Explanation of symbols]

[0117] 1 First main surface 2 Second main surface 3 Orientation Flat 4 Arc-shaped section 5 outer edge 7 Outer area 8 central area 9 notches 10 Silicon carbide substrate 11 Buffer layer 13 3rd layer 14 Drift Layer 15 Third main surface 20 Silicon carbide epitaxial layer 30 Groove bottom surface 31 Groove side 31a 1st side part 31b Second side part 32 Board placement groove 55 chips 56 Stacking faults 100 Silicon carbide epitaxial substrate 101 1st direction 102 Second direction 103 Third direction 106 Trench 113 Body Region 114 Source Region 115 Gate insulating film 116 Source electrode 117 Mask 118 Contact Area 119 Source wiring 120 drain electrode 123 Side 124 bottom 126 Interlayer insulating film 127 Gate electrode 201 Chamber 203 Heating element 204 Quartz tube 205 Inner wall surface 206 Stages 207 Gas inlet 208 Gas exhaust port 209 Rotational Axis 210 Holder 231 First Gas Supply Unit 232 Second gas supply unit 233 Third Gas Supply Section 234 4th Gas Supply Section 235 Gas Supply Section 241 First gas flow control section 242 Second gas flow control section 243 Third gas flow control section 244 Fourth gas flow control section 245 Control Unit 250 Manufacturing equipment 300 Silicon carbide semiconductor device A1 1st position A2 2nd position A3 3rd position A4, Position 4 A5 Center A6, Position 6 B1 Concentration of the first impurity B2 Concentration of the second impurity B3 Concentration of the third impurity B4 Concentration of the 4th Impurity B5 Concentration of the 5th Impurity B6 Concentration of the 6th Impurity C1 First straight line C2, second straight line R1, Domain 1 R2, Second Domain R3, Third Domain R4, 4th Domain W1 Maximum Diameter

Claims

1. a silicon carbide substrate; a silicon carbide epitaxial layer on the silicon carbide substrate, the silicon carbide epitaxial layer includes a main surface, the main surface is formed by an outer peripheral region within 5 mm from the outer peripheral edge and a central region surrounded by the outer peripheral region, a silicon carbide epitaxial substrate, wherein in the central region, the maximum rate of increase of the impurity concentration in the <1-100> direction is smaller than the maximum rate of increase of the impurity concentration in the <11-20> direction;

2. In the central region, the maximum rate of increase in the impurity concentration in the <1-100> direction is 3% cm -1 The silicon carbide epitaxial substrate of claim 1 , wherein the thickness of the silicon carbide epitaxial substrate is less than 100 μm.

3. In the central region, the maximum rate of increase in the impurity concentration in the <11-20> direction is 3% cm -1 3. The silicon carbide epitaxial substrate according to claim 1 or 2.

4. a silicon carbide substrate; a silicon carbide epitaxial layer on the silicon carbide substrate, the silicon carbide epitaxial substrate is provided with an orientation flat or a notch; the silicon carbide epitaxial layer includes a main surface, the main surface is formed by an outer peripheral region within 5 mm from the outer peripheral edge and a central region surrounded by the outer peripheral region, When viewed in a direction from the silicon carbide epitaxial layer toward the silicon carbide substrate, a direction from the center of the main surface toward the orientation flat or the notch is defined as a first direction, and a direction perpendicular to the first direction is defined as a second direction. a silicon carbide epitaxial substrate, wherein in the central region, a maximum value of a rate of increase of the impurity concentration in the first direction is smaller than a maximum value of a rate of increase of the impurity concentration in the second direction.

5. In the central region, the maximum rate of increase of the impurity concentration in the first direction is 3% cm -1 The silicon carbide epitaxial substrate of claim 4 , wherein the thickness of the silicon carbide epitaxial substrate is less than 100 μm.

6. In the central region, the maximum rate of increase of the impurity concentration in the second direction is 3% cm -1 6. The silicon carbide epitaxial substrate according to claim 4 or 5.

7. In the central region, the maximum rate of increase of the impurity concentration in the second direction is 1.5% cm -1 The silicon carbide epitaxial substrate according to claim 6 .

8. a straight line that is parallel to the second direction and passes through the center when viewed in a direction from the silicon carbide epitaxial layer toward the silicon carbide substrate intersects with each of a first position and a second position; each of the first position and the second position is located on a boundary line between the outer circumferential region and the central region; 6. The silicon carbide epitaxial substrate according to claim 4, wherein a maximum value of a rate of increase of the impurity concentration in a first region between the center and the first position is greater than a maximum value of a rate of increase of the impurity concentration in a second region between the center and the second position.

9. The maximum rate of increase of the impurity concentration in the first region is 3% cm -1 The silicon carbide epitaxial substrate according to claim 8 .

10. The maximum rate of increase of the impurity concentration in the second region is 3% cm -1 The silicon carbide epitaxial substrate of claim 8 , wherein the thickness of the silicon carbide epitaxial substrate is less than 100 μm.

11. 9. The silicon carbide epitaxial substrate according to claim 8, wherein the impurity concentration is an n-type impurity concentration.

12. A step of preparing a silicon carbide epitaxial substrate according to any one of claims 1 to 5; and forming an electrode on the silicon carbide epitaxial substrate.

13. a silicon carbide substrate; a silicon carbide epitaxial layer on the silicon carbide substrate; an electrode on the silicon carbide epitaxial layer; a silicon carbide semiconductor device, wherein in a main surface of the silicon carbide epitaxial layer, a maximum rate of increase of the impurity concentration in a <1-100> direction is smaller than a maximum rate of increase of the impurity concentration in a <11-20> direction;

14. On the main surface, the maximum rate of increase of the impurity concentration in the <1-100> direction is 3% cm -1 The silicon carbide semiconductor device of claim 13 , wherein the thickness of the silicon carbide semiconductor device is less than 100 μm.

15. On the main surface, the maximum rate of increase of the impurity concentration in the <11-20> direction is 3% cm -1 The silicon carbide semiconductor device according to claim 13 or 14.

16. 15. The silicon carbide semiconductor device according to claim 13, wherein the impurity concentration is an n-type impurity concentration.

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