Gaming machine

Abstract

To provide a game machine having a circuit configuration capable of preventing an abnormal image performance.SOLUTION: If no response is received from a READ access request to the memory element 55 after a predetermined monitoring time, an initialization command for re-establishing communication with the memory element 55 is automatically effected in the image generation means.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a gaming machine that performs a lottery process based on gaming actions and executes image effects corresponding to the lottery results, and more particularly to a gaming machine that can stably execute powerful image effects. [Background technology]

[0002] A pinball game machine such as a pachinko machine is configured with a symbol start opening on the game board, a symbol display unit that displays a series of symbol changes based on multiple displayed symbols, and a jackpot opening with an opening / closing plate. When a detection switch on the symbol start opening detects the passage of a game ball, the machine enters a winning state. After the game ball is paid out as a prize ball, the displayed symbols on the symbol display unit change for a predetermined period of time. When the symbols then stop in a predetermined pattern, such as 7-7-7, the machine enters a jackpot state, and the jackpot opening is repeatedly opened, creating a game state advantageous to the player.

[0003] Whether or not such a game state occurs is determined by a jackpot lottery, which is executed on the condition that a gaming ball enters the symbol start slot, and the above-mentioned symbol variation action is based on the result of this lottery. For example, if the lottery result is a winning state, a presentation action called a reach action is executed for about 20 seconds, and then special symbols are aligned. On the other hand, a similar reach action may be executed even in a losing state, and in this case, the player will closely watch the progression of the presentation action while strongly hoping for a jackpot state. Then, if the predetermined symbol is aligned on the stop line at the end of the symbol variation action, the player is guaranteed a jackpot state. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-040883 [Patent Document 2] Japanese Patent Publication No. 2020-065707 [Patent Document 3] Japanese Patent Publication No. 2020-022673 Summary of the Invention [Problem to be solved by the invention]

[0005] In this type of gaming machine, it is desirable to make the various effects more complex and abundant, and there is a particularly high demand for image effects. Therefore, the applicant has made various proposals (References 1 to 3), but further advances in image effects and improvements in image effect control are desired. Specifically, a circuit configuration that can prevent abnormal image effects is required, and simplification of the image effect circuit and stable access operation of image data are also desired.

[0006] The present invention has been made in consideration of the above-mentioned problems, and aims to provide a gaming machine capable of executing improved image presentation control. [Means for solving the problem]

[0007] In order to achieve the above-mentioned object, the gaming machine of the present invention is configured to have an image control means for issuing a display list that specifies the display screen of a display device, an image generation means for receiving the display list and outputting specified image data to the display device, and a memory element that stores data necessary for the operation of the image control means and is accessed for READ by the image generation means, and is configured so that if no response is received after a specified monitoring time has elapsed since a READ access request to the memory element, an initialization command for re-establishing (typically initializing) communication with the memory element is automatically executed in the image generation means.

[0008] Preferably, the boot program, the game control program, and all or part of the various data are stored in the memory element after being obfuscated. Here, obfuscation refers to encryption processing that cannot be restored to its original state (usable state) without relying on one or more unique pieces of data (scrambling processing). In the embodiment, decryption is possible based on a decryption key and a user ID (descrambling processing). The unique decryption key and user ID are preferably each kept private, and in the embodiment, are set by the chip manufacturer and made public to the gaming machine manufacturer. [Effects of the Invention]

[0009] According to the present invention described above, it is possible to execute image control operations smoothly and appropriately, such as by appropriately executing initialization commands. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a perspective view showing a pachinko machine according to an embodiment of the present invention; [Figure 2] 2 is a front view showing the gaming area of ​​the gaming machine of FIG. 1. [Figure 3] FIG. 2 is a block diagram showing the overall circuit configuration of the gaming machine of FIG. 1. [Figure 4] This diagram illustrates the internal configuration of the performance interface board, performance control board, and liquid crystal interface board. [Figure 5] FIG. 1 is a circuit block diagram illustrating a composite chip including its associated circuit elements. [Figure 6] FIG. 10 is a block diagram illustrating the connection relationship between an external memory and a watchdog timer and a combined chip. [Figure 7] 1 is a diagram illustrating an index space and a virtual drawing space. [Figure 8] 1 is a diagram illustrating a display circuit. [Figure 9] 1 is a diagram illustrating an internal configuration of a data transfer circuit. [Figure 10]10 is a diagram for explaining the transfer operation of a display list and a voice command list. [Figure 11] 10 is a diagram illustrating a filter process based on a display list. [Figure 12] 1 is a diagram illustrating a procedure for playing back IPB streaming video. [Figure 13] 1 is a diagram illustrating the internal configuration and control procedure of an audio processing unit. [Figure 14] 10 is a diagram for explaining a drawing pipeline process of a drawing circuit. [Figure 15] FIG. 1 is a process diagram illustrating various rendering modes that utilize all or part of the rendering pipeline steps. [Figure 16] 10 is a flowchart illustrating an operation inside the composite chip at the time of power-on reset. [Figure 17] 17 is a diagram illustrating a portion of FIG. 16 in more detail. [Figure 18] 10 is a flowchart illustrating the control operation of a performance control CPU that does not include a preload operation. [Figure 19] 19 is a flowchart illustrating a part of FIG. 18. [Figure 20] 10 is a flowchart illustrating the control operation of the performance control CPU, including the preload operation. DETAILED DESCRIPTION OF THE INVENTION

[0011] The present invention will be described in detail below with reference to the following embodiments. FIG. 1 is a perspective view of a pachinko machine GM according to this embodiment. This pachinko machine GM is composed of a rectangular wooden outer frame 1 that is detachably attached to an island structure, and an inner frame 3 that is pivotally attached so as to be able to open and close via hinges 2 fixed to the outer frame 1. A game board 5 is detachably attached to the inner frame 3 from the front side, not the back side, and a glass door 6 and a front panel 7 are pivotally attached to the front side so as to be able to open and close. In this specification, the glass door 6 and the front panel 7 are collectively referred to as the "front door member." The inner frame 3 to which the front door member (glass door 6 and front panel 7) is pivotally attached may also be referred to as the "game frame."

[0012] Illuminated lamps such as LED lamps are arranged in a roughly C-shape around the periphery of the glass door 6. Meanwhile, a total of three speakers are arranged on the upper left and right sides and on the lower side of the glass door 6. The two upper speakers output audio for the left and right channels R and L, respectively, and the lower speaker is configured to output low-pitched sounds.

[0013] An upper tray 8 for storing game balls to be launched is attached to the front panel 7, and a lower tray 9 for storing game balls that have spilled over or been removed from the upper tray 8, and a launch handle 10 are provided at the bottom of the inner frame 3. The launch handle 10 is linked to a launch motor, and the game balls are launched by a striking hammer that operates according to the rotation angle of the launch handle 10.

[0014] A chance button 11 is provided on the outer periphery of the upper tray 8. This chance button 11 is provided in a position where it can be operated by the player's left hand, and the player can operate the chance button 11 without taking his / her right hand off the launch handle 10. This chance button 11 is normally inactive, but when the game state is in the button chance state, a built-in lamp lights up and the button becomes operable. The button chance state is a game state that is set as needed.

[0015] In addition, a rotary switch-type volume switch VLSW is located below the chance button 11, and by operating the volume switch VLSW, the player can adjust the speaker volume in eight stages, from silent (=0) to the highest level (=7). The speaker volume is initially set by a setting switch (not shown) that can only be operated by an attendant, and the initial setting volume is maintained unless the player operates the volume switch VLSW. In addition, the abnormality alert sound that notifies the occurrence of an abnormal situation is emitted at the maximum volume, regardless of the volume initially set by the attendant or the volume set by the player.

[0016] On the right side of the upper tray 8, there is provided an operation panel 12 for operating the ball lending operation for the card-type ball lending machine, which is provided with a degree display section that displays the remaining balance on the card in three digits, a ball lending switch that commands the lending of game balls for a specified amount, and a return switch that commands the return of the card when the game ends.

[0017] As shown in Figure 2, a guide rail 13 consisting of an outer and inner metal rail is provided in a ring shape on the surface of the game board 5, and a central opening HO is provided in approximately the center of the guide rail 13. A movable effect body (not shown) is stored in a concealed state below the central opening HO, and during the movable preview effect, the movable effect body rises and becomes exposed, thereby realizing a preview effect with a predetermined reliability. Here, the preview effect is an effect that uncertainly notifies the player that a favorable jackpot state will occur, and the reliability of the preview effect means the probability that the jackpot state will occur.

[0018] A display device DS consisting of a large (for example, 1280 horizontal x 1024 vertical pixels) liquid crystal color display is disposed in the central opening HO. The display device DS is composed of a main liquid crystal display section MONI and an LED backlight section BL, and is a device that variably displays specific symbols related to the jackpot state, as well as animated background images and various characters. This display device DS has special symbol display sections Da-Dc in the center and a normal symbol display section 19 in the upper right corner. The special symbol display sections Da-Dc may execute reach effects that raise expectations for the arrival of a jackpot state, and appropriate preview effects are executed in and around the special symbol display sections Da-Dc.

[0019] The game area where the game balls fall and move is provided with a first symbol start opening 15a, a second symbol start opening 15b, a first big prize opening 16a, a second big prize opening 16b, a normal prize opening 17, and a gate 18. Each of these winning openings 15 to 18 has a detection switch inside, so that it can detect the passage of the game balls.

[0020] Above the first symbol start opening 15a, there is arranged a performance stage 14 configured so that the gaming ball that has entered from the introduction opening IN can move in a seesaw or roulette shape and then enter the first symbol start opening 15. When the gaming ball enters the first symbol start opening 15, the variable operation of the special symbol display sections Da to Dc is started.

[0021] The second pattern starting port 15b is configured to be opened and closed by an electric tulip equipped with a pair of opening and closing claws on the left and right, and when the stopped pattern after the normal pattern display section 19 changes displays a winning pattern, the opening and closing claws are opened for a predetermined time or until a predetermined number of game balls are detected.

[0022] The normal symbol display unit 19 displays normal symbols, and when a gaming ball that has passed through the gate 18 is detected, the normal symbol changes for a predetermined period of time and stops by displaying a stopping symbol determined by a random number value for lottery that is extracted at the time the gaming ball passes through the gate 18.

[0023] The first large prize opening 16a is configured with a slide plate that moves back and forth, and the second large prize opening 16b is configured with an opening / closing plate whose lower end is supported by a shaft and opens forward. The operation of the first large prize opening 16a and the second large prize opening 16b is not particularly limited, but in this embodiment, the first large prize opening 16a is configured to correspond to the first symbol starting opening 15a, and the second large prize opening 16b is configured to correspond to the first symbol starting opening 15b.

[0024] In other words, when a game ball enters the first pattern start port 15a, the special pattern display sections Da to Dc begin to change, and then when a predetermined jackpot pattern is aligned in the special pattern display sections Da to Dc, a special game representing the first jackpot begins, and the slide plate of the first jackpot entry port 16a opens forward, making it easier for the game ball to enter.

[0025] On the other hand, as a result of the varying operation initiated by the entry of a gaming ball into the second symbol start opening 15b, when a predetermined jackpot symbol is aligned in the special symbol display sections Da to Dc, a special game representing a second jackpot is initiated, and the opening and closing plate of the second large winning opening 16b is opened to facilitate the entry of the gaming ball. The gaming value of the special game (jackpot state) varies depending on the aligned jackpot symbols, etc., but which gaming value is awarded is determined in advance based on the result of a lottery according to the timing of the entry of the gaming ball.

[0026] In a typical jackpot state, after the opening / closing plate of the jackpot opening 16 is opened, the opening / closing plate closes after a predetermined time has elapsed or when a predetermined number of game balls (for example, 10 balls) have entered. This operation may continue up to, for example, 15 times, and is controlled to be advantageous to the player. If the stopped symbol after the change of the special symbol display sections Da to Dc is a specific symbol among the special symbols, a special benefit is given in which the game after the special game ends will be in a high probability state (probability variable state).

[0027] Fig. 3(a) is a block diagram showing the overall circuit configuration of the pachinko machine GM that realizes the above-mentioned operations. Fig. 3(b) is a circuit diagram showing the circuit configuration of the power supply monitor unit MNT arranged on the payout control board 25. As shown in Figure 3(a), this pachinko machine GM is mainly composed of a power supply board 20 that receives AC 24V and outputs various DC voltages (35V, 12V, 5V) together with AC 24V, a main control board 21 that is responsible for central and overall game control operations, a presentation interface board 22 that is equipped with a digital amplifier 29 for sound presentation, etc., a presentation control board 23 that executes lamp presentations, sound presentations, and image presentations in a unified manner based on control commands CMD received from the main control board 21, a liquid crystal interface board 24 located between the presentation control board 23 and the display device DS, a payout control board 25 that controls the payout motor M based on control commands CMD' received from the main control board 21 to pay out game balls, and a launch control board 26 that launches game balls in response to player operations.

[0028] Figure 4 is a slightly more detailed illustration of a portion of Figure 3(a), and shows the internal configuration of the performance interface board 22, performance control board 23, and LCD interface board 24. As shown in Figures 4 and 3(a), the performance interface board 22, performance control board 23, and LCD interface board 24 are directly connected via male and female connectors without using wiring cables. This makes it possible to minimize the storage space for the entire board even if the circuit configuration of each electronic circuit is made complex and advanced, and by shortening the connection lines, noise resistance can be improved.

[0029] As shown in Figure 3(a), the control command CMD' output by the main control board 21 is transmitted to the dispensing control board 25. On the other hand, the control command CMD output by the main control board 21 is transmitted to the performance control board 23 via the performance interface board 22. Here, the control commands CMD and CMD' are both 16 bits long, but are sent in parallel twice, each 8 bits long.

[0030] The main control board 21 and the payout control board 25 are equipped with computer circuits including a one-chip microcomputer. The performance control board 23 is equipped with a composite chip 50 incorporating computer circuits such as an overall performance circuit 52 and an internal CPU circuit 51. Therefore, in this specification, the main control unit 21, the performance control unit 23, and the payout control unit 25 are sometimes referred to functionally as the control boards 21, 25, and 23, the circuits mounted on the performance interface board 22, and the LCD interface board 24, and the operations realized by these circuits. The performance control unit 23 and the payout control unit 25 are sub-control units relative to the main control unit 21.

[0031] This pachinko machine GM is broadly divided into a frame side member GM1 surrounded by a dashed line in Figure 3(a) and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes an inner frame 3 to which a glass door 6 and a front panel 7 are pivotally attached, and an outer wooden frame 1 outside of that, and is installed in a fixed position in the game hall for a long period of time regardless of changes in the model. On the other hand, the board side member GM2 is replaced in response to a model change, and a new board side member GM2 is attached to the frame side member GM1 in place of the original board side member. All parts except the frame side member GM1 are board side members GM2.

[0032] As shown in the dashed-line frame in Figure 3(a), the frame-side member GM1 includes a power supply board 20, a backup power supply board 33, a payout control board 25, a launch control board 26, a frame relay board 36, and a motor / lamp drive board 37, and these circuit boards are each fixed in appropriate locations on the inner frame 3. Meanwhile, a main control board 21 and a performance control board 23 are fixed to the back of the gaming board 5, along with a display device DS and other circuit boards. The frame-side member GM1 and the board-side member GM2 are electrically connected by centralized connectors C1 to C3, which are centrally located in one place.

[0033] The power supply board 20 generates three types of DC voltages (35V, 12V, 5V) based on the AC voltage AC24V distributed from the gaming hall, and distributes each DC voltage to the performance interface board 22 via the centralized connection connector C2. The three types of DC voltages (35V, 12V, 5V) are distributed to the payout control board 25 together with the AC voltage AC24V. The DC voltages (35V, 12V, 5V) distributed to the payout control board 25 are then distributed to the main control board 21 together with the backup power supply BAK via the centralized connection connector C1.

[0034] The DC 35V is used to drive the ball-feeding solenoid and launch solenoid involved in the launching of gaming balls, and to drive the electromagnetic solenoids that open and close the electric tulip (variable winning device) and the large winning slot 16. The DC 12V is used to drive the LED lamps and motors controlled by each control board, and as the power supply voltage for the digital amplifier, while the DC 5V is used as the power supply voltage for the one-chip microcomputers on the payout control board 25 and main control board 21, and for the logic elements mounted on each control board. The DC 5V is stepped down by the DC / DC converters on the performance interface board 22 and performance control board 23, and the stepped down voltages at various levels are then used as the power supply voltage for various computer circuits (such as the composite chip 50).

[0035] The backup power supply BAK is a DC 5V power supply for maintaining the data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25 after the power is cut off, and is realized by, for example, an electric double layer capacitor. In this embodiment, a dedicated backup power supply board 33 is provided, and the electric double layer capacitor arranged on the backup power supply board 33 is configured to be charged by the DC voltage of 5V received from the payout control board 25 during game operation.

[0036] On the other hand, after the power is cut off, the backup power supply BAK retains the data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25, so that the main control unit 21 and the payout control unit 25 can resume the gaming operation before the power was cut off after the power is turned on. The backup power supply board 33 is equipped with an electric double layer capacitor that can retain the memory contents of the built-in RAM of each one-chip microcomputer for at least several days.

[0037] In this embodiment, the power supply abnormality signal ABN, which indicates an abnormal drop in the AC voltage AC24V, is generated not by the power supply board 20 but by the power supply monitor unit MNT of the dispensing control board 25. As shown in FIG. 3(b), the power supply monitor unit MNT includes a full-wave rectifier circuit that rectifies the AC24V received from the power supply board 20, a photodiode D that receives the output of the full-wave rectifier circuit and emits light, a phototransistor TR that is powered by the DC voltage 5V received from the power supply board 20 and turns ON based on the light emitted by the photodiode D, and an output unit that outputs an H-level detection signal ABN (power supply abnormality signal) based on the ON state of the phototransistor TR. The photodiode D and phototransistor TR together form a photocoupler PH.

[0038] In the above configuration, after power is turned on, the photocoupler PH quickly switches to the ON state, causing the power supply abnormality signal ABN to go to a normal level (H). However, if the AC power subsequently drops abnormally for some reason (normally due to a power outage), the photocoupler PH switches to the OFF state, causing the power supply abnormality signal ABN to go to an abnormal level (L). This power supply abnormality signal ABN is transmitted to the one-chip microcomputer on the payout control board 25 and also to the one-chip microcomputer on the main control board 21 via the centralized connection connector C1. Therefore, each one-chip microcomputer that receives the abnormal-level power supply abnormality signal ABN executes a backup process to store necessary information in its own internal RAM. As explained above, the information in the internal RAM is maintained by the backup power supply BAK, allowing game operation to resume as it was before the power was turned off after power is turned on.

[0039] As shown in Figures 3(a) and 4, the performance interface board 22 is equipped with a reset circuit RST3 and a digital amplifier 29 (AMP), the performance control board 23 is equipped with a composite chip 50 that has built-in computer circuits such as a general performance circuit 52 and an internal CPU circuit 51, and the LCD interface board 24 is equipped with a clock circuit 38 (RTC), a performance data memory 39 (SRAM) that stores performance data, and a power supply control circuit SPY.

[0040] In this embodiment, the integrated effect circuit 52 built into the composite chip 50 includes a video display processor (VDP), an audio processor (SND), a motor controller MT_CTL, and a lamp controller L_CTL. Based on control from the built-in CPU circuit 51, the integrated effect circuit 52 operates intermittently with an operating period δ (= 1 / 30 seconds) to execute image effects using the display device DS, audio effects that drive speakers via the digital amplifier 29, motor effects that rotate effect motors M1 to Mn to move props, and lamp effects that flash LED lamps, etc. In the following description, the built-in CPU circuit 51 may be abbreviated as the CPU circuit 51.

[0041] When power is turned on, the reset circuit RST3 generates a power reset signal based on the rise in the power supply voltage of 5V received from the power supply circuit 20, and resets the power supply to the internal circuits and other electronic elements of the composite chip 50. As explained above, the internal circuits of the composite chip 50 include a video display processor (VDP) and an audio processor (SND), and the power reset signal is nothing other than the system reset signal HRESET of the composite chip 50, and synchronously resets the power supply to the CPU circuit 51 and the overall performance circuit 52.

[0042] In this embodiment, during the L assertion period of the system reset signal HRESET, all internal circuits are uniformly initialized, and default values ​​are set in the performance control register RGij of the composite chip 50. After that, when the system reset signal HRESET transitions to H level, a boot program described later based on Fig. 19 is started, and the necessary initial setting operations are performed on the performance control register RGij. On the other hand, when the DC voltage of 5V drops (usually when the power is cut off), the system reset signal HRESET drops to L level, so that the CPU circuit 51 and the overall performance circuit 52 of the performance control board 23 are put into a stopped state.

[0043] As will be described later, this embodiment is configured so that the system reset signal HRESET does not change even when the WDT (Watch Dog Timer) circuit 58 is activated, and so not all internal circuits are initialized uniformly even in the event of an abnormality that activates the WDT 58. In other words, this embodiment is configured so that arbitrarily selected predetermined internal circuits are initialized.

[0044] Next, the clock circuit 38 and effect data memory 39 mounted on the liquid crystal interface board 24 are driven by a secondary battery (not shown), and this secondary battery is charged appropriately during game operation by the power supply voltage from the power supply board 20. Therefore, even after the power is cut off, the timekeeping operation of the clock circuit 38 continues, and the game performance information stored in the effect data memory 39 is permanently stored and held (non-volatile).

[0045] The clock circuit 38 is configured to be able to output an interrupt signal (RTC interrupt) to the CPU circuit 51. This RTC interrupt includes an alarm interrupt that can specify the date, day of the week, hour, minute, and second, and a timer interrupt that is activated after a predetermined time has elapsed, but in this embodiment, an alarm interrupt IRQ_RTC is used that updates the daily gaming performance information at the end of business each day.

[0046] As shown in Figure 3(a), the payout control board 25 and the main control unit 21 are each equipped with reset circuits RST1 and RST2, and are configured so that when the power is turned on, a power reset signal is generated and the power to each computer circuit is reset. In this way, in this embodiment, the main control unit 21, the payout control unit 25, and the performance interface board 22 are each equipped with reset circuits RST1 to RST3, and for example, a system reset signal generated by the power supply board 20 is not transmitted between circuit boards. In other words, since there is no wiring cable to transmit the system reset signal, the risk of the computer circuit being abnormally reset by noise superimposed on the wiring cable is eliminated.

[0047] However, the reset circuits RST1 and RST2 provided in the main control unit 21 and the dispensing control unit 25 each incorporate a watchdog timer, and if they do not receive a regular clear pulse from the CPU of each control unit 21, 25, the CPU is forcibly reset. The main control unit 21 is also provided with an initialization switch SW that can be operated by an attendant, and is configured to output a RAM clear signal CLR indicating whether the initialization switch SW has been turned ON when the power is turned on. This RAM clear signal CLR is transmitted to the one-chip microcomputers of the main control unit 21 and the dispensing control unit 25, and determines whether or not to initialize the entire RAM area of ​​the one-chip microcomputer of each control unit 21, 25.

[0048] As shown in Figure 3(a), the main control unit 21 receives from the payout control unit 25 a prize ball count signal indicating the payout operation of game balls, a status signal CON relating to abnormalities in the payout operation, and an operation start signal BGN. The status signal CON includes, for example, a supply shortage signal, a payout shortage error signal, and a lower tray full signal. The operation start signal BGN is a signal that notifies the main control unit 21 that the initial operation of the payout control unit 25 has been completed after power is turned on.

[0049] The main control unit 21 also receives switch signals from the detection switches built into each winning slot 16-18 on the gaming board, while driving solenoids such as electric tulips. The solenoids and detection switches are configured to operate on the power supply voltage VB (12V) distributed from the main control unit 21. Furthermore, each switch signal indicating the winning status of the symbol start slot 15 is converted into a TTL level or CMOS level switch signal by an interface IC that operates on the power supply voltage VB (12V) and the power supply voltage Vcc (5V), and then transmitted to the main control unit 21.

[0050] As explained above, the performance interface board 22 receives various levels of DC voltage (5V, 12V, 35V) from the power supply board 20 via the centralized connector C2 (see Figures 3(a) and 4). The 12V DC voltage is the power supply voltage for the digital amplifier 29 and is also used as a drive voltage for LED lamps and the like. The 35V DC voltage is distributed to appropriate locations in the game frame and is used as a drive voltage for solenoids that move movable objects back and forth.

[0051] Meanwhile, the 5V DC voltage is supplied as a power supply voltage to the circuit elements in various parts of the performance interface board 22, and is also supplied to the DC / DC converter DC to generate 3.3V (see Figure 4). The generated 3.3V DC voltage becomes the base voltage for the power reset signal (system reset signal) HRESET generated by the reset circuit RST3. The 5V DC voltage distributed to the performance interface board 22 is also distributed to the performance control board 23 together with the 3.3V generated by the DC / DC converter DC. The 3.3V DC voltage distributed to the performance control board 23 is then supplied as a power supply voltage to the composite chip 50 and external memory 55.

[0052] 4, two DC / DC converters DC1 and DC2 are arranged on the performance control board 23, and generate 1.5V and 1.05V based on the DC voltage of 5V supplied to each of them. Here, the DC voltage of 1.05V is the power supply voltage for the chip core of the composite chip 50, and the DC voltage of 1.5V is the power supply voltage for I / O (input / output) with the VRAM 53 and the expansion RAM 54. Therefore, the DC voltage of 1.5V is also supplied to the VRAM 53 and the expansion RAM 54 as a power supply voltage.

[0053] As shown in Figure 3(a), the performance interface board 22 receives a control command CMD and a strobe signal STB from the main control unit 21 and transfers them to the performance control board 23. More specifically, as shown in Figure 4, the control command CMD and strobe signal STB are transferred to the composite chip 50 (CPU circuit 51) of the performance control board 23 via an input buffer 40. Here, the strobe signal STB is a received interrupt signal IRQ_CMD, and the performance control CPU 57 acquires the control command CMD based on an interrupt processing program (interrupt handler) that is started in response to the received interrupt signal IRQ_CMD.

[0054] 4, the input buffer 44 of the performance interface board 22 receives switch signals from the chance button 11 and the volume switch VLSW from the frame relay board 36, and transmits each switch signal to the CPU circuit 51 of the performance control board 23. Specifically, it transmits to the CPU circuit 51 a 3-bit length of the encoder output indicating the contact position (0 to 7) of the volume switch VLSW, and a 1-bit length indicating the ON / OFF state of the chance button 11.

[0055] Furthermore, the performance interface board 22 is connected to the lamp drive board 30 and the motor lamp drive board 31, and is also connected to the lamp drive board 37 via the frame relay board 36. As shown in the figure, an output buffer 42 is arranged corresponding to the lamp drive board 30, and an input buffer 43a and an output buffer 43b are arranged corresponding to the motor lamp drive board 31. For convenience, in FIG. 4, the input buffer 43a and the output buffer 43b are collectively referred to as the input / output buffer 43. The input buffer 43a receives outputs SN0 to SNn from origin sensors that grasp the current positions of the movable performance objects (the rotational positions of the performance motors M1 to Mn), and transmits these to the motor control unit MT_CTL of the performance control board 23.

[0056] The lamp drive board 30, motor lamp drive board 31, and lamp drive board 37 are equipped with the same type of driver IC, and the performance interface board 22 transfers to each driver IC serial signals received from the lamp control unit L_CTL and motor control unit MT_CTL of the performance control board 23. Specifically, the serial signals are lamp (motor) drive signal SDATA and clock signal CK, and the drive signal SDATA is transmitted to each driver IC in a clock synchronization system, executing lamp performances using numerous LED lamps and electric lamps, and role-play performances using performance motors M1 to Mn.

[0057] In this embodiment, the lamp effects are performed by three systems of lamp groups CH0 to CH2, and the driver IC of the lamp drive board 37 receives the lamp drive signal SDATA0 for CH0 output by the lamp control unit L_CTL in synchronization with the clock signal CK0 via the frame relay board 36. The series of lamp drive signals SDATA0 transmitted as serial signals are output from the driver IC to the lamp group CH0 at the timing when the operation control signal ENABLE0 output from the CPU circuit 51 (PIO 62) changes to the active level, thereby updating the lighting status of the lamp group CH0 all at once.

[0058] The same applies to the lamp drive board 30, and the driver IC of the lamp drive board 30 receives the lamp drive signal SDATA1 for the lamp group CH1 output from the lamp control unit L_CTL in synchronization with the clock signal CK1. Then, when the operation control signal ENABLE1 output from the CPU circuit 51 (actually, PIO 62) changes to the active level, the lighting states of the lamp group CH1 are updated all at once.

[0059] Meanwhile, the driver IC mounted on the motor lamp drive board 31 receives a lamp drive signal transmitted in clock synchronization from the motor control unit MT_CTL to drive the lamp group CH2, and also receives a motor drive signal transmitted in clock synchronization to drive the performance motor group M1-Mn, which is made up of multiple stepping motors. Because the lamp drive signal and the motor drive signal are the same type of serial signal, a series of composite serial signals SDATA2 is output from the motor control unit MT_CTL in synchronization with the clock signal CK2, and the driver IC that receives this updates the drive status of the lamp group CH2 and the motor group M1-Mn when the operation control signal ENABLE2 changes to the active level.

[0060] In this embodiment, for convenience, the motor control unit MT_CTL is in charge of the motor and lamp effects for the motor lamp drive board 31, and therefore the operation control signal ENABLE2 is also output from the motor control unit MT_CTL. Note that the lamp drive signals SDATA0 and SDATA1 for the lamp drive board 37 and the lamp drive board 30 may also be configured to be output from the motor control unit MT_CTL.

[0061] 4, the data bus and address bus of the CPU circuit 51 of the performance control unit 23 extend to the clock circuit (Real Time Clock) 38 and performance data memory 39 mounted on the liquid crystal interface board 24. The clock circuit 38 is connected to the lower 4 bits of the address bus and the lower 4 bits of the data bus of the CPU circuit 51, and is configured so that when the clock circuit 38 is chip-selected by a chip select signal, the CPU circuit 51 can arbitrarily access the internal registers (which have 4-bit address values).

[0062] In addition, the performance data memory 39 is a high-speed accessible memory element SRAM (Static Random Access Memory), and is connected to 16 bits of the address bus of the CPU circuit 51 and the lower 16 bits of the data bus.When the chip is selected, the game performance information and other data stored in the SRAM (performance data memory) 39 can be accessed by the CPU circuit 51 via R / W as appropriate.

[0063] Furthermore, a power supply control circuit SPY that controls the power supply to the display device DS and the backlight board BL is mounted on the liquid crystal interface board 24. Specifically, the power supply control circuit SPY controls the start timing of supplying power supply voltages of 12V and 5V to the display device DS and the backlight board BL using a control signal STBY, and controls the brightness of the backlight light and the start timing of light emission using a control signal PWM.

[0064] As shown on the right side of Figure 4, the performance control board 23 is equipped with a composite chip 50 that incorporates a CPU circuit 51 and an overall performance circuit 52, a VRAM 53 that is accessed via R / W at high speed from the CPU circuit 51 and the overall performance circuit 52, an expansion RAM 54 that can store large amounts of data, an external memory 55 that stores CG data and other data in a non-volatile manner, and a watchdog timer 56 that initializes the external memory 55 when it is operating abnormally.

[0065] The VRAM 53 is capable of high-speed access with a theoretical transfer rate of approximately 102 GB / s and has a storage capacity of approximately 48 MB. The VRAM 53 is primarily used (1) to store reference data for the display circuit 71, drawing circuit 74, and GDEC circuit 73 (see FIG. 5(a)). It can also (2) store copies of data in the external memory 55, and (3) be used as a work area for the CPU circuit 51.

[0066] The expansion RAM 54 can operate at a theoretical transfer rate of approximately 17.0 GB / sec, has a storage capacity of approximately 1 GB, and can be used in the same manner as the VRAM 53. That is, the expansion RAM 54 can (1) store reference data for the display circuit 71, drawing circuit 74, and GDEC circuit 73, (2) store copies of data in the external memory 55, and (3) be used as a work area for the CPU circuit 51.

[0067] A portion of the data in the external memory 55 is configured to be transferred to the extended RAM 54 when the power is turned on. Specifically, the control program and various control data that cause the CPU circuit 51 to function are transferred and copied from the external memory 55 to the extended RAM 54 by a boot program stored in the external memory 55 when the power is turned on. This point will be described further below.

[0068] 5(a) is a circuit block diagram illustrating the composite chip 50 that constitutes the performance control unit 23, including its associated circuit elements. As shown in the figure, the composite chip 50 of the embodiment includes a CPU circuit 51 that issues a display list DL and a voice command list VC, and an overall performance circuit 52 that executes image performances based on the display list DL, executes voice performances based on the voice command list VC, and executes lamp and motor performances. The CPU circuit 51 and the overall performance circuit 52 are connected via a CPU bus unit 56 that relays data sent and received between them.

[0069] First, we will explain the CPU bus unit 56 located between the CPU circuit 51 and the overall performance circuit 52. As shown in Figure 5(a), the CPU bus unit 56 is connected to the VRAM 53, the extended RAM 54, and the external memory 55 via the VRAM IF unit 53a, the extended RAM IF unit 54a, and the CG bus IF unit 55a. Therefore, in this embodiment, the VRAM 53, the extended RAM 54, and the external memory 55 can be accessed not only by the overall performance circuit 52 but also by the CPU circuit 51.

[0070] The VRAM I / F unit 53a, the extended RAM I / F unit 54a, and the CG bus I / F unit 55a are connected to the VRAM 53, the extended RAM 54, and the external memory 55 via an arbitration circuit ICM (Inter Connect Module) not shown. The arbitration circuit ICM is located between each functional block of the overall performance circuit 52 and the VRAM I / F unit 53a, the extended RAM I / F unit 54a, and the CG bus I / F unit 55a, and arbitrates data requests issued by each functional block as appropriate to establish the required connection relationships.

[0071] In any case, the CPU circuit 51 of this embodiment can access the VRAM 53, the expansion RAM 54, and the external memory 55. However, after the CPU circuit 51 transfers and copies the control program and control data from the external memory 55 to the expansion RAM 54 when the power is turned on, it does not access the external memory 55. In other words, after the copy operation, the CPU circuit 51 executes control operations based on the control program and control data copied to the expansion RAM 54.

[0072] 6A is a circuit diagram showing the connection relationship between the external memory 55, the combined chip 50, and the watchdog timer 56. The external memory 55 in this embodiment is a Serial ATA (SATA) module compliant with Serial ATA Revision 3.3, and specifically, is configured as an SSD (Solid State Drive) made up of a read / write capable flash memory. However, in this embodiment, the SSD functions in a write and delete prohibited mode, and the external memory 55 essentially functions as a non-volatile ROM.

[0073] 6, the external memory 55 and the overall performance circuit 52 are connected by differential signal lines TD and RD, and serially transmit and receive data according to a protocol conforming to the Serial ATA standard. Note that the external memory (SSD) 55 in this embodiment functions at a communication speed of either 3 Gbps or 6 Gbps.

[0074] In any case, the external memory (SSD) 55 stores in a non-volatile manner a boot program that starts when the power is turned on, a control program for the CPU circuit 51 that realizes performance control, various control data (including lamp drive data) required to execute the control program, CG compressed data for image performance, and audio compressed data for audio performance.

[0075] Furthermore, information necessary for (1) CPU exception vector, (2) data protection parameters (obfuscation key), (3) CG bus address space setting, (4) CPU offset setting, and (5) device I / F setting is stored as configuration data in the leading area of ​​the external memory 55, and a general-purpose hash function and a unique CHAP key prepared for each gaming machine manufacturer are stored in appropriate locations in the external memory 55. Note that the configuration data will be described later in relation to the processing of steps SP3 and SP10 in Figure 16, and the general-purpose hash function and CHAP key will be described later in relation to the processing of step SP6 in Figure 16.

[0076] In the external memory 55 of the embodiment, the boot program and other programs to be transferred (step ST11 in FIG. 16), the CG compressed data for image effects, and other data are obfuscated using a method unique to each gaming machine manufacturer. The obfuscation method is not particularly limited, but for example, a method of appropriately scrambling the bit position of 1 byte data is employed. However, in any scrambling process, a unique obfuscation process is executed based on an obfuscation key based on a user ID unique to each gaming machine manufacturer, and the scrambled data is stored in the external memory 55 as the CG compressed data for image effects and other programs and data (see FIG. 17(a)).

[0077] The above scrambling process is performed by the manufacturer of the composite chip 50 and the SATA device (external memory) 55, and the randomly determined unique user ID is notified in advance to the gaming machine manufacturer that uses the composite chip 50 and the SATA device 55.

[0078] The descrambling circuit for restoring ROM data obfuscated by scrambling is built into the composite chip 50 as a general-purpose circuit. However, in order for this general-purpose circuit to function properly, it needs the obfuscation key written in the SATA device 55 and the de-scrambling key generated based on the user ID.

[0079] Therefore, as shown in Fig. 17(a), when the power is turned on, the composite chip 50 must read the obfuscation key from the SATA device (external memory) 55 and also read the user ID that is set as a terminal in the composite chip 50, and based on these, generate an obfuscation key to function a scramble circuit that operates uniquely to the gaming machine manufacturer. These operations will be described further below with reference to Figs. 16 and 17.

[0080] Therefore, next, the explanation will be continued by returning to Fig. 6(a). As shown in Fig. 6(a), the external memory 55, which is a SATA device, is configured to have a differential input terminal RX, a differential output terminal TX, a soft reset terminal INIT_REQ (initialization request terminal), an input terminal XIN that receives an operating clock from a crystal oscillator circuit OSC, a hard reset terminal HRST for performing a hardware reset of the internal circuit, an output terminal WDT for a clear signal, and an operation control terminal WP that defines the operation mode.

[0081] Here, the differential input terminal RX and the differential output terminal TX are connected to the combined chip 50 via differential signal lines TD and RD. The external memory 55 and the combined chip 50 realize data transmission using a protocol compliant with Serial ATA Revision 3.3. That is, the external memory 55 performs serial communication with the SATA controller of the combined chip 50, and returns requested data to the SATA controller. As explained above, the communication speed is high, at 3 Gbps or 6 Gbps.

[0082] The external memory 55 is configured as an SSD (Solid State Drive) and is essentially capable of read / write operations. However, to protect data once written, the SSD 55 is provided with an operation control terminal WP. As shown in the figure, a pull-up resistor keeps the WP terminal at the H level, thereby prohibiting data from being rewritten or erased.

[0083] Furthermore, the external memory 55 repeatedly supplies a clear signal at a predetermined interval from the clear signal output terminal WDT to the WD terminal of the watchdog timer 56. However, if the output of the clear signal is interrupted due to an abnormality in the internal circuitry of the external memory 55, the watchdog timer 56 outputs an abnormality reset signal (negative logic pulse) to the RESET terminal. When this abnormality reset signal is received at the hard reset terminal HRST, the external memory 55 enters a reset state, the same as a power reset state, and all internal circuits are initialized.

[0084] Meanwhile, the initialization terminal INIT_REQ of the external memory 55 receives the initialization signal XRST (negative logic pulse) output by the combined chip 50 via gates G1 and G2. As shown in the figure, the AND gate G2 also receives the abnormal reset signal output by the watchdog timer 56, and when either signal becomes active level (L), the external memory 55 executes a predetermined initialization operation. Incidentally, even during the initialization operation, the external memory 55 repeatedly outputs a clear signal from the clear signal output terminal WDT, so there is no risk of the external memory 55 being abnormally reset, regardless of the duration of the initialization operation.

[0085] The abnormal reset signal output by the watchdog timer 56 is also transmitted to the combined chip 50 via the XRST_OUT line. Therefore, in the combined chip 50, in response to the abnormal reset operation of the external memory 55, a SATA initialization command is executed, and an initialization operation similar to the processing of step SP2 in Fig. 16 is performed, thereby enabling the reconstruction of communications. The SATA initialization command is a type of "CG bus command" for controlling the CG bus IF unit 55a.

[0086] Here, the initialization operation is not particularly limited, but in this embodiment, the initialization operation is a reset operation of the PHY (Physical Layer), which is the physical layer in the SATA (Serial ATA) standard, and a reset operation of the MAC (Media Access Control), which is the data link layer.

[0087] A PHY reset (1) resynchronizes transmit and receive signals to correct communication errors and signal misalignment, and (2) reestablishes the physical link between the SATA device 55 and the SATA controller in the combined chip 50 to reconfirm the physical connection between the devices. A MAC reset (1) clears the state of the data link layer to reestablish the link protocol, and (2) resets error counters and other status information related to the data link layer.

[0088] These initialization operations are also effective when a communication error occurs, and in this embodiment, they are configured to be automatically executed not only when power is turned on or when an abnormal reset occurs in the external memory 55, but also when a communication abnormality is detected. However, this point will be described later with reference to FIG. 16 as the execution of a SATA initialization command.

[0089] Incidentally, the RESET terminal of the watchdog timer 56 in this embodiment is configured to maintain the L level for a predetermined time (37 ms or more) after the power supply voltage VS (=3.3 V) reaches the normal level after power is turned on, as shown in the time chart in the lower right of FIG. 6(a).

[0090] The RESET terminal of the watchdog timer 56 is connected to the hard reset terminal HRST of the external memory 55. The time during which the RESET terminal is maintained at the L level (37 mS or more) is long enough to reset the external memory 55, so after power is turned on, the external memory is reliably hardware reset based on the RESET signal from the watchdog timer 56.

[0091] Having explained the external memory 55 in detail above with reference to Fig. 6, we will return to Fig. 5 and continue explaining the CPU circuit 51. This CPU circuit 51 can read / write access various performance control registers RGij to control the internal operation of the overall performance circuit 52. The data transfer circuit 70 can also send and receive data between the CPU circuit 51 and the overall performance circuit 52 via the CPU bus unit 56. Note that data transmission from the CPU circuit 51 to the overall performance circuit 52 includes issuing a display list DL and a voice command list VC.

[0092] As shown on the right side of Figure 5(a), the overall performance circuit 52 includes (1) a data transfer circuit 70, (2) a display circuit 71, (3) a preloader 72, (4) a GDEC (Graphics Decoder) circuit 73, (5) a drawing circuit 74, (6) an image filter circuit 75, (7) an index table IDXTBL, (8) a motor control unit MT_CTL, (9) a lamp control unit L_CTL, and (10) an audio processing unit SND, and the performance control register RGij is used to enable the CPU circuit 51 to appropriately control these internal circuits of the overall performance circuit 52.

[0093] Therefore, the performance control register RGij is broadly divided into (1) data transfer register, (2) display register, (3) preload register, (4) GDEC register, (5) drawing register, (6) image filter register, (7) index table register, (8) MT_CTL register, (9) L_CTL register, (10) sound register, etc., corresponding to each of the above circuits (1) to (10), and a system control register is provided for overall system control (see Figure 5(b)). Note that the system control register and each of the registers (1) to (10) for individual circuits are actually composed of multiple register groups that are further divided.

[0094] Based on the above, we will now explain the CPU circuit 51. The CPU circuit 51 is a circuit with performance equivalent to that of a general-purpose one-chip microcomputer, and as shown on the left side of Figure 5(a), it is configured with a performance control CPU 57 that comprehensively controls image / audio / lamp / motor performances based on a control program, a watchdog timer (WDT) 58 that forcibly resets the CPU if the program goes out of control, an internal RAM 59 with a storage capacity of about 2 MB that is used as a working area for the performance control CPU 57, a DMAC (Direct Memory Access Controller) 60 that realizes data transfer without going through the performance control CPU 57, a serial input / output port (SIO) 61 having multiple input ports Si and output ports So, a parallel input / output port (PIO) 62 having multiple input ports Pi and output ports Po, and an operation control register REG in which setting values ​​are set to control the internal configuration of the CPU circuit 51.

[0095] For convenience, the term "input / output port" is used in this specification, but the input / output port includes an input port and an output port that operate independently in the performance control unit 23. This also applies to the input / output circuit 64p corresponding to the parallel input / output port 62 and the input / output circuit 63s corresponding to the serial input / output port 63, which will be described below.

[0096] The parallel input / output port (PIO) 62 is connected to an external device (performance interface board 22) through an input / output circuit 64p, and the performance control CPU 57 receives the 3-bit encoder output of the volume switch VLSW, the switch signal of the chance button 11, the control command CMD, and the interrupt signal STB via the input circuit 64p. The 3-bit encoder output and the 1-bit switch signal are supplied to the parallel input / output port 62 via the input / output circuit 64p.

[0097] Similarly, the received control command CMD is supplied to the parallel input / output port 62 via the input / output circuit 64p. The strobe signal STB is supplied to the interrupt terminal of the performance control CPU 57 via the input / output circuit 64p, thereby activating the reception interrupt process. Based on the reception interrupt process, the performance control CPU 57 grasps the control command CMD and, through a performance lottery or the like, performs unified control of the audio performance, lamp performance, motor performance, and image performance corresponding to the control command CMD. The parallel input / output port 62 outputs operation control signals ENABLE0 to ENABLE1 for the lamp performance via the input / output circuit 64p.

[0098] Furthermore, the serial input / output port (SIO) 61 is configured to be able to transmit and receive serial signals via the input / output circuit 63s. Therefore, as shown by the dashed lines in Figure 5(a), a clock signal CK that realizes synchronous serial transmission and a drive serial signal SDATA can also be output via the input / output circuit 63s internally connected to the serial input / output port SIO 61. However, in this embodiment, lamp / motor effects are realized using the lamp control unit L_CTL and motor control unit MT_CTL of the overall effect circuit 52 without using the serial input / output port 61.

[0099] Incidentally, a DL buffer BUF for sequentially updating and storing a display list DL in which a series of instruction commands specifying one frame of the display device DS are listed is secured in the built-in RAM 59 of the CPU circuit 51. Furthermore, this DL buffer BUF is configured by partitioning areas, and also sequentially updating and storing a voice command list VC specifying the performance contents of the voice performance.

[0100] In this embodiment, the instruction commands of the display list DL that define one frame of the display screen include (1) index table control commands related to the index table IDXTBL that manages the index space, (2) texture load commands such as the LOADTX command for reading and decoding (decompressing / expanding) image material (texture) from external memory 55, (3) filter execution commands that specify filter processing for the decompressed image data, (4) drawing commands such as the SPRITE command for placing the decoded (expanded) image material at a predetermined position in the virtual drawing space, (5) pipeline commands related to drawing pipeline operation, and (6) overall control commands that define the overall operation of the overall performance circuit 52. The display list DL is configured to list an appropriate number of instruction commands and then terminate with a predetermined end command EODL (32 bits long).

[0101] In addition, the voice command list VC, which specifies the operation of the voice processing unit SND that executes the voice performance, lists an appropriate number of voice commands and then concludes with a predetermined termination command EOSC (32 bits long). Here, the voice commands are roughly divided into track-related commands that specify the operation of the pre-processing unit FT shown in Fig. 13(a), master effect-related commands that specify the operation of the post-processing unit BK shown in Fig. 13(a), and other system-related commands, and all voice commands are composed of an integer multiple (>0) of 32 bits.

[0102] As will be described later, the rendering pipeline operation of this embodiment is executed using the vertex buffer VB built into the rendering circuit 74, the frame buffer FB reserved as an index space, and the depth / stencil buffer, and is configured to include an input assembler process IA, a geometry engine process TL, a rasterizer process RS, a texture sampler process TX, a texture process PS, a pixel drawing process PX, and a render process RO. The pipeline command (5) above functions as a setting command that specifies the specific operation of each process (IA, TL, RS, TX, PS, PX, RO) and the R / W position of the vertex buffer VB.

[0103] Incidentally, texture is generally a concept that refers to the feel and texture of an object's surface, but in this specification, the term texture is used to collectively refer to image data before and after decoding. For example, sprite image data that makes up a still image, frame image data that makes up one frame of video, and pasted image data that is pasted onto drawing primitives such as triangular polygons and quadrilateral polygons are also referred to as textures.

[0104] Then, (2) the texture is read from external memory 55 and decoded by the LOADTX command, which is a texture load command. (5) The source image data is set to be a texture by the SETTXINDEX command, which is a texture sampler process TX command included in the pipeline commands. (4) The texture is then virtually drawn in the virtual drawing space shown in Figure 7(c) by the SPRITE command, which is a drawing command. The contents drawn in the virtual drawing space are output to the display device DS via the frame buffer FB, which will be described later.

[0105] More specifically, in the SETTXINDEX command, the index space (space type and index number) to be used as a texture is set by embedded parameters. Here, any of the following can be specified as the space type: an arbitrary area of ​​the VRAM 53, a page area of ​​the VRAM 53, an AAC area of ​​the VRAM 53, an arbitrary area of ​​the extended RAM 54, or a page area of ​​the extended RAM 54. In this embodiment, however, the shared area of ​​the VRAM 53 is used as the ACC area, so that no page area exists in the VRAM 53 (see FIG. 7(a)).

[0106] Furthermore, when the LOADTX command is executed after the index space has been set with the SETTXINDEX command, the decoded results are stored in the set index space. This LOADTX command specifies the horizontal and vertical pixel sizes of the decoded texture, as well as the type of memory in which the basic data to be decoded is stored and the address of the basic data. By specifying the horizontal and vertical pixel sizes with the LOADTX command, the internal circuitry of the video processing unit (VDP) can easily manage the correspondence between the horizontal and vertical positions of each texture pixel (RGBA color information) and the data position in the index space.

[0107] Note that while there is normally only one type of pixel size information and basic data address information, when decoding an IPB stream, etc. (described later), two types of information for the main frame and subframe may be specified with one LOADTX command. Note that the memory type is normally external memory 55, but it is also possible to specify expansion RAM 54 or VRAM 53. For example, in Figure 12, the reference buffer to be accessed by the LOADTX command is an index space secured in any area of ​​VRAM 53 or expansion RAM 54.

[0108] The SPRITE command is a command that pastes a rectangular texture into a rectangular area in window coordinates. In this embodiment, one SPRITE command can reference up to four textures, and the embedded parameters of the SPRITE command specify the upper left and lower right coordinates of the texture (only if necessary) and the upper left and lower right coordinates of the window coordinates to which the texture will be pasted. Note that if the entire texture is to be used, it is not necessary to specify the upper left and lower right coordinates of the texture; only the window coordinate values ​​to which the texture will be pasted are sufficient.

[0109] The index space managed by the index table control command (1) above refers to a one-dimensional or two-dimensional memory work area (logical address space) used by the overall performance circuit 52 during drawing operations, etc. This index space is specified as a one-dimensional or two-dimensional logical address space by the index number written in the instruction command of the display list DL.

[0110] That is, in this embodiment, an index space is reserved in an appropriate location in memory (VRAM 53 and expansion RAM 54) that can be accessed as a memory work area, and this is specified by an index number. Also, the VRAM 53 and expansion RAM 54 are divided into virtual work areas (AAC area, page area, arbitrary area), and an index space can be reserved for each (see Figures 7(a) and 7(b)). Therefore, the index number becomes a unique value for each virtual work area, which simplifies texture load commands, filter execution commands, drawing commands, pipeline commands, etc.

[0111] It also allows for individual operation for each virtual work area (AAC area, page area, arbitrary area). For example, in the AAC area, index space is automatically reserved as an area for expanding decoded data, and then automatically released. Therefore, index numbers are not required in the ACC area.

[0112] Specifically, the virtual work area (AAC area, page area, optional area) is defined during the initial processing after power-on, and the necessary index space is secured in the necessary virtual work area at the necessary timing thereafter. The secured index space is then linked to the index number and managed by the index table IDXTBL, thereby realizing subsequent operations based on the index number.

[0113] The relationship between the virtual work area and the actual work area, which is VRAM 53 and expansion RAM 54, will be explained below. First, VRAM 53 is divided into a shared area that can be used as both an AAC area and a page area, and other optional areas. Specifically, in the initial processing after power-on, the shared area of ​​VRAM 53 is secured by setting an appropriate starting address and area data size for VRAM 53 in the corresponding performance control register RGij. Then, areas other than the shared area secured in VRAM 53 automatically become optional areas of VRAM 53 (Figure 7(a)).

[0114] The shared area reserved in VRAM 53 can be used as both an ACC area, which does not require management of index numbers, and a page area, which requires management of index space using index numbers. Therefore, when using a shared area, you simply specify that index space is to be reserved in the AAC area with the SETTXINDEX command, and then specify the pixel size and storage address of the texture (image material) with the LOADTX command, and the decompressed data of the read texture can be expanded in the index space automatically reserved in the ACC area.

[0115] Therefore, in this embodiment, taking the above-mentioned simplicity into consideration, for still images and I-stream moving images (S-stream moving images consisting only of I-pictures, which will be described later), decoded data is developed in the AAC area of ​​the VRAM 53. That is, in this embodiment, the shared area of ​​the VRAM 53 is used exclusively as an AAC area.

[0116] Next, in the initial processing after power-on, the expansion RAM 54 secures a page area in the expansion RAM 54 by setting the starting address and area data size in the expansion RAM 54 in the corresponding performance control register RGij, and the remaining area becomes an arbitrary area in the expansion RAM 54 (FIG. 7(b)). Here, the "arbitrary area" refers to an area in the expansion RAM 54 and VRAM 53 that can be used arbitrarily, and can be used not only for securing index space but also for other purposes. Therefore, in this embodiment, a preload area for pre-transferring (preloading) CG data acquired from the external memory 55 is secured in an arbitrary area in the expansion RAM 54 (see FIG. 7(b)), and a preload buffer for storing a rewrite list DL' obtained by the preloader 72 rewriting the display list DL is secured in an arbitrary area in the VRAM 53 (see FIG. 7(a)).

[0117] In this embodiment, the control programs and control data stored in the external memory 55 are transferred and copied to any area of ​​the extended RAM 54 when the power is turned on (see FIG. 7(b)). Of course, all or part of the control programs and control data may be transferred and copied to the VRAM 53 instead of the extended RAM 54. Furthermore, not only the control programs and control data but also compressed CG data and compressed audio data may be transferred and copied in whole or in part to the RAMs 53 and 54.

[0118] In any case, the index space can be allocated appropriately in the extended RAM 54 and VRAM 53 in (1) the ACC area, (2) the VRAM page area, (3) the VRAM optional area, (4) the extended RAM page area, and (5) the extended RAM optional area, but in this embodiment, the shared area of ​​the VRAM 53 is used exclusively as the AAC area. However, the area allocated as a shared area in the VRAM 53 can be used as both a page area and an AAC area, so the following explanation will be based on this point.

[0119] When reserving index space in the page area of ​​the VRAM 53, it is necessary to set an index number and space size in a predetermined performance control register RGij for the VRAM. Furthermore, the index space in the page area of ​​the expansion RAM 54 is reserved by setting an index number and space size in a predetermined performance control register RGij for the expansion RAM. In this embodiment, the page area of ​​the expansion RAM 54 is used to expand video frames. In addition, in the page area, the starting address of the index space is determined appropriately based on internal processing, which is convenient as it eliminates the need to manage the starting address. In other words, when reserving index space in the page area, there is no need to worry about overlap with existing index space.

[0120] On the other hand, when a two-dimensional index space is secured in any area of ​​the VRAM 53 or any area of ​​the extended RAM 54, it is necessary to set the index number, the starting address of the index space, and the horizontal and vertical sizes of the index space in the corresponding predetermined performance control register RGij. In the case of a one-dimensional index space, the horizontal and vertical sizes are not required, and only the space size needs to be set.

[0121] In this way, when an index space is allocated in an arbitrary area, the starting address and size can be set precisely, which has the advantage of allowing for efficient memory use. Therefore, in this embodiment, image data for one frame of the display device DS is completed and the frame buffer FB is allocated as a two-dimensional index space in an arbitrary area of ​​the VRAM 53 (see FIG. 7(a)). Of course, the frame buffer FB may also be allocated in an arbitrary area of ​​the expansion RAM 54.

[0122] The frame buffer FB allocated in any area of ​​the VRAM 53 corresponds to the drawing area of ​​the virtual drawing space that is the drawing target for drawing commands such as the SPRITE command. Figure 7(c) shows the relationship between the virtual drawing space (horizontal X direction ±8192: vertical Y direction ±8192), the drawing area that can be set arbitrarily within the virtual drawing space, and the frame buffer FB that stores image data to be output to the display device DS.

[0123] One frame of image data for the display screen is written into the frame buffer FB by the drawing circuit 74, while one frame of image data for the display screen is read out by the display circuit 71. The frame buffer FB has a double buffer structure consisting of a pair of index spaces, and is composed of a first buffer with index number N1 and a second buffer with index number N2.

[0124] For the display circuit 71, the first buffer and the second buffer are read-out areas for image data, and the image data in the first buffer and the second buffer are read out in sequence for each operating cycle δ by toggling the index numbers N1 / N2 based on the information embedded in a predetermined display register RGij.

[0125] On the other hand, for the drawing circuit 74, the first buffer and the second buffer are areas for writing image data, and image data is written alternately to the first buffer and the second buffer by toggling the index numbers N1 / N2 every operating period δ based on the instruction command on the display list DL.

[0126] The writing operation of the drawing circuit 74 corresponds to the reading operation of the display circuit 71, so that image data written to the first buffer in one operation cycle is read by the display circuit 71 in the next operation cycle, and in the operation cycle in which the image data in the first buffer is read, the drawing circuit 74 writes image data to the second buffer. Subsequent operations are the same, and the first buffer and second buffer are used alternately as the "writing area" and the "reading area".

[0127] In this embodiment, index spaces reserved in any area of ​​the VRAM 53 or expansion RAM 54 are used as general work spaces other than the frame buffer FB and the space for expanding compressed data. These various index spaces can be reserved when needed and can be released when not needed, but when an index space is reserved / released, the contents of the index table IDXTBL, which stores the index space in association with the index number, are updated, enabling subsequent consistent operation.

[0128] The index space and the CPU circuit 51 have been explained above, so next, the overall performance circuit 52 will be explained.

[0129] The overall presentation circuit 52 includes (1) various presentation control registers RGij, whose setting values ​​that define internal operations are set by the presentation control CPU 57; (2) a data transfer circuit 70 that transmits and receives data between circuits inside and outside the chip; (3) an index table IDXTBL that manages an index space, which is a working area secured in the VRAM 53 and the expansion RAM 54; (4) a preloader 72 that can perform a preload operation to read and access the external memory 55 prior to a drawing operation; (5) a GDEC (Graphics Decoder) circuit 73 that decodes compressed data for image presentation read from the external memory 55; (6) a drawing circuit 74 that appropriately combines the decoded still image data and video data to generate image data for one frame of the display device DS in the frame buffer FB; (7) a plurality of display circuits 71 that read the image data from the frame buffer FB generated by the drawing circuit 74, perform appropriate image processing, and output the image data; and (8) (9) an output selection unit 76 that appropriately selects and outputs the output of the display circuit 71 from multiple systems, (10) an output unit 77 that converts the image data output by the output selection unit 76 into an LVDS signal or the like and outputs it, (11) an audio processing unit SND that executes audio effects based on the audio command list VC, (12) a motor control unit MT_CTL that executes motor effects, and (13) a lamp control unit L_CTL that executes lamp effects (see FIG. 5(a)). The audio processing unit SND includes an audio decoder that decodes compressed data for audio effects read from the external memory 55.

[0130] The motor performance is executed based on the control operation of the performance control CPU 57, specifically, based on the set value of the predetermined performance control register RGij for the motor performance and the control data (motor drive data) copied to the expansion RAM 54. The lamp performance is also executed in the same way based on the control operation of the performance control CPU 57, specifically, based on the set value of the predetermined performance control register RGij for the lamp performance and the control data (lamp drive data) copied to the expansion RAM 54.

[0131] 5(b) illustrates the relationship between the CPU bus unit 56, CG bus IF unit 55a, extended RAM IF unit 54a, and VRAM IF unit 53a and the performance control register RGij, external memory 55, extended RAM 54, and VRAM 53. As illustrated, the CG compressed data acquired from the external memory 55 is supplied to the GDEC circuit 73 via the CG bus IF unit 55a and data transfer circuit 70, and the decompressed (decoded) data is expanded in a predetermined index space secured in the extended RAM 54 or VRAM 53.

[0132] As explained above, in this embodiment, an ACC area for storing still images is allocated in the VRAM 53, and a page area for storing video frames is allocated in the expansion RAM 54. Decoded data for still images and videos is then stored in a predetermined index space in the ACC area / page area. Note that decompressed data of compressed CG data acquired from the external memory 55 may also be transferred as preload data to the preload area of ​​the expansion RAM 54.

[0133] Next, the display circuit 71 will be described with reference to FIG. 8. The display circuit 71 is a circuit that reads image data from the frame buffer FB in synchronization with the dot clock DCK, performs final image processing, and outputs the data. The final image processing includes, for example, scaling processing by a scaler that enlarges or reduces the image to a similar shape, subtle color correction processing, and dithering processing that minimizes quantization error of the entire image. These image processing operations are performed uniformly based on the setting values ​​of the performance control register RGij (display register). The digital RGB signal that has undergone the uniform image processing is then output together with horizontal and vertical synchronization signals.

[0134] As shown in Fig. 8, three display circuits A / B / C are provided that perform the above operations in parallel, but in this embodiment, since there is only one display device, only the frame buffer FB (=FBa) is reserved for the display circuit A. However, if frame buffers FBa to FBc are reserved, it is also possible to drive two other display devices that can perform independent image presentations.

[0135] Next, returning to Fig. 5(a), the data transfer circuit 70 will be explained. The data transfer circuit 70 is a circuit that performs data transfer operations between the internal resources of the overall performance circuit 52 and an external storage medium as the transfer source or transfer destination in a DMA (Direct Memory Access) manner. Fig. 9 is a block diagram showing the internal configuration of this data transfer circuit 70 together with the related circuit configuration.

[0136] The transfer sources of the data transfer circuit 70 in this embodiment include the CPU address space via the CPU bus unit 56, the external memory 55, the extended RAM 54, and the VRAM 53, as well as the CPU register port PORT. On the other hand, the transfer destinations of the data transfer circuit 70 include the CPU register port PORT, the CPU address space, the extended RAM 54, the VRAM 53, the checksum circuit, the drawing circuit 74, the preloader 72, and the audio processing unit SND.

[0137] Here, the CPU address space refers to a storage area accessible by the performance control CPU 57. The CPU register port PORT is a 32-bit register connected to the CPU bus unit 56, and the performance control CPU 57 can arbitrarily access it via R / W.

[0138] Furthermore, virtual work areas such as page areas and arbitrary areas are defined in the expansion RAM 54 and VRAM 53, and index spaces specified by index numbers are secured / released within these virtual work areas. Therefore, the operation of the data transfer circuit 70 is executed by referring to an index table IDXTBL that stores the relationship between the index spaces and real address spaces. The index spaces secured in the expansion RAM 54 or VRAM 53 can also be set as the data transfer source or data transfer destination of the data transfer circuit 70. Therefore, data in the frame buffer FB secured in an arbitrary area of ​​the VRAM 53 can also be transferred to the expansion RAM 54.

[0139] 9, the transfer size that the data transfer circuit 70 can transfer is 32 bits × (01h to 4000_0000h) when passing through data relay units CH0 to CH1, and 32 bits × (01h to 100_0000h) when passing through data relay units CH2 to CH4. That is, the data transfer circuit 70 of this embodiment can transfer data of any size that is an integer multiple of 32 bits, although there is a predetermined upper limit. Here, h represents a hexadecimal number, and the upper limit of the transfer size is specifically 32 × 1,073,741,824 bits when passing through data relay units CH0 to CH1, and 32 × 16,777,216 bits when passing through data relay units CH2 to CH4.

[0140] 9, the data transfer circuit 70 is configured to receive necessary data from the external memory 55 via an arbitration circuit ICM that has a router function and arbitrates access paths, and to transmit and receive necessary data to and from the VRAM 53 and the extended RAM 54. The external memory 55, VRAM 53, and extended RAM 54 are accessed via a CG bus IF unit 55a, a VRAM IF unit 53a, and an extended RAM IF unit 54a.

[0141] This data transfer circuit 70 is composed of a 32-bit x 130-stage CPU data FIFO (First In First Out) circuit connected to a 32-bit CPU register port PORT, and five channel data relay units CH0 to CH4. As explained above, the CPU register port PORT is configured to be R / W accessible from the performance control CPU 57.

[0142] The data relay unit CH0 is composed of a CH0 data FIFO circuit of 1024 bits x 18 stages and a checksum circuit. Each of the data relay units CH1 to CH4 is composed of a CH0 data FIFO circuit of 1024 bits x 18 stages. The data relay units CH2 to CH4 are unidirectionally connected to the drawing circuit 74, preloader 72, and audio processing unit SND.

[0143] On the other hand, the CPU data FIFO circuit and the data relay units CH0-CH1 are configured to be capable of bidirectional communication, so that a predetermined amount of data set in the data transfer register is sent and received from a predetermined transfer source set in the data transfer register to a predetermined transfer destination set in the data transfer register via the CPU data FIFO circuit or the data relay units CH0-CH1.

[0144] Regardless of which path is taken among the data relay units CH0 to CH4, the amount of data to be transferred (transfer data size) must be set in 32-bit units, as described above, and there are also certain restrictions on the start addresses of the transfer source and destination. Specifically, the start addresses of the transfer source and destination must be set in 8-bit units in the CPU address space, and in 32-bit units in the VRAM 53 and expansion RAM 54. The transfer source start address in the external memory 55 is also set in 32-bit units.

[0145] When data passes through the data relay units CH0 to CH1, the source and / or destination of the transfer is the external memory 55, the VRAM 53, or the expansion RAM 54, and when data passes through the CPU data FIFO circuit connected to the CPU register port PORT, the source or destination of the transfer is the CPU address space, which naturally includes the internal RAM 59.

[0146] While the data relay units CH0 to CH1, which are capable of two-way communication, have been described above, data relay units CH2 to CH4 form one-way communication paths. The performance control CPU 57 can then write-access the CPU register port PORT in 32-bit units via the CPU bus unit 56, thereby transmitting the display list DL and voice command list VC in the DL buffer BUF of the internal RAM 59 to the data relay units CH2 to CH4 in one direction.

[0147] In addition, the internal RAM 59 can be selected as the data transfer source, so that data can be transferred via the data relay units CH2 to CH4 (without going through the CPU register port PORT) with the DL buffer BUF as the data transfer source and the drawing circuit 74, preloader 72, or audio processing unit SND as the data transfer destination.

[0148] In this case, the start address of the data transfer source internal RAM 59 is specified in 8-bit units, so the lower 7 bits of the start address of the DL buffer BUF must be 0. Also, regardless of whether the data is transferred via the CPU register port PORT or not, the amount of data to be transferred (data transfer size) must be set in 32-bit units.

[0149] In any case, the data relay units CH2, CH3, and CH4 are unidirectionally connected to the drawing circuit 74, the preloader 72, and the audio processing unit SND, respectively. Therefore, a display list DL of a predetermined data transfer size is transferred to the drawing circuit 74 via the data relay unit CH2, and to the preloader 72 via the data relay unit CH3. Also, a voice command list VC of a predetermined data transfer size is transferred to the audio processing unit SND via the data relay unit CH4.

[0150] As described above, in this embodiment, the transfer paths for the display list DL and the voice command list VC are (1) a first path that passes through the CPU register port PORT, and (2) a second path that does not pass through the CPU register port PORT, and either of these paths can be used. This also applies to data other than the display list DL and the voice command list VC, and there are (1) a first path that passes through the CPU register port PORT and data relay units CH0 to CH4, and (2) a second path that passes only through the data relay units CH0 to CH4. The first path is used for data transfers in which the performance control CPU 57 is directly involved, and the second path is used for data transfers in which the performance control CPU 57 is not directly involved (DMA operations).

[0151] 9, the CPU data FIFO circuit receives data in 32-bit units, while the data relay units CH0 to CH4 receive data in 1024-bit units. Therefore, when the first path is used, once 1024 bits of data have accumulated in the CPU data FIFO circuit, the accumulated data will be transferred to one of the data relay units CH0 to CH4 (hereinafter referred to as a channel data FIFO).

[0152] In other words, if less than 32 levels of data are written to the CPU data FIFO circuit, no data transfer to the channel data FIFO occurs. When the 32nd level of data is written, the 32 levels of accumulated data are transferred to the channel data FIFO, and the data is then transferred to further destinations.

[0153] On the other hand, since the data transfer size is an arbitrary value that is an integer multiple of 32 bits, it is possible that the data in the CPU data FIFO circuit will end up at less than 32 levels, but when the cumulative size of the written data reaches the transfer size previously set in the data transfer register, the accumulated data less than 32 levels will be transferred to the channel data FIFO or further destination.

[0154] As described above, in this embodiment, the transfer size of the data transfer circuit 70 is an arbitrary value that is an integer multiple of 32 bits, regardless of whether the data is transferred via the first path or the second path. Corresponding to this configuration, the instruction commands that make up the display list DL and the voice commands that make up the voice command list VC are all configured as an integer multiple of 32 bits. Therefore, in this embodiment, there is no restriction on the number of commands in the display list DL or the voice command list VC, allowing for a free list configuration, and there is no need to adjust the total data size by adding dummy commands, etc.

[0155] Figure 10 shows the operation of transferring the display list DL to the drawing circuit 74 via the CPU register port PORT and the data relay unit CH2 (Figure 10(a)), the operation of transferring the display list DL from the internal RAM 59 to the drawing circuit 74 via the data relay unit CH2 (Figure 10(b)), and the operation of transferring the rewrite list DL', which is a modified display list, from the VRAM 53 to the drawing circuit 74 via the data relay unit CH2 (Figure 10(c)).

[0156] Figures 10(d) and 10(e) show the operation of transferring a display list DL to the preloader 72 via the CPU register port PORT and the data relay unit CH3, and the operation of transferring a display list DL from the internal RAM 59 to the preloader 72 via the data relay unit CH3.

[0157] Also, Figures 10(f) and 10(g) show the operation of transferring the voice command list VC to the voice processing unit SND via the CPU register port PORT and the data relay unit CH4, and the operation of transferring the voice command list VC from the built-in RAM 59 to the voice processing unit SND via the data relay unit CH4.

[0158] The CPU circuit 51 starts the operations of the drawing circuit 74, preloader 72, and audio processing unit SND prior to the start of operation of the data transfer circuit 70, so that the drawing circuit 74 starts drawing operations based on the transferred display list DL. Meanwhile, the preloader 72 executes the necessary preloading operations based on the transferred display list DL. The transferred display list DL is analyzed by a display list analyzer built into the drawing circuit 74 and preloader 72, and processing is executed according to the type of instruction command. Furthermore, the audio processing unit SND starts or progresses audio performance based on the transferred audio command list VC.

[0159] Note that data other than the display list DL and the voice command list VC in the CPU address space can be transmitted to the data relay units CH0 to CH4 via the CPU bus unit 56, and then further via the CPU register port PORT, or directly. The data relay units CH0 to CH1 then transfer the transmitted data to a predetermined destination in the VRAM 53 or the expansion RAM 54 via the arbitration circuit ICM. The reverse transfer operation is similar, and the data relay units CH0 to CH1 that receive data via the arbitration circuit ICM transfer the data to a predetermined destination in the CPU address space either via the CPU register port PORT, or directly.

[0160] Next, the preloader 72 will be described, but it is optional whether or not to utilize the preloader 72. When the display list analyzer interprets the display list DL transferred from the data relay unit CH3 of the data transfer circuit 70 and detects a LOADTX command, the preloader 72 pre-transfers (preloads) the CG data in the external memory 55 referenced by the LOADTX command to the preload area of ​​the expansion RAM 54 (see FIG. 7(b)).

[0161] Furthermore, the preloader 72 stores a rewrite list DL' in which the reference destination of the CG data is rewritten to the address after transfer in the DL buffer BUF' (see FIG. 7(a)) of the VRAM 53 for the above-mentioned LOADTX command. The DL buffer BUF' and the preload area are reserved in advance during the initial processing after the CPU is reset.

[0162] The rewrite list DL' is then transferred to the drawing circuit 74 via the arbitration circuit ICM and data relay unit CH2 of the data transfer circuit 70 when the drawing operation of the drawing circuit 74 starts (see FIG. 10(c)). The drawing circuit 74 then executes the drawing operation based on the rewrite list DL'. Therefore, CG data that should normally be obtained from the external memory 55 based on a LOADTX command or the like is quickly obtained from the preload area of ​​the expansion RAM 54 as preload data that has been pre-read into the preload area. Taking this into consideration, the preloader 72 is put into operation in a normal device configuration.

[0163] In this embodiment, since the preload area is set in the external expansion RAM 54, which has sufficient storage capacity, multiple preloading, for example, in which multiple frames of CG data are preloaded at once, is also possible. That is, multiple preloading is realized by appropriately setting the operating period of the preloader 72, which is a series of preloading operations including the CG data prefetching operation, within the range of an integer multiple of the operating cycle δ of the overall performance circuit 52 during intermittent operation.

[0164] However, in the following explanation, for the sake of convenience, an embodiment without multiple preloading will be described, and therefore the preloader 72 of the embodiment will complete the preloading operation for one frame during one operation period δ. In this embodiment, the operation period δ during intermittent operation of the overall performance circuit 52 is 1 / 30 seconds, which is twice the period of the vertical synchronization signal of the display device DS.

[0165] Next, the drawing circuit 74 sequentially analyzes the instruction command sequences of the display list DL and the rewrite list DL′ transferred via the data transfer circuit 70, and works in cooperation with the GDEC circuit 73, the geometry engine, etc. to draw one frame of an image of the display device DS in the frame buffer FB secured in the VRAM 53.

[0166] As described above, when the preloader 72 is activated, the CG data in the rewrite list DL' is referenced not in the external memory 55 but in the preload area set in the expansion RAM 54. This allows for rapid sequential access to CG data that occurs while the rendering circuit 74 is rendering, making it possible to render high-resolution moving images with rapid movement without any problems.

[0167] Regardless of whether the preloader 72 is enabled or disabled, even if data bit corruption occurs during transfer of the display list DL or the rewrite list DL', the drawing circuit 74 cannot detect this. Therefore, in this embodiment, a timeout monitoring circuit having a configuration similar to that of a watchdog timer is provided to detect an abnormality in which memory access is not performed for a certain period of time after the drawing circuit 74 starts operating.

[0168] In this embodiment, a time setting register TO capable of setting a timeout time is provided to detect an operational abnormality in the drawing circuit 74. The time setting register TO is a type of drawing register, and the operation of the drawing circuit 74 is configured to be started based on the value set in a predetermined drawing register (drawing operation permission register).

[0169] When a predetermined timeout time is set in the time setting register TO and start information is set in the drawing operation permission register, the drawing circuit 74 starts operation, and in response, the timeout monitoring circuit monitors the memory access cycle. If no memory access is made after the timeout time has elapsed, an abnormality flag in a predetermined drawing register is set ON and an abnormality interrupt is initiated.

[0170] Although it is possible to deal with this abnormal interrupt by starting an interrupt processing program, in this embodiment, the appearance of an abnormal screen is prevented by checking the ON / OFF state of the abnormal flag for each operation cycle δ of the overall performance circuit 52. Specifically, if the abnormal flag is ON, the screen update for that operation cycle is skipped even if the operation of the drawing circuit 74 has been completed.

[0171] Here, if measures such as activating the WDT 58 or resetting the drawing circuit 74 are taken, as in the configurations of Patent Documents 1 and 2, there is a risk that an unnatural screen display will appear, but in this embodiment, the appearance of an abnormal screen is easily prevented with minimal measures. Also, the timeout period to be monitored can be set arbitrarily taking into consideration the arrangement of commands such as the LOADTX command in the display list DL and the access time of the external memory 55, etc., thereby achieving optimal monitoring operation.

[0172] In the above configuration, the memory access cycle is monitored from the start to the end of the drawing circuit 74 operation, but instead of or in addition to this configuration, it is preferable to adopt a configuration that monitors the operation time from the start to the end of the GDEC circuit 73 operation. In this case, too, an optimal value can be set in the time setting register TO' taking into account the texture data capacity, thereby achieving optimal monitoring operation.

[0173] In the latter configuration, the timeout monitoring circuit starts monitoring each time the GDEC circuit 73 starts decoding CG compressed data, and ends the monitoring operation when the decoding ends. Note that, like the former configuration, when a timeout occurs, an abnormality flag in a specified drawing register is set to ON, an abnormality interrupt is initiated, and when an abnormality is detected, screen updates are skipped for that operating cycle. Note that this embodiment uses a flag polling method that checks the ON / OFF state of the abnormality flag for each operating cycle δ of the overall performance circuit 52. However, a configuration may also be adopted in which an abnormality interrupt processing program is initiated to skip screen updates for the operating cycle in which a problem occurred.

[0174] Next, the image filter circuit 75 is a circuit that functions based on instruction commands (filter execution commands) written in the display list DL and performs appropriate filter processing on textures temporarily stored in the VRAM 53 or the extended RAM 54. In other words, the image filter circuit 75 of the embodiment does not perform a uniform filter operation based on the setting value of the performance control register RGij, but rather allows for free filter processing of required image data by arbitrarily writing appropriate instruction commands in the display list DL.

[0175] The content of the filter processing is determined by the selection of a filter execution command and the setting parameters of the selected command, but the executable filter processing includes (1) FIR (Finite Impulse Response) filter processing, (2) downsampling processing, and (3) linear interpolation processing. Here, downsampling processing is a process that differs from the uniform scaling processing in the display circuit 71 that operates based on the setting value of the performance control register RGij (display register).

[0176] That is, downsampling does not reduce an image to a similar shape as scaling does, but involves reducing the image only in the vertical or horizontal direction. Although not limited to this, downsampling reduces the texture by calculating the average value of the image information of pixels in a predetermined range surrounding the target pixel and performing a thinning process such as moving average processing.

[0177] 11(a) is a diagram illustrating an example of an operation in which FIR filter processing is executed twice consecutively using a filter execution command. First, the SETFTINDEX command sets the destination index space where the reference texture to be filtered should be saved (command process L20), and then the LOADTX command retrieves the reference texture from the external memory 55 specified by the command's setting parameters, and saves the decoded image data in the destination index space (command process L21).

[0178] The following SETFTINDEX command sets the index space where the resultant texture will be saved (command process L22), and the SETFTSAMP command and SETFTCOEF command set the filter coefficients and other information (command process L23), before executing the FIR filter process with the FTEXECFIR command (command process L24). Note that the SETFTINDEX command distinguishes between specifying an index space for the reference texture or an index space for the resultant texture, depending on the setting parameters of the command.

[0179] As shown in Figure 11(b), the image data expanded in the index space for the reference texture specified by the instruction command L20 undergoes FIR filter processing specified by the instruction command L23, and then is stored in the index space for the result texture specified by the instruction command L22.

[0180] Next, the SETFTINDEX command sets the index space of the reference texture (command process L25), and the SETTXINDEX command sets the index space where the resultant texture will be saved (command process L26). In command L25, the image data after the filter process is set as the reference texture, so the resultant texture specified by command L22 is changed to the reference texture by command L25.

[0181] After that, the necessary filter coefficients are set using the SETFTSAMP and SETFTCOEF commands, and other information is set (command process L27), after which the necessary FIR filter processing is executed using the FTEXECFIR command (command process L28).The image data after filtering is then stored in the index space specified by instruction command L26, so by executing the SPRITE command after activating the SETTXMODE command (command process L29), the image data that has undergone FIR filtering will be drawn in an appropriate rectangular section in the virtual drawing space.

[0182] 11(c) is a diagram illustrating an example of an operation in which scaling processing is performed using a filter execution command. First, the SETFTINDEX command sets the destination index space where the reference texture to be scaled should be saved (command process L30), and then the LOADTX command retrieves the reference texture from the external memory 55 specified by the setting parameters of that command (command process L31).

[0183] Next, the SETTXINDEX command is used to set an index space for storing auxiliary data required for scaling (command process L32). The auxiliary data is plane information extracted from the reference texture and characterizes the reference texture. The reason why such auxiliary data is important is that the scaling process of this embodiment involves deformations of dissimilar shapes, not similar shapes, and therefore appropriate interpolation processing is performed to eliminate unnaturalness in the image after deformation.

[0184] Therefore, in the scaling process of this embodiment, following command L32, the FTEXECGRD command is written to generate auxiliary information (plane information) in the index space specified by command L32 (command process L33). The necessary preparations are completed with the commands up to this point, so next, the SETTXINDEX command is used to set the index space to be used as the texture (command process L34), and after setting the necessary information with the SETTXSAMP command, the scaling process is executed with the SETTXMODE command (command process L35).

[0185] As a result of the above, the image data after scaling is saved in the index space specified by instruction command L34, so by activating the SETTXMODE command and then executing the SPRITE command (command processing L36), the image data after scaling is drawn in an appropriate rectangular section in the virtual drawing space.

[0186] The image filter circuit 75 has been described above, but the GDEC circuit 73 performs decoding processing by software processing corresponding to each compression algorithm for compressed data such as streaming video, still images, and other α values. In this embodiment, streaming video is divided into S streams, IP streams, and IPB streams, and the frames that make up the streaming video are composed of an appropriate combination of I pictures, S pictures, P pictures, or B pictures.

[0187] An I (Intra coded) picture refers to an intra (intra-picture) coded picture, and refers to image data obtained by compressing an input image as is, independent of other pictures. On the other hand, an S picture is image data that is predictively coded by referring to the I pictures immediately before and after it, and has the advantage of a higher compression rate than an I picture. The S stream video of this embodiment is a video that combines these I pictures and S pictures, and by arranging the I pictures according to a fixed cycle, random access and reverse playback starting from the I picture can be performed, thereby realizing effective image presentation. Note that S stream video that does not include S pictures is also possible, and S stream video without S pictures is essentially the same as I stream video.

[0188] Next, a P picture (Predictive coded) is image data that undergoes forward predictive coding, which predicts the current frame from a temporally past frame, and is predictively coded from an I picture or P picture located in the past. On the other hand, a B picture (Bidirectional coded) is image data that undergoes bidirectional predictive coding, which performs forward prediction as well as backward prediction, which predicts the current frame from a future frame, and is predictively coded from an I picture or P picture located in the past and future.

[0189] Generally, inter-frame prediction techniques include forward prediction, which predicts the current frame from a past frame, backward prediction, which predicts the current frame from a future frame, and bidirectional prediction, which performs backward prediction in addition to forward prediction.B pictures perform bidirectional prediction, which allows for improved prediction accuracy.

[0190] Therefore, in this embodiment, in addition to S-stream video, which is a combination of I-pictures and S-pictures, it is configured to be able to play IP-stream video and IPB-stream video, which are appropriate combinations of I-pictures, P-pictures, and B-pictures. Note that IP-stream video is made up of a combination of I-pictures and P-pictures, and IPB-stream video is made up of a combination of I-pictures, P-pictures, and S-pictures.

[0191] As is clear from the above relationship, in S stream video containing S pictures and IPB stream video, due to the need for backward predictive coding, it is necessary to acquire and decode I pictures and P pictures that will be played back later in time before acquiring S pictures and B pictures.

[0192] Therefore, this embodiment is configured so that one LOADTX command can specify multiple textures, i.e., main-frame CG data and sub-frame CG data. Here, main-frame refers to CG frame data that should be played at the current timing, and sub-frame refers to CG frame data that should be played at a different timing.

[0193] For example, in an S picture, predictive coding is performed by referring to the nearest (previous or next) I picture, so in an S stream video that consists of a series of I pictures and S pictures, the CG data for the S picture as the main frame and the I picture as the sub-frame can be obtained and decoded with a single LOADTX command.

[0194] Furthermore, since bidirectional predictive coding is performed on B pictures (bidirectional coded), it is necessary to reserve CG data of past frames and CG data of future frames in a decoded state prior to the decoding process of the B picture. Therefore, in this embodiment, when playing IPB stream video, it is necessary to reserve a first reference buffer for storing past frames and a second reference buffer for storing future frames prior to this playback operation. The reference buffer is an index space with sufficient capacity to store reference images, and is reserved in any area of ​​the VRAM 53 or expansion RAM 54 and identified by a unique index number.

[0195] Figure 12 explains the playback procedure for IPB video streams, with the playback operation progressing from top to bottom of the page. Figure 12 is divided horizontally into six sections, showing, from left to right, (1) the LOADTX command on the display list DL, (2) pictures constituting the IPB video stream, (3) mainframe and subframe decoding processing, (4) reference image decoding processing, (5) a reference buffer where the reference images are stored, and (6) an index space (expansion space) where the decoded images displayed on the display screen are stored.

[0196] The downward arrow in the first column indicates the transition of the operating cycle of the general performance circuit 52 (GDEC circuit 73), which operates intermittently, and the downward arrow in the sixth column indicates the display order of the images displayed on the display device DS. In the following explanation, for convenience, a group of video frames played at timings T1 to T7 is referred to as a GOP (Group Of Picture), but the GOP can be changed as appropriate based on the embedded parameters of the LOADTX command on a series of display lists for video playback.

[0197] First, the LOADTX command at timing T1 to play back an I-picture specifies the addresses of the I-picture (I1) as the main frame and the P-picture (P1) as the sub-frame by the embedded parameters of the command, as well as the index number of the expansion space where the decoded data should be stored.

[0198] Therefore, the I-picture (I1) acquired based on the instruction of the LOADTX command at timing T1 is decoded and stored in the first reference buffer that stores past frames, along with the original expansion space. In other words, in this embodiment, the decoded result of a given image data (I-picture) is stored in both the first and second buffers.

[0199] Furthermore, the LOADTX command at timing T1 instructs the P picture (P1) to be acquired, and the decoded data is stored as a reference image in the second reference buffer for storing future frames. Although not limited to this, the reference image is stored in a compressed state using a special method.

[0200] Next, the LOADTX command at timing T2 specifies only the B picture (B1) as the main frame. Then, as a bidirectional prediction operation, the image data B1 of the current frame is reproduced based on the I picture (I1) in the first reference buffer, the P picture (P1) in the second reference buffer, and the B picture (B1), and is saved in the decompression space.

[0201] As described above, the reference image in the reference buffer is compressed using a special method, and the compressed reference image is decompressed appropriately based on the embedded parameters of the LOADTX command (instructions to restore the image in the reference buffer). That is, the decode command (LOADTX) of this embodiment may instruct decoding of not only the basic data stored in the ROM area (external memory 55) but also the basic data stored in the RAM area based on the embedded parameters.

[0202] The same applies to the following LOADTX command at timing T3, which reproduces the image data B2 of the current frame based on the I picture (I1) in the first reference buffer, the P picture (P1) in the second reference buffer, and the B picture (B2) and stores it in the decompression space.

[0203] Next, the LOADTX command at timing T4 when a P picture should be played back instructs that the P picture (P1) serving as the main frame should be retrieved from the second reference buffer by the embedded parameters of the command, and also specifies the address of the P picture (P2) serving as the sub-frame.

[0204] Therefore, at timing T4, the P picture (P1) in the second reference buffer, which has been compressed using a special method, is decompressed and saved in the decompression space, and the P picture (P1) is stored in the first reference buffer as a past frame image for subsequent processing. Furthermore, a future P picture (P2) is acquired in response to the instruction of the LOADTX command at timing T4, and its decoded data is saved in the second reference buffer as a reference image for the future frame.

[0205] The subsequent operations at timings T5 and T6 are substantially the same as those at timings T2 and T3. That is, at timing T5, a B3 picture image based on the P picture (P1) in the first reference buffer, the P picture (P2) in the second reference buffer, and the B picture (B3) is rendered in the rendering space based on bidirectional prediction. At timing T6, a B4 picture image based on the P picture (P1) in the first reference buffer, the P picture (P2) in the second reference buffer, and the B picture (B4) is rendered in the rendering space.

[0206] Next, the LOAD command at timing T7 instructs that a P picture (P2) serving as a main frame should be retrieved from the second reference buffer. The address of the I picture (I2), a sub-frame, is also specified. Therefore, at timing T7, the P picture (P2) in the second reference buffer is decompressed and stored in the decompression space. The LOADTX command at timing T7 also instructs that an I picture (I2) be retrieved, and the decoded data is stored in the second reference buffer as a reference image for a future frame.

[0207] At the next timing T9, an instruction is issued to retrieve an I-picture (I2) as a main frame from the second reference buffer. Therefore, the I-picture (I2) in the second reference buffer is decompressed and saved in the decompression space, and the I-picture (I2) is stored in the first reference buffer as a past frame image for subsequent processing. Note that the LOAD command at timing T9 specifies the address of the P-picture (P3), which is a sub-frame, so the P-picture (P3) is retrieved and its decoded data is saved in the second reference buffer as a reference image for a future frame.

[0208] 13(a) is a block diagram showing the internal configuration of the audio processing unit SND. As shown in the figure, the audio processing unit SND is divided into a pre-processing unit FT in which 64-track processing blocks are arranged so that they can operate in parallel, a post-processing unit BK consisting of a master effect unit, a master volume unit, an output protection unit, and a serializer, and a mixer MX that transmits the output of the pre-processing unit FT to the post-processing unit BK.

[0209] As shown in the figure, the pre-processing unit FT is provided with 64 decoders that receive compressed audio data (compressed phrase data) from the external memory 55. Meanwhile, the post-processing unit BK is configured to be able to output audio signals SDOUTA to SDOUTD of four paths A / B / C / D as serial data together with the clock signal SBCLK and the control signal SLRCLK via a serializer. The serial data SDOUTA to SDOUTD of the four paths A / B / C / D each contain right data R and left data L on one data line, and depending on whether the control signal SLRCLK is in an H level period or an L level period, it is determined whether the serial data SDOUTA at that timing is left data L or right data R.

[0210] Next, the internal operation of the preprocessing unit FT will be explained. The phrase data decompressed by the decoder has its volume adjusted appropriately in the primary volume, secondary volume, and panpot units. Here, the primary volume and secondary volume are responsible for two-stage volume adjustment, and the panpot unit adjusts the volume ratio between the left and right speakers. The specific operations of the primary volume, secondary volume, and panpot units are each specified by a voice command listed in the voice command list VC.

[0211] Phrase data is audio data that realizes one unit of audio performance, and includes one unit of audio performance such as a piece of background music for one song, sound effects, or shouts. One phrase data is output to eight paths from the panpot section of the pre-processing section FT. As shown in the figure, in this embodiment, 64-track processing blocks (pre-processing sections FT) are arranged to be able to operate in parallel, and up to 64 phrase data can be output to the mixer MX. The audio data collected on eight paths, which are left and right audio R / L on four paths A / B / C / D, is transmitted to the post-processing section BK.

[0212] The panpot section can adjust the volume ratio between the left and right speakers, so for example, the panpot section of the first track can set the left and right volume ratio to maximum:zero and output only to the first line of mixer MX, while the panpot section of the second track can set the left and right volume ratio to zero:maximum and output only to the second line of mixer MX. As a result, for example, the first phrase data, which is the left audio, will be output only to the first line, and the second phrase data, which is the right audio, will be output only to the second line, making it possible to play in stereo with the left and right speakers of system A.

[0213] Next, the internal operation of the post-processing unit BK will be explained. The master effect performs audio filtering, and the master volume determines the volume. The specific operations are specified by the voice commands listed in the voice command list VC. The master volume is used, for example, to provide a silent warning that instantly silences the volume effect, while the master effect is used, for example, to provide a warning that the sound quality will be changed drastically.

[0214] 13(b) illustrates the relationship between the voice command list VC and the voice effects realized by the voice commands written in the voice command list VC. Here, a START command for instructing the start of playback of specific phrase data, a PAUSE command for instructing the stop of playback of specific phrase data, a RESUME command for instructing the restart of playback of specific phrase data, and a STOP command for instructing the end of playback of specific phrase data are shown as examples. The voice command list VC is composed of one or more voice commands written therein, but must be terminated by a predetermined end command EOSC.

[0215] First, in the voice command list VC1, the start of reproduction of 64 types of phrase data is instructed by voice commands START1 to START64. Therefore, when the decoding process of the 64 types of compressed phrase data is completed, the reproduction operation of the 64 types of phrase data is started.

[0216] Next, since the voice command list VC2 contains the voice commands PAUSE1, PAUSE2, and STOP64, playback of the phrase data 1, 2, and 64 is paused or stopped. After that, the voice command list VC2 contains the voice commands RESUME1 and RESUME2, so playback of the paused phrase data 1 and 2 is resumed.

[0217] The voice command list VC can be output not only at the start and end of phrase data playback, but also at any necessary timing in the operation cycle δ (= 1 / 30 seconds) of the overall performance circuit 52. In other words, the display list DL is output for each operation cycle δ of the overall performance circuit 52, but the voice command list VC is generally output irregularly.

[0218] Next, the drawing pipeline processing executable in the drawing circuit 74 will be described. Fig. 14(a) illustrates the portion of the drawing circuit 74 that is relevant to the drawing pipeline processing. The display list analyzer sequentially analyzes the instruction commands written in the display list DL and transfers the instruction commands to an appropriate internal circuit according to their type. Note that in Fig. 14(a), the instruction commands are specifically referred to as drawing commands, and in the following description, the instruction commands may also be referred to as drawing commands.

[0219] The internal circuits that receive the drawing commands are configured to operate in parallel, and the display list analyzer analyzes the drawing commands written in the display list DL in the order they are written, and transfers the drawing commands to the corresponding internal circuits one after another (see Figure 14(a)).

[0220] Incidentally, the internal circuitry of the drawing circuit 74 operates asynchronously with the CPU circuit 51 that issues the display list DL and the data transfer circuit 70 that transfers the configuration data of the display list DL in sequence, and in general, the operating speed of the internal circuitry of the drawing circuit 74 is much slower than the transfer speed of the configuration data of the display list DL.

[0221] Therefore, the internal circuit that receives the drawing commands is provided with a standby queue that stores drawing commands before processing begins, and the display list analyzer puts the drawing commands into the standby queue on the condition that there is space in the standby queue. In other words, the display list analyzer stalls (temporarily stops) the putting operation until the standby queue becomes empty, so there is no risk of the drawing commands being lost. Note that the numbers shown for the standby queue are merely an example of the number of stages in the queue.

[0222] As explained above, the instruction commands written in the display list DL include: (1) index table control commands related to the index table IDXTBL that manages the index space; (2) texture load commands such as the LOADTX command for reading and decoding (decompressing / expanding) image material (texture) from the external memory 55; (3) filter execution commands that specify the filter processing to be performed on the decompressed image data; (4) drawing commands such as the SPRITE command for placing the decoded (expanded) image material at a predetermined position in the virtual drawing space; and (5) pipeline commands related to drawing pipeline operations.

[0223] 14(a), an index table control command (1) is transferred to the control circuit of the index table IDXTBL, a texture load command (2) is transferred to the GDEC circuit 73, and a filter execution command (3) is transferred to the image filter circuit 75, and each is processed appropriately by the circuit to which it is transferred. Specifically, the GDEC circuit 73 operates based on the transferred drawing command (texture load command), obtains the required texture, and expands the decompressed data into the decode space.

[0224] Furthermore, the index table IDXTBL is updated as appropriate by the functioning of the control circuit for the index table IDXTBL. The image filter circuit 75 performs a specified filter process on a predetermined reference texture and stores the filter process result in a predetermined index space (see FIG. 11). When a predetermined drawing command (high-speed transfer command) is received, the high-speed transfer circuit TRNS functions to transmit and receive data at high speed between the VRAM 53 and the expansion RAM 54. The high-speed transfer circuit TRNS is an internal circuit of the drawing circuit 74 and is a circuit separate from the data transfer circuit 70.

[0225] When using the data transfer circuit 70, the CPU circuit 51 must set the type of source medium and transfer start address, the type of destination medium and receiving start address, and transfer size in a specified performance control register RGij (data transfer register), but the high-speed transfer circuit TRNS has the advantage of being simple, being able to function when needed using an instruction command (transfer execution command) from the display list DL, and also being able to transfer two-dimensional data at high speed in units of index space. Note that, without adopting the configuration of this embodiment, it is not easy in terms of program configuration to use the data transfer circuit 70 only when necessary in a control program that is constantly functioning.

[0226] As explained above, the rendering pipeline operation is performed using the vertex buffer VB built into the rendering circuit 74, the frame buffer FB reserved as an index space, and the depth / stencil buffer that manages the front-to-back relationship of polygons and whether or not pixels are displayed, and is configured to execute an input assembler process IA, a geometry engine process TL, a rasterizer process RS, a texture sampler process TX, a texture process PS, a pixel drawing process PX, and a render process RO as needed.

[0227] That is, the rendering pipeline processing is executed from upstream to downstream, passing through all or some of the processes in the following order: Process IA → Process TL (Process VB) → Process RS → Process TX → Process PS → Process PX → Process RO. Each process operates in parallel, but since the downstream processes take longer to complete the execution of rendering commands, the number of stages in the waiting queue that stores the rendering commands input to each process is configured so that it is not less than the number of stages in the waiting queue on the upstream side.

[0228] As shown in Figure 14(a), the number of stages in the waiting queue is 1 stage → 5 stages → 14 stages → 18 stages → 18 stages → 23 stages, corresponding to process IA → process TL → process RS → process TX → process PS → process PX → process RO, and the number of stages at each process is the same as or greater than the number of stages in the waiting queue upstream.

[0229] The pipeline commands described above are setting commands that specify the operation details of each pipeline process (IA, TL, VB, RS, TX, PS, PX, RO). The acquired pipeline commands are transferred to the parameter setting unit SET, which sets the operating parameters required for the necessary internal circuits, such as the geometry engine.

[0230] In this embodiment, as shown in FIG. 14(b), the drawing pipeline is composed of step IA, step TL, step RS, step TX, step PS, step PX, and step RO. First, the input assembler step IA acquires the vertex stream of a three-dimensional 3D drawing object, which is usually defined in local coordinates, stores the information required for subsequent processing, and outputs vertex data having predetermined vertex information.

[0231] In this process IA, in addition to the setting commands for process IA (pipeline commands), drawing commands such as the DRAW command and the DRAWD command are used. The DRAW command specifies the starting address of the memory (external memory 55 in this embodiment) in which a series of vertex streams are stored, and the number of vertices.

[0232] On the other hand, a DRAWD command has a series of vertex streams embedded in it. The specific operation of the DRAW command and the DRAWD command is specified by the embedded information of each command and the setting commands for process IA. Note that a vertex color (RGBA color information) can be specified for each vertex in the vertex stream, but if a vertex color is not specified, a default value is set as the vertex information in the input assembler process IA. Here, RBG refers to color information of R=Red, B=Blue, and G=Green, and A is an alpha value α that indicates opacity and is used in the alpha blending process when overlapping images.

[0233] The following geometry engine process TL performs matrix operations to transform the vertex coordinates of the 3D drawing object and lighting processing related to light sources, etc., on the vertex data output from the input assembler process IA. The coordinate transformation process performs view matrix operations to transform local coordinates into view coordinates and matrix operations for projective transformation (perspective projection).

[0234] Here, the view coordinate system is a coordinate system in which the viewpoint is the origin and the point at infinity (0,0,-∞) is the line of sight. In projective transformation, in order to realize a sense of perspective that corresponds to the placement position of the 3D drawing object, the view coordinate system is transformed into the clip coordinate system by enlarging or reducing the shape of the 3D drawing object.

[0235] The specific content of the matrix operation is specified by the setting command (pipeline command) for the TL process, and the execution of a specified geometry matrix operation is instructed by the DRAW command or DRAWD command. Therefore, process IA and process TL can be executed together with a single drawing command (DRAW / DRAWD). However, in either case, the execution result of the geometry matrix operation by the drawing command (DRAW / DRAWD) is saved in the vertex buffer VB.

[0236] The geometry engine process TL is not essential, and when a vertex stream defined by clip coordinates is acquired from the external memory 55, the information passes through the input assembler process IA and is stored directly in the vertex buffer VB. The input assembler process IA and the geometry engine process TL may be repeated for multiple 3D drawing objects, and the vertex buffer VB is configured to be able to store a maximum of 256 vertices.

[0237] Next, in the rasterizer process RS, primitives are generated and drawn based on the vertex information in the vertex buffer VB, and pixel data for 3D drawing objects is generated after removing polygons that do not need to be drawn by converting from the clip coordinate system to the window coordinate system, clipping, culling, scissoring, etc. In other words, a three-dimensional 3D image object is determined to be placed at a predetermined position and with a predetermined orientation in the window coordinate system (world coordinates) corresponding to the virtual drawing space.

[0238] To generate primitives, a triangle drawing method such as a triangle list, triangle strip, or triangle fan, or a line drawing method such as a line list, line strip, or line fan can be selected and used as appropriate.

[0239] In addition, in the rasterizer process RS, in addition to setting commands (pipeline commands) for the RS process that specifically define the processing content, drawing commands DRAW command, DRAWD command, DRAWI command, and SPRITE command are used as appropriate.

[0240] Here, the DRAWI command generates and draws primitives based on vertex data obtained from the vertex buffer VB, while the DRAW command generates and draws primitives based on a vertex stream obtained from external memory 55, and the DRAWD command generates and draws primitives based on a vertex stream embedded in the command.

[0241] Therefore, the rasterizer process RS can be executed without going through the geometry engine process TL. For example, in the case of a two-dimensional (2D) drawing object, the geometry engine process TL is not particularly necessary. In either case, each polygon generated through the rasterizer process RS has RGBA color information for each pixel based on the vertex color for each vertex.

[0242] Next, in the texture sampler process TX, the index space to be used as the texture and the texture coordinates for each pixel are specified. Then, in the texture process PS, the pixel color obtained in the rasterizer process RS and the texture color are calculated appropriately.

[0243] In these steps TX and PS, and the following step PX, in addition to the setting commands (pipeline commands) in each step, the drawing commands DRAW, DRAWD, DRAWI, and SPRITE are used as appropriate. With the DRAW, DRAWD, or DRAWI command, a texture is pasted into the area surrounded by specified vertices, and with the SPRITE command, a texture is pasted into a specified rectangular area.

[0244] Then, in the subsequent pixel drawing process PX, the drawing color and background color are combined, and tone mapping and inverse tone mapping are performed to adjust contrast. In this PX process, pixel data containing predetermined information is input for each pixel from the texture process PS, and data (background color) stored at the pixel drawing position is input for each pixel from the frame buffer FB.

[0245] The final rendering step RO refers to the depth and stencil buffers and performs a pixel test to determine whether or not to display the pixel based on the pixel's depth and stencil information, and then performs alpha blending on overlapping multiple drawing objects before writing the completed drawing object to the frame buffer FB. Writing to the frame buffer FB is nothing more than drawing in the virtual drawing space shown in Figure 7, and normally the SPRITE command is used.

[0246] In addition to the DRAW, DRAWD, DRAWI, and SPRITE commands, the rendering process RO can also use the CLEAR command, which fills the frame buffer FB with a single color, and the CLEARZ command, which fills the depth and stencil buffers with a single color. The CLEAR command is used to clear the frame buffer FB prior to the start of drawing operations, and the CLEARZ command is used when depth information and stencil information are not required.

[0247] In this way, in the present invention, all or some of the series of drawing pipeline processes function, and two-dimensional or three-dimensional drawing objects are written one after another into the frame buffer FB, ultimately completing image data for one frame of the display device. Note that in this embodiment, two-dimensional and three-dimensional drawing objects are distinguished by whether or not they undergo three-dimensional coordinate conversion processing.

[0248] Figure 15 is a process diagram showing various rendering modes that use all or part of the rendering pipeline processes. First, the rendering mode in Figure 15(a) is an operating mode that uses the above-mentioned CLEAR command and CLEARZ command, and only the render process RO functions.

[0249] 15(b), the rasterizer process RS, texture sampler process TX, texture process PS, pixel drawing process PX, and render process RO function. Note that the rasterizer process RS simply adds an offset value to the X and Y coordinates of the vertices of the window coordinate system, but this offset value is related to the rectangular area where the SPRITE command is pasted.

[0250] In actual operation, the SETTXINDEX command sets the destination index space, the LOADTX command acquires a specified texture and deploys it in the index space, and the SPRITE command secures this deployed texture in a specified location. The deployed texture information is then referenced and ultimately written to the frame buffer FB. In principle, video playback and playback of simple still images are realized in this sprite drawing mode, but preferably all still images and / or all video playback are played in sprite drawing mode.

[0251] The rendering mode shown in Figure 15(c) is an example of an operation in which triangle rendering and line rendering are performed using all processes of the rendering pipeline. Note that the only difference between triangle rendering and line rendering is the method of generating primitives. In either case, primitives are identified and rendered based on the vertex stream of the 3D rendering object supplied to the input assembler process IA.

[0252] 15(d) shows a drawing operation using the DRAW command, DRAWD command, etc., in which pixel data for a drawing object is generated in the rasterizer process RS without performing coordinate transformation processing. This operation is typically used when displaying a two-dimensional (2D) drawing object, the contour of which can be identified by a vertex stream, on a display screen.

[0253] Figures 15(e) and (f) show operation modes when vertex data is stored in the vertex buffer VB, and are divided into (e) when coordinate transformation processing is performed and (f) when coordinate transformation processing is not performed. These operations are executed by the DRAW command and DRAWD command. Figure 15(g) shows an operation mode that uses vertex data stored in the vertex buffer VB, and is executed by the DRAWI command.

[0254] As described above, the rendering pipeline of this embodiment can be used in various ways. For example, playback of 2D still images and streaming video (S stream, IPB stream, IP stream) requires simple sprite rendering, so the playback operation is realized in the operating mode of Figure 15(b), as described above.

[0255] As explained above, the display analyzer determines the drawing commands in the display list DL and transfers them to the processing blocks of the pipeline steps corresponding to the drawing commands. The transferred drawing commands are then first put into the waiting queues of the respective pipeline steps, and the processing corresponding to the drawing commands is executed in the order of their entry.

[0256] However, the operation of the data transfer circuit 70 that transfers the display list DL is much faster than the progress of this rendering pipeline, so if, for example, you want to display multiple 3D rendering objects on the screen and also other 2D rendering objects on the screen, you will have to wait a long time for the execution of the SPRITE command in the rendering process RO.

[0257] In other words, since it takes a certain amount of time to process the coordinate transformation matrix for a 3D drawing object, a large number of sprite commands will accumulate in the standby queue of, for example, an RO process. However, in this embodiment, as explained above, the input of drawing commands is put on hold until the standby queue is empty (stall state), and moreover the number of stages in the standby queue of a downstream process is the same as or greater than the number of stages in the standby queue of an upstream process, so the commands written in the display list DL can be executed smoothly in the order they are written.

[0258] Note that the execution of a drawing command transferred from the waiting queue is also put on hold (stall state) until the necessary start conditions are met, so that inconsistent drawing operations such as rewriting the index space do not occur.

[0259] Having explained the circuit configuration above, we will now explain the control operation by the CPU circuit 51. As explained above, when power is turned on, prior to the start of the control operation, a reset period occurs in which the system reset signal HRESET is maintained at L level for a predetermined period of time.

[0260] During this reset period, first, one or two oscillator circuits that control the operation of the integrated performance circuit 52 and the built-in CPU circuit 51 start oscillating, and wait for the oscillation frequency of each system clock to stabilize. Next, the internal circuits of the composite chip 50 are initialized in synchronization with each system clock, and predetermined default values ​​are set in the performance control register RGij and the operation control register REG. Hereinafter, this operation will be referred to as a hardware reset (power-on reset) to distinguish it from the software reset described below.

[0261] When this hardware reset period ends, the built-in CPU circuit 51 starts up together with the internal circuits of the composite chip 50. The operation after the power-on reset will be described below with reference to Fig. 16. The operation of steps SP1 to SP10 in Fig. 16 is realized as an internal operation of the CG bus IF unit 55a without being controlled by the CPU circuit 51.

[0262] That is, after a power-on reset, the internal control circuit including the SATA controller of the CG bus IF unit 55a executes the processing of steps SP2 to SP7 up to four times (SP1). However, in the processing of steps SP2 to SP7, the control of the CPU circuit 51 is not particularly prohibited, and the CPU circuit 51 and the CG bus IF unit 55a can cooperate to realize the same operation by appropriately issuing a "CG bus command" that controls the CG bus IF unit 55a.

[0263] Based on the above, the control operation of the internal control circuit of the CG bus IF unit 55a will be explained. First, the internal control circuit determines the type of memory device storing the boot program and the security mode of the gaming machine based on the information from the HBTSL terminal (FIG. 6(a)) of the composite chip 50. The type of memory device storing the boot program is specified as either a normal parallel / serial ROM device or a SATA device, and the security mode is specified as whether user authentication is required, whether the ROM data (including the program) is obfuscated, etc.

[0264] In this embodiment, as shown in FIG. 6(a), the 3-bit HBTSL terminal is, for example, all at H level, which identifies that (1) the boot program is stored in the SATA device, (2) user authentication is required at the time of startup, and (3) the ROM data (including the program) is obfuscated.

[0265] Based on this information, the internal control circuit of the CG bus IF unit 55a first executes an RST assert command (a type of CG bus command) to establish serial communication with the SATA device (SP2). Specifically, it outputs an initialization signal XRST, which is a negative logic pulse, to the external ROM 55, which is the SATA device.

[0266] The timing for outputting the initialization signal XRST is after the reset period by the system reset signal HRESET has elapsed. Therefore, when power is turned on, the SATA device (external memory 55) that receives the RESET signal from the watchdog timer 56 at the hard reset terminal HRST has reliably completed the hardware reset operation at the timing when the initialization signal XRST is output. In other words, the external memory 55 receives the initialization signal XRST after completing the hardware reset operation.

[0267] Upon receiving the initialization signal XRST at the soft reset terminal NIT_REQ, the external ROM 55 executes a PHY (Physical Layer) reset operation and a MAC (Media Access Control) reset operation. In response to these reset operations, the internal control circuit of the CG bus IF unit 55a operates, thereby realizing the best possible communication environment between the external ROM 55 (a SATA device) and the SATA controller of the combined chip 50. The fastest communication speed of 6 Gbps is first attempted, and if this is difficult, 3 Gbps is adopted. In this embodiment, the communication speed is set to one of two levels, but three or more levels are also suitable. In either case, the communication speed is gradually decreased from the fastest speed to establish appropriate communication.

[0268] Next, the internal control circuit of the CG bus IF unit 55a performs READ access to the SATA device 55 to obtain the configuration data stored in the head area of ​​the external ROM 55 (SP3). The configuration data refers to setting data related to the operation of the combined chip 50, and specifically includes (1) CPU exception vector, (2) data protection parameters (obfuscation key), (3) CG bus address space setting, (4) CPU offset setting, and (5) non-obfuscated information required for device I / F setting.

[0269] The validity of the acquired configuration data is then determined by a CRC check or the like (SP4), and if a CRC error or the like occurs, the process returns to step SP1 and starts again from the process of constructing the communication environment (SP2).

[0270] However, since the determination in step SP4 is normally a normal determination, the internal control circuit then transmits a randomly generated random number value Seed to the external ROM 55, which is a SATA device (SP5), and then obtains from the SATA device 55 a hash value generated by the SATA device 55 based on this random number value Seed (SP6).The SATA device 55 then executes a predetermined hash function based on the random number value Seed received from the composite chip 50 and a unique CHAP key secured and stored for each gaming machine manufacturer, and returns the resulting hash value to the CG bus IF unit 55a.

[0271] The internal control circuit of the CG bus IF unit 55a then determines whether the hash value acquired from the SATA device 55 matches the hash value it generated (SP6). Here, the internal control circuit calculates the hash value by running a hash function based on the user ID terminal-set on the circuit board of the composite chip 50 and the random number value Seed it generated in the processing of step SP5. The hash function used by the internal control circuit of the CG bus IF unit 55a is the same as the hash function that functions inside the SATA device 55.

[0272] If the two hash values ​​do not match, the process returns to step SP1 (SP7), and in the present embodiment, user authentication is ultimately performed through the processes of steps SP5 and SP6. If user authentication is not successful, the initialization signal XRST remains at L level (SP8), and no control operation is initiated.

[0273] In other words, according to the configuration of this embodiment, only SATA devices certified in advance by the chip manufacturer can be installed in each gaming machine, which reliably prevents tampering with ROM data and alteration of game control programs and game control data. Furthermore, copyright protection is also achieved by prohibiting data reading using a debugger, etc. These protection functions are particularly effective in the secondhand market, eliminating the risk of gaming machines being modified to have gameplay not intended by the gaming machine manufacturer.

[0274] Next, a case where the user authentication is successful in the determination of step SP7 will be described. After the determination of step SP7 is completed, next, a process of setting necessary parameters is executed to realize scrambling processing corresponding to the user (gaming machine manufacturer) (SP9).

[0275] Specifically, as shown in Figure 17(a), an obfuscation key specific to the user is generated based on an obfuscation key specific to the user stored in the SATA device 55 and a user ID that is fixedly set on the circuit board, and descrambling processing specific to the user is enabled based on this obfuscation key.

[0276] As explained in relation to Figure 17, the CG compressed data stored in the SATA device 55 is obfuscated using a user-specific algorithm (scrambling process), but by undergoing the above-mentioned user-specific descrambling process, the obfuscated CG compressed data and program read from the SATA device 55 can be used normally during subsequent game performance operations.

[0277] Note that although the descrambling process does not function before step SP9, the configuration data and other data are not obfuscated and there is no problem. On the other hand, if the process of step SP9 fails, the descrambling process will not function thereafter either, and the CG compressed data and programs read from the SATA device 55 will not function properly, thereby realizing reliable security.

[0278] After the processing of step SP9 is completed, the configuration data read in step SP3 is executed (SP10). As explained in relation to step SP3, the configuration data includes information necessary for (1) CPU exception vector, (2) data protection parameters (obfuscation key), (3) CG bus address space settings, (4) CPU offset settings, and (5) device I / F settings.

[0279] First, (1) based on the CPU exception vector, the built-in CPU circuit 51 constructs an address table (Interrupt Vector Table) of the exception handler (processing program) (FIG. 17(c) SP10a). The Interrupt Vector Table is a management table that lists the start addresses of exception processing programs (exception handlers) that process exceptions or interrupts when they occur in the CPU 57. Note that (2) the use of data protection parameters (obfuscation keys) has already been processed, as explained in step SP9.

[0280] Next, (3) CG bus address space setting is executed. CG bus address space setting refers to the process of dividing the CG bus address space, which has a maximum length of 256 GB, into chip select spaces CS0 to CS3 as appropriate (FIG. 17(c) SP10b). However, the chip select space CS0, which starts from address 0, is defined in advance, and in this embodiment, the chip select space CS0 is assigned to the SATA device 50.

[0281] That is, in this embodiment, as shown in Figure 17(d), the chip select space CS0 is allocated to an 8GB long SATA device 50, the first 512 bytes of which are the configuration data area, followed by the boot program, game control program, game control data, CG compressed data, etc.

[0282] Therefore, when using additional memory modules, the chip select space CSi is secured by setting the starting address (boundary position) and module type in the corresponding performance control register RGij after the chip select space CS0 based on the CG bus address space setting information, which is the configuration data.

[0283] Next, we will explain (4) CPU offset setting. CPU offset setting refers to the operation of changing the correspondence between the first 2 GB space of the CPU address space and the CG address space (Fig. 17(c) SP10c). In other words, in the initial state after power-on, the first 2 GB space of the CPU address space is mapped to the first 2 GB space of the CG address space based on the default value of the corresponding performance control register RGij (see Fig. 17(d)), but this mapping relationship can be changed by the offset value set in a specified register RGij.

[0284] To explain further, in this embodiment, the first 2 GB of the CPU address space is managed as 16 memory banks, each consisting of 128 MB (= 134,217,728) bytes. By setting an appropriate address value as an offset value for each of the 16 memory banks, the first 2 GB of the CPU address space corresponds to a CG bus address space that is the address value plus the offset value. For example, if the offset value for the first memory bank is set to 1000H, when the CPU accesses the area of ​​the first memory bank, which is 0000_0000H to 0800_0000H, the CPU actually accesses the CG address space of 0000_1000H to 0800_1000H.

[0285] However, in this embodiment, the mapping relationship is not particularly changed, so the CPU 57 of the built-in CPU circuit 51 can appropriately perform read access to the first 2 GB space of the CG address space. In principle, write access is also possible, but in this embodiment, the WP terminal of the SATA device 55 is maintained at H level, so write access is effectively ignored (FIG. 6).

[0286] 17(d), the first 2 GB space of the CG address space is the leading area of ​​the chip select space CS0, and stores configuration data, a boot program, a control program, control data, etc. Therefore, the CPU 57 of the built-in CPU circuit 51 can access these data for READ as needed.

[0287] Finally, (5) Device I / F Setting will be explained. Device I / F setting for a SATA device means setting a timeout value for detecting communication abnormalities (FIG. 17(c) SP10d). That is, in this embodiment, the timeout value, which is configuration data, is set in a predetermined performance control register RGij (SP10). The reason for providing such processing is that, since data is sent and received between the combined chip 50 and the SATA device 55 by handshaking, if a communication failure occurs due to an external disturbance, there is a risk that the data sent and received will stop.

[0288] For this reason, in this embodiment, the time from when a read request is made to the SATA device 55 until a response (read data) is returned is constantly measured, and this measured time is compared with the timeout value set in the processing of step SP10. If the time until the response exceeds the timeout value, an abnormal interrupt is automatically generated, and in the activated abnormal interrupt, a SATA initialization command (a type of CG bus command) is executed, thereby starting the same control operation as in step SP2 and restoring communication with the SATA device 55.

[0289] After the processing of step SP10, which has the various significances explained above, is completed, the control operation is performed by the CPU 57 of the built-in CPU circuit 51. If the CPU 57 is not involved in the processing of steps SP1 to SP10, the CPU 57 checks the status register RGij, which indicates the internal operating state of the CG bus IF unit 55a, and waits for the processing of steps SP1 to SP10 to end normally before starting the processing of step ST11.

[0290] In addition to the processing of steps SP10a to SP10c described above, it is also preferable to set a predetermined performance control register RGij to output an RST assert command or a SATA initialization command at predetermined time intervals prior to the processing of step ST11 in order to ensure the stability of communication (Fig. 17(c) SP10e). In any case, when all processing is completed, the status register RGij (operation completion flag) indicating this is set and the processing is completed (Fig. 17(c) SP10f).

[0291] After checking this operation completion flag, the performance control CPU 57 executes the processing from step ST11 onward. First, in step ST11, the CPU 57 loads the boot program stored in the external memory 55 into the internal RAM 59 or the like, and then executes this boot program to transfer the game control program and game control data from the external memory 55 to the expansion RAM 54. Note that in this embodiment, the boot program, game control program, and game control data are all obfuscated, but are automatically de-scrambled in the descrambling processing unit (FIG. 6) as they are read from the external memory 55 and pass through the CG bus IF unit 55a.

[0292] Thereafter, the performance control CPU 57 continues control operations based on the control program transferred to the expansion RAM 54. The control operations are divided into an initial setting process ST1 executed by the CPU 57 and regular processes ST3 to ST10, the details of which are shown in Figure 18. As shown by the dashed line, in this embodiment, an appropriate timeout value is set in (5) Device I / F Settings, so that even if a communication abnormality occurs, a SATA initialization command is executed in an automatically activated abnormality interrupt, and communication with the SATA device 55 is restored based on the same control operations as in step SP2.

[0293] The control operations executed by the performance control CPU 57 are as shown in Figure 18, and include a main process (a) consisting of an initial process and subsequent regular process, a timer interrupt process (b) that is started every 1 mS, a VBLANK interrupt process (c) that is started in response to a VBLANK signal output from the general performance circuit 52 at the start of the vertical blanking period of the display device DS, and a reception interrupt process (not shown) for receiving the control command CMD. The VBLANK signal is generated every 1 / 60 seconds.

[0294] As shown in Figure 18(b), in the timer interrupt process, a sensor signal is acquired to grasp the motor position, etc. (ST20), and when necessary, a lamp effect or a motor effect is started or progressed (ST21). In this embodiment, the lamp effect is realized by the operation of the effect control CPU 57 and the lamp control unit L_CTL based on the lamp drive data, which is the control data. The motor effect is realized by the operation of the effect control CPU 57 and the motor control unit MT_CTL based on the lamp drive data, which is the control data. In addition, in the VBLANK interrupt process, which is activated in response to the VBLANK signal, the interrupt counter VCNT is incremented and the process ends (ST25), as shown in Figure 18(c).

[0295] First, the main processing will be described for the case where the preloader 72 is not utilized. As shown in Fig. 18(a), first, an initial setting process (ST1) is executed, and appropriate setting values ​​are set in the performance control register RGij of the overall performance circuit 52 and the operation control register REG of the CPU circuit 51.

[0296] The setting process for the performance control register RGij includes reserving appropriate virtual working areas (AAC area, page area, optional area) in the VRAM 53 and the extended RAM 54 (see Figures 7(a) and 7(b)), and reserving index space essential for game control operations, such as the frame buffer FB. As explained above, the frame buffer FB is composed of a first buffer with index number N1 and a second buffer with index number N2.

[0297] The start address of the shared area (used as the AAC area in this embodiment) secured in the VRAM 53 is set in 4k byte units (the lower 15 bits are zero), and the area size is secured as an integer multiple of 4k bytes. Also, the page area secured in the expansion RAM 54 is set in 32k byte units (the lower 18 bits are zero), and the area size is secured as an integer multiple of 32k bytes.

[0298] The set values ​​in the operation control register REG include operation parameters for the watchdog timer WDT 58, which include an operation start instruction and a counter value. The WDT 58 in this embodiment is configured to count down an initial value (counter value), and by reloading the counter value before the count value reaches zero (underflow), activation of the WDT 58 is prevented.

[0299] On the other hand, when the count value underflows, a WDT reset request is generated, and the WDT 58 is activated, resulting in a software reset state. Then, as a standard operation, all internal circuits are initialized, and the values ​​of all registers RGij and REG except for specified registers are returned to their initial values ​​(default values), and the WDT 58 stops operating. Note that the register value that is exceptionally maintained is the register that indicates the operating state of the WDT.

[0300] However, in this embodiment, operations other than the standard operation described above are also possible, and (1) whether to initialize the internal circuit, and (2) whether to initialize the system clock circuit even if initialization is performed, can be arbitrarily selected by setting a corresponding value in a predetermined operation control register REG during the initial setting process after a hardware reset. Therefore, in this embodiment, based on the set value in the predetermined operation control register REG, when a software reset is performed, the internal circuit is not initialized and game operation resumes from the processing of step ST1.

[0301] Thus, in this embodiment, unlike the configurations of Prior Art Documents 1 and 2, even if the WDT 58 underflows, the hardware reset state is not entered, which has the advantage that the game operation can be resumed quickly. After the software reset, the WDT stops operating, so there is no risk of the software reset operation being repeatedly initiated.

[0302] When the initial setting process (ST1) including the above processes is completed, the intermittently executed steady-state process (ST2 to ST10) starts. As shown as step ST2 in Figure 18(a), the steady-state process starts when the interrupt counter VCNT becomes VCNT≧2, so the operation period (operation cycle) δ of the steady-state process is 1 / 30 seconds, corresponding to the operation period (1 / 60 seconds) of the VBLANK signal.

[0303] Then, in the processing of step ST3, after resetting the interrupt counter VCNT, it is determined whether or not the operation start conditions for starting normal operation are met. Specifically, a predetermined performance control register RGij indicating the operating state of the drawing circuit 74 is accessed for READ, and it is determined at this timing whether or not the drawing circuit 74 has completed the drawing operation based on the display list DL of the previous operation cycle. Also, in the drawing operation of the previous operation cycle, it is determined whether or not the memory access period of the drawing circuit 74 has exceeded the timeout time set in the time setting register TO based on the ON / OFF state of a predetermined abnormality flag.

[0304] If the abnormality flag is ON because the memory access of the drawing circuit 74 has taken an abnormally long time, even if the drawing circuit 74 has finished the drawing operation, it is determined that the operation start conditions have not been met, and the process proceeds to the performance command analysis process of step ST9.

[0305] The reason for skipping the processing of steps ST4 to ST8 is to avoid unreasonable screen display, since there is a possibility that normal image data may not be generated, including bit garbled command data, since the memory access of the drawing circuit 74 is taking an abnormally long time.

[0306] In the performance command analysis process (ST9), it is determined whether or not a control command CMD has been received from the main control board 21, and if a control command CMD has been received, the control command CMD is analyzed and necessary processing is performed. Here, the necessary processing includes a process for preparing to start a new variable performance based on the control command CMD that instructs the start of a variable performance, and a process for starting an error notification based on the control command CMD that indicates the occurrence of an error.

[0307] Next, the counter value is reloaded into the watchdog timer WDT 58, thereby preventing the watchdog timer 58 from starting (ST10). As explained above, even in the event of an abnormality that causes the watchdog timer 58 to start, the combined chip 50 of this embodiment enters a software reset state, which is different from a hardware reset. This completes the operation of this operation cycle, so the process proceeds to step ST2 and waits for the next VBLANK interrupt.

[0308] Although the above has explained the case where the operation start conditions are not satisfied, normally, after the judgment process of step ST3, the image data to be read by the display circuit 71 is identified based on the set value of the predetermined display register RGij, and the operation of the display circuit is started (ST4). As explained above, the frame buffer FB has a double buffer structure, and the first buffer and the second buffer are controlled by the set value of the predetermined display register RGij so that they toggle between each other.

[0309] Specifically, the index number N1 / N2 of the first buffer or second buffer specified as the "write area" by the display list DL of the previous operation cycle is set. By executing this step ST4, the "write area" of the previous operation cycle changes to the "read area" of the current operation cycle, so that the display circuit 71 outputs the image data completed by the drawing circuit 74 in the immediately previous operation cycle to the display device DS. In other words, the processing of step ST4 also includes an instruction to start the read operation of the display circuit 71.

[0310] When the processing of step ST4 having the above significance is completed, the performance control CPU 57 then completes a display list DL that specifies the image data that the display circuit 71 should output to the display device DS in the next operation cycle (ST5). Although not particularly limited, in this embodiment, a list buffer area (DL buffer BUF) in the built-in RAM 59 is reserved in advance, and the display list DL is completed there (see FIG. 9).

[0311] In principle, the display list DL is created every time with its contents changed for each operation cycle, but the leading area of ​​the display list DL contains a command that specifies the index number of the frame buffer FB. As explained earlier, the frame buffer FB is an index space with a double buffer structure, with index numbers N1 and N2. And, in order to use the double buffer in a toggle manner, each display list DL alternately specifies the frame buffer FB with index number N1 and the frame buffer FB with index number N2, rotating the "write area."

[0312] The performance control CPU 57 issues the display list DL thus completed to the general performance circuit 52 (ST6). Next, the performance control CPU 57 updates the performance scenario EN that centrally manages image performance, audio performance, lamp performance, and motor performance (ST7), and if it is the necessary performance timing, issues a voice command list VC to the audio processing unit SND to start or progress the audio performance (ST8).

[0313] When the start time of the motor or lamp performance managed by the performance scenario EN is reached, the timer interrupt process (FIG. 18(b)) executes the motor or lamp performance based on the corresponding motor drive data or lamp drive data. The processes of steps ST9 to ST10 following step ST8 are as described above.

[0314] 19(a) and 19(b) are flowcharts showing the specific contents of the display list DL issuing process (ST6), and Fig. 19(c) is a schematic diagram showing the operation contents of the DL issuing process (ST6). As explained with reference to Fig. 10, the display list DL issuing process can be performed in two ways: by accessing the CPU register port PORT by write access in 32-bit units (Fig. 10(a)), or by not accessing the CPU register port PORT (Fig. 10(b)). The operation contents of each are shown in Fig. 19.

[0315] First, referring to Figure 19(a), the performance control CPU 57 sets the transfer register RGij to use the data relay unit CH2 (data transfer channel CH2), and also sets the total size of the transfer data in a specified transfer register RGij (ST30).

[0316] Here, the display list DL has different contents for each operation cycle, but is issued after being terminated by a predetermined end command EODL. In this embodiment, the instruction commands used for the display list DL, including the end command EODL, are one word or multiple words (=N*32 bits), so no adjustment processing of the data amount is required. Therefore, the total size of the transfer data (display list DL) set in the transfer register RGij is any value that is an integer multiple of 32 bits.

[0317] Next, the performance control CPU 57 sets the number of writes corresponding to the total size of the transfer data in the management counter CN (ST31), starts the operation of the drawing circuit 74 (ST32), and then starts the operation of the data transfer circuit 70 (ST33). Here, the instructions to start the operation of the drawing circuit 74 and the data transfer circuit 70 are realized by setting processes to the predetermined drawing register RGij and transfer register RGij, respectively.

[0318] Next, the performance control CPU 57, while checking that the 130-stage CPU data FIFO circuit is not full, writes the configuration data of the display list DL to the CPU register port PORT in 32-bit units (ST35). Then, it continues the writing operation while decrementing the management counter CN (ST36, ST37).

[0319] As explained above, the CPU data FIFO circuit receives data in 32-bit units, while the data relay units CH0 to CH4 receive data in 1024-bit units. Therefore, in principle, when 1024 bits of data have accumulated in the CPU data FIFO circuit, the accumulated data is transferred to the data relay unit CH2, but when the set value for the transfer register RGij (the total size of the display list DL, which is the data to be transferred) is reached, the accumulated data in the CPU data FIFO circuit at that time is transferred to the data relay unit CH2.

[0320] The above process ends the DL issuing process (ST6) via the CPU register port PORT, but next, Figure 19 (b) shows an example in which the data transfer circuit 70 reads the display list from the list buffer (DL buffer BUF) without going through the CPU register port PORT. In this case, the performance control CPU 57 sets the transfer register RGij to use the data relay unit CH2 (ST40), and also sets the total size of the transfer data and the starting address of the list buffer BUF in the specified transfer register RGij (ST41).

[0321] As explained above, the starting address of the list buffer BUF set in the internal RAM 59 must be set in 8-bit units, so the lowest 7 bits of the starting address of the DL buffer BUF are set to zero. This address condition applies not only to the starting address of the list buffer BUF that stores the display list DL, but also to the starting address of the list buffer BUF that stores the voice command list VC.

[0322] Next, the performance control CPU 57 starts the operation of the drawing circuit 74 (ST42), and then starts the operation of the data transfer circuit 70 (ST43). Note that these operation instructions are also realized by setting processes to the predetermined drawing register RGij and transfer register RGij, respectively. Then, the data transfer process is started by this operation instruction, and the data transfer circuit 70 ends its operation upon completion of the transfer of a predetermined amount of data. Therefore, after processing step ST43, the performance control CPU 57 can immediately proceed to another process following the display list issuance process (ST6).

[0323] In this case as well, when the amount of transfer data reaches the set value in the transfer register RGij (total size of the display list DL, which is the transfer data), the data stored in the CPU data FIFO circuit at that time is transferred to the data relay unit CH2.

[0324] The above has explained the process of issuing a display list DL based on Figures 19(a) and 19(b), but when issuing a voice command list VC to the voice processing unit SND, the processing content is essentially the same as Figures 19(a) and 19(b) (see Figures 10(f) and 10(g)).

[0325] That is, the voice command list VC listing the voice commands is terminated with a predetermined end command EOSC before being issued. Note that a voice command, including the end command EOSC, is one word or multiple words (=N*32 bits), so no adjustment processing of the data amount is required.

[0326] The above has been a description of the case where the preloader 72 is not used, but the main processing when the preloader 72 is used is as shown in Fig. 20(a). The processing content shown in Fig. 20(a) is similar to the processing content in Fig. 18(a).

[0327] However, as shown in FIG. 20(a), (a) after creating a display list DL for the next operation cycle (ST5), the display list DL is issued to the preloader 72 (ST60) instead of the drawing circuit 74, and (b) this display list DL is rewritten by the preloader 72 to become a rewrite list DL', but the rewrite list DL' rewritten in the previous operation cycle is acquired by the drawing circuit 74 (ST41) prior to the processing of step ST5, which is different from the processing of FIG. 18(a).

[0328] 20(a), the issue process (ST60) for issuing the display list DL to the preloader 72 is almost the same as that of Figures 19(a) and 19(b), except that the issue destination is changed to the preloader 72. The outline of the operation is as shown in Figures 10(d) and 10(e), and in response to the change in the issue destination to the preloader 72, the data relay unit CH2 is changed to the data relay unit CH3 (data transfer channel CH3), but other than that, the operation is the same as that of Figures 19(a) and 19(b), and the corresponding operations are shown in Figures 20(b) and 20(c).

[0329] On the other hand, the process of acquiring the rewrite list DL' by the drawing circuit 74 (ST41 in FIG. 20) is shown in FIG. 20(d). As shown in FIG. 10(c), in this embodiment, the rewrite list DL' is stored in the preload buffer of the VRAM 53 (see FIG. 7(a)).

[0330] In the processing of step ST41 in Fig. 20, the performance control CPU 57 sets the transfer register RGij to use the data relay unit CH2 (transfer channel CH2) (ST50 in Fig. 20(d)). Next, the total size of the rewrite list DL', which is the transfer data, and the starting address of the preload buffer in which the rewrite list DL' is stored are set in a predetermined transfer register RGij (ST51).

[0331] Since the starting address in VRAM 53 must be set in 32-bit units, the starting address of the preload buffer that stores the rewrite list DL' must have the lower 31 bits set to zero, and in this embodiment, the preload buffer is allocated at a location that meets this condition.

[0332] Next, the performance control CPU 57 starts the operation of the drawing circuit 74 (ST52) and starts the operation of the data transfer circuit 70 (ST53). Note that these operation instructions are realized by setting processes to the predetermined drawing register RGij and transfer register RGij, respectively. Then, the data transfer process is started by this operation instruction, and upon completion of the data transfer, the data transfer circuit 70 ends its operation.

[0333] Although one embodiment of the present invention has been described above, the specific description does not particularly limit the present invention and can be changed as appropriate. For example, in the above embodiment, a configuration was described in which, when the memory access period of the drawing circuit 74 or the decoding processing time is prolonged, the abnormality is detected by flag polling processing, but it goes without saying that abnormal interrupt processing may also be utilized.

[0334] Figure 18(d) shows an example of a configuration for such a case. When a drawing abnormality interrupt occurs, only the drawing circuit 74 is reset individually (ST23), the operating parameters required for the operation of the drawing circuit 74 are reset, the stack area is appropriately released (ST24), and the process proceeds to step ST9.

[0335] Although the embodiments have been described in detail above, the specific description does not limit the present invention in any way. That is, for convenience, a pinball game machine has been described, but the present invention can of course be suitably applied to other game machines such as a slot machine.

[0336] 16 are performed by the internal control circuit of the CG bus IF unit 55a, but as explained above, the CPU may also be involved. If the CPU is involved, the processing in step SP2 issues an RST assert command (1) and a SATA initialization command (4) to the internal control circuit of the CG bus IF unit 55a, and the processing in step SP3 issues a parameter load command (3). The processing in step SP10 issues a parameter upload command (2) to the internal control circuit of the CG bus IF unit 55a.

[0337] The numbers in parentheses in the previous paragraph are examples of command numbers assigned to each "CG bus command," and the CG bus commands are used to control the CG bus IF unit 55a. The issuance process of these "CG bus commands" is actually realized by writing the corresponding command number and chip select number to a predetermined performance control register RGij. In this embodiment, where the SATA device 55 constitutes the chip select space CS0, the chip select number is always 0.

[0338] Furthermore, the connection relationship between the SATA device 55 and the watchdog timer 56 is not limited to the configuration shown in Fig. 6(a), and may be the configuration shown in Fig. 6(b) in which a hardware reset is performed based on the initialization signal XRST. Such a configuration can also be applied to ROM devices of types other than the SATA device 55.

[0339] In the embodiment, a configuration has been described in which a SATA initialization command is automatically issued in the event of a timeout abnormality in the CG bus IF unit 55a, but a similar configuration can also be provided in the CPU bus unit 56 to enable automatic recovery from a CPU access abnormality. In other words, if no response is received from the READ / WRITE access request from the performance control CPU 57 within a predetermined monitoring time, it is preferable to adopt a configuration in which predetermined exception processing (for example, processing to initialize the CPU circuit 51) is automatically executed.

[0340] Furthermore, in the embodiment, the timeout monitoring circuit is provided in the drawing circuit and the GDEC circuit 73, but this is not limited thereto. That is, a similar configuration can be provided in the display circuit 71, the audio processing unit SND, etc., to resolve dot clock abnormalities or abnormalities in each circuit. In this case, a configuration may be adopted in which a specific initialization command is automatically issued to attempt recovery from each abnormality, but it is also preferable to start an interrupt process when an abnormality occurs and select whether to issue the necessary initialization command or to take other measures.

[0341] In this embodiment, the obfuscation key and user ID are assigned to each gaming machine manufacturer, but this is not limited to this. For example, they may be unique information assigned to (1) each company group including related companies, (2) each gaming machine model, or (3) each gaming machine sales period. In short, the user ID and obfuscation key are sufficient as long as they are confidential, non-public information (usually so that a third party cannot know them).

[0342] In addition, in the embodiment, for convenience, the boot program, the game control program, and all the various data in the external memory are described as being obfuscated, but this is not limited to this. For example, by appropriately controlling the descrambling processor, it is possible to adopt a configuration in which only a portion of the boot program, the game control program, or the game control data is obfuscated. When only a portion of a data (program) group is obfuscated, it is desirable to specify whether or not to obfuscate and the total amount of data for each data (program) group as header information for the data group. [Explanation of symbols]

[0343] 52 Image generation means 51 Image control means 55 Memory elements

Claims

1. The image processing device is configured to include an image control means for issuing a display list that specifies a display screen of a display device, an image generation means for receiving the display list and outputting predetermined image data to the display device, and a memory element for storing data necessary for the operation of the image control means and being accessed for READ by the image generation means, A gaming machine configured such that if no response is received within a predetermined monitoring time from a READ access request to the memory element, an initialization command for re-establishing communication with the memory element is automatically executed in the image generation means.

2. The gaming machine described in claim 1, wherein when the initialization command is executed, the image generation means and the memory element are configured to establish appropriate communication by gradually decreasing the communication speed from the fastest possible state.

3. 2. The gaming machine according to claim 1, wherein the monitoring time is set in a predetermined built-in register of the image generating means by the image control means when the power is turned on.

4. 2. The gaming machine according to claim 1, wherein when the monitoring time is exceeded, an interrupt process is started in the image generating means, and the initialization command is executed.

5. 2. The gaming machine according to claim 1, wherein the execution of the initialization command is also realized when necessary by the image control means writing a predetermined command number into a predetermined built-in register of the image generation means.

6. The image processing device is configured to include an image control means for issuing a display list that specifies a display screen of a display device, an image generation means for receiving the display list and outputting predetermined image data to the display device, and a memory element for storing data necessary for the operation of the image control means and being accessed for READ by the image generation means, A gaming machine configured such that if no response is received from a READ / WRITE access request by the CPU of the image control means within a predetermined monitoring time, a predetermined exception process is automatically executed.

Images