Wiring board

Abstract

To suppress peeling between a via conductor and a conductor layer.SOLUTION: The wiring substrate 1 of the embodiment includes the first conductor layer 21, the insulating layer 31 covering the first conductor layer 21, the second conductor layer 22 formed on the surface of the insulating layer 31, and the via conductors 4 that are respectively formed in the holes 5 penetrating the insulating layer 31 and connect the first conductor layer 21 and the second conductor layer 22. The holes 5 each include a first portion 51 that is reduced in width on the first conductor layer 21 side, a second portion 52 that is positioned on the first conductor layer 21 side of the first portion 51 and is increased in width on the first conductor layer 21 side, and a third portion 53 that is positioned on the first conductor layer 21 side of the second portion 52 and is reduced in width on the first conductor layer 21 side.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a wiring board. [Background technology]

[0002] Patent Document 1 discloses a wiring board including a via-hole conductor filled in a via hole that penetrates an insulating layer. The via bottom portion of the via-hole conductor is formed of crystal grains that are smaller than the crystal grains that form the other portions in order to prevent cracks and peeling between the via-hole conductor and the via land. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-17639 Summary of the Invention [Problem to be solved by the invention]

[0004] In the wiring board disclosed in Patent Document 1, the via bottom is formed using small crystal particles, which requires precise control of the electrolytic plating conditions when forming the via hole conductor, which can complicate the manufacturing of the wiring board. Furthermore, it is thought that an unnecessary interface will occur between the via bottom, which is formed using crystal particles of different sizes, and the rest of the wiring board. However, if the via bottom is not formed using small crystal particles, cracks and peeling may occur between the via hole conductor and the via land. [Means for solving the problem]

[0005] The wiring board of the present invention comprises a first conductor layer, an insulating layer covering the first conductor layer, a second conductor layer formed on the surface of the insulating layer, and a via conductor formed inside a hole penetrating the insulating layer and connecting the first conductor layer and the second conductor layer, wherein the hole includes a first portion whose width is narrowed on the first conductor layer side, a second portion located on the first conductor layer side of the first portion and whose width is widened on the first conductor layer side, and a third portion located on the first conductor layer side of the second portion and whose width is narrowed on the first conductor layer side.

[0006] According to an embodiment of the present invention, it may be possible to suppress peeling between via conductors and conductor layers in an easily manufactured wiring board. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a cross-sectional view showing an example of a wiring substrate according to an embodiment. [Figure 2] FIG. 2 is an enlarged view of part II of the wiring board of FIG. [Figure 3] 10 is a photographed image of a cross section of a via conductor in the wiring board according to the embodiment. [Figure 4] FIG. 10 is a cross-sectional view showing a first modified example of the wiring board according to the embodiment. [Figure 5] FIG. 10 is a cross-sectional view showing a second modified example of the wiring board according to the embodiment. [Figure 6A] 1A and 1B are cross-sectional views showing an example of a wiring substrate according to an embodiment during a manufacturing process. [Figure 6B] 1A and 1B are cross-sectional views showing an example of a wiring substrate according to an embodiment during a manufacturing process. [Figure 6C] 1A and 1B are cross-sectional views showing an example of a wiring substrate according to an embodiment during a manufacturing process. [Figure 6D] 1A and 1B are cross-sectional views showing an example of a wiring substrate according to an embodiment during a manufacturing process. [Figure 6E] 1A and 1B are cross-sectional views showing an example of a wiring substrate according to an embodiment during a manufacturing process. [Figure 6F] 1A and 1B are cross-sectional views showing an example of a wiring substrate according to an embodiment during a manufacturing process. [Figure 6G] 1A and 1B are cross-sectional views showing an example of a wiring substrate according to an embodiment during a manufacturing process. [Figure 6H] 1A and 1B are cross-sectional views showing an example of a wiring substrate according to an embodiment during a manufacturing process. DETAILED DESCRIPTION OF THE INVENTION

[0008] <Basic configuration of wiring board according to embodiment> Wiring boards according to embodiments of the present invention will be described with reference to the drawings. FIG. 1 illustrates a wiring board 1, which is an example of a wiring board according to an embodiment, and FIG. 2 illustrates an enlarged view of part II of the wiring board 1 in FIG. 1. Note that the wiring boards illustrated in the drawings referred to in the following description are merely examples of wiring boards according to an embodiment. The layered structure of the wiring board according to the embodiment is not limited to the layered structure of the wiring board illustrated in the drawings, and the number of conductor layers and insulating layers included in the wiring board according to the embodiment is not limited to the number of conductor layers and insulating layers included in the wiring board according to the embodiment. The wiring board according to the embodiment may include any number of insulating layers and conductor layers in addition to the insulating layers and conductor layers included in the wiring board illustrated in the drawings, and may not include all of the insulating layers and conductor layers included in the wiring board illustrated in the drawings. Note that in the drawings referred to in the following description, certain portions may be enlarged to facilitate understanding of the disclosed embodiments. Therefore, the components may not be drawn to exact proportions relative to each other in terms of size or length.

[0009] As shown in Fig. 1, the wiring board 1 includes conductor layers 21 to 24 and insulating layers 31 to 33. The conductor layers 21 to 24 and the insulating layers 31 to 33 are alternately stacked. The stacking direction of these conductor layers and insulating layers is the thickness direction of the wiring board 1, which will hereinafter also be referred to as the "Z direction." In Fig. 1, insulating layer 31 is stacked so as to cover one of the two surfaces of conductor layer 21 that are perpendicular to the Z direction, and on the side of insulating layer 31 opposite to the conductor layer 21 side, conductor layer 22, insulating layer 32, conductor layer 23, insulating layer 33, and conductor layer 24 are stacked in this order.

[0010] In the following description of the wiring board of the embodiment, the conductor layer 24 side of the wiring board 1 is also referred to as the "upper side," and the conductor layer 21 side is also referred to as the "lower side." Therefore, in each conductor layer and each insulating layer, the surface facing away from the conductor layer 21 or the surface facing the conductor layer 24 side is also referred to as the "upper surface," and the surface facing away from the conductor layer 24 or the surface facing the conductor layer 21 side is also referred to as the "lower surface."

[0011] Via conductors 4 are formed in each of the insulating layers 31 to 33, penetrating the insulating layer. Each via conductor 4 is formed inside a hole 5 penetrating the insulating layer. Each via conductor 4 connects two conductor layers that sandwich the insulating layer (one of the insulating layers 31 to 33) through which the via conductor 4 penetrates. For example, the via conductor 4 penetrating the insulating layer 31 connects the conductor layer 21 and the conductor layer 22. Each via conductor 4 is formed integrally with the conductor layer above the via conductor 4. The via conductor 4 penetrating the insulating layer 31 is formed integrally with the conductor layer 22, the via conductor 4 penetrating the insulating layer 32 is formed integrally with the conductor layer 23, and the via conductor 4 penetrating the insulating layer 33 is formed integrally with the conductor layer 24.

[0012] In the description of the wiring board of the embodiment, the conductor layer in contact with the lower surface of each insulating layer is also referred to as the first conductor layer, while the conductor layer in contact with the upper surface of each insulating layer is also referred to as the second conductor layer. In the example of FIG. 1 , for each of insulating layers 31 to 33, the conductor layer integrally formed with the via conductor 4 penetrating each insulating layer is also referred to as the second conductor layer, and the conductor layer connected to the second conductor layer by the via conductor 4 is also referred to as the first conductor layer. That is, for insulating layer 31, conductor layer 21 can be the first conductor layer for conductor layer 22, and conductor layer 22 can be the second conductor layer for conductor layer 21. Similarly, for insulating layer 32, conductor layer 22 can be the first conductor layer for conductor layer 23, and conductor layer 23 can be the second conductor layer for conductor layer 22. Furthermore, for insulating layer 33, conductor layer 23 can be the first conductor layer for conductor layer 24, and conductor layer 24 can be the second conductor layer for conductor layer 23.

[0013] Thus, a wiring board of an embodiment such as wiring board 1 includes a first conductor layer such as conductor layer 21, an insulating layer such as insulating layer 31 that covers the first conductor layer, and a second conductor layer such as conductor layer 22 that is formed on the surface of the insulating layer. The wiring board of the embodiment further includes via conductors 4 that connect the first conductor layer and the second conductor layer.

[0014] 1 further includes a solder resist 61 covering the lower surface of the conductor layer 21 and the lower surface of the insulating layer 31, and a solder resist 62 covering the upper surface of the conductor layer 24 and the upper surface of the insulating layer 33. The solder resists 61 and 62 are formed of, for example, a photosensitive epoxy resin. Each solder resist has an opening formed therein that exposes a predetermined region of the conductor layer 21 or the conductor layer 24.

[0015] The conductor layers 21-24 and the via conductor 4 are each formed of any metal having suitable conductivity. Examples of materials that constitute these conductive elements include copper, nickel, gold, titanium, palladium, and tungsten. However, the materials of the conductor layers 21-24 and the via conductor 4 are not limited to these metals.

[0016] In Fig. 1, the conductor layers 21-24 and the via conductor 4 are depicted as being composed of only one layer for simplicity, but as shown in Fig. 2, they may have a multi-layer structure composed of two or more metal films. In the example of Fig. 2, the conductor layer 21 and the via conductor 4 are composed of a lower layer composed of a metal film 4a and an upper layer composed of a plating film 4b. The metal film 4a may be, for example, an electroless plating film or a sputtering film of copper, and the plating film 4b may be, for example, an electrolytic plating film of copper.

[0017] The insulating layers 31 to 33 are mainly formed of any insulating resin. Examples of insulating resins used to form the insulating layers 31 to 33 include epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, fluororesin, liquid crystal polymer (LCP), acrylic resin, fluoroethylene (PTFE) resin, polyester (PE) resin, and modified polyimide (MPI) resin. The resins constituting the insulating layers 31 to 33 are preferably photosensitive resins that react to light, such as photocurable (negative type) resins that crosslink when exposed to ultraviolet light or other light, or photosoluble (positive type) resins that decompose when exposed to light. For example, the resins exemplified above that primarily constitute the insulating layers 31 to 33 may themselves be photosensitive, or the insulating layers 31 to 33 may contain a photosensitizer in addition to the resins exemplified above. It may be more preferable that the photosensitive resin constituting the insulating layers 31 to 33 be negative type.

[0018] On the other hand, it is preferable that the insulating layers 31-33 do not contain inorganic particles made of, for example, silicon oxide or alumina, which are generally used as fillers to adjust various properties such as mechanical properties. It is also preferable that the insulating layers 31-33 do not contain a core material such as glass fiber, which is generally used to improve mechanical strength. The resins listed above as materials for the insulating layers 31-33 are merely examples of materials that can form the insulating layers. The insulating layers can be formed from any material that provides insulation to the conductor layers 21-24 and can support the conductor layers 21-24.

[0019] 2, in the wiring board of the embodiment, the hole 5 filled with the via conductor 4 has a first portion 51, a second portion 52, and a third portion 53. The first portion 51 is a portion that is narrower on the conductor layer 21 side than on the conductor layer 22 side in the example of FIG. 2. The second portion 52 is a portion that is wider on the conductor layer 21 side than on the conductor layer 22 side, and is located on the conductor layer 21 side of the first portion 51. The third portion 53 is a portion that is narrower on the conductor layer 21 side than on the conductor layer 22 side, and is located on the conductor layer 21 side of the second portion 52. Note that in FIG. 2, which shows the insulating layer 31 and the conductor layers 21 and 22 above and below it, the conductor layer 21 is the first conductor layer, and the conductor layer 22 is the second conductor layer, as described above. In explanations that refer to Figure 2 and to Figures 3 to 5 which, like Figure 2, show insulating layer 31 and the conductor layers 21 and 22 above and below it, conductor layer 21 is also referred to as first conductor layer 21, and conductor layer 22 is also referred to as second conductor layer 22.

[0020] 2, in the wiring board of the embodiment, hole 5 filled with via conductor 4 has first portion 51, second portion 52, and third portion 53, which respectively narrow and widen their widths on the first conductor layer 21 side relative to the second conductor layer 22 side, as described above. The first portion 51 and third portion 53 narrow their widths toward the first conductor layer 21, while the second portion 52 widens their width toward the first conductor layer 21. The "width" of each of first portion 51, second portion 52, and third portion 53, i.e., the "width" of hole 5, is the maximum distance between any two points on the periphery of hole 5 in any cross section perpendicular to the Z direction.

[0021] The first portion 51, the second portion 52, and the third portion 53 are arranged in series in this order from the second conductor layer 22 side to the first conductor layer 21 side along the Z direction.

[0022] Because the hole 5 has the first portion 51, the second portion 52, and the third portion 53 as shown in FIG. 2 , it is believed that cracks or peeling due to voids or the like are unlikely to occur between the via conductor 4 formed in the hole 5 and the first conductive layer 21. The reason for this is that the via conductor 4 is unlikely to contain voids in the third portion 53 that forms the vicinity of the bottom of the hole 5. That is, when the via conductor 4 is formed by filling the hole 5 with the metal film 4a and the plating film 4b, it is presumed that the presence of the second portion 52 that widens the width on the first conductive layer 21 side makes it easier for a plating solution, such as electrolytic plating, to penetrate deep into the hole 5. It is therefore believed that the metal film 4a and the plating film 4b are likely to be formed all the way to the corners of the hole 5.

[0023] In addition, it is believed that the presence of third portion 53, which narrows the width on the first conductor layer 21 side, makes it less likely that a portion like imaginary portion IM shown by the dashed line in Figure 2 will occur around hole 5 at the interface with first conductor layer 21. For example, if second portion 52 reaches first conductor layer 21, a tapered corner like imaginary portion IM will occur inside hole 5 near the interface with first conductor layer 21. If hole 5 includes a portion like imaginary portion IM, it is difficult for fresh plating solution to reach such a portion. Therefore, it is believed that a via conductor formed in a hole including a portion like imaginary portion IM is likely to include an unfilled portion, such as a void, near its bottom.

[0024] In contrast, in the wiring board 1 of the embodiment, the hole 5 has the third portion 53, so a portion such as the imaginary portion IM in FIG. 2 is unlikely to occur. That is, the via conductor 4 is unlikely to include an unfilled portion such as a void near its bottom. Therefore, in the wiring board of the embodiment, due to the above-mentioned action of at least the second portion 52 and the third portion 53 in the hole 5, cracks or peeling are unlikely to occur between the via conductor 4 and the first conductor layer 21. Therefore, it is believed that defects such as peeling between the via conductor 4 and the first conductor layer 21 are suppressed.

[0025] The hole 5 may have any opening shape, such as circular or elliptical, at both end faces of the hole 5 and in a cross section perpendicular to the Z direction. When the hole 5 has a circular or elliptical opening shape, the first portion 51 and the third portion 53 may have a smaller diameter on the first conductor layer 21 side, while the second portion 52 may have a larger diameter on the first conductor layer 21 side. Furthermore, the width of the hole 5 in the first portion 51 and the third portion 53 may be smaller toward the first conductor layer 21 side than toward the second conductor layer 22 side, and the width of the hole 5 in the second portion 52 may be larger toward the first conductor layer 21 side than toward the second conductor layer 22 side. That is, the width of the hole 5 in the first portion 51 and the third portion 53 may gradually decrease as it approaches the first conductor layer 21, while the width of the hole 5 in the second portion 52 may gradually increase as it approaches the first conductor layer 21. In this case, the width of the hole 5 in the first portion 51 and the third portion 53 may decrease continuously or in steps as it approaches the first conductor layer 21, while the width of the hole 5 in the second portion 52 may increase continuously or in steps as it approaches the first conductor layer 21.

[0026] Furthermore, the width W1 of the first portion 51 at the opening end (upper end) on the second conductor layer 22 side may be larger than the width W2 of the opening end (lower end) on the first conductor layer 21 side, and the width W3 of the second portion 52 at the upper end (same as width W2 in FIG. 2) may be smaller than the width W4 of the lower end. Furthermore, the width W5 of the third portion 53 at the upper end (same as width W4 in FIG. 2) may be larger than the width W6 of the lower end.

[0027] Furthermore, in the wiring board 1 of the embodiment, the wall surface 5a of the hole 5 may be inclined inward of the hole 5 toward the first conductor layer 21 in the first portion 51. The wall surface 5a of the hole 5 may be inclined outward of the hole 5 toward the first conductor layer 21 in the second portion 52. The wall surface 5a of the hole 5 may be inclined inward of the hole 5 toward the first conductor layer 21 in the third portion 53. That is, the first portion 51 and the third portion 53 may be forward tapered toward the first conductor layer 21, and the second portion 52 may be reverse tapered toward the first conductor layer 21.

[0028] Hole 5, an example of which is shown in FIG. 2 , has a shape including first portion 51, second portion 52, and third portion 53. For example, via conductor 4 may be formed by irradiating each insulating layer with light, such as ultraviolet light, in a predetermined exposure pattern and then removing the irradiated or unirradiated portions by development. That is, via conductor 4 may be a so-called "photovia." To facilitate the formation of hole 5 using photolithography techniques involving exposure and development, each insulating layer, such as insulating layer 31, in the wiring board of the embodiment is preferably formed from a photosensitive resin, as described above. For the same reason, each insulating layer, such as insulating layer 31, is preferably formed from a resin that does not contain inorganic particles, such as silicon oxide or alumina, referred to as "inorganic filler." Furthermore, for the same reason, each insulating layer, such as insulating layer 31, is preferably formed from a resin that does not contain a core material, such as glass fiber.

[0029] Forming holes 5 using photolithography techniques can sometimes form holes with a small width more easily than drilling holes using, for example, laser light irradiation. Therefore, holes 5 in wiring board 1 can have a relatively small opening width. Furthermore, as described above, in the wiring board of the embodiment, cracks and peeling are unlikely to occur between via conductors 4 and first conductor layer 21. Therefore, even if the width of via conductors 4 is small, problems such as open defects and increased electrical resistance are unlikely to occur between via conductors 4 and first conductor layer 21. Therefore, the wiring board of the embodiment is considered suitable as a wiring board including small via conductors. For example, the opening width W of hole 5 at the interface between insulating layer 31 and second conductor layer 22 in wiring board 1 (the same as width W1 at the upper end of first portion 51 in FIG. 2 ) may be 3 μm or more and 10 μm or less. Having holes 5 with a small opening width within such a range can allow wiring board 1 to include a fine wiring pattern at a high density.

[0030] 2, in the thickness direction (Z direction) of the wiring board 1, the length L3 of the third portion 53 is shorter than the length L1 of the first portion 51 and shorter than the length L2 of the second portion 52. Therefore, it is considered that the contact area between the via conductor 4 and the first conductor layer 21 does not become too small, and an appropriate contact area is maintained. As an example, with respect to the thickness T31 of the insulating layer 31, the length L1 of the first portion 51 is about 30%, the length L2 of the second portion 52 is about 60%, and the length L3 of the third portion 53 is about 10%.

[0031] The thickness T31 of the insulating layer 31 is, for example, 3 μm or more and 15 μm or less. The aspect ratio of the via conductor 4 formed in the insulating layer 31 having such a thickness is, for example, 1.0 or more and 3.0 or less. The aspect ratio of the via conductor 4 is a ratio expressed as (width W6 at the bottom end of the third portion 53 of the hole 5) / (distance between the first conductive layer 21 and the second conductive layer 22).

[0032] 2, the inclination θ1 of the wall surface 5a of the hole 5 relative to the thickness direction (Z direction) of the wiring board 1 in the first portion 51 is larger than the inclination θ2 of the wall surface 5a of the hole 5 relative to the Z direction in the second portion 52. Therefore, when forming the via conductor 4 by plating, it is thought that the plating solution easily enters the hole 5, and the via conductor 4 is quickly formed. The inclination θ1 is determined by the arc tangent of the absolute value of (length L1 of the first portion 51) / ((width W1 at the upper end of the first portion 51 - width W2 at the lower end of the first portion 51) / 2). The inclination θ2 is also determined similarly for the second portion 52.

[0033] 2, the second portion 52 is connected to the first portion 51, and the third portion 53 is connected to the second portion 52. Furthermore, the first portion 51 is in contact with the second conductor layer 22, and the third portion 53 is in contact with the first conductor layer 21. That is, the hole 5 in the example of FIG. 2 is made up of the first portion 51, the second portion 52, and the third portion 53, that is, is composed only of the first portion 51, the second portion 52, and the third portion 53. This has the advantage that it is easy to prevent voids from forming in the third portion 53.

[0034] Fig. 3 shows a photographed image of a cross section of a via conductor 4 in an example of a wiring board of the embodiment. As described with reference to Fig. 2, the hole 5 filled with the via conductor 4 in Fig. 3 has a first portion 51 whose width narrows on the first conductor layer 21 side, a second portion 52 located on the first conductor layer 21 side of the first portion 51 and whose width widens on the first conductor layer 21 side, and a third portion 53 located on the first conductor layer 21 side of the second portion 52 and whose width narrows on the first conductor layer 21 side. In this way, the wiring board of the embodiment actually has a via conductor 4 formed in a hole 5 having the first portion 51, the second portion 52, and the third portion 53.

[0035] <First Modification> FIG. 4 shows a via conductor 41 and its surrounding area penetrating the insulating layer 31 in a first modified example of the wiring board of the embodiment. In the modified example of FIG. 4, the via conductor 41 is formed inside a hole 5 penetrating the insulating layer 31. The via conductor 41 is formed of a metal film 4a and a plating film 4b filling the hole 5, and connects the first conductor layer 21 and the second conductor layer 22. The hole 5 has a first portion 51, a second portion 52, and a third portion 53, similar to the example shown in FIG. 2. In the example of FIG. 4, the via conductor 41 does not include a void in the portion of the plating film 4b filling the third portion 53, but includes a void B in the portion filling the first portion 51. In the first modified example of FIG. 4, in which the void B is included in the first portion 51 rather than in the third portion 53, peeling between the via conductor 41 and the first conductor layer 21 is thought to be less likely to occur than in a conventional wiring board in which a void exists at the bottom of the via conductor. 4, the void B may be included in the second portion 52 instead of the first portion 51, or may be included in the second portion 52 in addition to the first portion 51. Even in this case, since the third portion 53 does not include a void, it is believed that peeling between the via conductor 41 and the first conductor layer 21 is less likely to occur.

[0036] <Second Modification> 5 shows a via conductor 42 and its surrounding area that penetrates the insulating layer 31 in a second modified example of the wiring board of the embodiment. The via conductor 42 is formed inside a hole 50 that penetrates the insulating layer 31 and connects the first conductor layer 21 and the second conductor layer 22. The hole 50 included in the modified example of FIG. 5 also has a first portion 51 that narrows on the first conductor layer 21 side, a second portion 52 that is located on the first conductor layer 21 side of the first portion 51 and widens on the first conductor layer 21 side, and a third portion 53 that is located on the first conductor layer 21 side of the second portion 52 and narrows on the first conductor layer 21 side.

[0037] The hole 50 in the example of FIG. 5 further includes a fourth portion 54 whose width does not change substantially from the second conductor layer 22 side to the first conductor layer 21 side. That is, the width of the hole 50 in the fourth portion 54 is substantially constant from the top end to the bottom end of the fourth portion 54. The hole 50 in the example of FIG. 5 includes the fourth portion 54 between the first portion 51 and the second portion 52. However, when a hole for a via conductor such as the hole 50 in the wiring board of the embodiment has a parallel portion whose width does not change, the parallel portion may be located between the second portion 52 and the third portion 53. As in the example of FIG. 5, the hole filled with the via conductor in the wiring board of the embodiment may include a parallel portion such as the fourth portion 54 in addition to the first portion 51, the second portion 52, and the third portion 53. Furthermore, the hole filled with the via conductor in the wiring board of the embodiment may include a portion whose diameter increases or decreases on the first conductor layer 21 side in addition to the first portion 51 to the third portion 53.

[0038] <Method for manufacturing wiring board according to embodiment> With reference to FIGS. 6A to 6H, an example of a method for manufacturing a wiring board according to an embodiment will be described using wiring board 1 shown in FIG. 1 as an example.

[0039] As shown in Figure 6A, a support substrate SP is prepared, which includes a core layer GS and metal film layers ML1 and ML2 laminated on both sides of the core layer GS. The core layer GS is made of, for example, glass or glass epoxy material. The metal film layers ML1 and ML2 are single-layer or multi-layer metal films formed by electroless plating or sputtering using materials such as copper and titanium. The metal film layers ML1 and ML2 are joined together by an adhesive layer AL made of, for example, an adhesive whose adhesiveness changes depending on the amount of light received.

[0040] In the following description, the side of the support substrate SP closer to the core layer GS is also referred to as the "bottom" or "lower side," and the side farther from the core layer GS is also referred to as the "top" or "upper side." Therefore, the surface of each element constituting the wiring board that faces the support substrate SP is also referred to as the "lower surface," and the surface that faces away from the support substrate SP is also referred to as the "upper surface."

[0041] Conductor layers 21 are formed on the metal film layers ML2 on both sides of the prepared support substrate SP. In forming the conductor layer 21, for example, a plating resist (not shown) with predetermined openings is formed on the metal film layer ML2. A plating film is deposited in the openings of the plating resist by electrolytic plating using the metal film layer ML2 as a power supply layer. The plating resist is then removed. The conductor layer 21 is formed, including each conductor pattern made of the plating film deposited in the openings of the plating resist.

[0042] After the conductor layer 21 is formed, an insulating layer 31 is formed to cover the conductor layer 21. The insulating layer 31 is preferably formed of a photosensitive resin. Examples of photosensitive resins include epoxy resin, BT resin, or phenolic resin to which a photosensitizer has been added. In forming the insulating layer 31, for example, a resin film made of a resin constituting the insulating layer 31, such as epoxy resin, is laminated on the conductor layer 21 and the metal film layer ML2, and is temporarily cured to an intermediate reaction state such as a B-stage state by, for example, heating. In one example, the photosensitive resin constituting the insulating layer 31 is negative. Below, a method for forming holes 5 (see FIG. 6D) in the insulating layer 31 will be described using an example in which the photosensitive resin constituting the insulating layer 31 is negative.

[0043] As shown in Fig. 6B, an exposure mask EM having a shielding portion EM1 at a formation position of the via conductor 4 (see Fig. 6G) is provided on the insulating layer 31, for example, by laminating a dry film resist, exposing it to light, and developing it. Note that Fig. 6B and Figs. 6E and 6H, which will be referred to later, show only one surface side of the support substrate SP, and do not show the state of the other side. However, each insulating layer and each conductor layer may be formed on the surface of the support substrate SP on the side not shown, just as on the side shown in the figures, or such conductor layers and insulating layers may not be formed.

[0044] FIG. 6C shows an enlarged view of the VIC portion of FIG. 6B. As shown in FIG. 6C, exposure light EL, such as ultraviolet light, is irradiated onto the insulating layer 31 through an exposure mask EM. The wavelength of the exposure light EL is selected depending on the photosensitivity characteristics of the photosensitive resin constituting the insulating layer 31. The exposure light EL is irradiated onto the portion of the upper surface 31a of the insulating layer 31 exposed through the opening EM2 of the exposure mask EM. By adjusting the diffusion and irradiation angle of the exposure light EL, a portion of the exposure light EL that penetrates into the insulating layer 31, namely, exposure light EL1, propagates through the insulating layer 31 so as to extend to the portion directly below the shielding portion EM1 of the exposure mask EM. Therefore, the portion of the insulating layer 31 directly below the shielding portion EM1 and close to the opening EM2 is exposed to the exposure light EL1. In the insulating layer 31 made of a negative photosensitive resin, the exposed portion crosslinks. Therefore, even in the portion directly below the shielding portion EM1, the crosslinking reaction proceeds in the region AR exposed to the exposure light EL1 in the same manner as in the portion directly below the opening EM2.

[0045] Here, it is considered that the luminous intensity of the exposure light EL propagating through the insulating layer 31 gradually weakens in a portion closer to the conductor layer 21 and away from the upper surface 31a of the insulating layer 31. Therefore, the exposed area AR in the portion directly below the shielding portion EM1 gradually becomes smaller in a portion that is somewhat away from the upper surface 31a as it approaches the conductor layer 21. Therefore, in a portion of the insulating layer 31 directly below the shielding portion EM1 that is somewhat away from the upper surface 31a, the area AN that does not exhibit a cross-linking reaction gradually becomes larger as it approaches the conductor layer 21.

[0046] Meanwhile, in the insulating layer 31 immediately adjacent to the conductor layer 21, a small portion of the portion immediately below the shielding portion EM1, close to the portion immediately below the opening EM2, is exposed to the reflected light EL2 of the exposure light EL1 reflected by the surface of the conductor layer 21. As a result, the exposed region AR immediately below the shielding portion EM1 expands in the portion immediately adjacent to the conductor layer 21. That is, in the portion of the insulating layer 31 immediately adjacent to the conductor layer 21, the region AN that does not exhibit a cross-linking reaction shrinks. As a result, as shown in FIG. 6C , the region AN that does not exhibit a cross-linking reaction shrinks in a certain range near the top surface 31a of the insulating layer 31 as it approaches the conductor layer 21, expands further on the conductor layer 21 side, and then shrinks in the small portion immediately adjacent to the conductor layer 21 as it approaches the conductor layer 21. This region AN that does not exhibit a cross-linking reaction is removed in a subsequent process.

[0047] After the insulating layer 31 is irradiated with the exposure light EL, the exposure mask EM is removed using an appropriate stripper. By performing development after removing the exposure mask EM, the regions AN of the insulating layer 31 that do not show a cross-linking reaction in the exposure process described above are removed.

[0048] By removing the region AN that does not exhibit a cross-linking reaction, a hole 5 is formed in the insulating layer 31 as shown in FIG. 6D . As described above, the region AN that does not exhibit a cross-linking reaction has three portions that shrink or expand as they approach the conductor layer 21, resulting in the formation of the hole 5 having the shape shown in FIG. 6D . That is, the hole 5 has a first portion 51 that narrows on the conductor layer 21 side, a second portion 52 that widens on the conductor layer 21 side, and a third portion 53 that narrows on the conductor layer 21 side. The second portion 52 is located on the conductor layer 21 side of the first portion 51, and the third portion 53 is located on the conductor layer 21 side of the second portion 52. In the hole 5 of the example of FIG. 6D , the second portion 52 is connected to the first portion 51, and the third portion 53 is connected to the second portion 52. The hole 5 of the example of FIG. 6D consists of only the first portion 51, the second portion 52, and the third portion 53.

[0049] As described above, by appropriately selecting and adjusting the irradiation conditions such as the diffusion, irradiation angle, and luminous intensity of the exposure light EL (see FIG. 6C), it is possible to form a hole 5 including first to third portions 51 to 53 as shown in FIG. 6D. Furthermore, a hole 50 having a fourth portion 54 as shown in FIG. 5, which was previously referred to, can also be formed by adjusting the irradiation conditions of the exposure light EL.

[0050] After the holes 5 are formed, a metal film 4a made of, for example, copper is formed on the upper surface 31a of the insulating layer 31 and inside the holes 5 by electroless plating or sputtering.

[0051] As shown in Fig. 6E, a plating resist PR is provided on the metal film 4a, for example, by laminating a dry film resist. Openings PO are formed in the plating resist PR, for example, by photolithography. The openings PO are provided in areas where each conductor pattern of the conductor layer 22 (see Fig. 6H) will be formed. Openings PO are also provided above the holes 5.

[0052] As shown in FIG. 6F , a plating film 4b is deposited inside the opening PO by, for example, electrolytic plating using the metal film 4a as a power supply layer. The plating film 4b is also deposited inside the hole 5 exposed at the opening PO, gradually filling the hole 5 with the plating film 4b. As described above, in the hole 5 having the first portion 51 to the third portion 53, the plating solution easily penetrates to the bottom of the hole 5, and there is no portion near the bottom where the plating solution has difficulty reaching. Therefore, the hole 5 is easily filled with the plating film 4b all the way to the corners of the third portion 53. In other words, unfilled portions such as voids are unlikely to occur near the interface between the bottom of the hole 5 and the conductor layer 21.

[0053] The plating film 4b fills the entire third portion 53, the entire second portion 52, and the first portion 51. In the manufacturing process of the wiring board according to the embodiment, the second portion 52, which widens on the conductor layer 21 side, is present, so filling the third portion 53 and the second portion 52 may take a relatively long time. In this case, after filling the second portion 52, the upper end of the first portion 51 may be blocked by the plating film 4b deposited on the inner wall surrounding the hole 5 before the first portion 51 is completely filled. Alternatively, by adjusting the irradiation conditions of the exposure light EL (see FIG. 6C ) to form a hole 5 of a desired shape or by adjusting the plating conditions, the upper end of the first portion 51 may be blocked by the plating film 4b deposited on the inner wall surrounding the hole 5 before the first portion 51 or the second portion 52 is completely filled. In this case, a void B, as shown in FIG. 4 , is formed in the first portion 51 and / or the second portion 52. Even in this case, voids B are unlikely to form in the third portion 53 (especially near the interface with the conductor layer 21), so in the wiring board of the embodiment, it is believed that cracks and peeling between the via conductor 4 (see Figure 6G) formed in the hole 5 and the conductor layer 21 are suppressed.

[0054] 6F, as the electrolytic plating continues to deposit the plating film 4b, the entire hole 5 is filled with the plating film 4b, and the opening PO of the plating resist PR is filled to a predetermined depth, as shown in Fig. 6G. As a result, the via conductor 4 is formed in the hole 5, and each conductor pad of the conductor layer 22 (see Fig. 6H) is formed in the opening PO.

[0055] After the plating film 4b is formed and the via conductors 4 are formed by the formation of the plating film 4b, the plating resist PR is removed using an appropriate stripping solution. Furthermore, the portions of the metal film 4a exposed by the removal of the plating resist PR are removed, for example, by etching. As a result, a conductor layer 22 consisting of the conductor patterns formed in the openings PO of the plating resist PR is formed.

[0056] 6H, insulating layer 32, conductor layer 23, and via conductor 4 penetrating insulating layer 32 are further formed in a manner similar to the previously described method for forming insulating layer 31, conductor layer 22, and via conductor 4. Furthermore, via conductor 4 penetrating insulating layer 33, conductor layer 24, and insulating layer 33 are formed in a manner similar to the previously described method for forming insulating layer 31, conductor layer 22, and via conductor 4 penetrating insulating layer 31.

[0057] A solder resist 62 (see FIG. 1) is formed on the conductor layer 24 and the insulating layer 33. The solder resist 62 is formed by any method, such as spraying, laminating, or coating, using, for example, a photosensitive polyimide resin or epoxy resin. Note that the solder resist 62 may be formed after removing the metal film layer ML2 of the support substrate SP, which will be described below, rather than immediately after the formation of the conductor layer 24.

[0058] The core layer GS of the support substrate SP is removed. The lower surface of the metal film layer ML2 of the support substrate SP is exposed. The core layer GS is removed, for example, by softening the adhesive layer AL by irradiation with laser light, and then peeling the metal film layer ML2 from the adhesive layer AL. Then, the metal film layer ML2 is removed by etching. The lower surfaces of the conductor layer 21 and the insulating layer 31 are exposed. A solder resist 61 (see FIG. 1) covering the exposed conductor layer 21 and the insulating layer 31 is formed by a method similar to the method for forming the solder resist 62.

[0059] 1, openings that expose the conductor layer 21 or conductor layer 24 are formed in the solder resists 61 and 62. The openings in the solder resists 61 and 62 are formed, for example, by photolithography including exposure and development steps, or by irradiation with laser light. For example, by the above steps, the wiring board 1 of the embodiment illustrated in FIG. 1 can be manufactured.

[0060] The wiring board of the embodiment is not limited to those having the structure illustrated in each drawing and the structure, shape, and material illustrated in this specification. As described above, the wiring board of the embodiment may have any laminated structure. Any insulating layer of the wiring board of the embodiment may have a hole filled with a via conductor, the hole having three portions such as the first portion 51 to the third portion 53. In at least one insulating layer of the wiring board of the embodiment, a via conductor is formed to fill the hole having three portions such as the first portion 51 to the third portion 53. The wiring board of the embodiment does not have to be a so-called coreless substrate such as the wiring board 1 of FIG. 1, and may include a core substrate and build-up layers formed on both sides of the core substrate. [Explanation of symbols]

[0061] 1. Wiring board 21 Conductor layer (first conductor layer) 22 Conductor layer (second conductor layer) 31~33 Insulation layer 4, 41, 42 Via conductor 4b Plating film 5, 50 holes 51 Part 1 52 Part 2 53 Part 3 5a Wall B Void L1 Length of the first part L2 Length of the second part L3 Length of the third part W: Hole opening width θ1 Inclination of the wall of the first section θ2 Inclination of the wall of the second section

Claims

1. a first conductor layer; an insulating layer covering the first conductor layer; a second conductor layer formed on a surface of the insulating layer; a via conductor formed inside a hole penetrating the insulating layer and connecting the first conductor layer and the second conductor layer; A wiring board comprising: The hole is a first portion whose width is reduced on the first conductor layer side; a second portion located on the first conductor layer side of the first portion and expanding in width on the first conductor layer side; a third portion located on the first conductor layer side of the second portion and having a reduced width on the first conductor layer side; Contains:

2. 2. The wiring board according to claim 1, wherein the insulating layer is formed of a photosensitive resin.

3. 2. The wiring board according to claim 1, wherein the insulating layer is formed of a resin that does not contain inorganic particles.

4. A wiring board as described in claim 1, wherein the via conductor is formed by a plating film that fills the hole, and the plating film does not contain voids in the portion that fills the third portion, but does contain voids in the portion that fills the first portion or the portion that fills the second portion.

5. 2. The wiring board according to claim 1, wherein the third portion is shorter than the first portion and shorter than the second portion in a thickness direction of the wiring board.

6. 2. The wiring board according to claim 1, wherein an inclination of the wall surface of the hole with respect to the thickness direction of the wiring board in the first portion is greater than an inclination of the wall surface of the hole with respect to the thickness direction in the second portion.

7. 2. The wiring board according to claim 1, wherein the opening width of the hole at the interface between the insulating layer and the second conductor layer is 3 [mu]m or more and 10 [mu]m or less.

8. 2. The wiring board according to claim 1, the second portion is connected to the first portion; The third portion is connected to the second portion.

9. 9. The wiring board according to claim 8, wherein the hole comprises the first portion, the second portion, and the third portion.

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