Display device

Abstract

To provide a display device suitable for enlargement.SOLUTION: Three or more source lines are arranged for each row of pixels, and video signal of the same polarity is input to adjacent source lines during one frame period. To reduce flickers, crosstalks, etc., by dot inversion driving.SELECTED DRAWING: Figure 24

Description

[Technical Field]

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, Electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, or manufacturing methods thereof The law can be cited as an example.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Transistors, semiconductor circuits, arithmetic units, memory devices, etc. are examples of semiconductor devices. In addition, imaging devices, electro-optical devices, power generation devices (thin film solar cells, organic thin film solar cells, etc.) ), and electronic devices may have semiconductor devices. [Background technology]

[0004] In recent years, there has been a demand for high-resolution display devices. For example, in home television sets (TV , or television receiver), the resolution is full high definition (192 pixels) 0×1080) is the mainstream, but 4K (pixel count 3840×2160) The development of high-resolution display devices such as 8K (7680 x 4320 pixels) is progressing. There are.

[0005] A liquid crystal display device is known as one of the display devices. By using the optical modulation effect of the It represents the image and displays it as an image.

[0006] Also, as a type of field effect transistor, a semiconductor formed on a substrate having an insulating surface A thin film transistor in which a channel forming region is formed using a film is known. In this case, amorphous silicon is used in the semiconductor film used in the channel formation region of the thin film transistor. For example, in the case of a liquid crystal display device, a thin film transistor is used for each pixel. Used as a switching transistor. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-053283 Summary of the Invention [Problem to be solved by the invention]

[0008] In the case of display devices such as televisions and monitors, the higher the resolution or the larger the screen size, the better. The larger the difference, the more significant the increase in load on the transistors and the like included in the display device. This allows transistors to be operated at high drive frequencies, especially when the field-effect mobility of the transistor is low. It can sometimes be difficult.

[0009] An object of one embodiment of the present invention is to provide a high-resolution display device and a manufacturing method thereof. Another object is to realize a display device suitable for large size and a manufacturing method thereof. Another object is to provide a low-cost display device and a manufacturing method thereof. Another object is to provide a highly reliable display device and a manufacturing method thereof. Another object is to provide a display device using a metal oxide or the like and a manufacturing method thereof. Another object is to provide a novel display device and a manufacturing method thereof.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. can be extracted from the description, drawings, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a display device including a plurality of gate lines, a plurality of source lines, and a display portion. The display unit has multiple display elements arranged in m rows and n columns (m and n are integers of 2 or more). Each of the plurality of pixels has a transistor and a display element, and The pixels arranged in the ith position are electrically connected to the ith gate line (i is an integer between 1 and m). The display device has g source lines per column, and the jth column (j is 1 or more and n or less) g source lines arranged in the j+1th column (j is an integer between 1 and n) and Of the g source lines placed, g source lines that supply signals of the same polarity are placed adjacent to each other. The display device is characterized in that g is preferably 3 or more.

[0012] In the above, at least one of the g source lines provided adjacently is a plurality of source lines in the j-th column. and at least one of the pixels in the j+1-th column is electrically connected to a part of the pixels in the j+1-th column. During one frame period, g adjacent source lines are electrically connected. In addition, signals of the same polarity are supplied to multiple gate lines, one for each f lines, and f lines are supplied with signals simultaneously. It is preferable that f is 3 or more.

[0013] The display device preferably operates by dot inversion driving.

[0014] The semiconductor layer of the transistor may contain amorphous silicon or metal oxide. stomach. [Effects of the Invention]

[0015] According to one embodiment of the present invention, a display device suitable for large size and a manufacturing method thereof can be provided. Alternatively, a high-resolution display device and a manufacturing method thereof can be provided. Alternatively, a low-cost display device can be provided. A highly reliable display device and a manufacturing method thereof can be provided. Alternatively, a display device using a metal oxide or the like and a manufacturing method thereof can be provided. Alternatively, a novel display device and a manufacturing method thereof can be provided.

[0016] The description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. It can be extracted from descriptions in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0017] [Figure 1] 1A and 1B illustrate a configuration example of a display device. [Figure 2] 1A and 1B illustrate a configuration example of a display device. [Figure 3] 1A and 1B illustrate a configuration example of a display device. [Figure 4] 1A and 1B illustrate a configuration example of a display device. [Figure 5] 1A and 1B illustrate a configuration example of a display device. [Figure 6] 1A and 1B illustrate a configuration example of a display device. [Figure 7] 1A and 1B illustrate a configuration example of a display device. [Figure 8]1A and 1B illustrate a configuration example of a display device. [Figure 9] 1A and 1B illustrate a configuration example of a display device. [Figure 10] 1A and 1B illustrate a configuration example of a display device. [Figure 11] 1A and 1B illustrate a configuration example of a display device. [Figure 12] 1A and 1B illustrate a configuration example of a display device. [Figure 13] 1A and 1B illustrate a configuration example of a display device. [Figure 14] 1A and 1B illustrate a configuration example of a display device. [Figure 15] 1A and 1B illustrate a configuration example of a display device. [Figure 16] 1A and 1B illustrate a configuration example of a display device. [Figure 17] 1A and 1B illustrate a configuration example of a display device. [Figure 18] 1A and 1B illustrate a configuration example of a display device. [Figure 19] 1A to 1C illustrate an example of a method for manufacturing a display device. [Figure 20] 1A to 1C illustrate an example of a method for manufacturing a display device. [Figure 21] 1A to 1C illustrate an example of a method for manufacturing a display device. [Figure 22] 1A and 1B illustrate a configuration example of a display device. [Figure 23] FIG. 2 is a diagram illustrating an example of the configuration of a display unit. [Figure 24] FIG. 2 is a diagram illustrating an example of the configuration of a display unit. [Figure 25] FIG. 2 is a diagram illustrating an example of the configuration of a display unit. [Figure 26] FIG. 2 is a diagram illustrating an example of the configuration of a display unit. [Figure 27] FIG. 2 is a diagram illustrating an example of the configuration of a display unit. [Figure 28] FIG. 2 is a diagram illustrating an example of the configuration of a display unit. [Figure 29] FIG. 2 is a diagram illustrating an example of the configuration of a display unit. [Figure 30] FIG. 2 is a diagram illustrating an example of the configuration of a display unit. [Figure 31] FIG. 2 is a diagram illustrating an example of the configuration of a display unit. [Figure 32]FIG. 2 illustrates an example of the configuration of a driver circuit. [Figure 33] FIG. 2 illustrates an example of the configuration of a driver circuit. [Figure 34] FIG. 2 is a diagram illustrating an example of connection between a demultiplexer and a display unit. [Figure 35] FIG. 2 is a diagram illustrating an example of connection between a demultiplexer and a display unit. [Figure 36] FIG. 2 is a diagram illustrating an example of connection between a demultiplexer and a display unit. [Figure 37] FIG. 2 is a diagram illustrating an example of connection between a demultiplexer and a display unit. [Figure 38] FIG. 1 illustrates an example of a memory circuit. [Figure 39] 1A to 1C illustrate structural examples of transistors. [Figure 40] 1A to 1C illustrate structural examples of transistors. [Figure 41] 1A to 1C illustrate structural examples of transistors. [Figure 42] 1A to 1C illustrate structural examples of transistors. [Figure 43] 1A to 1C illustrate structural examples of transistors. [Figure 44] 1A to 1C illustrate structural examples of transistors. [Figure 45] 1A and 1B are diagrams illustrating an example of the configuration of a display panel. [Figure 46] 1A to 1C are diagrams illustrating a laser irradiation method and a laser crystallization apparatus. [Figure 47] 1A to 1C are diagrams illustrating a laser irradiation method. [Figure 48] 1A to 1C illustrate examples of the configuration of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0018] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. Therefore, the present invention is based on the following embodiments. It should not be construed as being limited to the contents of the description of the state.

[0019] In the configuration of the invention described below, the same parts or parts having similar functions are The same reference numerals are used in common between different drawings, and repeated explanations thereof will be omitted. When referring to a function, the hatch pattern may be the same and no particular symbol may be assigned.

[0020] In each drawing described in this specification, the size of each component, the thickness of a layer, or the area is not clearly indicated. The figures may be exaggerated for clarity and are not necessarily limited to that scale. .

[0021] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. The number is not a numerical limit.

[0022] A transistor is a type of semiconductor device that amplifies current and voltage and controls conduction or non-conduction. In this specification, the transistor is a GFET(Insulated Gate Field Effect Transis) transistors (TFTs) and thin film transistors (TFTs) include.

[0023] Also, the functions of "source" and "drain" may differ depending on whether transistors with different polarities are used or not. , and may be swapped when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" are used interchangeably. This shall be the case.

[0024] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. Switching elements, resistive elements, coils, capacitive elements, and other elements with various functions Includes:

[0025] In this specification, a display panel, which is one aspect of a display device, displays (outputs) an image on a display surface. ) Therefore, the display panel is one aspect of an output device.

[0026] In this specification, the substrate of the display panel is provided with, for example, an FPC (Flexible Printed Circuit). Switched Circuit) or TCP (Tape Carrier Packet e) or COG (Chip On Glass) on the board. The IC is mounted using the assembly method, etc., and is called a display panel module or display module. , or simply referred to as a display panel, etc.

[0027] In this specification, a touch sensor is a sensor that detects a touch or pressure of a detection object such as a finger or a stylus. It has the function of detecting when something moves or approaches. It also detects the location information. Therefore, the touch sensor is one aspect of the input device. For example, the touch sensor may have one or more sensor elements.

[0028] In this specification and the like, a substrate having a touch sensor is referred to as a touch sensor panel, or simply In this specification, the substrate of the touch sensor panel is For example, those with FPC or TCP connectors attached, or those with CO The IC mounted by the G method is called a touch sensor panel module or touch sensor It may be called a module, a sensor module, or simply a touch sensor.

[0029] In this specification, a touch panel, which is one aspect of a display device, is a device that displays an image or the like on a display surface. The function of the display is to display (output) the information when a finger, stylus, or other object touches, presses, or The touch panel has a function as a touch sensor that detects approaching objects. A panel is one aspect of an input / output device.

[0030] The touch panel is, for example, a display panel (or display device) with a touch sensor, a touch sensor It can also be called a functional display panel (or display device).

[0031] The touch panel may also have a configuration including a display panel and a touch sensor panel. Alternatively, the display panel may be configured to have a touch sensor function inside or on its surface. It can also be done as follows.

[0032] In this specification, a connector such as a TCP is provided on the substrate of the touch panel. Touch the board that has the IC mounted on it or the board that has the IC mounted on it by the COG method or the like. It may be called a panel module, a display module, or simply a touch panel.

[0033] (Embodiment 1) In this embodiment, a display device according to one embodiment of the present invention will be described.

[0034] One embodiment of the present invention is a display device having a display portion in which a plurality of pixels are arranged in a matrix. The display section has a plurality of wirings (also called gate lines or scanning lines) to which selection signals are supplied. and a plurality of wirings (source lines, Signal lines, data lines, etc. are provided.

[0035] The gate lines extend along the row direction (also referred to as the "first direction"), and the source lines In the display unit 17, a plurality of At least one of the gate lines and at least one of the plurality of source lines have an overlapping region. Has.

[0036] One pixel has at least one transistor and one display element. The transistor has a conductive layer that functions as a pixel electrode. The gate of the transistor is electrically connected to the gate line or the drain. The other of the source and the drain is electrically connected to a source line.

[0037] Here, it is preferable that the same selection signal is supplied to two or more adjacent gate lines. In other words, it is preferable that the selection periods of these gate lines are the same. It is preferable to use one set of these because it simplifies the configuration of the drive circuit.

[0038] When the same selection signal is supplied to two gate lines, two adjacent pixels in the column direction are simultaneously Therefore, these two pixels are connected to different source lines. That is, two source lines are provided for each column.

[0039] By providing two source lines for each column, one horizontal period can be made longer than before. For example, when the same selection signal is supplied to two gate lines, The length can be doubled. Also, if the same select signal is supplied to the three gate lines, In this case, the length of one horizontal period can be tripled. Since the number of connected pixels 11 is reduced, the output load of the source driver can be reduced. Cut.

[0040] This allows even extremely high-resolution display devices, such as those with 4K or 8K resolution, to achieve It is possible to operate it using transistors with low effective mobility. Even with display devices with resolutions exceeding 10K, 12K, or 16K, the present invention By using one embodiment of the present invention, it is possible to operate the device. Large size: 50 inches or more diagonal, 60 inches or more diagonal, or 70 inches or more diagonal This makes it easier to realize a display device.

[0041] In the case of a configuration in which four source lines are provided for each column, two source lines are provided on the left side of the pixel, Two source lines can be provided on the right side of the pixel, i.e., on the left outer side, left inner side, and right side of the pixel. In this configuration, source lines can be provided on the inner side and the outer right side of the pixel. The source of the transistor electrically connected to the source line intersects with the source line on the left inside of the pixel. In this configuration, the transistor electrically connected to the source line on the right outer side of the pixel is In one aspect of the present invention, the source of the pixel electrode is the same as the source line of the pixel electrode. A conductive layer that can be formed in the same process as the gate of a transistor. and a conductive layer that can be used to form a transistor electrically connected to the source line on the left outside of the pixel. The source of the transistor and the source line on the left inside of the pixel are not short-circuited. In one embodiment, a conductive layer that can be formed in the same process as a pixel electrode and a transistor A conductive layer that can be formed in the same process as the gate is used to form the source on the right outside of the pixel. The source of the transistor electrically connected to the line is short-circuited to the source line on the right inside of the pixel. This allows the configuration to be such that four source lines are provided for each column. Even in this case, the number of steps and the specific number of steps are the same as when one or two source lines are provided for each column. It is possible to provide four source lines without increasing the number of photolithography steps. In other words, four source lines can be provided without increasing the number of photomasks. This makes it possible to suppress an increase in the manufacturing cost of the display device.

[0042] A more specific example of the display device will be described below with reference to the drawings.

[0043] <Example of display device configuration> FIG. 1A is a block diagram of a display device 10 according to one embodiment of the present invention. 1, the display unit 17, the gate driver 12a, the gate driver 12b, and the source driver The display unit 17 has a plurality of pixels 11 arranged in m rows. The electrodes are arranged in a matrix of n columns, where m and n are integers of 2 or more. In this specification, the pixel 11 in the i-th row and j-th column is referred to as pixel 11(i,j). j is an integer between 2 and n. One or both of the source drivers may be referred to as the "drive circuit."

[0044] In FIG. 1A, a gate driver 12a and a gate driver 12b sandwich a display unit 17. 1 shows an example in which the gate driver 12a and the gate driver A plurality of wirings GL0 are connected to the driver 12b. In this specification, the k-th wiring GL0 is denoted as wiring GL0(k), where k is an integer equal to or greater than 1.

[0045] In FIG. 1(A), the wiring GL0(k) is made up of two wirings GL(wiring GL(i), wiring GL(i +1)) are electrically connected to the same selection signal. The wiring GL0 and the wiring GL function as gate lines. In this specification, the i-th wiring GL is referred to as wiring GL(i).

[0046] The gate driver 12a and the gate driver 12b transmit the same selection signal to the same wiring GL0. This allows the display device 10 to be configured with only one gate driver. This allows the charge / discharge time of the wiring GL0 to be shorter than when the wiring GL1 is used. Even in extremely high-resolution displays such as 1080p and 8K, transistors with low field-effect mobility It is possible to operate it using a register. Also, the screen size is 50 inches or more diagonally, This makes it easier to realize large display devices with a diagonal of 60 inches or more, or 70 inches or more.

[0047] In FIG. 1A, a source driver 13a and a source driver 13b are arranged with a display unit 17 interposed therebetween. The source driver 13a and the source driver 13b are provided with a 2× In FIG. 1A, two lines SL are provided for one pixel column. In addition, g (g is an integer of 2 or more) wirings SL are provided for one pixel column. In this case, the source driver 13a and the source driver 13b have g×n wirings SL. Connected.

[0048] In FIG. 1A, the two wirings SL corresponding to the j-th pixel column are designated as wiring SL1(j) and wiring S L2(j). Different signals can be supplied to different wirings SL. For example, different signals can be applied to the wiring SL1(j) and the wiring SL2(j). The wiring SL functions as a source line.

[0049] The source driver 13a and the source driver 13b supply the same signal to the same line SL. This allows the display device 10 to operate in a manner similar to that described above, even if the display device 10 has only one source driver. This allows the charging and discharging time of the wiring SL to be shortened. Even in extremely high-resolution display devices such as LCDs, transistors with low field-effect mobility are used. It is also possible to operate it using a screen size of 50 inches or more diagonally, 60 inches or more diagonally. This makes it easier to realize large display devices with a diagonal of 70 inches or more.

[0050] Figure 1(A) shows an example in which two gate drivers and two source drivers are arranged. However, as a configuration in which only one gate driver or one source driver or both are arranged, Good too.

[0051] One pixel 11 corresponds to one color. When color display is performed using color mixing, the pixel 11 can also be called a sub-pixel.

[0052] In addition, a pixel 11 that controls red light, a pixel 11 that controls green light, and a pixel 11 that controls blue light are also included. The pixels 11 are grouped together to function as one pixel, and the amount of light emitted by each pixel 11 (light emission brightness) ) can be controlled to achieve full color display. 11 each function as a sub-pixel. That is, the three sub-pixels each emit red light. The amount of light, such as green light or blue light, is controlled by each of the three sub-pixels. The color of the light is not limited to a combination of red (R), green (G), and blue (B), but can also be cyan (C), magenta (Magenta), and blue (C). It may also be black (M) or yellow (Y).

[0053] Alternatively, four sub-pixels may be combined to function as one pixel. For example, red light, green light, A subpixel for controlling white light may be added to the three subpixels for controlling colored light and blue light, respectively. By adding a sub-pixel that controls white light, the brightness of the display area can be increased. In addition, there are three sub-pixels that control red light, green light, and blue light, and one sub-pixel that controls yellow light. In addition, three elements that control cyan, magenta, and yellow light, respectively, may be added. A sub-pixel for controlling white light may be added to the sub-pixels.

[0054] By increasing the number of sub-pixels that function as one pixel, red, green, blue, cyan, magenta, and By appropriately combining sub-pixels that control light such as red and yellow, the reproduction of intermediate tones can be improved. Therefore, the display quality can be improved.

[0055] In addition, if the pixels are arranged in a 1920 x 1080 matrix, it becomes what is known as full high-definition. (also known as "2K resolution," "2K1K," or "2K") In addition, for example, the pixel count can be increased to 384. When arranged in a matrix of 0x2160, it becomes what is known as Ultra Hi-Vision (4K resolution). It is also called "4K2K" or "4K" resolution and can display in full color. In addition, for example, the pixel size can be set to 7680 x 4320. When arranged in a matrix, it can produce what is known as super high-definition (8K resolution, 8K4 A display device capable of full-color display at a resolution of 1080p (also known as "8K" or "8K"). By increasing the number of pixels, full color at 16K or 32K resolution can be achieved. It is also possible to realize a display device 10 that can display.

[0056] It is also preferable that the plurality of pixels arranged in the column direction each exhibit the same color. When liquid crystal elements are used as display elements, the pixels arranged in the column direction are It is preferable to provide a colored layer that transmits light of the same color on top of the light source.

[0057] Here, when a transistor with low field effect mobility is used, the display portion of the display device is divided into a plurality of display areas. However, in this method, the characteristics of the driving circuit Due to the fluctuation of brightness, the boundary between the divided display areas becomes visible, reducing visibility. In addition, image processing to divide the input image data in advance may be required. This requires high-speed, large-scale image processing equipment.

[0058] On the other hand, the display device of one embodiment of the present invention uses a transistor with relatively low field-effect mobility. Even in this case, it is possible to drive the display without dividing it into a plurality of display areas.

[0059] Also, as shown in FIG. 1B, the wiring GL0 is not provided, and the gate driver 12a and the gate The port driver 12b may be connected to the wiring GL.

[0060] A protection circuit may be provided in the display device 10. FIG. 2 shows a display device having the configuration shown in FIG. 10, a protection circuit 18a, a protection circuit 18b, a protection circuit 19a, and a protection circuit 19b are provided. The wiring GL0 is connected to the protection circuit 18a or the protection circuit 18b. The protection circuit 19a and the protection circuit 19b are electrically connected to the wiring SL (wiring SL1 , and wiring SL2).

[0061] The protection circuit 18a can be provided on the gate driver 12a side, and the protection circuit 18b can be provided on the gate driver 12b side. That is, the protection circuit 18a and the protection circuit 18b can be provided on the side of the gate driver 12b. b can be provided at positions facing each other across the display unit 17. , the protection circuit 19b can be provided on the source driver 13a side, That is, the protection circuit 19a and the protection circuit 19b can be provided on the display unit 17b side. The two can be provided at opposing positions across the gap.

[0062] By providing a protection circuit in the display device 10, the image can be protected from noise, surges, electrostatic discharge, etc. This can protect the element 11, thereby improving the reliability of the display device 10. do.

[0063] In FIG. 1A, an example in which two source lines are provided per pixel column is shown. In FIG. 3, three source lines (line SL1, line S In the display device 10 shown in FIG. k) consists of three wires GL (wire GL(i), wire GL(i+1), wire GL(i+2)) The same selection signal is applied to these three wires.

[0064] In FIG. 4, four source lines (line SL1, line SL2, line SL3, line SL4) are provided for each pixel column. In the display device 10 shown in FIG. 4, the wiring GL0(k) is Four wires GL (wire GL(i), wire GL(i+1), wire GL(i+2), wire GL (i+3)) and the same selection signal is given to these four wires. In one embodiment of the present invention, five or more source lines may be provided for one pixel column. Needless to say.

[0065] In FIG. 5, the source driver 13a and the source driver 13b are connected to one pixel column. In other words, the same number of source drivers 13a as the number of pixel columns are arranged in the example shown. The source driver 13a is provided along one side of the rectangular display unit 17, and the display unit 17 is sandwiched between the source driver 13a and the The source drivers 13b are provided at positions opposite to the gate electrodes. One driver 12a and one gate driver 12b are arranged for each wiring GL0. FIG. 5 shows an example of a display device 10 in which four source lines are provided for each pixel column. In this case, the number of gate drivers 12a is equal to the number of pixel rows divided by 4, and the number of gate drivers 12a is set along one side of the rectangular display unit 17. The pixel rows are divided by four at a position facing the gate driver 12a and the display unit 17. 5 shows an example in which the same number of gate drivers 12b are provided as the number of gate drivers 12a. This reduces the load on the display driver and eliminates potential drops caused by wiring resistance even in large display devices. This can reduce the accompanying display unevenness.

[0066] The display device 10 may be provided with a reference voltage generating circuit. The reference voltage generation circuit has the function of generating a reference voltage for the signal supplied by the switch driver. , for example, a gamma reference generation circuit.

[0067] FIG. 6 shows a configuration of the display device 10 shown in FIG. 5, in which a reference voltage is supplied to the source driver 13a. a reference voltage generating circuit 16a having a function of supplying a reference voltage to the source driver 13b; The display device 10 is provided with a reference voltage generating circuit 16b having a function of generating a reference voltage. By using the configuration shown in FIG. 6, the voltage of the signal generated from each source driver 13a This can improve the accuracy of the voltage of the signal generated by each source driver 13b. Cut.

[0068] FIG. 7 shows a configuration of the display device 10 shown in FIG. 5, in which a source driver 13a and a source driver 13b is provided with a reference voltage generating circuit 16 having a function of supplying a reference voltage. Even when the display device 10 is configured as shown in FIG. and the accuracy of the voltage of the signal generated from each source driver 13b. Accuracy can be improved.

[0069] The increase in the screen size and resolution of display devices leads to an increase in wiring resistance and parasitic capacitance. Increased wiring resistance can cause delays in signal transmission to the end of the wiring, distortion of the signal waveform, and other problems. This can result in a decrease in display quality, such as uneven display and poor gradation, and an increase in power consumption. In addition, the increase in parasitic capacitance in the wiring also leads to a decrease in display quality and power consumption. This is one of the reasons for increased strength, etc.

[0070] In order to reduce the wiring resistance and parasitic capacitance, the wiring SL is semi-circular like the wiring SLa and the wiring SLb. In the block diagram shown in FIG. 8(A), the display unit 17 The area including the wiring SLa is designated as the display section 17_1, and the area including the wiring SLb is designated as the display section 17_2. It shows 17_2.

[0071] The wiring SLa is electrically connected to the source driver 13a, and the wiring SLb is electrically connected to the source driver 13b. The source driver 13a supplies a signal to the line SLa. The source driver 13b supplies a signal to the line SLb.

[0072] By dividing the wiring SL in half, the wiring resistance and parasitic capacitance can each be halved. Therefore, the influence of signal delay and distortion can be reduced to 1 / 4. This can improve the display quality of the display device, and also reduce the load on the source driver. Therefore, the power consumption of the display device can be reduced.

[0073] Furthermore, the wiring GL may be divided into two halves, such as wiring GLa and wiring GLb (see FIG. 8B). In the block diagram shown in FIG. 8B, the wiring SLa and the wiring GL The area including the wiring SLb and the wiring GLa is designated as the display area 17_1. The area including the wiring SLa and the wiring GLb is indicated as a display portion 17_2, and the area including the wiring SLa and the wiring GLb is indicated as a display portion 17_3. An area including SLb and wiring GLb is shown as a display portion 17_4.

[0074] The wiring GLa is electrically connected to the gate driver 12a, and the wiring GLb is electrically connected to the gate driver 12b. The gate driver 12a supplies a signal to the line GLa. The gate driver 12b supplies a signal to the line GLb.

[0075] Furthermore, when the display unit 17 is divided as shown in FIGS. 8(A) and 8(B), the boundary Therefore, as shown in FIG. 9(A), the wiring S The source driver 13a and the source driver 13b connected to L are arranged alternately or in plural rows. For example, the wiring SL electrically connected to the pixels 11 in the odd-numbered columns may be The wiring SL electrically connected to the pixel 11 in the even-numbered columns is a source wiring SL. It is sufficient to electrically connect it to the driver 13b.

[0076] By using the configuration shown in FIG. 9(A), the dividing stripes are eliminated and the delay in signal transmission to the wiring end is reduced. This makes it possible to reduce the degradation of display quality caused by the distortion of signal waveforms.

[0077] Furthermore, as shown in FIG. 9(B), the gate driver 12a and the gate driver 12b connected to the wiring GL are The driver 12b may be changed every other row or every several rows. For example, The wiring GL electrically connected to the pixel electrodes 1 is electrically connected to the gate driver 12a. The wiring GL electrically connected to 11 may be electrically connected to the gate driver 12b.

[0078] [Example of pixel planar configuration] An example of the planar configuration of pixels arranged in the display unit 17 of the display device 10 shown in FIG. 5 will be described below. explain.

[0079] FIG. 10 shows four pixels arranged in the column direction, namely, pixel 11(i,j), pixel 11(i+1 ,j), pixel 11(i+2,j), and pixel 11(i+3,j). There are.

[0080] Each pixel 11 includes a transistor 30, a liquid crystal element 20, and a capacitor 60.

[0081] The wirings S1 to S4 correspond to source lines, and the wirings G1 to G4 correspond to source lines. For example, in the case shown in FIG. 10, the line S1 corresponds to the line SL1(j). The wiring S2 corresponds to the wiring SL2(j), the wiring S3 corresponds to the wiring SL3(j), The wiring S4 corresponds to the wiring SL4(j). In the case shown in FIG. 10, the wiring G1 corresponds to the wiring GL(i), wiring G2 corresponds to wiring GL(i+1), and wiring G3 corresponds to wiring GL(i The wiring G4 corresponds to the wiring GL(i+3). 60 and is electrically connected to one of the electrodes of the sensor 60, and a predetermined potential is applied to the sensor 60.

[0082] The pixel 11(i, j) has a transistor 30 connected to either the source or the drain of a wiring. S1 is electrically connected, and the gate of the transistor 30 of the pixel 11(i, j) is The wiring G1 is electrically connected to the transistor 30 of the pixel 11(i+1, j). A wiring S3 is electrically connected to either the source or drain of the pixel 11(i+1, j). The gate of the transistor 30 in the pixel 11 (i +2, j) has a source or a drain of the transistor 30, and the wiring S2 is connected to the source or the drain of the transistor 30. The gate of the transistor 30 of the pixel 11(i+2, j) is electrically connected to the wiring G3 is electrically connected to the source of the transistor 30 in the pixel 11(i+3,j). Alternatively, a wiring S4 is electrically connected to one of the drains, and the pixel 11(i+3, j) is enabled. The gate of the transistor 30 is electrically connected to a wiring G4.

[0083] The other of the source and drain of the transistor 30 is connected to one electrode of the capacitor 60. and is electrically connected to one electrode (pixel electrode) of the liquid crystal element 20. A common potential is applied to one electrode.

[0084] The transistor 30 switches between an on state and an off state to receive the voltage supplied from the source line. The transistor 11 has a function of controlling the writing of the signal to the pixel 11. By turning on the transistor 30, the charge corresponding to the signal supplied from the source line is transferred to the corresponding transistor. It is possible to write data to the capacitor 60 electrically connected to the transistor 30. By turning off the transistor 30, the charge written in the capacitance element 60 is held. It is possible.

[0085] FIG. 11(A) shows the layout of pixel 11(i+2,j) and pixel 11(i+3,j). An example is shown.

[0086] In FIG. 11(A) and other figures, components provided on the same layer are marked with the same hatching. In the following figures, the same symbols are used for components on the same layer. Hatching may be used.

[0087] As shown in FIG. 11(A), the wiring G3, the wiring G4, and the wiring CS are arranged in the row direction (horizontal direction). The wirings S1 to S4 extend in the column direction (vertical direction).

[0088] An example of the configuration of the pixel 11(i+2,j) will be described. In the transistor 30, a semiconductor layer 32 is provided on the wiring G3, and a part of the wiring G3 is In addition, a part of the wiring S2 functions as either a source or a drain. The semiconductor layer 32 has a region located between the wiring S2 and the wiring S3.

[0089] The other of the source and drain of the transistor 30 and one of the electrodes of the capacitance element 60 A conductive layer 33a having a function as an electrode is provided so as to be electrically connected to the semiconductor layer 32. In addition, a conductive layer 21 having a function as a pixel electrode is provided, and in the opening 38 Thus, the conductive layer 33a and the conductive layer 21 are electrically connected to each other.

[0090] An example of the configuration of pixel 11(i+3,j) will be described. In the transistor 30, a semiconductor layer 32 is provided on the wiring G4, and a part of the wiring G4 is The semiconductor layer 32 has a function as a gate. do.

[0091] In addition, the conductive layer 51 which functions as one of the source and drain of the transistor 30 is provided so as to be electrically connected to the semiconductor layer 32. The conductive layer 51 is The conductive layer 52 is electrically connected to the conductive layer 52 formed in the same layer through the opening 71. The conductive layer 52 is formed in the opening 72 with the conductive layer 53 formed in the same layer as the wiring G4. The conductive layer 53 is formed in the same layer as the conductive layer 21. The conductive layer 54 is electrically connected to the wiring S4 through the opening 73. , are electrically connected at the opening 74.

[0092] That is, in the pixel 11(i+3,j), the source or drain of the transistor 30 The conductive layer 51 having the function of one of the conductive layers 52, 53, and 54 is The pixel 11(i+3, j) is electrically connected to the wiring S4 via the In this case, the conductive layer 51, the wiring S3, and the wiring S4 are provided in the same layer. The conductive layer 53 has an area overlapping with the wiring S3, but the area overlapping with the source or drain of the transistor 30 is In addition, the conductive layer 52 and the wiring S3 can be prevented from short-circuiting. The conductive layer 54 can be formed in the same process as the conductive layer 21 having the function as a pixel electrode. The conductive layer 53 can be formed in the same process as the wiring G4. Even if four source lines are provided for each column, one or two source lines are provided for each column. The number of steps is the same as that for the case where a wire is provided, specifically, the number of steps in the photolithography process. Four source lines can be provided without increasing the number of photomasks. This allows four source lines to be provided without increasing the manufacturing cost of the display device. This can suppress the increase in

[0093] FIG. 11B shows an example of the layout of pixel 11(i, j) and pixel 11(i+1, j). As shown in FIG. 11(B), the wiring G1 and the wiring G2 extend in the row direction. There are.

[0094] In pixel 11(i,j), as either the source or drain of transistor 30 The conductive layer 51 having a function is connected to the wiring S via the conductive layer 52, the conductive layer 53, and the conductive layer 54. 1. Other than that, the configuration of pixel 11(i,j) and pixel 11( The configuration of i+3,j) is similar.

[0095] In the pixel 11(i+1, j), a part of the wiring S3 is connected to the source of the transistor 30 or The other points are the same as those of the pixel 11(i+1, j). The configuration of pixel 11(i+2,j) is similar to that of pixel 11(i+2,j).

[0096] The above is a description of an example of the planar configuration of a pixel.

[0097] [Example of pixel cross-sectional structure] An example of a cross-sectional configuration of a pixel arranged in the display unit 17 of the display device 10 shown in FIG. 5 will be described below. and explain.

[0098] [Cross-section example 1] FIG. 12 shows an example of a cross section corresponding to the cutting line A1-A2 in FIG. 11(A). This shows an example in which a transmissive liquid crystal element 20 is used as a display element. The substrate 15 side is the display surface side.

[0099] The display device 10 has a configuration in which a liquid crystal 22 is sandwiched between a substrate 14 and a substrate 15. The liquid crystal element 20 has a conductive layer 21 provided on the substrate 14 side and a conductive layer 22 provided on the substrate 15 side. 23 and a liquid crystal 22 sandwiched therebetween. An alignment film 24a is provided between the liquid crystal 22 and the conductive layer 23, and an alignment film 24b is provided between the liquid crystal 22 and the conductive layer 23. do.

[0100] The conductive layer 21 functions as a pixel electrode, and the conductive layer 23 functions as a common electrode, etc. In addition, both the conductive layer 21 and the conductive layer 23 have the function of transmitting visible light. Therefore, the liquid crystal element 20 is a transmissive liquid crystal element.

[0101] A colored layer 41 and a light-shielding layer 42 are provided on the surface of the substrate 15 facing the substrate 14. An insulating layer 26 is provided to cover the light-shielding layer 42 and the insulating layer 26, and a conductive layer 23 is provided to cover the insulating layer 26. The colored layer 41 is provided in an area overlapping the conductive layer 21. The light-shielding layer 42 is , and is provided to cover the transistor 30 and the opening 38, etc.

[0102] A polarizing plate 39a is disposed outside the substrate 14, and a polarizing plate 39b is disposed outside the substrate 15. Furthermore, a backlight unit 90 is provided outside the polarizing plate 39a. In the display device 10 shown in Fig. 12, the substrate 15 side is the display surface side.

[0103] The transistor 30, the capacitance element 60, etc. are provided on the substrate 14. The transistor 30 is , which functions as a selection transistor for the pixel 11. The transistor 30 is The liquid crystal display panel 20 is electrically connected to the liquid crystal element 20 at the liquid crystal display panel 20 .

[0104] The transistor 30 shown in FIG. 12 is a so-called bottom gate type channel etch structure transistor. The transistor 30 includes a conductive layer 31 that functions as a gate, and a gate The insulating layer 34 having a function as an insulating layer, the semiconductor layer 32, and the semiconductor layer 33 having a function as a source and a drain are provided. The semiconductor layer 32 has a pair of conductive layers 33a and 33b that have both functions. The portion overlapping with the conductive layer 31 functions as a channel formation region.

[0105] The conductive layer 31 corresponds to a part of the wiring G3 in FIG. 11(A), and the conductive layer 33b corresponds to The conductive layer 31a and the conductive layer 33c correspond to a part of the wiring S3. It corresponds to a part of the line CS and a part of the wiring S4.

[0106] Materials that can be used for the semiconductor layer 32 will be described later. The transistor 32 is made of a semiconductor containing a metal oxide. In other words, the transistor 30 is made of an OS transistor, which will be described later. By using a transistor, as described above, the charge corresponding to the signal supplied from the source line is This allows the charge to be stored in the capacitance element 60 for a long period of time. This reduces the frequency of loading, i.e., the frequency of refresh operations, thereby reducing the power consumption of the display device 10. The force can be reduced.

[0107] The capacitance element 60 is composed of a conductive layer 31a, an insulating layer 34, and a conductive layer 33a. Furthermore, a conductive layer 33c is provided on the conductive layer 31 with an insulating layer 34 interposed therebetween.

[0108] In addition, insulating layers 82 and 81 are laminated to cover the transistor 30 and the like. The conductive layer 21, which functions as a pixel electrode, is provided on the insulating layer 81. In the opening 38 formed in the edge layer 81 and the insulating layer 82, the conductive layer 21 and the conductive layer 33a The insulating layer 81 preferably functions as a planarizing layer. The insulating layer 82 also serves as a protective film that prevents impurities from diffusing into the transistor 30 and other components. For example, the insulating layer 82 may be made of an inorganic insulating material. Layer 81 can be made of an organic insulating material.

[0109] In this specification and the like, the insulating layer 82 and the insulating layer 81 may be collectively referred to as one insulating layer. be.

[0110] [Cross-section example 2] FIG. 13 shows an example of a cross section corresponding to the section line B1-B2 in FIG. 11(A). The transistor 30 has a conductive layer 31 that functions as a gate and a gate insulating layer. the insulating layer 34 having the function of the source and drain, the semiconductor layer 32, and the The semiconductor layer 32 has a pair of conductive layers 33a and 51. The overlapping portion functions as a channel forming region.

[0111] The conductive layer 31 corresponds to a part of the wiring G4 in FIG. As shown in FIG. 1, the conductive layer 31a, the conductive layer 33b, and the conductive layer 33c are the wirings CS. The conductive layer 33b corresponds to a part of the wiring S3 and a part of the wiring S4. The layer 34 is provided to have an area overlapping the conductive layer 53 .

[0112] As described above, the conductive layer 71 is formed in the insulating layer 81 and the insulating layer 82. The conductive layer 51 and the conductive layer 52 are electrically connected. The conductive layer 52 and the conductive layer 53 are electrically connected through an opening 72 provided in the layer 34. In the opening 73 provided in the insulating layer 81, the insulating layer 82, and the insulating layer 34, a conductive layer is formed. The conductive layer 53 and the conductive layer 54 are electrically connected to each other. The conductive layer 54 and the conductive layer 33c are electrically connected through the opening 74. As described above, the transistor 3 is connected to the conductive layer 52, the conductive layer 53, and the conductive layer 54. A conductive layer 51 having a function as either the source or drain of the semiconductor device 10 and a part of the wiring S4 The openings 72 and 73 are electrically connected to the corresponding conductive layers 33c. , and the conductive layer 33b are sandwiched between them. The conductive layer 51 having the function of one of the drains is connected to the conductive layer 3 corresponding to a part of the wiring S3. 13, the conductive layer 52 and the conductive layer 3b are prevented from shorting out. The conductive layer 54 is formed in the same layer as the conductive layer 21, and the conductive layer 53 is formed in the same layer as the conductive layer 31. and is formed in the same layer as the conductive layer 31a.

[0113] It should be noted that components formed on the same layer may have the same material. For example, the conductive layer 21, the conductive layer 52, and the conductive layer 54 each have the same material. In addition, for example, the conductive layer 31, the conductive layer 31a, and the conductive layer 53 can be respectively They may have the same material.

[0114] [Cross-section example 3] Fig. 14 shows a modified example of the configuration shown in Fig. 13. In Fig. 14, the colored layer 41 is provided on the substrate 14 side. This simplifies the configuration on the substrate 15 side.

[0115] When the colored layer 41 is used as a planarizing film, the insulating layer 81 may be omitted. This reduces the number of steps for manufacturing the display device 10. This can reduce manufacturing costs.

[0116] [Cross-section example 4] Fig. 15 shows a modification of the configuration shown in Fig. 14. In Fig. 15, conductive layer 52, conductive layer 53, and conductive 1 shows an example in which the conductive layer 54, the opening 72, and the opening 73 are omitted. The conductive layer 51 and the conductive layer 33c are connected via a conductive layer 55 formed in the same layer as the conductive layer 21. Specifically, the conductive layer 51 and the conductive layer 55 are electrically connected to each other through the opening 71. are electrically connected, and the conductive layer 33c and the conductive layer 55 are electrically connected in the opening 74. Even in the configuration shown in FIG. 15, the conductive layer 51 and the conductive layer 33b are prevented from short-circuiting. It is possible.

[0117] [Cross-section example 5] 16 shows a modification of the configuration shown in FIG. 15. In FIG. 16, the conductive layer 5 The conductive layer 55a is formed in the same layer as the conductive layer 31 and the conductive layer 31a. The conductive layer 51 and the conductive layer 55a are formed in an opening 71 provided in the insulating layer 34. The conductive layer 33c and the conductive layer 55a are electrically connected to each other. The electrodes are electrically connected at the openings 74 formed therein.

[0118] [Cross-section example 6] 17 and 18, a top-gate transistor is used as the transistor 30. FIG. 17 is a plan view corresponding to FIG. 11(A). FIG. 18 is a plan view corresponding to FIG. 11(B). 18 is an example of a cross section corresponding to the section line C1-C2 in FIG. This corresponds to the cross section shown in 5.

[0119] In FIG. 18, the transistor 30 is provided on the substrate 14. The semiconductor layer 32 of the transistor 30 shown is provided on the substrate 14. 2 has a source region 32s, a drain region 32d, and a channel forming region 32c. In addition, a conductive layer 31 is provided on a channel forming region 32c of the semiconductor layer 32 via an insulating layer 34. The channel forming region 32c and the conductive layer 31 overlap each other via an insulating layer 34. The conductive layer 31 can function as a gate. The insulating layer 34 can also function as a gate insulating layer. It can function as such.

[0120] In the cross-sectional configuration shown in FIG. 18, a conductive layer 33a, a conductive layer 51, a conductive layer 33b, and and conductive layer 33c. Conductive layer 51 is the source or drain of transistor 30. The conductive layer 33a functions as one of the source and drain of the transistor 30. The other electrode functions as one electrode of the capacitor element 60. The region where the conductive layer 31a and the conductive layer 33a overlap each other via the insulating layer 82 is the capacitance element 60. It functions as:

[0121] An opening 38 is provided in a part of the insulating layer 81. In the opening 38, the conductive layer 33a and The conductive layer 21 is electrically connected. In addition, the insulating layer 82 has an opening 72 and an opening 77. In the opening 72, the conductive layer 53 and the conductive layer 51 are electrically connected. In the opening 74, the conductive layer 53 and the conductive layer 33c are electrically connected. The conductive layer 51 and the conductive layer 33c are electrically connected via the conductive layer 53.

[0122] The above is a description of an example of the cross-sectional structure of a pixel.

[0123] [About each component] Each of the above components will be described below.

[0124] [substrate] A material having a flat surface can be used for the substrate of the display panel. The substrate from which the light is extracted is made of a material that transmits the light. For example, glass, quartz, ceramic Materials such as black, sapphire, and organic resin can be used.

[0125] By using a thin substrate, it is possible to reduce the weight and thickness of the display panel. By using a substrate with a thickness that allows flexibility, a flexible display panel can be realized. Alternatively, a thin glass substrate that is flexible can be used. Alternatively, a composite material in which glass and a resin material are bonded together with an adhesive layer may be used.

[0126] [Transistor] A transistor is made up of a conductive layer that functions as a gate, a semiconductor layer, and a gate electrode that functions as a source. a conductive layer having a function as a drain; a conductive layer having a function as a gate insulating layer; and an insulating layer having a function.

[0127] Note that the structure of a transistor included in a display device of one embodiment of the present invention is not particularly limited. For example, a planar type transistor or a staggered type transistor may be used. Alternatively, a top-gate or bottom-gate transistor may be used. Alternatively, gates may be provided above and below the channel. It may be possible.

[0128] [Semiconductor layer] The crystallinity of the semiconductor layer used in the transistor is not particularly limited. Semiconductors (microcrystalline semiconductors, polycrystalline semiconductors, single-crystal semiconductors, or semiconductors having crystalline regions in part) When a crystalline semiconductor is used, transistor characteristics are improved. This is preferable because it can suppress deterioration of the film.

[0129] Semiconductor materials used in transistors include, for example, elements of Group 14 (silicon, germanium, silicon carbide, gallium arsenide, metal oxides, nitride semiconductors, and other compounds Semiconductors, organic semiconductors, etc. can be used.

[0130] For example, amorphous silicon (amorphous silicon) is used as a semiconductor material for transistors. In particular, amorphous silicon is excellent for mass production and can be used for large-area substrates. Generally, amorphous silicon used in transistors is hydrogenated. Therefore, amorphous silicon that contains a lot of hydrogen is called "hydrogenated amorphous silicon." " or "a-Si:H." Amorphous silicon is also called polycrystalline silicon. Since it can be formed at a lower temperature than silicon, the maximum temperature during the manufacturing process can be reduced. Therefore, materials with low heat resistance can be used for the substrate, conductive layer, insulating layer, and the like.

[0131] In addition, semiconductor materials used in transistors include microcrystalline silicon, polycrystalline silicon, and single-crystal silicon. It is also possible to use silicon having crystallinity, such as crystalline silicon. In particular, polycrystalline silicon can be formed at a lower temperature than single crystal silicon and has a higher electrical conductivity than amorphous silicon. It has high field effect mobility and high reliability.

[0132] In addition, an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor material for the transistor. Typically, an oxide semiconductor containing indium can be used. Oxide semiconductors have higher field-effect mobility and higher reliability than amorphous silicon. In addition, oxide semiconductors are easy to mass-produce and can be easily applied to large-area substrates. is.

[0133] In addition, oxide semiconductors, which are a type of metal oxide, have a wider band gap than silicon, Since the carrier density is low, it is preferable to use it for the semiconductor layer of a transistor. When an oxide semiconductor is used for the semiconductor layer, the source and drain of the transistor in the off state This is preferable because it can reduce the current flowing between the electrodes.

[0134] Oxide semiconductors, a type of metal oxide, have an energy gap of 2 eV or more. It is preferable that the voltage is 2.5 eV or more, more preferable that the voltage is 3 eV or more. In this way, by using an oxide semiconductor with a wide energy gap, The off-state current of the transistor can be reduced by adding a metal oxide to the semiconductor layer where the channel is formed. A transistor using an oxide semiconductor, which is one type of transistor, is also called an "OS transistor."

[0135] The low off-state current of OS transistors reduces the capacitance connected in series with the transistor. It is possible to retain the accumulated charge for a long period of time. By applying this technology to the device, the drive circuit can be stopped while maintaining the gradation of the image displayed on each display unit. As a result, a display device with extremely reduced power consumption can be realized.

[0136] The oxide semiconductor, which is a kind of metal oxide, contains, for example, at least indium, zinc, and M( Aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum In-M-Zn oxide containing metals such as silicon, cerium, tin, neodymium, or hafnium In addition, the semiconductor layer may be used as a material for the transistor. It is preferable to include a stabilizer therewith to reduce variations in air properties.

[0137] The stabilizer includes the metals listed above under M, such as gallium, tin, hafnium, etc. Other stabilizers include sulphur, aluminium and zirconium. , the lanthanides lanthanum, cerium, praseodymium, neodymium, samarium, Uropium, gadolinium, terbium, dysprosium, holmium, erbium, Examples include rhenium, ytterbium, and lutetium.

[0138] Examples of metal oxides that form the semiconductor layer include In-Ga-Zn oxides and In-Al -Zn-based oxides, In-Sn-Zn-based oxides, In-Hf-Zn-based oxides, In-La- Zn-based oxides, In-Ce-Zn-based oxides, In-Pr-Zn-based oxides, In-Nd-Z n-based oxides, In-Sm-Zn-based oxides, In-Eu-Zn-based oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides Oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides oxides, In-Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, In-Hf-Ga -Zn-based oxides, In-Al-Ga-Zn-based oxides, In-Sn-Al-Zn-based oxides, In-Sn-Hf-Zn oxide and In-Hf-Al-Zn oxide can be used. do.

[0139] Here, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as its main components. The atomic ratio of In, Ga, and Zn does not matter. For example, In :Ga:Zn=1:1:1 or In:Ga:Zn=2:2:1 Alternatively, the ratio may be In:Ga:Zn=3:1:2, or In:Ga:Zn=4:2:3. Alternatively, In:Ga:Zn=5:1:6 may be used, or a composition close to these may be used. Also, metal elements other than In, Ga, and Zn may be included.

[0140] The semiconductor layer and the conductive layer may contain the same metal element from the oxides. By using the same metal element for the dielectric layer and the conductive layer, manufacturing costs can be reduced. For example, by using a metal oxide target of the same metal composition, the manufacturing cost can be reduced. In addition, the etching gas or etching solution used in processing the semiconductor layer and the conductive layer can be However, the semiconductor layer and the conductive layer do not have to contain the same metal element. For example, during the manufacturing process of a transistor or a capacitor, In this case, metal elements in the film may be released, resulting in a different metal composition.

[0141] When the metal oxide constituting the semiconductor layer is In-M-Zn oxide, The atomic ratio of the metal elements in the sputtering target used for film formation satisfies In≧M. It is preferable that the atomic ratio of the metal elements in such a sputtering target is , In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3 :1:2, In:M:Zn=4:2:4.1, In:M:Zn=2:1:3, In:M: Zn=3:1:2, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In: M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5 etc. It is preferable that the atomic ratio of the semiconductor layers to be formed is adjusted by taking into account the error of the sputtering. This includes a ±40% variation in the atomic ratio of metal elements contained in the ring target.

[0142] The metal oxide constituting the semiconductor layer is CAC-OS or CAC-metal o This can increase the field-effect mobility of the transistor. This can be done.

[0143] It is preferable to use a metal oxide having a low carrier density for the semiconductor layer. The layer has a carrier density of 1×10 17 / cm 3 Less than 1 × 10 15 / cm 3 below , and more preferably 1 × 10 13 / cm 3 Less than or equal to 1×10 11 / cm 3 Below or less, more preferably 1 × 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 The above Such a semiconductor layer can be made of a metal oxide having a low impurity concentration. The semiconductor layer is made of metal oxide, and the defect level density is low, so it has stable characteristics. In this case, examples of impurities include water and hydrogen.

[0144] In this specification and the like, a metal oxide having a low impurity concentration and a low defect level density is referred to as a high-purity intrinsic metal oxide. These metal oxides may be referred to as pure metal oxides or substantially high-purity intrinsic metal oxides.

[0145] High-purity intrinsic or substantially high-purity intrinsic metal oxides have fewer carrier sources, making them less likely to generate carriers. Therefore, the carrier density can be reduced. The threshold voltage rarely becomes negative (also known as normally-on) Furthermore, highly pure intrinsic or substantially highly pure intrinsic metal oxides have a low density of defect states. In addition, the trap level density may be low due to the high purity intrinsic or substantially high purity. Highly intrinsic metal oxides have significantly lower off-state currents and channel widths of 1×10 6 μm Even if the channel length L of the element is 10 μm, the voltage between the source and drain (drain voltage) In the range of 1V to 10V, the off-state current is below the measurement limit of the semiconductor parameter analyzer. Bottom, i.e. 1 x 10 -13 It can achieve a characteristic of A or below.

[0146] Note that a semiconductor layer applicable to one embodiment of the present invention is not limited to the above, and may be any other suitable semiconductor layer. The appropriate composition is selected according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the In order to obtain the required semiconductor characteristics of the transistor, Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density It is preferable to set the degree etc. appropriately.

[0147] The metal oxides that make up the semiconductor layer contain silicon and carbon, which are elements of Group 14. If the semiconductor layer is filled with oxygen, oxygen vacancies may increase, causing the semiconductor layer to become n-type. , the concentration of silicon and carbon in the semiconductor layer (concentrations obtained by secondary ion mass spectrometry) , 2 × 10 18atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 It is preferable to do the following:

[0148] In addition, alkali metals and alkaline earth metals generate carriers when bonded with metal oxides. This may increase the off-state current of the transistor. of alkali metals or alkaline earth metals obtained by secondary ion mass spectrometry in the layer The concentration is 1 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / c m 3 It is preferable to do the following:

[0149] The semiconductor layer may have a non-single crystal structure, for example. In non-single crystalline structures, the amorphous structure is the most defective. The level density is high.

[0150] Amorphous metal oxides, for example, have disordered atomic arrangements and do not have crystalline components. Alternatively, an oxide film having an amorphous structure has, for example, a completely amorphous structure and does not have any crystalline portions.

[0151] The semiconductor layer may have an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a single crystalline structure region, or the like. The mixed film may be a film having two or more of the above-mentioned regions. It may have a single layer structure containing two or more of the above regions, or a laminated structure. .

[0152] [Conductive layer] In addition to the gate, source, and drain of the transistor, various wiring and Materials that can be used for the conductive layers such as electrodes include aluminum, titanium, chromium, Nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tung Examples include metals such as stainless steel, or alloys that contain these as their main components. The film containing silicon can be used as a single layer or as a laminate structure. Single layer structure of aluminum film, double layer structure with aluminum film laminated on titanium film, tungsten Two-layer structure with aluminum film laminated on top of copper-magnesium-aluminum alloy film Two-layer structure with copper film laminated, two-layer structure with copper film laminated on titanium film, copper film laminated on tungsten film Two-layer structure with laminated films: titanium film or titanium nitride film and aluminum film on top of it Or a three-layer structure in which a copper film is laminated and a titanium film or titanium nitride film is further formed thereon. Molybdenum film or molybdenum nitride film is laminated on top of which aluminum film or copper film is stacked. There are three-layer structures, such as a layer of silicon dioxide and a molybdenum film or molybdenum nitride film formed on top of that. It is to be noted that oxides such as indium oxide, tin oxide, or zinc oxide may also be used. The use of copper containing gun is preferred because it improves the controllability of the shape by etching.

[0153] In addition to the gate, source, and drain of a transistor, various wirings that make up a display device are also Examples of conductive materials having light-transmitting properties that can be used for conductive layers such as wires and electrodes include oxides. Indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, gallium doped Conductive oxides such as zinc oxide or graphene can be used. Alternatively, gold, silver, , platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, Use of metal materials such as copper, palladium, or titanium, or alloy materials containing such metal materials. Alternatively, nitrides of the metal materials (for example, titanium nitride) may be used. When using a metal material or an alloy material (or a nitride thereof), the material should have a degree of transparency. Furthermore, a laminated film of the above materials can be used as the conductive layer. By using a laminated film of an alloy of silver and magnesium and indium tin oxide, the conductivity can be increased. These are preferable because they can be used for conducting the various wirings and electrodes that constitute the display device. and the conductive layer of the display element (a conductive layer that functions as a pixel electrode or a common electrode). can also be used.

[0154] [Insulating layer] Examples of insulating materials that can be used for each insulating layer include resins such as acrylic and epoxy. In addition to resins with siloxane bonds, silicon oxide, silicon oxynitride, silicon nitride oxide, Inorganic insulating materials such as silicon, silicon nitride, and aluminum oxide can also be used.

[0155] Insulating films with low water permeability include those containing nitrogen and silicon, such as silicon nitride film and silicon nitride oxide film. and films containing nitrogen and aluminum, such as an aluminum nitride film. Alternatively, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, or the like may be used.

[0156] In addition, when the semiconductor layer contains a metal oxide, the insulating layer having a region in contact with the semiconductor layer is It is preferable to have a region (excess oxygen region) containing oxygen in excess of the stoichiometric composition. For example, the insulating layer 34 and the insulating layer 82 having a region in contact with the semiconductor layer 32 may be formed by adding excess oxygen. It is preferable that the insulating layer has an oxygen region, which allows oxygen to be supplied to the semiconductor layer from the insulating layer. When the semiconductor layer 32 contains a metal oxide, oxygen vacancies are formed in the metal oxide. When this happens, impurities such as hydrogen enter the oxygen vacancies, generating electrons as carriers. This may cause the electrical characteristics of the transistor to deteriorate. When an insulating layer having a region in contact with a semiconductor layer has an excess oxygen region, oxygen is transferred from the insulating layer to the semiconductor layer. This allows oxygen vacancies to be compensated for. In order to provide an excess oxygen region in the insulating layer, for example, For example, the insulating layer may be formed in an oxygen atmosphere. Heat treatment may be performed.

[0157] [Display element] The display device according to one embodiment of the present invention may have various forms or various display elements. The display element can be, for example, an LED (white LED, red LED, green LED, blue LED). EL (electroluminescence) elements (organic and inorganic) including color LEDs EL elements, organic EL elements, inorganic EL elements), transistors (which emit light according to the current) transistors), plasma display panels (PDPs), electron-emitting devices, liquid crystal devices, Electrophoretic elements, grating light valves (GLVs) and digital micromirror devices (DMD), DMS (Digital Micro Shutter) element, MIRASOL (registered trademark) Display, IMOD (Interferometric Modulation) element, pressure MEMS (Micro-Electro-Mechanical Systems) such as electro-ceramic displays In addition to these, display elements using OLEDs and electrowetting elements are also available. However, the contrast, brightness, reflectance, transmittance, etc. may change due to electrical or magnetic effects. The display medium may be a quantum dot.

[0158] An example of a display device using an EL element is an EL display. An example of a display device using this is a field emission display (FED) or is a SED (Surface-conduction E) flat panel display. LCD displays include liquid crystal displays. An example of the device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display). LCD, reflective LCD, direct view LCD, projection LCD) An example of a display device using an electrophoretic element is electronic paper. An example of a display device using quantum dots is a quantum dot display.

[0159] When realizing a semi-transmissive or reflective LCD display, the pixel voltage A part or all of the electrodes may be made to function as a reflective electrode. For example, A part or all of the pixel electrodes may be made of aluminum, silver, or the like. Furthermore, in this case, it is also possible to provide a memory circuit such as an SRAM below the reflective electrode. This further reduces power consumption.

[0160] [Liquid crystal element] As the liquid crystal element, for example, a vertical alignment (VA) model A liquid crystal element to which a vertical alignment mode is applied can be used. ulti-Domain Vertical Alignment) mode, PVA(P atterned Vertical Alignment) mode, ASV (Adva nced Super View mode, etc. can be used.

[0161] In addition, the liquid crystal element may be one that employs various modes. In addition to the VA mode, there are also TN (Twisted Nematic) and IPS (In- Plane-Switching mode, VA-IPS mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetry ic aligned micro-cell) mode, OCB (Optically Compensated Birefringence mode, FLC (Ferrero) lectric Liquid Crystal) mode, AFLC (AntiFerr oelectric Liquid Crystal) mode, ECB (Electri Call Controlled Birefringence mode, guest host A liquid crystal element to which a liquid crystal mode or the like is applied can be used.

[0162] The liquid crystal element is an element that controls the transmission or non-transmission of light by the optical modulation action of the liquid crystal. The optical modulation effect of the liquid crystal is due to the electric field applied to the liquid crystal (horizontal electric field, vertical electric field). The liquid crystal used in the liquid crystal element is Thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, polymer dispersed liquid crystal (PDLC) Polymer Dispersed Liquid Crystal), polymer net Work type liquid crystal (PNLC: Polymer Network Liquid Crystal al), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials include Depending on the conditions, it can be in a cholesteric phase, smectic phase, cubic phase, or chiral nematic phase. phase, isotropic phase, etc.

[0163] The liquid crystal material may be either a positive type liquid crystal or a negative type liquid crystal. The optimum liquid crystal material may be used depending on the mode and design to be applied.

[0164] In addition, an alignment film can be provided to control the alignment of the liquid crystal. When using a liquid crystal, a liquid crystal that exhibits a blue phase without using an alignment film may be used. When the temperature of a cholesteric liquid crystal is increased, the phase transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range. To improve this, a liquid crystal composition containing several weight percent or more of a chiral agent is used in the liquid crystal layer. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response time and optically isotropic In addition, the liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent does not require alignment treatment. The viewing angle dependency is small. Also, no alignment film is required, so rubbing treatment is not required. Therefore, electrostatic breakdown caused by the rubbing treatment can be prevented. This reduces defects and damage to the liquid crystal display device during the manufacturing process.

[0165] In addition, by using a liquid crystal material that operates in the guest-host mode for the liquid crystal element, light diffusion This allows functional components such as layers and polarizing plates to be omitted, thereby improving the productivity of display devices. Furthermore, by not providing a functional member such as a polarizing plate, the reflection of the liquid crystal element can be reduced. The brightness can be increased, and therefore the visibility of the display device can be improved.

[0166] In addition, the switching between the on and off states (bright state) of a reflective liquid crystal display device using a circular polarizer is The switching between the dark and the bright state is achieved by aligning the long axes of the liquid crystal molecules in a direction approximately perpendicular to the substrate, or in a direction approximately parallel to the substrate. Generally, horizontal electric field methods such as IPS mode are used. The liquid crystal element operates in such a way that the long axes of the liquid crystal molecules are approximately parallel to the substrate in both the on and off states. Since the polarizers are aligned in the same direction, it is difficult to use them in reflective liquid crystal display devices.

[0167] The liquid crystal element that operates in VA-IPS mode operates in a horizontal electric field mode and has an on / off state. The state can be switched by aligning the long axis of the liquid crystal molecules in a direction almost perpendicular to the substrate or in a direction almost parallel to the substrate. For this reason, the reflective LCD device uses the in-plane switching method. When using a liquid crystal element that operates in VA-IPS mode, use a liquid crystal element that operates in VA-IPS mode. It is preferable that:

[0168] In one embodiment of the present invention, a transmissive liquid crystal element can be particularly suitably used.

[0169] When using a transmissive or semi-transmissive liquid crystal element, two polarizing plates are placed between a pair of substrates. A backlight is provided outside the polarizing plate. The backlight may be a bottom-type backlight or an edge-light type backlight. Direct backlight with LED (Light Emitting Diode) This is preferred because it makes local dimming easier and increases contrast. In addition, when an edge-light type backlight is used, the module including the backlight can be This is preferable because it allows the thickness of the foil to be reduced.

[0170] In addition, by turning off the edge-lit backlight, a see-through display can be achieved. This can be done.

[0171] [Colored layer] Materials that can be used for the coloring layer include metal materials, resin materials, pigments, and dyes. Examples of such materials include resin materials.

[0172] [Light blocking layer] Materials that can be used for the light-shielding layer include carbon black, titanium black, gold, Examples of the light-shielding layer include metals, metal oxides, and composite oxides including solid solutions of multiple metal oxides. The film may be a film containing a resin material, or may be a thin film of an inorganic material such as a metal. The light-shielding layer may be a laminated film of a film containing the material of the colored layer. A film containing a material used for a colored layer that transmits light of a different color and a film containing a material used for a colored layer that transmits light of a different color are used. By using the same material for the colored layer and the light-shielding layer, This is preferable because it allows the use of common equipment and simplifies the process.

[0173] This concludes the explanation of each component.

[0174] [Example of a method for producing pixels, etc.] An example of a method for fabricating the pixel 11(i+3, j) etc. having the configuration shown in FIG. 13 will be described below. do.

[0175] The thin films (insulating films, semiconductor films, conductive films, etc.) that make up the display device are each formed by sputtering. method, chemical vapor deposition (CVD) method , vacuum evaporation, pulsed laser deposition (PLD) ion) method, Atomic Layer Deposition (ALD) The CVD method can be, for example, plasma-enhanced chemical vapor deposition (PE Examples of thermal CVD include metal organic chemical vapor deposition (MOCVD) and thermal CVD. deposition (MOCVD: Metal Organic CVD) method.

[0176] The thin films (insulating films, semiconductor films, conductive films, etc.) that make up the display device are formed by spin coating, Dip, spray application, inkjet printing, dispensing, screen printing, offset Printing, doctor knife, slit coating, roll coating, curtain coating, knife coating The film can be formed by a method such as a coating method.

[0177] The thin film constituting the display device can be processed using a lithography method or the like. Alternatively, an island-shaped thin film may be formed by a film formation method using a shielding mask. The thin film may be processed by a lint method, a sandblasting method, a lift-off method, or the like.

[0178] When processing using photolithography, the light used for exposure is, for example, i-line (wavelength ray (wavelength 365nm), g-ray (wavelength 436nm), h-ray (wavelength 405nm), and a mixture of these. Other examples include ultraviolet light, KrF laser light, and ArF laser light. The exposure may also be performed by immersion exposure. Extreme ultraviolet (EUV) and X In place of light used for exposure, an electron beam can also be used. Extreme ultraviolet light, X-rays, or electron beams are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photo No sc is required.

[0179] For etching thin films, there are dry etching, wet etching, and sandblasting methods. etc. can be used.

[0180] When manufacturing the display device 10, first, a conductive layer is formed on the substrate 14. Next, photolithography is performed. Patterning is performed by a lithography method or the like, and the conductive layer is processed by an etching method or the like. Thus, the conductive layer 31, the conductive layer 31a, and the conductive layer 53 are formed (FIG. 19(A)). As described above, the conductive layer 31 corresponds to a part of the wiring G3, and the conductive layer 31a corresponds to a part of the wiring CS. Respond.

[0181] Next, the insulating layer 34 is formed. As described above, the insulating layer 34 is formed on the substrate 11 provided in the display device 10. It functions as a gate insulating layer for the transistor.

[0182] Thereafter, a semiconductor layer is formed on the insulating layer 34. For example, a metal oxide is used as the semiconductor layer. In this case, the semiconductor layer can be formed by sputtering. -When using Zn-based oxides, sputtering using In-Ga-Zn-based oxides as the target The film can be formed by the ring method.

[0183] Thereafter, patterning is performed by photolithography or the like, and the formed semiconductor layer is etched. The semiconductor layer 32 is formed by processing it using a coating method or the like (FIG. 19(B)).

[0184] Next, a conductive layer is formed on the insulating layer 34 and the semiconductor layer 32. The conductive layer is patterned by a film method or the like, and then processed by an etching method or the like. As a result, the conductive layer 51, the conductive layer 33a, the conductive layer 33b, and the conductive layer 33c are formed (FIG. 1 9(C)). As previously mentioned, the conductive layer 51 is one of the source and drain of the transistor 30. The conductive layer 33a functions as the other of the source and drain of the transistor 30, and The conductive layer 33b functions as one electrode of the wiring S3 and one electrode of the capacitor 60. The conductive layer 33b corresponds to a portion of the wiring S4, and the conductive layer 33c corresponds to a portion of the wiring S4. 53.

[0185] Next, the insulating layer 82 is formed, and then the insulating layer 81 is formed. After the insulating layer 81 is formed, Mechanical polishing (CMP) The insulating layer 81 is subjected to a planarization process by a method or the like.

[0186] Next, patterning is performed by photolithography or the like, and then etching or the like is performed. By processing the insulating layer 81 and the insulating layer 82, openings 71 and 82 reaching the conductive layer 51 are formed. An opening 38 reaching the conductive layer 33a and an opening 74 reaching the conductive layer 33c are formed. In addition, the insulating layer 81, the insulating layer 82, and the insulating layer 34 are processed by etching or the like. As a result, the openings 72 and 73 reaching the conductive layer 53 are formed so as to sandwich the conductive layer 33b. As a result, the opening 38 and the openings 71 to 74 are formed (FIG. 20(A)). is formed.

[0187] Next, a conductive layer is formed on the insulating layer 81, the opening 38, and the openings 71 to 74. Then, patterning is performed using a photolithography method or the like, and the corresponding The conductive layer is processed to form conductive layer 21, conductive layer 52, and conductive layer 54. (FIG. 20(B)). The conductive layer 21 is electrically connected to the conductive layer 33a through the opening 38. The conductive layer 52 is electrically connected to the conductive layer 51 in the opening 71. The conductive layer 54 is electrically connected to the conductive layer 53 in the opening 73. and electrically connected to the conductive layer 33c in the opening 74. As described above, the conductive layer 21 functions as a pixel electrode of the liquid crystal element provided in the display device 10. In addition, a conductive layer functioning as one of the source and drain of the transistor 30 51 is a conductive layer 33c corresponding to a part of the wiring S4, a conductive layer 52, a conductive layer 53, and a conductive They are electrically connected via the conductive layer 54.

[0188] Next, an alignment film 24a is formed (FIG. 21(A)). A colored layer 41, an insulating layer 26, a conductive layer 23, and an alignment film 24b are formed (FIG. 21(B)). The colored layer 41 is formed by using a photolithography method, a printing method, or an inkjet method. For example, by using an inkjet method, it is possible to manufacture at room temperature and at low vacuum. This allows for resolutions of 4K, 8K, etc. The colored layer 41 can be formed even in such a display device with extremely high resolution. Also, the screen size is 50 inches or more diagonally, 60 inches or more diagonally, or 70 inches or more diagonally. The colored layer 41 can be formed on a large display device. Since the colored layer 41 can be formed without the need for a second layer, the number of steps for manufacturing the display device 10 can be reduced. This allows for a reduction in manufacturing costs.

[0189] Next, an adhesive layer ( The liquid crystal 22 is sealed using a polarizing plate 39a, a polarizing plate 39b, and The backlight unit 90 is formed as described above. It can be made.

[0190] Here, when manufacturing a display device, the fewer photolithography steps in the manufacturing process, the better. That is, the fewer the number of photomasks, the lower the manufacturing cost. .

[0191] For example, in the steps shown in FIGS. 19 and 20 (steps on the substrate 14 side), the shape of the conductive layer 31, etc. 19(A), the step of forming the semiconductor layer 32 (FIG. 19(B)), the step of forming the conductive layer 33a, etc. (FIG. 19C), a process of forming the opening 38 and the like (FIG. 20A), and a process of forming the conductive layer 21 and other processes (Fig. 20(B)). In other words, a backplane substrate can be manufactured using five photomasks. can.

[0192] When the display device is configured to have one or two source lines per pixel column, as shown in FIG. 3 may not be provided, and for example, the configuration of all the pixels 11 may be Even in this case, when manufacturing the backplane substrate, This requires a total of five photolithography processes, meaning five photomasks are required. From the above, in the case of a configuration in which four source lines are provided per pixel column, In this case, the number of photomasks is the same as when one or two source lines are provided per pixel column. This allows the display device to be manufactured using four source lines per pixel column. The manufacturing cost of a display device having such a configuration is reduced by providing one or two source lines per pixel column. Therefore, it is possible to suppress an increase in the manufacturing cost of a display device having such a configuration.

[0193] The above is an explanation of an example of a method for manufacturing pixels and the like.

[0194] [Conductive layer shape] Conductive films that can be used for wiring such as gate lines and source lines are made of low-resistance materials such as metals and alloys. The use of such a material is preferable because it can reduce wiring resistance. In this case, it is effective to increase the width of the wiring. Since the conductive film does not transmit visible light, the width of the wiring itself is large in a transmissive LCD device. In addition, an increase in the number of wirings may result in a decrease in the aperture ratio.

[0195] Therefore, by devising the shape of the edge of the conductive film, it is possible to efficiently transmit the light from the backlight unit. can be taken out.

[0196] FIG. 22A shows a cross-sectional view of a conductive layer 33 constituting a source line and the like and its vicinity. The conductive layer 33 has an inversely tapered end. The conductive layer 33 may be, for example, a conductive layer 33a, a conductive layer 33b, and a conductive layer 33c. It can be layer 51.

[0197] Here, the taper angle is the angle between the bottom surface (the surface in contact with the surface on which the film is formed) and the side surface at the end of the thin film. The taper angle is the angle between the surface and the taper. The taper angle is greater than 0 degrees and less than 180 degrees. If the taper angle is less than 90 degrees, it is called a forward taper, and if it is more than 90 degrees, it is called a reverse taper.

[0198] As shown in FIG. 22(A), the conductive layer 33 has an inverse tapered shape, so that the backlight unit A part of the light 50 incident from the unit is reflected by the side surface of the conductive layer 33 and reaches the liquid crystal 22. As a result, compared with when the side surface of the conductive layer 33 is vertical or has a forward tapered shape, This can increase the light extraction efficiency.

[0199] Here, the taper angle of the conductive layer 33 is greater than 90 degrees and less than 135 degrees, preferably 91 degrees or less. It is preferable that the angle is 120 degrees or less, and more preferably 95 degrees or more and 110 degrees or less.

[0200] In addition, in FIG. 22(B), when the conductive layer 31 constituting the gate line etc. has an inverse tapered shape, By forming the conductive layer 31 in an inverse tapered shape in addition to the conductive layer 33, the The light extraction efficiency can be effectively increased.

[0201] The above is the explanation of the shape of the wiring.

[0202] This embodiment may be appropriately combined with at least a part of another embodiment described in this specification. It can be implemented in combination.

[0203] (Embodiment 2) In this embodiment, the connection relationship between the wiring SL and the pixels 11 in the display section 17 will be described. As an example, a case where a liquid crystal element is used as a display element will be described. 5 and 27 to 29 are block diagrams showing parts of the display unit 17. 23 to 25 and 27 to 29 show the polarity of the signal supplied to the pixel 11. These are indicated by the "+" and "-" symbols.

[0204] <About the drive system> Generally, liquid crystal elements tend to deteriorate easily when a DC voltage is continuously applied. In a display device using a liquid crystal element as a display element, a signal applied to the liquid crystal element for each frame is A driving method that inverts the polarity of the signal (also called "frame inversion driving") is used. For example, a positive polarity signal is supplied to all pixels in odd frames, and a negative polarity signal is supplied to all pixels in even frames. The polarity is not necessarily reversed every frame, but every time the liquid crystal element is used Alternatively, the process may be performed every specific number of frames.

[0205] In addition, in frame inversion driving, which supplies a potential of the same polarity to all pixels, This can easily cause phenomena such as blurring and crosstalk, which can degrade the display quality of the display device. To suppress this phenomenon, source line inversion driving, gate line inversion driving, and Driving methods such as dot inversion driving have been devised.

[0206] [Source line inversion drive] Source line inversion driving (also called "row inversion driving" or "column inversion driving") is a method for The polarity of the signal supplied to the pixel is changed every certain number of frames and every certain number of signal lines (source lines). This is a driving method that inverts the signal.

[0207] [Gate line inversion drive] Gate line inversion driving (also called "row inversion driving" or "row inversion driving") is a method for driving a specific The polarity of the signal supplied to the pixel is reversed for every frame and every specific number of scanning lines (gate lines). This is a driving method that rotates the vehicle.

[0208] [Dot inversion drive] Dot inversion driving (also called "row inversion driving" or "row inversion driving") is a method of driving a specific frame. A drive circuit that inverts the polarity of signals supplied to adjacent pixels in the row and column directions for each pixel. In dot inversion driving, the signal polarity is inverted for each specific number of pixels. For example, the polarity of the signal supplied to each pixel may be inverted, or the polarity of the signal supplied to each of multiple pixels may be inverted. The polarity of the supplied signal may be inverted.

[0209] Dot inversion driving is less prone to flicker than source line inversion driving and gate line inversion driving. It is highly effective in suppressing phenomena such as crosstalk. Bit inversion drive is often used.

[0210] <Connection Relationship Between Wiring SL and Pixel 11> Next, the connection relationship between the wiring SL and the pixels 11 in the display section 17 will be described. The connection relationships when dot inversion driving is performed for each pixel will be described below.

[0211] [Connections when performing dot inversion driving] [Display with two source lines per column] 23(A) and 23(B) show a display section 17 having two source lines per column. In FIG. 23A, there is a pixel 11 in the jth column and a pixel 11 in the j+1th column. Wiring SL1(j) and wiring SL2(j) are provided.

[0212] In addition, in FIG. 23(A), the pixel 11(i, j) and the pixel 11(i+2, j) are connected to the wiring SL1( j), and the pixel 11(i+1, j) and the pixel 11(i+3, j) are electrically connected to the wiring SL 2(j) and is electrically connected to

[0213] That is, in FIG. 23(A), the pixel number provided in the jth column and the i+2xth row (x is an integer equal to or greater than 0) is The pixel 11 is electrically connected to the wiring SL1(j). The pixels 11 provided in the second row are electrically connected to the line SL2(j).

[0214] When performing dot inversion driving with the connection shown in FIG. 23(A), the adjacent wiring SL1(j) and It is necessary to supply signals of different polarities to the wiring SL2(j). Since a parasitic capacitance Cst occurs between the wiring SL1(j) and the wiring SL2( j) is large, the load on the source driver increases, and power consumption tends to increase. stomach.

[0215] Therefore, it is preferable to arrange the wiring SL and the pixel 11 as shown in FIG. In FIG. 3(B), the pixel 11 in the jth column is provided between the line SL1(j) and the line SL2(j). In addition, in FIG. 23B, a wiring S is provided between the pixel 11 in the jth column and the pixel 11 in the j+1th column. L2(j) and wiring SL1(j+1) are provided.

[0216] The pixel 11 provided in the jth column and the i+2xth row is electrically connected to the wiring SL1(j). The pixel 11 provided in the jth column and the i+2x+1th row is connected to the wiring SL2(j). are electrically connected.

[0217] When performing dot inversion driving with the connection shown in FIG. 23(B), the adjacent wiring SL2(j) and A signal of the same polarity is supplied to the wiring SL1(j+1). +1) and the wiring SL1(j+2) are supplied with signals of the same polarity. By making the polarity of the signals transmitted the same, the potential difference between the two wires can be reduced. This reduces the load on the source driver when rewriting signals, and reduces power consumption. Cut.

[0218] [Display with three source lines per column] 24 and 25 show a part of a display section 17 in which three source lines are provided per column. In FIG. 24 and FIG. 25, the pixel 11 in the jth column is connected to the wiring SL2(j) and the wiring SL3(j). The wiring SL1(j) is provided adjacent to the wiring SL2(j). do.

[0219] In addition, in FIG. 24, pixel 11(i,j) is electrically connected to line SL1(j), and pixel 1 1(i+1,j) and pixel 11(i+5,j) are electrically connected to the wiring SL3(j). The pixel 11(i+2,j) and the pixel 11(i+4,j) are electrically connected to the wiring SL2(j). The pixel 11(i+3, j) is electrically connected to the wiring SL1(j+1). do.

[0220] That is, in FIG. 24, the pixel located in the jth column and the i+6xth row (x is an integer equal to or greater than 0) 11 is electrically connected to the wiring SL1(j). The pixel 11 provided in the jth column and the i+6x+5th row is connected to the wiring SL3(j ) are electrically connected to the pixel 11 provided in the jth column and the i+6x+2th row. The pixel 11 provided in the (i+6x+4)th row of the column is electrically connected to the wiring SL2(j). The pixel 11 provided in the jth column and the i+6x+3th row is connected to the wiring SL1(j+1). are electrically connected.

[0221] 25, the wiring SL and the pixel 11 may be connected. (i, j) and pixel 11(i+4, j) are electrically connected to the wiring SL2(j), and pixel 11 (i+1, j), and pixel 11(i+3, j) are electrically connected to the wiring SL3(j). , pixel 11(i+2,j) is electrically connected to the line SL1(j), and pixel 11(i+5, j) is electrically connected to the wiring SL1(j+1).

[0222] That is, in FIG. 25, the pixel located in the jth column and the i+6xth row (x is an integer equal to or greater than 0) The pixel 11 and the pixel 11 provided in the jth column and the i+6x+4th row are electrically connected to the wiring SL2(j). In addition, the pixel 11 provided in the jth column and the i+6x+1th row is connected to the pixel 12 provided in the jth column and the i+6x+2th row. The pixel 11 in the third row is electrically connected to the line SL3(j). The pixel 11 provided in the (i+6x+2)th row of the column is electrically connected to the wiring SL1(j). The pixel 11 provided in the jth column and the i+6x+5th row is connected to the wiring SL1(j+1). are electrically connected.

[0223] In FIGS. 24 and 25, a line SL3(j ), wiring SL1(j+1), and wiring SL2(j+1). SL3(j), wiring SL1(j+1), and wiring SL2(j+1) are located close to each other. A raw capacitance Cst is generated.

[0224] In particular, the wiring SL1(j+1) sandwiched between the wiring SL3(j) and the wiring SL2(j+1) has the following: The parasitic capacitance Cst occurring between the wiring SL3(j) and the parasitic capacitance Cst occurring between the wiring SL2(j+1) Since the amount Cst is added, the load on the source driver is likely to increase. j), wiring SL1(j+1), and wiring SL2(j+1) are supplied with signals of the same polarity. It is preferable that this be done.

[0225] As described above, one aspect of the present invention is particularly effective when there are three or more source lines per column. In other words, when g wirings GL are provided for one pixel column, g is 3 or more. Similarly, when the wiring GL0 is electrically connected to f wirings GL, f is preferably 3 or more. is preferred.

[0226] When performing dot inversion driving with the connections shown in FIGS. 24 and 25, the wiring SL3(j), Signals of the same polarity are supplied to the line SL1(j+1) and the line SL2(j+1). The same applies to wiring SL3(j+1), wiring SL1(j+2), and wiring SL2(j+2). By making the polarity of the adjacent wiring SL the same, the potential between both wirings This reduces the load on the source driver when rewriting signals. This allows for a reduction in power consumption.

[0227] [Drive waveform] FIG. 26 shows an example of a driving waveform for performing dot inversion driving in the display unit 17 shown in FIG. During a certain frame period, the wiring SL1(j) and the wiring SL2(j) are supplied with a positive polarity A signal of negative polarity is supplied to the wiring SL3(j), and a signal of negative polarity is supplied to the wiring SL3(j).

[0228] During the frame period, a pulse-like selection signal is sequentially supplied to all the wirings GL0. For example, when a selection signal is supplied to the wiring GL0(k), three wirings GL(i ), wiring GL(i+1), wiring GL(i+2)) are simultaneously supplied with a selection signal. A positive polarity signal is supplied to the pixel connected to the line GL(i) via the line SL1(j). In addition, a negative polarity signal is supplied to the pixel connected to the line GL(i+1) via the line SL3(j). In addition, the signal of the line SL2(j) is supplied to the pixel connected to the line GL(i+2). A positive polarity signal is supplied via

[0229] All the wirings GL0 can be selected in sequence to supply signals to all the pixels 11. During this frame period, a negative polarity signal is supplied to the wiring SL1(j) and the wiring SL2(j). A positive signal is supplied to the wiring SL3(j). Furthermore, signals of different polarities can be supplied to adjacent pixels in the row and column directions.

[0230] For example, in the dot inversion driving, the polarity of the signal supplied to the wiring SL is inverted for each row. In this method, the voltage amplitude supplied to the line SL becomes large, which places a heavy load on the source driver. In the display device of one embodiment of the present invention, in the dot inversion driving, Even if the number of lines is 1, signals of the same polarity can be supplied to the wiring SL during one frame period. Therefore, the voltage amplitude supplied to the wiring SL can be reduced, and the source driver at the time of signal rewriting can be reduced. This reduces the load on the server and reduces power consumption.

[0231] In addition, in the configuration shown in FIG. 24, signals are supplied to the pixels 11 in three rows by selecting a row at a time. Therefore, the selection period per row can be extended. According to this, it is possible to reliably write signals to the pixels 11, and therefore the display of the display device The display quality can be improved.

[0232] [Display with 4 source lines per column] 27 and 28 show a part of a display section 17 in which four source lines are provided per column. In FIG. 27 and FIG. 28, the pixel 11 in the jth column is connected to the wiring SL1(j) and the wiring SL2( It is provided between the line SL3(j) and the line SL3(j) and the line SL4(j).

[0233] In addition, in FIG. 27, the pixel 11(i, j) and the pixel 11(i+4, j) are connected to the wiring SL1(j). The pixel 11(i+1, j) and the pixel 11(i+5, j) are electrically connected to the wiring SL3(j ), and the pixel 11(i+2,j) and the pixel 11(i+6,j) are electrically connected to the wiring SL2 (j), and pixel 11(i+3,j) and pixel 11(i+7,j) are electrically connected to wiring S It is electrically connected to L4(j).

[0234] That is, in FIG. 27, the pixel located in the jth column and the i+4xth row (x is an integer equal to or greater than 0) 11 is electrically connected to the wiring SL1(j). The pixel 11 is electrically connected to the wiring SL3(j). The pixel 11 provided in the (4x+2)th row is electrically connected to the line SL2(j). In addition, the pixel 11 provided in the jth column and the i+4x+3th row is electrically connected to the wiring SL4(j). It has been done.

[0235] In addition, in FIG. 28, the pixel 11(i, j) and the pixel 11(i+4, j) are connected to the wiring SL2(j). The pixel 11(i+1, j) and the pixel 11(i+5, j) are electrically connected to the wiring SL3(j ), and the pixel 11(i+2, j) and the pixel 11(i+6, j) are electrically connected to the wiring SL1 (j), and pixel 11(i+3,j) and pixel 11(i+7,j) are electrically connected to wiring S It is electrically connected to L4(j).

[0236] In FIGS. 27 and 28, a line SL3(j ), wiring SL4(j), wiring SL1(j+1), and wiring SL2(j+1) are provided. In addition, wiring SL3(j), wiring SL4(j), wiring SL1(j+1), and wiring A parasitic capacitance Cst occurs between each of the lines SL2(j+1).

[0237] When performing dot inversion driving with the connections shown in FIGS. 27 and 28, the wiring SL3(j), Signals of the same polarity are applied to line SL4(j), wiring SL1(j+1), and wiring SL2(j+1). Similarly, the wiring SL3(j+1), the wiring SL4(j+1), and the wiring SL1(j A signal of the same polarity is supplied to the adjacent wiring SL By making the polarity of the two wires the same, the potential difference between the two wires can be reduced. The load on the source driver during rewriting is reduced, and power consumption can be reduced.

[0238] [Display with 5 source lines per column] FIG. 29 shows a part of a display section 17 in which five source lines are provided per column. indicates that the pixel 11 in the jth column is connected to the wiring SL1(j), the wiring SL2(j), and the wiring SL3(j). and the wiring SL4(j) and the wiring SL5(j).

[0239] In addition, in FIG. 29, pixel 11(i,j) is electrically connected to line SL1(j), and pixel 1 1(i+1,j), pixel 11(i+5,j) are electrically connected to the wiring SL4(j), and the pixel The pixel 11(i+2,j) and the pixel 11(i+6,j) are electrically connected to the wiring SL2(j). , pixel 11(i+3,j) and pixel 11(i+7,j) are electrically connected to wiring SL5(j). The pixel 11(i+4,j) and the pixel 11(i+8,j) are connected to the line SL3(j). The pixel 11(i+9, j) is electrically connected to the wiring SL1(j+1). There are.

[0240] That is, in FIG. 29, the pixel located in the jth column and the i+10xth row (x is an integer equal to or greater than 0) The element 11 is electrically connected to the wiring SL1(j). The pixel 11 provided in the jth column and the pixel 11 provided in the i+10x+5th row are connected to the wiring SL 4(j) and is electrically connected to it. In addition, pixel 11 provided in the jth column and the i+6x+2th row and pixel 12 provided in the jth column and the i+6x+6th row are connected to each other. The pixel 11 is electrically connected to the wiring SL2(j). The pixel 11 provided in the third row and the pixel 11 provided in the i+6x+7th row of the jth column are connected to the wiring S L5(j). The pixel located in the jth column and the i+6x+4th row is electrically connected to the pixel The pixel 11 and the pixel 11 provided in the jth column and the i+6x+8th row are electrically connected to the wiring SL3(j). The pixel 11 provided in the jth column and the i+6x+9th row is connected to the wiring SL1(j +1).

[0241] In FIG. 29, a wiring SL4(j) and a wiring SL 5(j), wiring SL1(j+1), wiring SL2(j+1), and wiring SL3(j+1) is provided.

[0242] When performing dot inversion driving with the connection shown in FIG. 29, the wiring SL4(j) and the wiring SL5(j) ), wiring SL1(j+1), wiring SL2(j+1), and wiring SL3(j+1) Similarly, the wiring SL4(j+1), the wiring SL5(j+1), the wiring Signals of the same polarity are applied to SL1(j+2), wiring SL2(j+2), and wiring SL3(j+2). By making the polarity of the adjacent wiring SL the same, the potential difference between the two wirings is reduced. This reduces the load on the source driver when rewriting signals, and reduces power consumption. Power consumption can be reduced.

[0243] [Display with 6 source lines per column] FIG. 30 shows a part of a display section 17 in which six source lines are provided per column. indicates that the pixel 11 in the jth column is connected to the wiring SL1(j), the wiring SL2(j), and the wiring SL3(j). and the wiring SL4(j), the wiring SL5(j), and the wiring SL6(j). are.

[0244] In addition, in FIG. 30, the pixel 11(i, j) and the pixel 11(i+6, j) are connected to the wiring SL1(j). The pixel 11(i+1, j) and the pixel 11(i+7, j) are electrically connected to the wiring SL4(j ), and the pixel 11(i+2, j) and the pixel 11(i+8, j) are electrically connected to the wiring SL2 (j), and pixel 11(i+3,j) and pixel 11(i+9,j) are electrically connected to the wiring S L5(j), and pixel 11(i+4,j) and pixel 11(i+10,j) are electrically connected. The pixel 11(i+5,j) and the pixel 11(i+11, SL6(j) is electrically connected to the wiring SL6(j).

[0245] That is, in FIG. 30, the pixel located in the jth column and the i+6xth row (x is an integer equal to or greater than 0) 11 is electrically connected to the wiring SL1(j). The pixel 11 is electrically connected to the wiring SL4(j). The pixel 11 provided in the 6x+2th row is electrically connected to the line SL2(j). The pixel 11 provided in the jth column and the i+6x+3rd row is electrically connected to the wiring SL5(j). The pixel 11 provided in the jth column and the i+6x+4th row is connected to the wiring SL3(j). The pixel 11 provided in the jth column and the i+6x+5th row is electrically connected to the It is electrically connected to the line SL6(j).

[0246] In FIG. 30, a wiring SL4(j) and a wiring SL 5(j), wiring SL6(j), wiring SL1(j+1), wiring SL2(j+1), and wiring A line SL3(j+1) is provided.

[0247] When performing dot inversion driving with the connection shown in FIG. 30, the wiring SL4(j) and the wiring SL5(j) ), wiring SL6(j), wiring SL1(j+1), wiring SL2(j+1), and wiring SL Similarly, a signal of the same polarity is supplied to the wiring SL4(j+1) and the wiring SL 5(j+1), wiring SL6(j+1), wiring SL1(j+2), wiring SL2(j+2), A signal of the same polarity is supplied to the wiring SL3(j+2). By making them the same, the potential difference between the two wires can be reduced. This reduces the load on the source driver during the period, thereby reducing power consumption.

[0248] [Connection Relationship When Source Line Inversion Driving is Performed] [Display with two source lines per column] FIG. 31(A) shows a part of a display section 17 in which two source lines are provided per column. In 31(A), a wiring SL1(j) and a wiring SL2(j) are provided between the pixel 11 in the jth column and the pixel 11 in the j+1th column. A wiring SL2(j) is provided.

[0249] In addition, in FIG. 31(A), the pixel 11(i, j) and the pixel 11(i+2, j) are connected to the wiring SL1( j), and the pixel 11(i+1, j) and the pixel 11(i+3, j) are electrically connected to the wiring SL 2(j) and is electrically connected to

[0250] That is, in FIG. 31(A), the pixel number provided in the jth column and the i+2xth row (x is an integer equal to or greater than 0) is The pixel 11 is electrically connected to the wiring SL1(j). The pixels 11 provided in the second row are electrically connected to the line SL2(j).

[0251] When source line inversion driving is performed with the connection shown in FIG. 31(A), the adjacent wiring SL1( Similarly, a signal of the same polarity is supplied to the adjacent wiring SL1(j) and the wiring SL2(j). A signal of the same polarity is supplied to the wiring SL2(j+1) and the wiring SL2(j+1). By making the properties the same, the potential difference between the two wires can be reduced. The load on the source driver during switching is reduced, and power consumption can be reduced.

[0252] [Connections when performing gate line inversion driving] [Display with two source lines per column] FIG. 31(B) shows a part of the display section 17 in which two source lines are provided per column. In 31(B), the pixel 11 in the jth column is provided between the wiring SL1(j) and the wiring SL2(j). In addition, in FIG. 31(B), a wiring is provided between the pixel 11 in the jth column and the pixel 11 in the j+1th column. SL2(j) and wiring SL1(j+1) are provided.

[0253] In FIG. 31(B), the pixel 11 provided in the jth column and the i+2xth row is connected to the line SL1(j). The pixel 11 provided in the jth column and the i+2x+1th row is electrically connected to the It is electrically connected to the line SL2(j). The pixel 11 is electrically connected to the wiring SL2(j+1). The pixel 11 provided in the x+1th row is electrically connected to the line SL1(j+1).

[0254] When gate line inversion driving is performed with the connection shown in FIG. 31(B), the adjacent wiring SL2 ( j) and the wiring SL1(j+1) are supplied with signals of the same polarity. A signal of the same polarity is supplied to the adjacent wiring SL2(j+1) and the wiring SL1(j+2). By making the polarity of the two wires the same, the potential difference between the two wires can be reduced. The load on the source driver during rewriting is reduced, and power consumption can be reduced.

[0255] This embodiment may be appropriately combined with at least a part of another embodiment described in this specification. It can be implemented in combination.

[0256] (Embodiment 3) In this embodiment, an example of the configuration of the gate driver 12a and the source driver 13a will be described. do.

[0257] [Gate driver configuration example] FIG. 32(A) shows an example of the configuration of the gate driver 12a. The gate driver 12a includes a resistor 511 and a buffer amplifier 514. It is electrically connected to the wiring GL (or a plurality of wirings GL0).

[0258] A start pulse SP, a clock signal CLK, etc. are input to the shift register 511. The shift register 511 is connected to a line through which a selection signal is supplied in synchronization with a clock signal CLK. The selection signal is amplified by a buffer amplifier 514 and output to the wiring GL The buffer amplifier 514 has a function of increasing the current supply capacity (a function of amplifying power). In addition, to increase the voltage amplitude of the selection signal, the power supply voltage can be switched. The gate driver 12b may also have a level shifter. It can have the same configuration as a.

[0259] [Source driver configuration example] FIG. 32B shows an example of the configuration of the source driver 13a. A register 521, a latch 522, a DA converter 523, and a buffer amplifier 524 are The source driver 13a is electrically connected to a plurality of lines SL.

[0260] A start pulse SP, a clock signal CLK, etc. are supplied to the shift register 521. Digital video information Video is supplied to the latch 522. The latch 522 The DA converter 523 has a function of holding the video information Video. Generates analog video signals using the video information stored in the When the DA converter 523 generates a video signal, Gamma correction may also be performed.

[0261] The shift register 521 is connected to a line through which a video signal is supplied in synchronization with a clock signal CLK. The video signal is input to the line SL via a buffer amplifier 524. The buffer amplifier 524 has the function of increasing the current supply capacity. In order to increase the voltage amplitude of the video signal, a level shifter is provided to switch the power supply voltage. The source driver 13b may have the same configuration as the source driver 13a. This can be done.

[0262] Also, as shown in FIG. 33(A), a demultiplexer is provided between the buffer amplifier 524 and the wiring SL. The demultiplexer 525 may be provided to demultiplex the input signal into a control signal DM It has the function of supplying to one of multiple outputs depending on Xc.

[0263] By providing the demultiplexer 525, the number of signal lines input to the source driver 13a is Therefore, the number of connection terminals of the display device can be reduced, and the reliability of the display device can be improved. It can be increased.

[0264] As shown in FIG. 33(B), a A demultiplexer 525 and an analog latch 526 may be provided. In this configuration, the video signal supplied from the demultiplexer 525 is stored in the analog latch 526. After that, the video signal is amplified by a buffer amplifier 524 and output to a line SL. By providing the analog latch 526, the output of the buffer amplifier 524 can be stabilized. Therefore, unintended potential fluctuations in the wiring SL can be prevented, and the display quality of the display device can be improved. It is possible.

[0265] 34 to 36 show the demultiplexer 5 of the source driver 13a shown in FIG. 33(A). 25 and the display unit 17. The demultiplexer 525 is a multiple demultiplexer 5 35. Therefore, the demultiplexer 525 can be called a "demultiplexer group." 34 to 36, the pth (p is an integer equal to or greater than 1) demultiplexer 535 is It is shown as multiplexer 535(p).

[0266] 34 and 35, a display unit 17 having two source lines per column and a display unit having one input and two outputs 1 shows an example of connections for demultiplexer 525 including power demultiplexer 535.

[0267] In FIG. 34, one of the output terminals of the demultiplexer 535(p) is electrically connected to the wiring SL1(j). The other end is electrically connected to the wiring SL2(j). One of the output terminals of the multiplexer 535(p+1) is electrically connected to the wiring SL1(j+1). The other end is electrically connected to the wiring SL2(j+1).

[0268] In FIG. 35, one of the output terminals of the demultiplexer 535(p) is connected to the wiring SL2(j-1). 1(j) and the other end is electrically connected to the wiring SL1(j). One of the output terminals of the demultiplexer 535(p+1) is electrically connected to the wiring SL2(j). The other end is electrically connected to the wiring SL1(j+1).

[0269] As explained in the above embodiment, by making the polarity of adjacent wirings SL the same, the signal writing This reduces the load on the source driver during switching, and reduces power consumption. 33A to the display unit 17, the source driver 13a shown in FIG. 33A is connected to the display unit 17. It is preferable to use the connection method shown.

[0270] In FIG. 36, a display unit 17 having three source lines per column and a demultiplexer with one input and three outputs are shown. 1 shows an example of connections for a demultiplexer 525 including a demultiplexer 535.

[0271] In Figure 36, the first output terminal of the demultiplexer 535(p) is wired. SL3(j-1) and the second output terminal is electrically connected to the wiring SL1(j). Next, an example is shown in which the third output terminal is electrically connected to the wiring SL2(j). , the first output terminal of the demultiplexer 535(p+1) is the wiring SL3 The first output terminal is electrically connected to the wiring SL1(j+1), and the second output terminal is electrically connected to the wiring SL1(j+1). The third output terminal is electrically connected to the wiring SL2(j+1).

[0272] In FIG. 37, a display unit 17 having four source lines per column and a demultiplexer with one input and four outputs are shown. 1 shows an example of connections for a demultiplexer 525 including a demultiplexer 535.

[0273] In Figure 37, the first output terminal of the demultiplexer 535(p) is wired. Electrically connect it to SL3(j-1), and the second output terminal is electrically connected to SL4(j-1). The third output terminal is electrically connected to the wiring SL1(j), and the fourth output terminal is 10 shows an example of electrical connection with the wiring SL2(j). Of the (p+1) output terminals, the first output terminal is electrically connected to the wiring SL3(j). , the second output terminal is electrically connected to the wiring SL4(j), and the third output terminal is electrically connected to the wiring S L1(j+1), and the fourth output terminal is electrically connected to the wiring SL2(j+1). is connected to.

[0274] [Analog latch] Here, an example of a semiconductor circuit that can be used for the analog latch 526 will be described.

[0275] In the semiconductor circuit shown in FIG. 38A, one of the source and the drain of the transistor 262 is connected to a , the gate of the transistor 263 and one electrode of the capacitor 258 are connected to the memory circuit 2 38B shows an example of the configuration of the transistor 262. A memory circuit 261 in which one of the source and drain is connected to one electrode of the capacitor 258 1 shows an example of the configuration of a.

[0276] The analog latch 526 includes a plurality of latch circuits. 61a can be used as the latch circuit.

[0277] The memory circuit 251a and the memory circuit 261a are connected to each other via a terminal 254 and a transistor 262. The charge inputted through the resistor R1 can be stored at node 257. It is possible to maintain the potential (amount of charge).

[0278] The memory circuit 251a includes a transistor 263. In FIG. Although a p-channel transistor is shown as an example, an n-channel transistor is also used. Alternatively, the transistor 263 may be an OS transistor.

[0279] Both the memory circuit 251a and the memory circuit 261a can hold analog signals. Regarding the memory circuit 251a shown in FIG. 38A and the memory circuit 261a shown in FIG. This will be explained in detail.

[0280] The memory circuit 251a includes a transistor 263 using a first semiconductor and a transistor 264 using a second semiconductor. The circuit includes a transistor 262 and a capacitor 258 .

[0281] The transistor 262 is preferably an OS transistor. By using a transistor with a small off-state current, the amount of charge held in the node 257 Therefore, the information can be stored more accurately.

[0282] In FIG. 38A, a terminal 252 is connected to one of the source and drain of a transistor 263. and the terminal 253 is electrically connected to the other of the source and drain of the transistor 263. The wiring 255 is electrically connected to the gate of the transistor 262. The source or drain of the transistor 262 is electrically connected to the node 257. The other of the source and drain of the transistor 262 is electrically connected to the terminal 254. The gate of the transistor 263 and one electrode of the capacitor 258 are connected to The wiring 256 is electrically connected to the node 257. The other of the two is electrically connected to the other of the two.

[0283] In the memory circuit 251a, the terminal 254 functions as an input terminal, and the terminal 253 functions as an output terminal. In the memory circuit 261a, the terminal 254 functions as an input / output terminal.

[0284] The storage circuit 251a and the storage circuit 261a can hold the charge applied to the node 257. This property allows information to be written, stored, and read as shown below. is.

[0285] [Write and Retention Operations] Regarding the data writing and holding operations of the memory circuit 251a and the memory circuit 261a, First, the potential of the wiring 255 is set to a potential at which the transistor 262 is turned on. As a result, the potential of the terminal 254 is applied to the node 257. A predetermined charge is applied (write). Here, a charge corresponding to an arbitrary potential is applied. After that, the potential of the wiring 255 is set to a potential at which the transistor 262 is turned off. By doing so, the charge is held at the node 257 (holding operation).

[0286] In addition, in the memory circuit 251a, a p-channel transistor is used as the transistor 263. When used, the arbitrary potential is higher than the threshold voltage of the transistor 263. In addition, when an n-channel transistor is used as the transistor 263, an arbitrary potential The potential is set to be lower than the threshold voltage of the transistor 263. This is also the potential at which the transistor 263 is turned off.

[0287] The memory circuit 261a illustrated in FIG. 38B differs from the memory circuit 2 in that it does not include the transistor 263. The other electrode of the capacitor 258 is electrically connected to the wiring 264. The potential of the wiring 264 may be any fixed potential. The memory circuit 261a also stores information in the same manner as the memory circuit 251a. It is possible to write

[0288] [Reading Operation of Memory Circuit 251a] The operation of reading out information stored in the memory circuit 251a will be described. When a potential (constant potential) is applied to the wiring 256, a read potential V R Given this, node 2 In other words, the potential held at the terminal 252 can be read out. potential and readout potential V R By setting A potential such as the above can be output to terminal 253.

[0289] [Reading Operation of Memory Circuit 261a] The data read operation of the memory circuit 261a will be described. When a potential is applied to turn on the terminal 262, the terminal 254 and the node 257 are electrically connected. The potential held at the node 257 is supplied to the capacitor 254. The larger the capacitance value of the capacitor 258, the more preferable it is. can be accurately supplied to terminal 254.

[0290] Furthermore, the memory circuits 251a and 261a do not require a high voltage to write information. For example, unlike conventional nonvolatile memory, The electrons are not injected into the floating gate or extracted from the floating gate. Therefore, the problem of deterioration of the insulator does not occur at all. There is no limit to the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and it is highly reliable. Furthermore, the transistors are in a conductive or non-conductive state, This allows information to be written, enabling high-speed operation.

[0291] Alternatively, the transistor 262 may have a back gate. By controlling the potential supplied to the gate of the transistor 262, the threshold voltage of the transistor 262 can be set arbitrarily. The memory circuit 251b shown in FIG. The difference from the memory circuit 251a is that a transistor having a back gate is used as the memory circuit 2. In the memory circuit 261b shown in FIG. 1(D), the transistor 262 has a back gate. The difference from the memory circuit 261a is that it uses a memory.

[0292] The memory circuit 251b and the memory circuit 261b are connected to the back gate of the transistor 262. is electrically connected to the wiring 259. By controlling the potential supplied to the wiring 259, The threshold voltage of the transistor 262 can be varied arbitrarily.

[0293] This embodiment may be appropriately combined with at least a part of another embodiment described in this specification. It can be implemented in combination.

[0294] (Fourth embodiment) In this embodiment mode, a transistor which can be used for a display device or the like shown in the above embodiment mode will be described. An example of the data will be described with reference to the drawings.

[0295] The transistor shown in FIG. 39(A) has a semiconductor layer between the semiconductor layer 32 and the impurity semiconductor layer 35. It has a layer 37.

[0296] The semiconductor layer 37 may be formed of a semiconductor film similar to the semiconductor layer 32. 37 indicates that the semiconductor layer 32 is etched away during etching of the impurity semiconductor layer 35. This can function as an etching stopper to prevent the 9(A) shows an example in which the semiconductor layer 37 is separated into left and right parts. A part of the insulating film 32 may cover the channel formation region of the semiconductor layer 32 .

[0297] The semiconductor layer 37 may contain impurities at a lower concentration than the impurity semiconductor layer 35. This allows the semiconductor layer 37 to be an LDD (Lightly Doped Drain) region. This can function as a gate electrode, suppressing the hot carrier effect when the transistor is driven. It can be controlled.

[0298] The transistor shown in FIG. 39(B) has an insulating layer 84 on the channel forming region of the semiconductor layer 32. The insulating layer 84 is provided to prevent the conductive layer 33a and the conductive layer 33b from being etched. It functions as an etching stopper.

[0299] The transistor shown in FIG. 39C includes a semiconductor layer 32p instead of the semiconductor layer 32. The semiconductor layer 32p includes a semiconductor film with high crystallinity. For example, the semiconductor layer 32p is a polycrystalline semiconductor. This allows the transistor to have high field-effect mobility. This can be done.

[0300] The transistor shown in FIG. 39(D) has a semiconductor layer 32p in the channel forming region of the semiconductor layer 32. For example, the transistor shown in FIG. 39(D) has a semiconductor film that becomes the semiconductor layer 32. It can be formed by irradiating the area with laser light or the like to crystallize it locally. This makes it possible to realize a transistor with high field-effect mobility.

[0301] The transistor shown in FIG. 39(E) is the same as the transistor shown in FIG. 39(A) except for the semiconductor layer 32 The channel formation region of the semiconductor device includes a crystalline semiconductor layer 32p.

[0302] The transistor shown in FIG. 39(F) is the same as the transistor shown in FIG. 39(B), except that the semiconductor layer 32 The channel formation region of the semiconductor device includes a crystalline semiconductor layer 32p.

[0303] This embodiment may be appropriately combined with at least a part of another embodiment described in this specification. It can be implemented in combination.

[0304] (Embodiment 5) In this embodiment mode, a transistor which can be used for a display device or the like shown in the above embodiment mode will be described. An example of a semiconductor device that is particularly suitable for use in an OS transistor will be described with reference to the drawings. An example of a new transistor structure will now be described.

[0305] <Transistor configuration example> [Configuration example 1] First, as an example of the structure of a transistor, a transistor 200a is shown in FIG. 40A is a top view of the transistor 200a. FIG. 40(B) is a cross-sectional view taken along the dashed line X1-X2 in FIG. 40(A). 40(C) is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 40(A). In order to avoid complication, in FIG. 40(A), the transistor Some of the components of the gate insulating layer 200a are omitted. In the following description, the direction of the dashed dotted line X1-X2 is the channel length direction, and the The direction of the chain line Y1-Y2 may be referred to as the channel width direction. In the following drawings, some of the components are omitted as in FIG. 40(A). It may be illustrated.

[0306] The transistor 200a includes a conductive layer 221 on an insulating layer 224 and a conductive layer 222 on the insulating layer 224 and a conductive layer 223 on the insulating layer 224. The insulating layer 211 on the layer 221, the semiconductor layer 231 on the insulating layer 211, and the semiconductor layer 231 on the and a conductive layer 222a on the insulating layer 211, and a conductive layer 222b on the semiconductor layer 231 and the insulating layer 211. layer 222b, and an insulating layer on the semiconductor layer 231, the conductive layer 222a, and the conductive layer 222b. 212 and a conductive layer 223 on the insulating layer 212.

[0307] The insulating layer 224 may be a substrate. When the insulating layer 224 is used as a substrate, the substrate The substrate may be made of the same material as the substrate 14 shown in the first embodiment.

[0308] Furthermore, the conductive layer 221 and the conductive layer 223 may be, for example, the conductive layer 31 shown in the first embodiment. The insulating layer 211 may include, for example, the insulating material shown in the first embodiment. The conductive layer 222a and the conductive layer 222b may include the same material as the edge layer 34. For example, the conductive layer 33 and the conductive layer 51 shown in the first embodiment may contain the same material. The insulating layer 212 may contain the same material as the insulating layer 82 shown in the first embodiment. can.

[0309] The semiconductor layer 231 may be made of the same material as the semiconductor layer 32 shown in the first embodiment. In this embodiment, the semiconductor layer 231 is a semiconductor layer containing a metal oxide. The explanation will be given assuming this.

[0310] The insulating layer 211 and the insulating layer 212 have an opening 235. The conductive layer 223 has an opening 235. It is electrically connected to the conductive layer 221 via 35 .

[0311] Here, the insulating layer 211 functions as a first gate insulating layer of the transistor 200a. The insulating layer 212 functions as a second gate insulating layer of the transistor 200a. In the transistor 200a, the conductive layer 221 functions as a first gate. The conductive layer 222a functions as either a source or a drain. 2b functions as the other of the source and drain. In a, the conductive layer 223 functions as a second gate.

[0312] The transistor 200a is a so-called channel-etched transistor. It has an algate structure.

[0313] The transistor 200a may also be configured without the conductive layer 223. In this case, the transistor 200a is a so-called channel-etched transistor, and the bottom It is a gate structure.

[0314] As shown in FIGS. 40(B) and (C), the semiconductor layer 231 is formed by the conductive layer 221 and the conductive layer 2 23 and is sandwiched between two conductive layers that function as gates. The length of the conductive layer 223 in the channel length direction and the length of the conductive layer 223 in the channel width direction are The length of the semiconductor layer 231 in the channel length direction and the length of the semiconductor layer 231 in the channel width direction are The entire semiconductor layer 231 is covered with the conductive layer 223 via the insulating layer 212. are.

[0315] In other words, the conductive layer 221 and the conductive layer 223 are provided on the insulating layer 211 and the insulating layer 212. The semiconductor layer 231 is connected to the opening 235 formed in the opening 235 and is positioned outside the side edge of the semiconductor layer 231. It has an area where

[0316] With this configuration, the semiconductor layer 231 included in the transistor 200a is The transistor can be electrically surrounded by the electric field of the conductive layer 221 and the conductive layer 223. As shown in 200a, the electric field of the first gate and the second gate forms a channel forming region. The device structure of the transistor that electrically surrounds the semiconductor layer on which the This can be called an ed channel (s-channel) structure.

[0317] The transistor 200a has an s-channel structure, and therefore functions as a first gate. The conductive layer 221 has an electric field for inducing a channel, which is effectively applied to the semiconductor layer 231. Therefore, the current driving capability of the transistor 200a is improved, and a high on-state current can be obtained. It is also possible to increase the on-current, which allows The transistor 200a can be miniaturized. The conductive layer 231 functions as a first gate and the conductive layer 221 functions as a second gate. Since the transistor 200a has a structure surrounded by the conductive layer 223, Strength can be increased.

[0318] The transistor 200a has an s-channel structure and has high field-effect mobility. Because of its high performance, transistor 200a is used in drive circuits, typically gate drivers. This makes it possible to provide a display device with a narrow frame width (also called a narrow frame).

[0319] [Configuration example 2] Next, as an example of the structure of a transistor, a transistor 200b will be described with reference to FIG. 41A is a top view of a transistor 200b. FIG. 41(B) is a cross-sectional view taken along the dashed line X1-X2 in FIG. 41(A). 41(C) corresponds to the cross section taken along the dashed line Y1-Y2 in FIG. 41(A). This corresponds to a cross-sectional view.

[0320] The transistor 200b includes a semiconductor layer 231, a conductive layer 222a, a conductive layer 222b, and an insulating layer. The transistor 200 differs from the transistor 200a in that the edge layer 212 has a laminated structure.

[0321] The insulating layer 212 is an insulating layer on the semiconductor layer 231, the conductive layer 222a, and the conductive layer 222b. The insulating layer 212 has a semiconductor layer 212a and an insulating layer 212b on the insulating layer 212a. The insulating layer 212 has a function of supplying oxygen to the layer 231. That is, the insulating layer 212 contains oxygen. In addition, the insulating layer 212a is an insulating layer that can transmit oxygen. a is a film for reducing damage to the semiconductor layer 231 when forming the insulating layer 212b to be formed later. It also functions as a

[0322] The insulating layer 212a has a thickness of 5 nm to 150 nm, preferably 5 nm to 50 Silicon oxide, silicon oxynitride, etc., having a thickness of 1 nm or less can be used.

[0323] Furthermore, it is preferable that the insulating layer 212a has a small amount of defects. The spin density of the signal at g=2.001 originating from the silicon dangling bond is 3 x 10 17 spins / cm 3 This is because the insulating layer 212a If the density of defects contained in the insulating layer 212a is high, oxygen will bond to the defects, and the insulating layer 212a This is because oxygen permeability decreases.

[0324] In the insulating layer 212a, all of the oxygen that has entered the insulating layer 212a from the outside is absorbed by the insulating layer 212a. Some oxygen does not move out of the insulating layer 212a and remains in the insulating layer 212a. As oxygen enters the insulating layer 212a, oxygen contained in the insulating layer 212a moves out of the insulating layer 212a. This may cause oxygen migration in the insulating layer 212a. When an oxygen-permeable oxide insulating layer is formed over the insulating layer 212a, The oxygen desorbed from the insulating layer 212b is transferred to the semiconductor layer 231 via the insulating layer 212a. It can be done.

[0325] The insulating layer 212a is formed using an oxide insulating layer having a low density of states due to nitrogen oxides. The density of levels caused by the nitrogen oxides can be calculated by the valence electrons of the metal oxide. can be formed between the energy of the upper edge of the band and the energy of the lower edge of the conduction band of the metal oxide As the oxide insulating layer, a silicon oxynitride film which releases a small amount of nitrogen oxide, or Alternatively, an aluminum oxynitride film or the like which releases a small amount of nitrogen oxides can be used.

[0326] The silicon oxynitride film, which emits a small amount of nitrogen oxide, was analyzed by thermal desorption spectroscopy (TDS). In Thermal Desorption Spectroscopy (TDS), nitrogen This is a film that releases more ammonia than oxide, and typically releases ammonia is 1×10 18 / cm 3 5x10 or more 19 / cm 3 The following is a list of ammonia release rates. The amount is set so that the surface temperature of the film is 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower. This is the amount released by heat treatment.

[0327] Nitrogen oxides (NO x , x is greater than 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2), typically NO or NO forms a level in the insulating layer 212a, etc. The level Therefore, the nitroxide is located within the energy gap of the insulating layer 212a and When the electrons diffuse to the interface of the semiconductor layer 231, the level traps electrons on the insulating layer 212a side. As a result, the trapped electrons may be trapped in the insulating layer 212a and the semiconductor layer 2 31 Because they remain near the interface, they shift the threshold voltage of the transistor in the positive direction. Wow.

[0328] Nitrogen oxides also react with ammonia and oxygen during the heat treatment. The nitrogen oxide contained in a reacts with the ammonia contained in the insulating layer 212b during the heat treatment. As a result, the nitrogen oxides contained in the insulating layer 212a are reduced. At the interface between 12a and the semiconductor layer 231, electrons are less likely to be trapped.

[0329] By using the oxide insulating layer as the insulating layer 212a, the threshold voltage of the transistor It is possible to reduce the shift in the electrical characteristics of the transistor. can.

[0330] The oxide insulating layer has a nitrogen concentration of 6×10 as measured by SIMS. 20 atoms / cm 3 The following is the result.

[0331] The substrate temperature is between 220℃ and 350℃, and PEC using silane and nitrous oxide is used. By forming the oxide insulating layer using a VD method, a dense and hard film can be obtained. It can be formed.

[0332] The insulating layer 212b is an oxide insulating layer containing more oxygen than the oxygen required for the stoichiometric composition. In the oxide insulating layer, part of the oxygen is released by heating. , the oxide insulating layer has an oxygen release rate of 1.0 × 10 19 atoms / cm 3 That's all good Preferably 3.0 x 10 20 atoms / cm 3 The above region is also The amount of release is determined when the temperature of the heat treatment in TDS is between 50°C and 650°C, or between 50°C and 650°C. The total amount of oxygen released is in the range of 550℃ or less. This is the total amount converted into atoms.

[0333] The insulating layer 212b has a thickness of 30 nm to 500 nm, preferably 50 nm or more. Silicon oxide, silicon oxynitride, etc., of 400 nm or less can be used.

[0334] Furthermore, it is preferable that the insulating layer 212b has a small amount of defects. The spin density of the signal at g=2.001 originating from the silicon dangling bond is 1.5 x 10 18 spins / cm 3 Less than, or even 1×10 18 spins / cm 3 It is preferable that the insulating layer 212b is a semiconductor compared to the insulating layer 212a. Since it is farther away from layer 231, it can have a higher defect density than insulating layer 212a.

[0335] In addition, since the insulating layer 212 can be made of the same material, the insulating layer 212a In some cases, the interface between the insulating layer 212b and the insulating layer 212b may not be clearly visible. In this example, the interface between the insulating layer 212a and the insulating layer 212b is shown by a broken line. In the embodiment, the two-layer structure of the insulating layer 212a and the insulating layer 212b has been described. The present invention is not limited to this, and may be embodied in various ways, such as a single layer structure of the insulating layer 212a or a laminated structure of three or more layers. You may do so.

[0336] In the transistor 200b, the semiconductor layer 231 is a semiconductor layer 231_ on the insulating layer 211. 1 and a semiconductor layer 231_2 on the semiconductor layer 231_1. The semiconductor layer 231_1 and the semiconductor layer 231_2 each contain the same element. The semiconductor layer 231_1 and the semiconductor layer 231_2 each independently contain the elements contained in the semiconductor layer 231. It is preferable that the

[0337] The semiconductor layer 231_1 and the semiconductor layer 231_2 each independently have the number of In atoms. It is preferable that the ratio of the number of atoms of M is larger than the ratio of the number of atoms of M. As an example, the semiconductor layer 231_1 The ratio of the number of atoms of In, M, and Zn in the semiconductor layer 231_2 is In:M:Zn=4 It is preferable that the ratio is in the vicinity of 2:3. Here, "in the vicinity" means that when In is 4, M is 1.5 or more and 2. 0.5 or less, and Zn is 2 or more and 4 or less. The ratio of the number of atoms of In, M, and Zn in the conductor layer 231_2 is In:M:Zn=5:1:6. In this way, the semiconductor layer 231_1 and the semiconductor layer 231_2 are preferably in the vicinity of each other. By making the composition approximately the same, the same sputtering target can be used for formation, making it possible to manufacture It is possible to reduce costs. Also, when using the same sputtering target, The semiconductor layer 231_1 and the semiconductor layer 231_2 are successively formed in a vacuum in the same chamber. Since the semiconductor layer 231_1 and the semiconductor layer 231_2 can be formed as a film, impurities are not present at the interface between the semiconductor layer 231_1 and the semiconductor layer 231_2. It is possible to suppress the uptake of

[0338] Here, the semiconductor layer 231_1 has a region with lower crystallinity than the semiconductor layer 231_2. The crystallinity of the semiconductor layer 231_1 and the semiconductor layer 231_2 may be, for example, For example, analysis can be performed using X-ray diffraction (XRD). Or, a transmission electron microscope (TEM) This can be analyzed using a microscope.

[0339] The low-crystallinity region of the semiconductor layer 231_1 becomes a diffusion path for excess oxygen, and the semiconductor layer 231_ The excess oxygen can be diffused into the semiconductor layer 231_2, which has higher crystallinity than the semiconductor layer 231_1. In this way, the semiconductor layer has a stacked structure with different crystal structures, and the region with low crystallinity is formed by the diffusion of excess oxygen. By using this as a path, a highly reliable transistor can be provided.

[0340] In addition, the semiconductor layer 231_2 has a region with higher crystallinity than the semiconductor layer 231_1. This can suppress impurities that may be mixed into the semiconductor layer 231. By increasing the crystallinity of the conductive layer 222a and the conductive layer 222b, damage during processing can be reduced. The surface of the semiconductor layer 231, that is, the surface of the semiconductor layer 231_2, can be suppressed. The surface is exposed to an etchant or etching agent used in processing the conductive layer 222a and the conductive layer 222b. However, if the semiconductor layer 231_2 has a region with high crystallinity, In this case, the semiconductor layer 231_1 has better etching resistance than the semiconductor layer 231_1 having low crystallinity. The semiconductor layer 231_2 functions as an etching stopper.

[0341] The semiconductor layer 231_1 has a region with lower crystallinity than the semiconductor layer 231_2. This can result in a high carrier density.

[0342] Furthermore, when the carrier density of the semiconductor layer 231_1 increases, the conduction band of the semiconductor layer 231_1 The Fermi level may become relatively high in the semiconductor layer 231_1. The lower end of the conduction band is lowered, and the lower end of the conduction band of the semiconductor layer 231_1 and the gate insulating layer (here In this case, the energy difference between the trap level that may be formed in the insulating layer 211 may become large. The larger the energy difference, the less charge is trapped in the gate insulating layer. This may reduce the fluctuation in the threshold voltage of the transistor. When the carrier density of the layer 231_1 is increased, the field effect mobility of the semiconductor layer 231 is increased. This can be done.

[0343] In the transistor 200b, an example in which the semiconductor layer 231 has a stacked structure of two layers is shown. However, the present invention is not limited to this, and a configuration in which three or more layers are laminated may also be used.

[0344] The conductive layer 222a included in the transistor 200b includes a conductive layer 222a_1 and a conductive layer 222 a_1 and a conductive layer 222a_3 on the conductive layer 222a_2. The conductive layer 222b included in the transistor 200b includes a conductive layer 222b_1 and The conductive layer 222b_2 on the conductive layer 222b_1 and the conductive layer 222b_2 on the conductive layer 222b_2 _3 and,.

[0345] For example, the conductive layer 222a_1, the conductive layer 222b_1, the conductive layer 222a_3, and the conductive layer 222b_3 includes titanium, tungsten, tantalum, molybdenum, indium, and gallium. It is preferable that the alloy contains one or more selected from the group consisting of sodium, tin, and zinc. The conductive layer 222a_2 and the conductive layer 222b_2 may be made of copper, aluminum, and silver.

[0346] More specifically, the conductive layer 222a_1, the conductive layer 222b_1, the conductive layer 222a_3, and and conductive layer 222b_3 is made of In—Sn oxide or In—Zn oxide, and conductive layer 222 Copper can be used for the a_2 and conductive layer 222b_2.

[0347] The end of the conductive layer 222a_1 is located outside the end of the conductive layer 222a_2. The conductive layer 222a_3 covers the upper and side surfaces of the conductive layer 222a_2 and has a conductive The conductive layer 222b_1 has an area in contact with the conductive layer 222a_1. The conductive layer 222b_3 has an area located outside the end of the conductive layer 22 The conductive layer 222b_1 covers the upper and side surfaces of the conductive layer 222b_2 and has a region in contact with the conductive layer 222b_1.

[0348] By adopting the above-mentioned structure, the wiring resistance of the conductive layer 222a and the conductive layer 222b is reduced, and This is preferable because it can suppress the diffusion of copper into the semiconductor layer 231 .

[0349] [Configuration Example 3] Next, as an example of the structure of a transistor, a transistor 200c will be described with reference to FIG. 42A is a top view of the transistor 200c. FIG. 42(B) is a cross-sectional view taken along the dashed line X1-X2 in FIG. 42(A). 42(C) corresponds to the cross section taken along the dashed line Y1-Y2 in FIG. 42(A). This corresponds to a cross-sectional view.

[0350] The transistor 200c has a conductive layer 221 on an insulating layer 224 and a conductive layer 221 on an insulating layer 224. The insulating layer 211 on the layer 224, the semiconductor layer 231 on the insulating layer 211, and the semiconductor layer 231 and and an insulating layer 216 on the insulating layer 211, and a conductive layer on the semiconductor layer 231 and the insulating layer 216. 222a, a conductive layer 222b on the semiconductor layer 231 and on the insulating layer 216, and the insulating layer 216 , the insulating layer 212 on the conductive layer 222a and the conductive layer 222b, and the conductive layer 223 and has.

[0351] The insulating layer 211, the insulating layer 216, and the insulating layer 212 have an opening 235. The conductive layer 221, which functions as the first gate of the gate electrode 200c, is exposed through an opening 235. The conductive layer 223 serving as the second gate of the transistor 200c is electrically connected to the conductive layer 223. The insulating layer 216 also has an opening 238a and an opening 238b. A conductive layer 222a that functions as either the source or the drain of the transistor 200c. The transistor 20 is electrically connected to the semiconductor layer 231 through the opening 238a. The conductive layer 222b having the function of the other of the source and drain of the Oc is formed in the opening 23. It is electrically connected to the semiconductor layer 231 via 8b.

[0352] The insulating layer 216 functions as a channel protection layer of the transistor 200c. When the conductive layer 216 is not provided, the conductive layer 222a and the conductive layer 222b are formed by etching or the like. When forming the semiconductor layer 231, the channel forming region of the semiconductor layer 231 may be damaged. This may cause the electrical characteristics of the transistor to become unstable. After the openings 238a and 238b are formed, a conductive layer is formed and then etched. The conductive layer 222a and the conductive layer 222b are formed by processing the semiconductor substrate 100 by a semiconductor processing method or the like. Damage to the channel forming region of the conductor layer 231 can be suppressed. This stabilizes the electrical characteristics of the transistor, enabling the realization of a highly reliable transistor.

[0353] Insulating layer 216 can include, for example, similar materials to insulating layer 212 .

[0354] The insulating layer 216 preferably has an excess oxygen region. By having the above structure, oxygen can be supplied to the channel formation region of the semiconductor layer 231. Therefore, oxygen vacancies formed in the channel formation region can be compensated for by excess oxygen. Therefore, a highly reliable display device can be provided.

[0355] After the openings 238a and 238b are formed, an impurity element is added to the semiconductor layer 231. Specifically, it is preferable to add an element that forms an oxygen vacancy or an element that bonds with the oxygen vacancy. As a result, the conductive property of the semiconductor layer 231 is improved, as will be described in detail later. The region overlapping with the layer 222a (either the source region or the drain region), and the conductive layer 222 The conductivity of the region overlapping with b (the other of the source region and the drain region) can be increased. This improves the current driving capability of the transistor 200c, and high on-current characteristics are obtained. This makes it possible to

[0356] The transistor 200c is a so-called channel protection type transistor, and It is a rugate structure.

[0357] The transistor 200c is s By having such a configuration, the transistor 200c has a -channel structure. The semiconductor layer 231 included therein is electrically connected by the electric field of the conductive layer 221 and the conductive layer 223. It can be surrounded.

[0358] The transistor 200c has an s-channel structure, and therefore the conductive layer 221 The electric field for inducing a channel is effectively applied to the semiconductor layer 231 by the electric layer 223. This improves the current driving capability of the transistor 200c, resulting in a high on-state current. It is also possible to increase the on-current, which allows The transistor 200c can be miniaturized. The conductor layer 231 has a structure surrounded by the conductive layer 221 and the conductive layer 223. Therefore, the mechanical strength of the transistor 200c can be increased.

[0359] Note that the transistor 200c may not include the conductive layer 223. In this case, the transistor 200c is a so-called channel protection type transistor, and It is a gate structure.

[0360] [Configuration Example 4] Next, an example of the structure of a transistor will be explained using FIGS. 43(A), (B), (C), and (D). and explain.

[0361] 43(A) and (B) are cross-sectional views of the transistor 200d, and FIGS. 43(C) and (D) are cross-sectional views of the transistor 200d. 1 is a cross-sectional view of a transistor 200e. Transistor 200e is a variation of transistor 200b shown above. Therefore, in Figures 43(A), (B), (C), and (D), The parts having the same functions as the transistors 200b and 200c are the same. The same reference numerals are used and detailed explanations are omitted.

[0362] 43(A) is a cross-sectional view of the transistor 200d in the channel length direction, and FIG. FIG. 43B is a cross-sectional view of the transistor 200d in the channel width direction. 43(D) is a cross-sectional view of the transistor 200e in the channel length direction. FIG. 10 is a cross-sectional view of 0e in the channel width direction.

[0363] The transistor 200d shown in FIGS. 43(A) and 43(B) has the following characteristics compared to the transistor 200b: The conductive layer 223 and the opening 235 are not provided. Compared to transistor 200b, insulating layer 212, conductive layer 222a, and conductive layer 222b The configuration is different.

[0364] In the transistor 200d, the insulating layer 212 is formed by an insulating layer 212c and a thin film transistor 212b. The insulating layer 212c is made of a material that supplies oxygen to the semiconductor layer 231. and a function of preventing the intrusion of impurities (typically, water, hydrogen, etc.). The insulating layer 212c may be an aluminum oxide film, an aluminum oxynitride film, or an aluminum nitride film. In particular, the insulating layer 212c may be a reactive sputtering film. It is preferable that the aluminum oxide film be formed by a deposition method. An example of a method for forming an aluminum oxide film by sputtering is the following method. Examples include:

[0365] First, an inert gas (typically Ar gas) and oxygen gas are introduced into the sputtering chamber. Then, a gas mixture of the above is introduced. By applying a voltage to the aluminum target, an aluminum oxide film can be formed. The power source for applying voltage to the aluminum target can be a DC power source, an AC power source, Alternatively, an RF power supply may be used. In particular, a DC power supply is preferred because it improves productivity. .

[0366] The insulating layer 212d has a function of suppressing the intrusion of impurities (typically water, hydrogen, etc.). The insulating layer 212d may be a silicon nitride film, a silicon nitride oxide film, or a silicon oxynitride film. In particular, the insulating layer 212d may be formed by the PECVD method. The silicon nitride film formed by the PECVD method has high This is preferable because it is easy to obtain a high film density. The silicon film may have a high hydrogen concentration in the film.

[0367] In the transistor 200d, an insulating layer 212c is disposed below the insulating layer 212d. Therefore, hydrogen contained in the insulating layer 212d does not diffuse to the semiconductor layer 231 side, or It is difficult to spread.

[0368] Unlike the transistor 200b, the transistor 200d is a single-gate transistor. By using a single gate transistor, the number of masks can be reduced. This allows for increased productivity.

[0369] The transistor 200e shown in FIGS. 43(C) and 43(D) has the following characteristics compared to the transistor 200c: The configurations of the insulating layer 216 and the insulating layer 212 are different. has insulating layer 216a instead of insulating layer 216, and insulating layer 212 instead of insulating layer 213. It has 2d.

[0370] The insulating layer 216a has the same function as the insulating layer 212c.

[0371] The structure of the transistor 200d and the transistor 200e reduces the need for large capital investment. It can be produced using existing production lines without the need for additional capital investment. Fast silicon manufacturing plants can be easily replaced with oxide semiconductor manufacturing plants. This becomes:

[0372] [Configuration Example 5] Next, as an example of the structure of a transistor, a transistor 200f will be described with reference to FIG. 44A is a top view of a transistor 200f. FIG. 44(B) is a cross-sectional view taken along the dashed line X1-X2 in FIG. 44(A). 44(C) corresponds to the cross section taken along the dashed line Y1-Y2 in FIG. 44(A). This corresponds to a cross-sectional view.

[0373] The transistor 200f shown in FIGS. 44(A), (B), and (C) has a conductive layer 224 on an insulating layer 224. 221, an insulating layer 211 on the conductive layer 221 and the insulating layer 224, and a semiconductor layer on the insulating layer 211. A conductor layer 231, an insulating layer 212 on the semiconductor layer 231, and a conductive layer 223 on the insulating layer 212. , an insulating layer 215 on the insulating layer 211 , on the semiconductor layer 231 , and on the conductive layer 223 . The semiconductor layer 231 has a channel forming region 231i overlapping with the conductive layer 223 and an insulating layer 2 a source region 231s in contact with the insulating layer 215, and a drain region 231d in contact with the insulating layer 215. Has.

[0374] The insulating layer 215 contains nitrogen or hydrogen. and the drain region 231d, the nitrogen or hydrogen in the insulating layer 215 is sorbed. The source region 231s and the drain region 231d are doped with ions. The carrier density of the drain region 231d is increased by adding nitrogen or hydrogen. do.

[0375] The transistor 200f is connected to the source via an opening 236a provided in the insulating layer 215. The transistor region 231s may have a conductive layer 222a electrically connected to the conductive layer 222a. The capacitor 200f is connected to the drain region 231d through an opening 236b provided in the insulating layer 215. The conductive layer 222b may be electrically connected to the

[0376] The insulating layer 211 functions as a first gate insulating layer, and the insulating layer 212 functions as a second gate insulating layer. The insulating layer 215 also functions as a protective insulating layer. .

[0377] Furthermore, the insulating layer 212 has an excess oxygen region. As a result, excess oxygen can be supplied into the channel formation region 231i of the semiconductor layer 231. Therefore, oxygen vacancies that may be formed in the channel formation region 231i can be compensated for by excess oxygen. Since the liquid crystal display device can be filled with the liquid crystal, a highly reliable display device can be provided.

[0378] In order to supply excess oxygen into the semiconductor layer 231, a layer formed below the semiconductor layer 231 is In this case, excess oxygen may be supplied to the insulating layer 211. The excess oxygen is contained in the source region 231s and the drain region 231d of the semiconductor layer 231. Excess oxygen can also be supplied to the source region 231s and the drain region 231d. When the voltage is supplied, the resistance of the source region 231s and the drain region 231d may become high. be.

[0379] On the other hand, the insulating layer 212 formed above the semiconductor layer 231 has excess oxygen. This makes it possible to selectively supply excess oxygen only to the channel formation region 231i. Alternatively, the channel forming region 231i, the source region 231s, and the drain region 231s may be formed by After supplying excess oxygen to the source region 231s and the drain region 231d, By selectively increasing the carrier density, the source region 231s and the drain region 231 It is possible to prevent the resistance of d from increasing.

[0380] The source region 231s and the drain region 231d of the semiconductor layer 231 are Each of them preferably has an element that forms an oxygen vacancy or an element that bonds with the oxygen vacancy. Representative examples of the element that forms the oxygen vacancy or the element that bonds to the oxygen vacancy include hydrogen, Examples include boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases. Representative examples of rare gas elements include helium, neon, argon, krypton, and xenon. The insulating layer 215 contains one or more of the above elements that form oxygen vacancies. In this case, the diffusion from the insulating layer 215 to the source region 231s and the drain region 231d occurs. and / or the source region 231s and the drain region 231 It is added during d.

[0381] When an impurity element is added to a metal oxide, the bond between the metal element and oxygen in the metal oxide is broken. When impurity elements are added to a metal oxide, oxygen vacancies are formed. The oxygen that was bonded to the metal element in the substance bonds with the impurity element, and the oxygen is released from the metal element. As a result, the carrier density in the metal oxide increases, and the The electrical conductivity increases.

[0382] The conductive layer 221 functions as a first gate, and the conductive layer 223 functions as a second gate. The conductive layer 222a functions as a gate, the conductive layer 222b functions as a source, and the conductive layer 222c functions as a gate. has a function as a drain.

[0383] As shown in FIG. 44(C), an opening 237 is formed in the insulating layer 211 and the insulating layer 212. The conductive layer 221 is electrically connected to the conductive layer 223 through the opening 237. Therefore, the same potential is applied to the conductive layer 221 and the conductive layer 223. The opening 237 may not be provided, and different potentials may be applied to the conductive layer 221 and the conductive layer 223. Alternatively, the conductive layer 221 may be used as a light-shielding film without providing the opening 237. For example, By forming the conductive layer 221 from a light-shielding material, the channel forming region 231i is This can suppress light from below that is projected.

[0384] As shown in FIGS. 44(B) and (C), the semiconductor layer 231 functions as a first gate. and a conductive layer 223 having a function as a second gate. and is sandwiched between two conductive layers that function as gates.

[0385] The transistor 200f is also connected to the transistors 200a, 200b, and The transistor 200c has an s-channel structure. As a result, the semiconductor layer 231 included in the transistor 200f functions as a first gate. The conductive layer 221 having the function of the second gate and the conductive layer 223 having the function of the second gate are electrically connected. It can be electrically surrounded by

[0386] The transistor 200f has an s-channel structure, and therefore the conductive layer 221 The electric field for inducing a channel is effectively applied to the semiconductor layer 231 by the electric layer 223. This improves the current driving capability of the transistor 200f, resulting in a high on-state current. It is also possible to increase the on-current, which allows The transistor 200f can be miniaturized. The conductor layer 231 has a structure surrounded by the conductive layer 221 and the conductive layer 223. Therefore, the mechanical strength of the transistor 200f can be increased.

[0387] The transistor 200f can be determined by the position of the conductive layer 223 relative to the semiconductor layer 231 or the From the method of forming the conductive layer 223, a TGSA (Top Gate Self Align) type It may also be called a FET.

[0388] In the transistor 200f, similarly to the transistor 200b, the semiconductor layer 231 It may be configured by laminating two or more layers.

[0389] In the transistor 200f, the insulating layer 212 is formed only in a portion overlapping with the conductive layer 223. However, the present invention is not limited to this, and the insulating layer 212 may have a configuration in which the semiconductor layer 231 is covered. Alternatively, the conductive layer 221 may not be provided.

[0390] This embodiment may be appropriately combined with at least a part of another embodiment described in this specification. It can be implemented in combination.

[0391] (Embodiment 6) Hereinafter, the configuration of the CAC (cl oud-aligned composite)-OS that can be used in the transistor disclosed in one aspect of the present invention will be described.

[0392] <Configuration of CAC-OS> The CAC-OS is, for example, a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less , preferably 1 nm or more and 2 nm or less, or in the vicinity of such a size. In the following, in the metal oxide, one or more metal elements are unevenly distributed and the region having the metal element is mixed in a state of 0.5 nm or more and 10 nm or less, preferably 1 nm or more 2 nm or less, or in the vicinity of such a size, and is also referred to as a mosaic state or a patch state.

[0393] The metal oxide preferably contains at least indium. Particularly preferably, it contains indium and zinc. In addition to these, one or more selected from aluminum, gallium, yttrium, lithium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, magnesium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc. may be contained.

[0394] For example, in the In-Ga-Zn oxide, the CAC-OS (among the CAC-OS, the In-G a-Zn oxide may be particularly referred to as CAC-IGZO.) is indium oxide (hereinafter, InO X1 (X1 is a real number greater than 0).), or indium zinc oxide (hereinafter, In X2 Zn Y2 O Z2 ​​(X2, Y2, and Z2 are real numbers greater than 0) ) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0) ), or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (X4, Y4, and Z1 and Z2 are real numbers greater than 0.) The material is separated into mosaics. Mosaic InO X1 , or In X2 Zn Y2 O Z2 is uniformly distributed in the film This is a cloud-like configuration (hereinafter also referred to as "cloud-like").

[0395] In other words, CAC-OS is X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 A composite metal oxide having a mixed structure with a region in which In this specification, for example, when the atomic ratio of In to the element M in the first region is , the atomic ratio of In to the element M in the second region is greater than the atomic ratio of In in the first region. The concentration of In is higher than in the region

[0396] IGZO is a common name and refers to a compound of In, Ga, Zn, and O. A typical example is InGaO3(ZnO) m1 (m1 is a natural number), or In ( 1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number) Examples of such crystalline compounds include:

[0397] The crystalline compounds may have a single crystal structure, a polycrystalline structure, or a c-axis alcove (CAAC) structure. The CAAC structure is a structure in which multiple IGZO The nanocrystals have a c-axis orientation and are connected without orientation in the ab plane. do.

[0398] On the other hand, CAC-OS is a material structure of metal oxide. In a material composition containing Zn and O, nanoparticles with Ga as the main component were observed in some areas. The region where In is observed as a nanoparticle and the region where In is observed as a nanoparticle are the main component are shown in the model. Therefore, in CAC-OS, the crystal structure Construction is a secondary element.

[0399] It should be noted that the CAC-OS does not include a laminated structure of two or more films with different compositions. For example, a structure consisting of two layers, one containing In as the main component and the other containing Ga as the main component, is not included. do not have.

[0400] In addition, GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 but In some cases, a clear boundary between the main component region and the main component region cannot be observed.

[0401] Instead of gallium, aluminum, yttrium, copper, vanadium, and beryllium can be used. , boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum , lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium If one or more selected elements from the group consisting of sodium, etc. are included, CAC-OS will The region observed is a nanoparticle with the metal element as the main component, and a nanoparticle with In as the main component in part. The structure is such that the areas observed as particles and the areas observed as particles are randomly dispersed in a mosaic pattern. cormorant.

[0402] CAC-OS is formed by sputtering without intentionally heating the substrate. In addition, when the CAC-OS is formed by a sputtering method, the deposition gas is The gas is selected from an inert gas (typically argon), oxygen gas, and nitrogen gas. One or more of these may be used. The lower the flow rate ratio of the gas, the more preferable. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%. It is more preferable to set the content to 0% or more and 10% or less.

[0403] CAC-OS is a type of X-ray diffraction (XRD) measurement method. When measured using the θ / 2θ scan by the out-of-plane method, In other words, from the X-ray diffraction, the measurement region It can be seen that no orientation in the ab plane direction or the c axis direction is observed.

[0404] In addition, the CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam). In the electron diffraction pattern obtained by irradiating the Therefore, the electron diffraction pattern indicates that CAC-OS The crystal structure is nc (nano-c) which has no orientation in the plane direction and cross-sectional direction. It can be seen that it has a crystal structure.

[0405] For example, in the case of CAC-OS, an In-Ga-Zn oxide, energy dispersive X-ray Energy Dispersive X-ray spectroscopy (EDX) EDX mapping obtained using a copy of the GaO X3 The region where is the principal component and , In X2 Zn Y2 O Z2 , or InO X1 The area where the main component is unevenly distributed and mixed. It can be confirmed that it has the structure shown in the figure.

[0406] CAC-OS has a structure different from that of IGZO compounds, in which metal elements are uniformly distributed. CAC-OS has different properties from ZO compounds. X3 The main components are In X2 Zn Y2 O Z2 , or InO X1 The area where is the principal component and It has a phase-separated structure with a mosaic of regions each consisting mainly of one element.

[0407] Here, In X2 Zn Y2 O Z2 , or InO X1 The region where is the main component is GaO X3 This is a region with high conductivity compared to the region where In is the main component. X2 Zn Y2 O Z2 , or InO X1 The carriers flow through the area where the main component is the metal oxide. Therefore, the conductivity of In is expressed as a crystalline oxide. X2 Zn Y2 O Z2 , or InO X1 but The main component is distributed in a cloud-like pattern in the metal oxide, resulting in high field-effect mobility. (μ) can be realized.

[0408] On the other hand, GaO X3 The region where In etc. are the main components is X2 Zn Y2 O Z2 , or InO X1 This region has higher insulating properties than the region where GaO is the main component. X3 etc. are the main components The distribution of these regions in the metal oxide suppresses leakage current and provides good switching performance. This allows for realizing a smoothing operation.

[0409] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 and insulation due to I n X2 Zn Y2 O Z2 , or InO X1 The conductivity caused by the This allows for a high on-state current (I on ) and high field-effect mobility (μ). Cut.

[0410] Furthermore, semiconductor devices using CAC-OS are highly reliable. It is ideal for a variety of semiconductor devices, including displays.

[0411] This embodiment may be appropriately combined with at least a part of another embodiment described in this specification. It can be implemented in combination.

[0412] (Embodiment 7) In this embodiment mode, another structural example of the display device described in the above embodiment mode will be described.

[0413] 45 shows an example of the configuration of the display device 10. The display device 10 is a display device provided on a substrate 14. The display unit 17 includes a plurality of pixels 11 connected to the wiring GL and the wiring SL. Has.

[0414] The display device 10 also includes a plurality of TAB tapes (Tape Automated Bond). The tab tape 121b is provided on the back surface of the substrate 121a. The TAB tape 121a and the TAB tape 121b are provided at positions facing each other with the display unit 17 in between. An integrated circuit including a gate driver 12a and the like is mounted on the TAB tape 121a. The TAB tape 121b has an integrated circuit formed with a gate driver 12b and the like. The gate driver 12a and the gate driver 12b are connected to a plurality of wirings GL. The line GL is connected to the gate electrode GL and has a function of supplying a selection signal to the line GL.

[0415] The display device 10 also includes a plurality of printed circuit boards 131a and a plurality of TAB tapes 132. a, and a plurality of printed circuit boards 131b and a plurality of TAB tapes 132b are provided. The printed circuit board 131a and the TAB tape 132a are provided. The TAB tape 132b and the display unit 17 are disposed opposite each other. There are.

[0416] The printed circuit boards 131a are connected to a plurality of TAB tapes 132a, and receive input from the outside. The printed circuit board 131b has the function of distributing the received signal to the TAB tape 132a. Each of them is connected to a plurality of TAB tapes 132b, and the externally input signal is transmitted to the TAB tape The TAB tape 132a has a function of distributing the signals to the source driver 132b. The TAB tape 132b is provided with an integrated circuit having a source driver 3a and the like. The integrated circuit on which the source driver 13a and the source driver 13b are formed is mounted. The switch driver 13b is connected to a plurality of wirings SL and has the function of supplying signals to the wirings SL. Has.

[0417] When manufacturing a large-screen display panel that can handle 2K, 4K, and 8K broadcasts, etc., In this way, a plurality of printed circuit boards 131a and a plurality of printed circuit boards 131b can be provided. This is preferable. This makes it possible to easily input image data to the display device 10.

[0418] The gate driver 12a, the gate driver 12b, the source driver 13a, and the The base driver 13b is a COG (Chip On Glass) type, COF (Chip It can also be provided on the substrate 14 by a method such as a "on film" method.

[0419] This embodiment may be appropriately combined with at least a part of another embodiment described in this specification. It can be implemented in combination.

[0420] (Embodiment 8) In this embodiment, a polycrystalline silicon film that can be used for a semiconductor layer of a transistor is An example of a crystallization method and a laser crystallization apparatus will be described.

[0421] To form a polycrystalline silicon layer with good crystallinity, an amorphous silicon layer is provided on a substrate. It is preferable to crystallize the amorphous silicon layer by irradiating it with laser light. is used as a linear beam, and the substrate is moved while the linear beam is irradiated onto the amorphous silicon layer. In this way, a polycrystalline silicon layer can be formed in a desired region on the substrate.

[0422] The linear beam method has a relatively good throughput. Since the laser beam is irradiated multiple times while moving relatively, the output of the laser beam is The resulting beam profile changes are likely to cause variations in crystallinity. For example, the semiconductor layer crystallized by this method can be used for a transistor in a pixel of a display device. When the film is heated, random stripes caused by variations in crystallinity may appear on the display.

[0423] In addition, the length of the linear beam is ideally equal to or greater than the length of one side of the substrate. The length of the system is limited by the output of the laser oscillator and the configuration of the optical system. In substrate processing, it is practical to irradiate the laser by folding it back within the substrate surface. The crystallinity of this region is different from that of the other regions. Since the crystallinity is easily different, display irregularities may occur in this region.

[0424] In order to prevent the above problems, a laser is locally applied to an amorphous silicon layer formed on a substrate. Local laser irradiation can be used to crystallize the material. A polycrystalline silicon layer can be easily formed.

[0425] FIG. 46(A) shows a method of locally irradiating an amorphous silicon layer formed on a substrate with laser. FIG.

[0426] The laser beam 826 emitted from the optical system unit 821 is reflected by the mirror 822. The laser light 826 is incident on the microlens array 823. The light is focused to form a plurality of laser beams 827 .

[0427] A substrate 830 on which an amorphous silicon layer 840 is formed is fixed to the stage 815. By irradiating the polycrystalline silicon layer 840 with a plurality of laser beams 827, a plurality of polycrystalline silicon The insulating layer 841 can be formed at the same time.

[0428] The individual microlenses of the microlens array 823 are arranged at the same pitch as the pixels of the display device. Alternatively, they may be provided at intervals that are an integral multiple of the pixel pitch. In any case, laser irradiation and movement of the stage 815 in the X or Y direction are repeated. By returning the polycrystalline silicon layer to the substrate, it is possible to form a polycrystalline silicon layer in the area corresponding to all the pixels.

[0429] For example, if the microlens array 823 has a pixel pitch of M rows and N columns (M and N are natural numbers), When a lens is used, laser light is first irradiated at a predetermined starting position, and a polycrystalline silicon with M rows and N columns is formed. Then, the stage 815 is moved in the row direction by a distance of N columns. The laser beam is irradiated to form a polycrystalline silicon layer 841 having M rows and 2N columns. By repeating this process, a plurality of polycrystalline silicon layers 841 can be formed in desired regions. In addition, when the laser irradiation process is performed by folding back, the stage 815 is moved in the row direction by a distance of N columns. Then, the stage 815 is moved in the column direction by a distance of M rows. The laser light irradiation may be repeated.

[0430] If the oscillation frequency of the laser light and the moving speed of the stage 815 are adjusted appropriately, Even if the laser irradiation is performed while moving the 815 in one direction, the polycrystalline silicon A thin film layer can be formed.

[0431] The size of the laser beam 827 is set to, for example, the size of the laser beam 827 that includes the entire semiconductor layer of one transistor. Alternatively, the entire channel formation region of one transistor can be formed in an area of ​​about 1000 μm. Alternatively, the area can be set to a value that includes the channel forming region of one transistor. These can be made to have an area that includes a part of the required transistor. The appropriate one can be selected depending on the electrical characteristics of the device.

[0432] In the case of a display device having a plurality of transistors in one pixel, The area of ​​the matrix 827 is set to be large enough to include the entire semiconductor layer of each transistor in one pixel. The laser beam 827 can be incident on the semiconductors of the transistors included in the plurality of pixels. The area may be large enough to include the entire layer.

[0433] As shown in FIG. 47(A), between the mirror 822 and the microlens array 823 A mask 824 may be provided. The mask 824 has a plurality of apertures corresponding to the respective microlenses. The shape of the opening can be reflected in the shape of the laser beam 827. When the mask 824 has a circular opening as shown in FIG. 47(A), a circular laser beam is In addition, when the mask 824 has a rectangular opening, a rectangular The mask 824 can be, for example, a mask of a transistor. This is effective when it is desired to crystallize only the channel forming region. As shown in FIG. 47(B), it may be provided between the optical system unit 821 and the mirror 822.

[0434] FIG. 46(B) shows a laser beam that can be used in the local laser irradiation process described above. FIG. 1 is a perspective view illustrating the main configuration of the laser crystallization device. The components include a moving mechanism 812, a moving mechanism 813, and a stage 815. A laser oscillator 820 for shaping a laser beam 827, an optical system unit 821, a mirror 822 and a microlens array 823.

[0435] The moving mechanism 812 and the moving mechanism 813 have the function of performing a reciprocating linear motion in the horizontal direction. The mechanism for powering the moving mechanism 812 and the moving mechanism 813 may be, for example, a motor-driven mechanism. A ball screw mechanism 816 that moves the moving mechanism 812 can be used. Since the movement directions of the stages 813 are perpendicular to each other, the stages fixed to the movement mechanism 813 815 can be freely moved in the X and Y directions.

[0436] The stage 815 has a fixing mechanism such as a vacuum suction mechanism, and can fix the substrate 830 etc. The stage 815 may also have a heating mechanism as needed. Although not shown, the stage 815 has a pusher pin and its up / down mechanism, and When carrying in or out the substrate 830, the substrate 830 can be moved up or down.

[0437] The laser oscillator 820 is only required to output light of a wavelength and intensity suitable for the purpose of processing. A CW laser is preferred, but a CW laser is also acceptable. Using an excimer laser that can irradiate ultraviolet light such as 308 nm (XeF) and 308 nm (XeCl), Alternatively, the doubled frequency of a solid-state laser (YAG laser, fiber laser, etc.) can be used. (515nm, 532nm, etc.) or tripled wavelength (343nm, 355nm, etc.) Also, there may be a plurality of laser oscillators 820.

[0438] The optical system unit 821 includes, for example, a mirror, a beam expander, a beam homogenizer, etc. The laser oscillator 820 outputs a laser beam 825 having a uniform energy distribution in the plane. It can be unified and stretched.

[0439] The mirror 822 may be, for example, a dielectric multilayer mirror, and the incident angle of the laser beam may be adjusted. The microlens array 823 is installed so that the angle is approximately 45°. The shape may be such that a plurality of convex lenses are provided on the top surface or on the upper and lower surfaces.

[0440] By using the above laser crystallization apparatus, polycrystalline silicon with little variation in crystallinity can be produced. A layer can be formed.

[0441] This embodiment may be appropriately combined with at least a part of another embodiment described in this specification. It can be implemented in combination.

[0442] (Embodiment 9) In this embodiment, an electronic device of one embodiment of the present invention will be described with reference to drawings.

[0443] The electronic devices exemplified below have a display device according to one embodiment of the present invention in their display portions. Therefore, it is an electronic device that has achieved high resolution. The electronic device may be a stand-alone electronic device.

[0444] The display unit of the electronic device according to one embodiment of the present invention may include, for example, full high-definition, 4K2K, 8K4K , 16K, 8K, or higher resolution images can be displayed. The display screen size must be 20 inches or more diagonally, or 30 inches or more diagonally, or It can be 50 inches or more diagonal, 60 inches or more diagonal, or 70 inches or more diagonal. do.

[0445] Examples of electronic devices include television sets, desktop or notebook PCs, etc. Personal computers, computer monitors, digital signage Signage: Digital signage, large game machines such as pachinko machines, etc. In addition to electronic devices, digital cameras, digital video cameras, digital photo frames, Examples of such devices include mobile phones, portable game machines, personal digital assistants, and sound reproducing devices.

[0446] The electronic device or lighting device according to one embodiment of the present invention can be applied to an interior or exterior wall of a house or building, or Alternatively, it can be incorporated along the curved surfaces of the interior or exterior of the automobile.

[0447] The electronic device according to one embodiment of the present invention may include an antenna. This allows the display of images, information, etc. on the display unit. If the device has a secondary battery, the antenna may be used for contactless power transmission.

[0448] The electronic device according to one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, etc.). , distance, light, liquid, magnetic, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, (including the ability to measure radiation, flow rate, humidity, gradient, vibration, odor or infrared radiation) It may be possible.

[0449] The electronic device according to one embodiment of the present invention can have various functions. Functions for displaying still images, videos, text images, etc. on the display, touch panel function, calendar - Functions to display date or time, etc., and functions to run various software (programs) functions, wireless communication functions, functions to read programs or data recorded on recording media, etc. can have:

[0450] FIG. 48A shows an example of a television device. The television device 7100 includes a housing 710 The display unit 7000 is built into the housing 710. This shows a configuration that supports 1.

[0451] The display device of one embodiment of the present invention can be used in the display portion 7000. The television device 7100 using the display device can display high-resolution images. In addition, the television device 7100 can display high-resolution images on a large screen. Furthermore, by using the display device of one embodiment of the present invention, the display of the television set 7100 can be The display quality can be improved.

[0452] The television set 7100 shown in FIG. 48A is operated by an operation switch provided in the housing 7101. This can be done by a separate remote control 7111 or the display unit 700. The display unit 7000 may be provided with a touch sensor, and the operation may be performed by touching the display unit 7000 with a finger or the like. The remote control unit 7111 displays the information output from the remote control unit 7111. The remote control 7111 may have a display unit for displaying the operation keys or touch screen. The panel allows you to operate the channel and volume, and the information displayed on the display unit 7000 You can control the video that is displayed.

[0453] The television device 7100 includes a receiver, a modem, and the like. It is also possible to receive general television broadcasts via wired or wireless connection via a modem. By connecting to a wired communication network, it can be transmitted in one direction (sender to receiver) or two directions. It is also possible to communicate information in two directions (between a sender and a receiver, or between receivers, etc.). .

[0454] FIG. 48(B) shows a notebook personal computer 7200. The computer 7200 includes a housing 7211, a keyboard 7212, a pointing device The housing 7211 has a display unit 7000 and an external connection port 7213. It is included.

[0455] The display device of one embodiment of the present invention can be applied to the display portion 7000. The notebook personal computer 7200 using the display device displays high-resolution images. The notebook personal computer 7200 can also display a high-resolution An image can be displayed on a large screen. This can improve the display quality of the notebook personal computer 7200.

[0456] Figure 48(C) and (D) show the digital signage. An example of a sign is shown below.

[0457] The digital signage 7300 shown in FIG. 48C includes a housing 7301, a display unit 7000, and and speaker 7303. In addition, LED lamps, operation keys (power switch, It may have a variety of functions, including a control switch, connection terminals, various sensors, a microphone, etc. Cut.

[0458] FIG. 48(D) shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 is a display unit 7 provided along the curved surface of a pillar 7401. 000.

[0459] 48C and 48D, the display device of one embodiment of the present invention is applied to the display portion 7000. A digital signage 7300 using the display device of one embodiment of the present invention and The digital signage 7400 can display high-resolution images. The Digital Signage 7300 and Digital Signage 7400 deliver high-resolution images to large screens. Furthermore, by using the display device of one embodiment of the present invention, Improves the display quality of the Signage 7300 and Digital Signage 7400 .

[0460] The larger the display unit 7000, the more information can be displayed at once. The wider the part 7000, the more noticeable it is, and for example, the more effective the advertisement. Cut.

[0461] By applying a touch panel to the display unit 7000, images or videos can be displayed on the display unit 7000. It is also preferable because it not only shows route information but also allows users to operate it intuitively. When used to provide information such as traffic information, the user can operate the device intuitively. This can improve accessibility.

[0462] Also, as shown in Figure 48(C) and (D), Digital Signage 7300 or Digital The signage 7400 is an information terminal 7311 such as a smartphone carried by a user or It is preferable that the display unit 7411 can be connected to the information terminal 7411 by wireless communication. The advertisement information displayed on 000 is displayed on the screen of the information terminal 7311 or the information terminal 7411. In addition, the information terminal 7311 or the information terminal 7411 can be operated. By doing so, the display on the display unit 7000 can be switched.

[0463] In addition, the digital signage 7300 or the digital signage 7400 is equipped with an information terminal 7 311 or the screen of the information terminal 7411 is used as a control means (controller) to play games. This allows an unspecified number of users to participate in the game at the same time and enjoy it. It is possible.

[0464] This embodiment may be appropriately combined with at least a part of another embodiment described in this specification. It can be implemented in combination. [Explanation of symbols]

[0465] 10 Display device 11 pixels 14 PCB 15 PCB 16 Reference voltage generation circuit 17 Display section 20 Liquid crystal element 21 Conductive layer 22 LCD 23 Conductive layer 26 Insulating layer 30 transistors 31 Conductive layer 32 Semiconductor layer 33 Conductive layer 34 Insulating layer 35 Impurity semiconductor layer 37 Semiconductor layer 38 Opening 41 Colored layer 42 Light blocking layer 50 light 51 Conductive layer 52 Conductive layer 53 Conductive layer 54 Conductive layer 55 Conductive layer

Claims

[Claim 1] a first pixel array arranged in a first column, a first pixel array arranged in a second column, a first source line array arranged in the first column, a second pixel array arranged in a second column, a third source line array arranged in the second column, a gate line, and the fourth to sixth source lines arranged in the second column are located between the first to third pixels arranged in the first column and the fourth to sixth pixels arranged in the second column; the first pixel is electrically connected to the second source line; the second pixel is electrically connected to the fourth source line; the third pixel is electrically connected to the third source line; the fourth pixel is electrically connected to the fifth source line; the fifth pixel is electrically connected to the seventh source line; the sixth pixel is electrically connected to the sixth source line; the first to sixth pixels are electrically connected to the gate lines; A display device in which signals of the same polarity are supplied to the second source line, the third source line, and the seventh source line.

Images