Multilayer ceramic capacitor and mounting structure of multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor which suppresses DC resistance and obtains a heat dissipation effect and low ESL.SOLUTION: A multilayer ceramic capacitor 10 includes a multilayer body 12 including a plurality of dielectric layers 14 and a plurality of inner-electrode layers 16 and having first and second surfaces 12a and b facing each other in an x direction, third and fourth surfaces 12c and d facing each other in a y direction orthogonal or substantially orthogonal to a stacking direction, and fifth and sixth surfaces facing each other in a direction orthogonal or substantially orthogonal to the x direction and the y direction, first inner-electrode layers 16a exposed at the third and fourth surfaces, and second inner-electrode layers 16b exposed at the fifth and sixth surfaces. The multilayer body includes a first outer layer portion 16a and a second outer layer portion 20a, the first outer layer portion 20b being located between the first surface and the capacitance forming unit 18, the second outer layer portion LA being located between the second surface and the capacitance forming unit 18, the first outer layer portion LA being located on the non-mounting substrate side, and the second outer layer portion LA being located between the second surface and the capacitance forming unit.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor and a mounting structure for the multilayer ceramic capacitor. [Background technology]

[0002] For example, a through-type multilayer ceramic capacitor is known, which is used to stabilize the power supply voltage supplied to an integrated circuit component (IC) operating at high speed, or to suppress noise in a power supply line supplied to the integrated circuit component (IC). For example, a through-type multilayer ceramic capacitor generally includes a ceramic base (laminate) having an outer surface consisting of first and second main surfaces facing each other, first and second side surfaces facing each other, and first and second end surfaces facing each other. A plurality of first internal electrodes and a plurality of second internal electrodes are alternately arranged in the lamination direction within the ceramic base. Each of the first internal electrodes has both ends extending to the first end surface and the second end surface, and is connected to a first external electrode and a second external electrode, respectively. Each of the second internal electrodes has both ends extending to the first side surface and the second side surface, and is connected to a third external electrode and a fourth external electrode, respectively.

[0003] As such a through-type multilayer ceramic capacitor, Patent Document 1 discloses a through-type three-terminal electronic component including a laminate having a structure in which one or more sets of signal internal electrodes and ground internal electrodes are stacked so as to face each other with a dielectric layer interposed therebetween, a pair of signal external electrodes to which lead-out portions of the signal internal electrodes are connected, and a ground external electrode to which the ground internal electrode is connected. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-022932 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the structure disclosed in Patent Document 1, there is a problem in that when a direct current flows through the signal internal electrodes, the amount of heat generated by the feedthrough three-terminal electronic component increases.

[0006] Therefore, a primary object of the present invention is to provide a multilayer ceramic capacitor and a mounting structure for the multilayer ceramic capacitor that can suppress an increase in DC resistance while still achieving sufficient heat dissipation and low ESL effects. [Means for solving the problem]

[0007] The multilayer ceramic capacitor according to the present invention is a multilayer ceramic capacitor comprising: a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, the laminate having a first surface and a second surface facing each other in the lamination direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the lamination direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the lamination direction and the first direction; a first external electrode disposed on the third surface, a second external electrode disposed on the fourth surface, a third external electrode disposed on the fifth surface, and a fourth external electrode disposed on the sixth surface. the plurality of internal electrode layers include a first internal electrode layer exposed on the third surface and a fourth surface, and a second internal electrode layer exposed on the fifth surface and a sixth surface; the laminate includes a capacitance forming portion where the first internal electrode layer and the second internal electrode layer face each other to form a capacitance, a first outer layer portion located between the first surface and the capacitance forming portion, and a second outer layer portion located between the second surface and the capacitance forming portion; the capacitance forming portion is arranged in the center in the stacking direction, the first outer layer portion is arranged on the non-mounting substrate side, and a current-carrying portion where one or more first internal electrode layers are arranged is arranged in the first outer layer portion.

[0008] According to the multilayer ceramic capacitor of the present invention, the laminate has a capacitance-forming portion in which the first internal electrode layer and the second internal electrode layer face each other to form a capacitance, a first outer layer portion located between the first surface and the capacitance-forming portion, and a second outer layer portion located between the second surface and the capacitance-forming portion, the capacitance-forming portion being arranged at the center in the stacking direction, the first outer layer portion being arranged on the non-mounting substrate side, and current-carrying portions in which one or more first internal electrode layers are arranged being arranged on the first outer layer portion, thereby making it possible to reduce the value of DC resistance (Rdc) and therefore the amount of heat generated by the multilayer ceramic capacitor 10. Furthermore, by arranging the current-carrying portions on the first outer layer portion, it is possible to ensure space for capacitance formation, and by arranging the capacitance-forming portions closer to the mounting substrate, it is possible to achieve both ensuring capacitance and reducing ESL.

[0009] Also, a mounting structure for a multilayer ceramic capacitor according to the present invention includes a mounting substrate and a multilayer ceramic capacitor mounted on the mounting substrate, wherein the multilayer ceramic capacitor is the multilayer ceramic capacitor according to the present invention, and the mounting substrate has a core material of the substrate, a first connecting conductor connected to a first external electrode arranged on the core material, a second connecting conductor connected to a second external electrode arranged on the core material, a third connecting conductor connected to a third external electrode arranged on the core material, and a fourth connecting conductor connected to a fourth external electrode arranged on the core material, and the multilayer ceramic capacitor is mounted so that its second surface faces the mounting substrate.

[0010] According to the mounting structure of the multilayer ceramic capacitor of this invention, the multilayer body is mounted so that the capacitance forming portion faces the mounting substrate, thereby shortening the current path from the second internal electrode layer located closest to the second surface of the multilayer ceramic capacitor to the mounting substrate. As a result, various effects of the multilayer ceramic capacitor according to this embodiment of the invention are reflected, and the effect of improving the low ESL characteristics in the mounting structure of the multilayer ceramic capacitor is achieved. [Effects of the Invention]

[0011] According to the present invention, it is possible to provide a multilayer ceramic capacitor and a mounting structure for the multilayer ceramic capacitor that can suppress an increase in DC resistance while still achieving sufficient heat dissipation and low ESL effects.

[0012] The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention; [Figure 2] 1 is a top view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention; [Figure 3] 1 is a bottom view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 4] 1 is a side view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 5] FIG. 2 is a cross-sectional view taken along line VV in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. [Figure 9] 1 is a cross-sectional view in a first direction showing an example of a mounting structure of a multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 10] 3 is a cross-sectional view in a second direction showing an example of a mounting structure of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0014] 1. Multilayer ceramic capacitors A description will be given of a multilayer ceramic capacitor 10 according to a first embodiment of the present invention. The multilayer ceramic capacitor 10 is a feedthrough multilayer ceramic capacitor (a three-terminal multilayer ceramic capacitor).

[0015] FIG. 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 2 is a top view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 3 is a bottom view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 4 is a side view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 5 is a cross-sectional view taken along line VV in FIG. 1. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 1. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 4. FIG. 9 is a cross-sectional view taken in a first direction showing an example of a mounting structure of a multilayer ceramic capacitor according to a first embodiment of the present invention. FIG. 10 is a cross-sectional view taken in a second direction showing an example of a mounting structure of a multilayer ceramic capacitor according to the first embodiment of the present invention.

[0016] As shown in FIGS. 1 to 9, a multilayer ceramic capacitor 10 includes, for example, a laminate 12 and external electrodes 30.

[0017] The laminate 12 has a plurality of laminated dielectric layers 14 and a plurality of internal electrode layers 16 laminated on the dielectric layers 14. The internal electrode layers 16 have a first internal electrode layer 16a and a second internal electrode layer 16b. Details of the first internal electrode layer 16a and the second internal electrode layer 16b will be described later.

[0018] The laminate 12 has a first surface 12a and a second surface 12b facing the stacking direction x, a third surface 12c and a fourth surface 12d facing the first direction y perpendicular to the stacking direction x, and a fifth surface 12e and a sixth surface 12f facing the second direction z perpendicular to the stacking direction x and the first direction y.

[0019] The laminate 12 has a rectangular parallelepiped shape, and preferably has rounded corners and ridges. The corners are portions where three faces of the laminate 12 intersect, and the ridges are portions where two faces of the laminate 12 intersect. In addition, unevenness may be formed on some or all of the first face 12a and the second face 12b, the third face 12c and the fourth face 12d, and the fifth face 12e and the sixth face 12f.

[0020] Here, the dimension of the laminate 12 in the first direction y is defined as dimension l, the dimension of the laminate 12 in the second direction z is defined as dimension w, and the dimension of the laminate 12 in the stacking direction x is defined as dimension t.

[0021] The laminate 12 has a capacitance forming portion 18, a first outer layer portion 20a located on the first surface 12a side and a second outer layer portion 20b located on the second surface 12b side, which are arranged so as to sandwich the capacitance forming portion 18 in the stacking direction x.

[0022] The capacitance forming portion 18 is formed by alternately stacking first internal electrode layers 16a and second internal electrode layers 16b with dielectric layers 14 interposed therebetween.

[0023] The first outer layer portion 20a is located on the first surface 12a side of the laminate 12, and is an assembly of multiple dielectric layers 14 located between the first surface 12a and the capacitance forming portion 18 closest to the first surface 12a. The second outer layer portion 20b is located on the second surface 12b side of the laminate 12, and is an assembly of multiple dielectric layers 14 located between the second surface 12b and the capacitance forming portion 18 closest to the second surface 12b. The region sandwiched between the first outer layer portion 20a and the second outer layer portion 20b is the capacitance forming portion 18.

[0024] The first outer layer portion 20a has a current-carrying portion 21 in which dielectric layers 14 and first internal electrode layers 16a are alternately stacked, and a dielectric portion 22 located between the first surface 12a and the current-carrying portion 21 and composed of the dielectric layers 14. The thickness of the dielectric portion 22 is smaller than the thickness of the second outer layer portion 20b. The current-carrying portion 21 is preferably arranged within a range from the first surface 12a to 1 / 5 of the stacking direction x of the laminate 12. One or more first internal electrode layers 16a are arranged in the current-carrying portion 21.

[0025] Since the thickness of the dielectric portion 22 located between the first surface 12a and the current-carrying portion 21 is smaller than the thickness of the second outer layer portion 20b, the color of the laminate 12 viewed from the first surface 12a is darker (different) than the color of the laminate 12 viewed from the second surface 12b, making it possible to distinguish between the top and bottom in the stacking direction x. The laminate 12 may have directional markings to distinguish between the top and bottom in the stacking direction x.

[0026] The dielectric portion 22 is located on the first surface 12a side of the laminate 12 and is an assembly of multiple dielectric layers 14 located between the first surface 12a and the conductive portion 21 closest to the first surface 12a.

[0027] The capacitance forming portion 18 is disposed at the center in the stacking direction x. More specifically, in the stacking direction x connecting the first surface 12a and the second surface 12b, the center position of the laminate 12 and the center position of the capacitance forming portion 18 are substantially the same.

[0028] The first outer layer portion 20a including the current-carrying portion 21 is disposed on the non-mounting substrate side, and the second outer layer portion 20b is disposed on the mounting substrate side.

[0029] In this way, by concentrating the current-carrying portions 21 on the first outer layer portion 20a, space for capacitance formation can be secured. Furthermore, by arranging the capacitance-forming portions 18 closer to the mounting substrate than the current-carrying portions 21, the current path from the capacitance-forming portions 18 that form capacitance to the mounting substrate is shortened, and a low ESL effect can be achieved.

[0030] As shown in FIG. 6, the laminate 12 is located between the capacitance forming portion 18 and the fifth surface 12e, and between the capacitance forming portion 18 and the sixth surface 12f, and has side portions (W gaps) 23a, 23b of the laminate 12 including the first extension portion 27a and the second extension portion 27b of the second internal electrode layer 16b.

[0031] Also, as shown in FIG. 5, the laminate 12 is located between the capacitance forming portion 18 and the third surface 12c, and between the capacitance forming portion 18 and the fourth surface 12d, and has ends (L gaps) 24a, 24b of the laminate 12 including the first lead portion 26a and the second lead portion 26b of the first internal electrode layer 16a.

[0032] The dielectric layer 14 may be made of a ceramic material such as a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Alternatively, a material containing these main components plus a secondary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound may be used.

[0033] The thickness of the dielectric layers 14 is preferably 1 μm or more and 15 μm or less. The number of laminated dielectric layers 14 is preferably 30 or more and 200 or less. Note that this number of dielectric layers 14 is the total number of the dielectric layers 14 in the capacitance forming portion 18 and the dielectric layers 14 in the first outer layer portion 20a and the second outer layer portion 20b.

[0034] Furthermore, it is preferable that the thickness of the dielectric layer 14 of the current-carrying portion 21 in the stacking direction x is smaller than the thickness of the dielectric layer 14 of the capacitance-forming portion 18 in the stacking direction x.

[0035] (Internal electrode layer) The internal electrode layer 16 includes a first internal electrode layer 16a and a second internal electrode layer 16b.

[0036] The first internal electrode layer 16a is disposed on the plurality of dielectric layers 14. The first internal electrode layer 16a is extended to the third surface 12c and the fourth surface 12d.

[0037] 7, the first internal electrode layer 16a extends between the third surface 12c and the fourth surface 12d of the laminate 12 and has a first opposing portion 25a at its center, a first lead portion 26a extending from the first opposing portion 25a and led to the third surface 12c of the laminate 12, and a second lead portion 26b extending from the first opposing portion 25a and led to the fourth surface 12d of the laminate 12. The first opposing portion 25a is located in the center of the dielectric layer 14. The first lead portion 26a is exposed to the third surface 12c of the laminate 12, and the second lead portion 26b is exposed to the fourth surface 12d of the laminate 12. Therefore, the first internal electrode layer 16a is not exposed to the fifth surface 12e or the sixth surface 12f of the laminate 12.

[0038] The shape of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. The shapes of the first opposing portion 25a, first lead portion 26a, and second lead portion 26b of the first internal electrode layer 16a are also not particularly limited, but are preferably rectangular in plan view. However, the corners may be rounded.

[0039] The second internal electrode layer 16b is disposed on a plurality of dielectric layers 14. The second internal electrode layer 16b is extended to the fifth surface 12e and the sixth surface 12f. The second internal electrode layer 16b is disposed on a dielectric layer 14 different from the dielectric layer 14 on which the first internal electrode layer 16a is disposed.

[0040] More specifically, as shown in FIG. 8 , the second internal electrode layer 16b extends between the fifth surface 12e and the sixth surface 12f of the laminate 12 and includes a second opposing portion 25b at its center, a first extension portion 27a extending from the second opposing portion 25b and extending to the fifth surface 12e, and a second extension portion 27b extending from the second opposing portion 25b and extending to the sixth surface 12f. The second opposing portion 25b is formed in a rectangular shape so as to extend toward the third surface 12c and toward the fourth surface 12d. The second opposing portion 25b is located in the center of the dielectric layer 14. The first extension portion 27a is exposed on the fifth surface 12e of the laminate 12, and the second extension portion 27b is exposed on the sixth surface 12f of the laminate 12. Therefore, the second internal electrode layer 16b is not exposed on the third surface 12c and the fourth surface 12d of the laminate 12.

[0041] The shapes of the second opposing portion 25b, the first extension portion 27a, and the second extension portion 27b of the second internal electrode layer 16b are not particularly limited, but are preferably rectangular in plan view, although the corners may be rounded.

[0042] The first opposing portion 25a of the first internal electrode layer 16a and the second opposing portion 25b of the second internal electrode layer 16b are opposed to each other. In this embodiment, the first opposing portion 25a of the first internal electrode layer 16a and the second opposing portion 25b of the second internal electrode layer 16b are opposed to each other via the dielectric layer 14, thereby forming capacitance and exhibiting capacitor characteristics.

[0043] The number of the first internal electrode layers 16a is preferably greater than the number of the second internal electrode layers 16b. By having the number of the first internal electrode layers 16a greater than the number of the second internal electrode layers 16b, the DC resistance is reduced, and the temperature rise of the laminate 12 is reduced.

[0044] The number of first internal electrode layers 16a is not particularly limited, but is preferably, for example, 10 to 100. The number of second internal electrode layers 16b is not particularly limited, but is preferably, for example, 10 to 50. Therefore, the total number of first internal electrode layers 16a and second internal electrode layers 16b is preferably 20 to 150.

[0045] It is preferable that the ratio of the total number of first internal electrode layers 16a arranged in the current-carrying portion 21 to the total number of first internal electrode layers 16a and second internal electrode layers 16b arranged in the capacitance forming portion 18 is not less than 0.03 and not more than 1.04.

[0046] Furthermore, it is preferable that the ratio of the total number of first internal electrode layers 16a arranged in the current-carrying portion 21 to the total number of first internal electrode layers 16a arranged in the capacitance forming portion 18 is 0.07 or more and 2.17 or less.

[0047] Furthermore, the number of first internal electrode layers 16a arranged in the current-carrying portion 21 is preferably 1 to 26.

[0048] The thickness of the first internal electrode layer 16a is not particularly limited, but is preferably, for example, 0.5 μm or more and 1.1 μm or less. The thickness of the second internal electrode layer 16b is not particularly limited, but is preferably, for example, 0.5 μm or more and 1.1 μm or less.

[0049] The thickness of the first internal electrode layer 16a arranged in the current-carrying portion 21 may be different from the thickness of the first internal electrode layer 16a arranged in the capacitance forming portion 18. The thickness of the first internal electrode layer 16a arranged in the current-carrying portion 21 may be greater than the thickness of the first internal electrode layer 16a arranged in the capacitance forming portion 18.

[0050] The first internal electrode layer 16a located at the current-carrying portion 21 is preferably located within a range of 1 / 5 of the length from the first surface 12a to the stacking direction x of the laminate 12. In other words, the length d between the first surface 12a and the first internal electrode layer 16a located at the current-carrying portion 21 that is located closest to the capacitance forming portion 18 is 1 / 5 or less of the dimension t that is the length dimension in the stacking direction x of the laminate 12. In this way, by positioning the first internal electrode layer 16a located at the current-carrying portion 21 within a range of 1 / 5 of the length from the first surface 12a to the length of the laminate 12 in the stacking direction x, a capacitance formation space can be secured.

[0051] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of an appropriate conductive material, for example, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy.

[0052] (external electrode) External electrodes 30 are arranged on the third surface 12c side, the fourth surface 12d side, the fifth surface 12e side, and the sixth surface 12f side of the laminate 12. The external electrodes 30 include a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0053] The first external electrode 30a is disposed on the third surface 12c. The first external electrode 30a is connected to the first internal electrode layer 16a. The first external electrode 30a may also be disposed on a portion of the first surface 12a, a portion of the second surface 12b, a portion of the fifth surface 12e, and a portion of the sixth surface 12f.

[0054] The second external electrode 30b is disposed on the fourth surface 12d. The second external electrode 30b is connected to the first internal electrode layer 16a. The second external electrode 30b may also be disposed on a portion of the first surface 12a, a portion of the second surface 12b, a portion of the fifth surface 12e, and a portion of the sixth surface 12f.

[0055] The third external electrode 30c is disposed on the fifth surface 12e. The third external electrode 30c is connected to the second internal electrode layer 16b. The third external electrode 30c may further include a first covering portion 30c1 that covers the second internal electrode layer 16b exposed on the fifth surface 12e, a first folded portion 30c2 that is formed on the first surface 12a in parallel to the second internal electrode layer 16b, and a second folded portion 30c3 that is formed on the second surface 12b in parallel to the second internal electrode layer 16b. By including the second folded portion 30c3, the reliability of the electrical connection with the mounting substrate 50 can be further maintained.

[0056] The fourth external electrode 30d is disposed on the sixth surface 12f. The fourth external electrode 30d is connected to the second internal electrode layer 16b. The fourth external electrode 30d may further include a second covering portion 30d1 (not shown) that covers the second internal electrode layer 16b exposed on the sixth surface 12f, a third folded portion 30d2 formed on the first surface 12a in parallel to the second internal electrode layer 16b, and a fourth folded portion 30d3 formed on the second surface 12b in parallel to the second internal electrode layer 16b. The inclusion of the fourth folded portion 30d3 makes it possible to further maintain the reliability of the electrical connection with the mounting board 50.

[0057] The external electrode 30 includes a base electrode layer 32 disposed on the surface of the laminate 12 and a plating layer 34 disposed so as to cover the base electrode layer 32 .

[0058] The base electrode layer 32 includes a first base electrode layer 32a, a second base electrode layer 32b, a third base electrode layer 32c, and a fourth base electrode layer 32d.

[0059] The plating layer 34 includes a first plating layer 34a, a second plating layer 34b, a third plating layer 34c, and a fourth plating layer 34d.

[0060] In other words, the first external electrode 30a has a first base electrode layer 32a and a first plating layer 34a. The second external electrode 30b has a second base electrode layer 32b and a second plating layer 34b. The third external electrode 30c has a third base electrode layer 32c and a third plating layer 34c. The fourth external electrode 30d has a fourth base electrode layer 32d and a fourth plating layer 34d.

[0061] The first base electrode layer 32a is disposed on the surface of the third face 12c of the laminate 12 and is formed so as to extend from the third face 12c to cover a portion of each of the first face 12a, the second face 12b, the fifth face 12e, and the sixth face 12f. The second base electrode layer 32b is disposed on the surface of the fourth face 12d of the laminate 12 and is formed so as to extend from the fourth face 12d to cover a portion of each of the first face 12a, the second face 12b, the fifth face 12e, and the sixth face 12f. The first base electrode layer 32a may be arranged only on the surface of the third side 12c of the laminate 12, and the second base electrode layer 32b may be arranged only on the surface of the fourth side 12d of the laminate 12.

[0062] The third base electrode layer 32c is disposed on the surface of the fifth surface 12e of the laminate 12, and is formed so as to extend from the fifth surface 12e to cover the second surface 12b. The fourth base electrode layer 32d is disposed on the surface of the sixth face 12f of the laminate 12, and is formed so as to extend from the sixth face 12f to cover the second face 12b.

[0063] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like. Hereinafter, the respective configurations when the base electrode layer 32 is the baked layer, the conductive resin layer, and the thin film layer will be described.

[0064] (For baked layers) The baking layer contains a glass component and a metal component. The glass component of the baking layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the baking layer contains at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The baking layer may be multiple layers. The baking layer is formed by applying a conductive paste containing a glass component and a metal component to the laminate 12 and baking it. The baking layer may be formed by simultaneously baking a laminated chip having an internal electrode layer 16 and a dielectric layer 14 and a conductive paste applied to the laminated chip, or by baking a laminated chip having an internal electrode layer 16 and a dielectric layer 14 to obtain the laminate 12, and then applying a conductive paste to the laminate 12 and baking it. In addition, when the baking layer is formed by simultaneously baking a laminated chip having an internal electrode layer 16 and a dielectric layer 14 and a conductive paste applied to the laminated chip, it is preferable to form the baking layer by baking a layer to which a dielectric material has been added instead of a glass component.

[0065] The thickness of the first base electrode layer 32a located on the third surface 12c in the center in the stacking direction x in the first direction y connecting the third surface 12c and the fourth surface 12d is preferably 20 μm or more and 50 μm or less. Furthermore, the thickness of the second base electrode layer 32b located on the fourth surface 12d in the center in the stacking direction x in the first direction y connecting the third surface 12c and the fourth surface 12d is preferably 20 μm or more and 50 μm or less.

[0066] When the first base electrode layer 32a is provided on a portion of the first surface 12a, a portion of the second surface 12b, and a portion of the fifth surface 12e and a portion of the sixth surface 12f, the thickness in the stacking direction x connecting the first surface 12a and the second surface 12b at the center in the first direction y connecting the third surface 12c and the fourth surface 12d of the first base electrode layer 32a located on the first surface 12a and the second surface 12b is preferably 5 μm or more and 20 μm or less.Furthermore, the thickness in the second direction z connecting the fifth surface 12e and the sixth surface 12f at the center in the first direction y connecting the third surface 12c and the fourth surface 12d of the first base electrode layer 32a located on the fifth surface 12e and the sixth surface 12f is preferably 5 μm or more and 20 μm or less.

[0067] When the second base electrode layer 32b is provided on a portion of the first surface 12a, a portion of the second surface 12b, and a portion of the fifth surface 12e and a portion of the sixth surface 12f, the thickness of the second base electrode layer 32b located on the first surface 12a and the second surface 12b in the stacking direction x connecting the first surface 12a and the second surface 12b at a center in the first direction y connecting the third surface 12c and the fourth surface 12d is preferably 5 μm or more and 20 μm or less.Furthermore, the thickness of the second base electrode layer 32b located on the fifth surface 12e and the sixth surface 12f in the second direction z connecting the fifth surface 12e and the sixth surface 12f at a center in the first direction y connecting the third surface 12c and the fourth surface 12d is preferably 5 μm or more and 20 μm or less.

[0068] It is preferable that the thickness in the second direction z connecting the fifth surface 12e and the sixth surface 12f at the center in the first direction y connecting the third surface 12c and the fourth surface 12d of the third base electrode layer 32c, located on the fifth surface 12e, is 20 μm or more and 40 μm or less. Furthermore, it is preferable that the thickness in the second direction z connecting the fifth surface 12e and the sixth surface 12f at the center in the first direction y connecting the third surface 12c and the fourth surface 12d of the fourth base electrode layer 32d, which is located on the sixth surface 12f, is 20 μm or more and 40 μm or less.

[0069] The thickness in the stacking direction x connecting the first surface 12a and the second surface 12b at the center in the first direction y connecting the third surface 12c and the fourth surface 12d of the third base electrode layer 32c located on the second surface 12b is preferably, for example, 5 μm or more and 20 μm or less. Furthermore, the thickness in the stacking direction x connecting the first surface 12a and the second surface 12b at the center in the first direction y connecting the third surface 12c and the fourth surface 12d of the fourth base electrode layer 32d located on the second surface 12b is preferably, for example, 5 μm or more and 20 μm or less.

[0070] (In the case of a conductive resin layer) The conductive resin layer may be disposed on the baked layer so as to cover the baked layer, or may be disposed directly on the laminate 12 without a baked layer. The conductive resin layer may completely cover the baked layer or may cover only a portion of the baked layer. The conductive resin layer may also be a multi-layer structure.

[0071] The conductive resin layer contains a thermosetting resin and a metal. Because the conductive resin layer contains a thermosetting resin, it is more flexible than a baked layer made of, for example, a plating film or a baked conductive paste. Therefore, even if the multilayer ceramic capacitor 10 is subjected to a physical impact or an impact due to a thermal cycle, the conductive resin layer functions as a buffer layer and can prevent cracks in the multilayer ceramic capacitor 10.

[0072] The metal contained in the conductive resin layer can be Ag, Cu, Ni, Sn, Bi, or an alloy containing these. It is also possible to use a metal powder whose surface is coated with Ag. When using a metal powder whose surface is coated with Ag, it is preferable to use Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder. The reason for using Ag conductive metal powder as the conductive metal is that Ag has the lowest resistivity of all metals, making it suitable as an electrode material, and Ag is a noble metal that does not oxidize and has high weather resistance. Furthermore, it is possible to use a cheaper base metal while maintaining the above-mentioned properties of Ag.

[0073] Furthermore, the metal contained in the conductive resin layer may be Cu or Ni that has been subjected to an oxidation prevention treatment. The metal contained in the conductive resin layer may be a metal powder whose surface is coated with Sn, Ni, or Cu. When using a metal powder whose surface is coated with Sn, Ni, or Cu, it is preferable to use Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder.

[0074] The metal contained in the conductive resin layer is mainly responsible for the electrical conductivity of the conductive resin layer. Specifically, when the conductive fillers come into contact with each other, a conductive path is formed inside the conductive resin layer.

[0075] The metal contained in the conductive resin layer may be spherical or flat, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0076] The resin for the conductive resin layer may be any of various known thermosetting resins, such as epoxy resin, phenol resin, urethane resin, silicone resin, polyimide resin, etc. Among these, epoxy resin is one of the most suitable resins, as it has excellent heat resistance, moisture resistance, adhesion, etc.

[0077] The conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, and amide-imide-based compounds can be used as the curing agent for the epoxy resin.

[0078] The thickness of the thickest part of the conductive resin layer is preferably, for example, 20 μm or more and 70 μm or less.

[0079] (for thin film layers) When a thin film layer is provided as the base electrode layer 32, the thin film layer is formed by a thin film forming method such as sputtering or vapor deposition, and is a layer of 1 μm or less in thickness in which metal particles are deposited.

[0080] The plating layer 34 is disposed so as to cover the base electrode layer 32 .

[0081] The plating layer 34 includes, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0082] The plating layer 34 may be formed of multiple layers. In this case, the plating layer 34 preferably has a two-layer structure of Ni plating and Sn plating. The Ni plating layer is used to prevent the base electrode layer 32 from being eroded by solder when mounting the multilayer ceramic capacitor 10. The Sn plating layer is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, thereby facilitating mounting. The thickness of each layer of the plating layer 34 is preferably 1 μm or more and 6 μm or less.

[0083] The external electrodes 30 may be formed only by plating layers without providing the base electrode layer 32 . Although not shown, a structure in which a plating layer is provided without providing a base electrode layer 32 will be described below.

[0084] For any one or each of the first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d, a plating layer may be formed directly on the surface of the laminate 12 without providing a base electrode layer 32. That is, the multilayer ceramic capacitor 10 may have a structure including a plating layer electrically connected to the first internal electrode layer 16a and the second internal electrode layer 16b. In such a case, a catalyst may be disposed on the surface of the laminate 12 as a pretreatment, and then the plating layer may be formed.

[0085] In addition, when a plating layer is formed directly on the laminate 12 without providing the base electrode layer 32, the reduction in the thickness of the base electrode layer 32 can be converted into a lower profile, i.e., a thinner laminate 12, or the thickness of the capacitance forming portion 18, thereby improving the design freedom of the thin chip.

[0086] The plating layer preferably includes a lower-layer plating electrode formed on the surface of the laminate 12 and an upper-layer plating electrode formed on the surface of the lower-layer plating electrode. The lower-layer plating electrode and the upper-layer plating electrode each preferably include at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such a metal. Furthermore, the lower-layer plating electrode is preferably formed using Ni, which has solder barrier properties, and the upper-layer plating electrode is preferably formed using Sn or Au, which have good solder wettability.

[0087] Furthermore, for example, when the first internal electrode layer 16a and the second internal electrode layer 16b are formed using Ni, it is preferable that the lower-layer plated electrodes be formed using Cu, which has good bonding properties with Ni. The upper-layer plated electrodes may be formed as needed, and the first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d may each be composed of only the lower-layer plated electrodes. The upper-layer plated electrodes may be the outermost layer of the plating layers, or other plated electrodes may be formed on the surface of the upper-layer plated electrodes.

[0088] Here, when the external electrode 30 is formed by plating layers only without providing the base electrode layer 32, the thickness of each plating layer disposed without providing the base electrode layer 32 is preferably 1 μm or more and 15 μm or less.

[0089] Furthermore, the plating layer preferably does not contain glass, and the metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0090] The dimension in the first direction y of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 is defined as dimension L. Dimension L is preferably 0.6 mm or more and 1.6 mm or less. The dimension in the lamination direction x of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 is defined as dimension T. Dimension T is preferably 0.2 mm or more and 0.6 mm or less. The dimension in the second direction z of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 is defined as dimension W. The dimension W is preferably 0.3 mm or more and 0.8 mm or less.

[0091] The multilayer ceramic capacitor 10 shown in FIG. 1 includes the current-carrying portion 21, which allows the value of the direct current resistance (Rdc) to be reduced, and therefore the amount of heat generated by the multilayer ceramic capacitor 10 to be reduced. Furthermore, by concentrating the conductive portions 21 in the first outer layer portion 20a, space for capacitance formation can be secured, and by arranging the capacitance forming portion 18 closer to the mounting substrate, it is possible to achieve both securing the electrostatic capacitance and reducing the ESL.

[0092] 2. Mounting structure of multilayer ceramic capacitors Next, a mounting structure of a multilayer ceramic capacitor according to an embodiment of the present invention will be described with reference to FIGS.

[0093] As shown in FIGS. 9 and 10 , a mounting structure 100 of a multilayer ceramic capacitor according to this embodiment includes a multilayer ceramic capacitor 10 according to this embodiment and a mounting substrate 50. The mounting substrate 50 includes a substrate core material 51 and conductive lands 52. The substrate core material 51 is configured, for example, as a substrate made of a material in which a base material made of a mixture of glass fabric (cloth) and glass nonwoven fabric is impregnated with epoxy resin or polyimide resin, or as a ceramic substrate manufactured by baking a sheet in which ceramic and glass are mixed. The substrate core material 51 may be a substrate made of a single layer, or may be configured as a substrate made of a laminate of multiple layers.

[0094] The thickness of the core material 51 of the substrate is not particularly limited, but is preferably, for example, 0.2 mm or more and 1.6 mm or less.

[0095] One main surface of the core material 51 of the substrate is provided with conductor lands 52 and constitutes a substrate-side mounting surface 51a on which the multilayer ceramic capacitor 10 is mounted.

[0096] The conductor lands 52 include a first conductor land 52a, a second conductor land 52b, a third conductor land 52c, and a fourth conductor land 52d.

[0097] The first conductor land 52a is a portion that is electrically connected and mechanically joined to the first external electrode 30a of the multilayer ceramic capacitor 10 by the bonding material 54. The second conductor land 52b is a portion that is electrically connected and mechanically joined to the second external electrode 30b of the multilayer ceramic capacitor 10 by the bonding material 54. The third conductor land 52c is a portion that is electrically connected and mechanically joined to the third external electrode 30c of the multilayer ceramic capacitor 10 by the bonding material 54. The fourth conductor land 52d is a portion that is electrically connected and mechanically joined to the fourth external electrode 30d of the multilayer ceramic capacitor 10 by the bonding material 54.

[0098] The conductor land 52 may be provided on the main surface of the core material 51 of the substrate opposite to the substrate-side mounting surface 51a.

[0099] The material of the conductor lands 52 is not particularly limited, but metals such as copper, gold, palladium, and platinum can be used. The thickness of the conductor lands 52, i.e., the dimension in the stacking direction x, is not particularly limited, but is preferably 20 μm or more and 200 μm or less, for example. The bonding material 54 can be, for example, solder or a high-heat-resistant epoxy adhesive.

[0100] In the above description, the mounting substrate 50 corresponds to the mounting substrate of the present invention. The core material 51 of the substrate corresponds to the core material of the substrate of the present invention. The substrate-side mounting surface 51a corresponds to the mounting surface of the present invention. The multiple conductor lands 52 correspond to the multiple connecting conductors of the present invention. However, the connecting conductors of the present invention are not limited to so-called lands or other conductors that are provided between the multilayer ceramic capacitor and the mounting substrate and can electrically connect the two, and are not limited by other uses, functions, shapes, names, etc.

[0101] 9 and 10 is mounted on a mounting substrate 50 so that the second surface 12b of the multilayer ceramic capacitor 10 faces the substrate-side mounting surface 51a. This allows electrical connection between the multilayer ceramic capacitor 10 and the mounting substrate 50 to be achieved with the distances between the first extensions 27a and the second extensions 27b drawn out from the fifth surface 12e and the sixth surface 12f and the substrate-side mounting surface 51a of the mounting substrate 50 being minimized.

[0102] 9 and 10 directly reflects the various functions of the multilayer ceramic capacitor 10 according to this embodiment of the present invention, and because the capacitance forming portion 18 is mounted so as to face the mounting substrate 50, it is possible to shorten the current path from the second internal electrode layer 16b located closest to the second surface 12b of the multilayer ceramic capacitor 10 to the mounting substrate 50. As a result, the various effects of the multilayer ceramic capacitor 10 according to this embodiment of the present invention are reflected, and an effect of improving the low ESL characteristics in the mounting structure of the multilayer ceramic capacitor is achieved.

[0103] 3. Manufacturing method of multilayer ceramic capacitors Next, a method for manufacturing the multilayer ceramic capacitor 10 according to the embodiment of the present invention will be described.

[0104] First, a dielectric sheet for the dielectric layer and a conductive paste for the internal electrode are prepared. The dielectric sheet and the conductive paste for the internal electrode layer contain a binder and a solvent. The binder and the solvent may be known.

[0105] On the dielectric sheet, a conductive paste for the internal electrode layers is printed in a predetermined pattern by, for example, screen printing, gravure printing, etc. In this way, a dielectric sheet on which the pattern of the first internal electrode layer is formed, and a dielectric sheet on which the pattern of the second internal electrode layer is formed are prepared.

[0106] More specifically, a screen plate for printing the first internal electrode layer and a screen plate for printing the second internal electrode layer are prepared separately, and the patterns of the respective internal electrode layers can be printed using a printer capable of printing the two types of screen plates separately.

[0107] Here, the sheets on which the first internal electrode layers are printed are stacked to form a portion that will become a current-carrying portion. Also, the sheets on which the first internal electrode layers are printed and the sheets on which the second internal electrode layers are printed are alternately stacked to form a portion that will become a capacitance forming portion 18. At this time, the sheets on which the first internal electrode layers are printed are stacked in greater numbers than the sheets on which the second internal electrode layers are printed.

[0108] Next, a predetermined number of dielectric sheets on which no internal electrode layer patterns are printed are stacked to form the portion that will become the second outer layer portion 20b on the second surface 12b side. Thereafter, the portion that will become the capacitance forming portion 18 formed by the above process is stacked on top of the portion that will become the second outer layer portion 20b. Next, the portion that will become the current conducting portion 21 constituting the first outer layer portion 20a formed by the above process is stacked on top of the portion that will become the capacitance forming portion 18. Thereafter, a predetermined number of dielectric sheets on which no internal electrode layer patterns are printed are stacked on top of the portion that will become the current conducting portion 21 to form the portion that will become the dielectric portion 22 constituting the first outer layer portion 20a on the first surface 12a side. In this way, a laminated sheet is produced.

[0109] Subsequently, the laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0110] The laminated block is then cut to a predetermined size to produce laminated chips, which may have rounded corners and ridges by barrel polishing or the like.

[0111] The cut-out laminated chips are then fired to produce the laminate 12. The firing temperature depends on the materials of the dielectric layers 14 and the internal electrode layers 16, but is preferably 900°C or higher and 1400°C or lower.

[0112] (base electrode layer) Subsequently, a third base electrode layer 32c of the third external electrode 30c is formed on the fifth surface 12e of the laminate 12 obtained by firing, and a fourth base electrode layer 32d of the fourth external electrode 30d is formed on the sixth surface 12f of the laminate 12.

[0113] When forming a baked layer as the base electrode layer 32, a conductive paste containing a glass component and a metal component is applied, and then a baking process is performed to form the baked layer as the base electrode layer 32. The baking temperature at this time is preferably 700° C. or higher and 900° C. or lower. In this embodiment, the base electrode layer 32 is formed as a baked layer.

[0114] Various methods can be used to form the baked layer. For example, a method can be used in which the laminate 12 is oriented with a camera or magnet so that the fifth surface 12e or the sixth surface 12f faces downward, and then the laminate 12 is held with a holding jig and conductive paste is applied by extruding it through slits or holes. In this method, by increasing the amount of conductive paste extruded, the third base electrode layer 32c and the fourth base electrode layer 32d can be formed not only on the fifth surface 12e and the sixth surface 12f, but also on a portion of the first surface 12a and a portion of the second surface 12b.

[0115] Next, a first base electrode layer 32a of the first external electrode 30a is formed on the third surface 12c of the laminate 12 obtained by firing, and a second base electrode layer 32b of the second external electrode 30b is formed on the fourth surface 12d of the laminate 12. In this embodiment, the first base electrode layer 32a and the second base electrode layer 32b are formed using a DIP method so as to extend not only to the third surface 12c and the fourth surface 12d, but also to parts of the first surface 12a, the second surface 12b, the fifth surface 12e, and the sixth surface 12f.

[0116] In the baking process, the first base electrode layer 32a of the first external electrode 30a, the second base electrode layer 32b of the second external electrode 30b, the third base electrode layer 32c of the third external electrode 30c, and the fourth base electrode layer 32d of the fourth external electrode 30d may be baked simultaneously, or the first base electrode layer 32a of the first external electrode 30a and the second base electrode layer 32b of the second external electrode 30b, and the third base electrode layer 32c of the third external electrode 30c and the fourth base electrode layer 32d of the fourth external electrode 30d may be baked separately.

[0117] (Conductive resin layer) When the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of a baked layer, or the conductive resin layer may be formed directly on the laminate 12 without forming a baked layer.

[0118] The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and a metal component onto the baking layer or the laminate 12, followed by heat treatment at a temperature of 250°C to 550°C to thermally cure the resin and form the conductive resin layer. The heat treatment is preferably performed in an N2 atmosphere. To prevent the resin from scattering and the various metal components from oxidizing, the oxygen concentration is preferably kept below 100 ppm.

[0119] The conductive resin paste can be applied by extruding the conductive resin paste through a slit, similar to the method for forming the base electrode layer 32 as a baked layer.

[0120] (thin film layer) When the base electrode layer 32 is formed as a thin film layer, masking or the like is performed, and the base electrode layer 32 can be formed by a thin film formation method such as sputtering or vapor deposition in the area where the external electrode 30 is to be formed. The base electrode layer 32 formed as a thin film layer is a layer of deposited metal particles having a thickness of 1 μm or less.

[0121] (plating layer) Furthermore, the external electrodes 30 may be formed only with a plating layer without providing the base electrode layer 32. In this case, they can be formed by the following method.

[0122] The third surface 12c and the fourth surface 12d of the laminate 12 are plated to form a lower-layer plating electrode on the exposed portion of the first internal electrode layer 16a. Similarly, the fifth surface 12e and the sixth surface 12f of the laminate 12 are plated to form a lower-layer plating electrode on the exposed portion of the second internal electrode layer 16b. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating requires pretreatment using a catalyst or the like to improve the plating deposition rate, which has the disadvantage of complicating the process. Therefore, electrolytic plating is usually preferred. Barrel plating is preferably used as the plating method. If necessary, an upper-layer plating electrode may be formed on the surface of the lower-layer plating electrode in the same manner.

[0123] Finally, a plating layer 34 is formed. The plating layer 34 may be formed on the surface of the base electrode layer 32, or may be formed directly on the laminate 12. In this embodiment, the plating layer 34 is formed on the surface of the base electrode layer 32. More specifically, a Ni plating layer as a lower plating layer and a Sn plating layer as an upper plating layer are formed on the base electrode layer 32. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating.

[0124] In the manner described above, the multilayer ceramic capacitor 10 according to this embodiment is manufactured.

[0125] 4. Experimental Example Next, in order to confirm the effects of the multilayer ceramic capacitor according to the present invention described above, multilayer ceramic capacitors were manufactured as experimental samples, and each sample was evaluated by measuring the capacitance, DC resistance, and temperature rise.

[0126] (1) Specifications of the multilayer ceramic capacitor fabricated as a sample for the experiment Using the manufacturing method according to the above embodiment, multilayer ceramic capacitors provided in the multilayer ceramic electronic components of the comparative example and examples 1 to 8 were fabricated. Multilayer ceramic capacitor structure: 3 terminals (see Figure 1) Multilayer ceramic capacitor dimensions (L): 1.6mm Multilayer ceramic capacitor dimensions (W): 0.8mm Multilayer ceramic capacitor dimensions (T): 0.6mm Capacitance: See Table 1 Dielectric thickness of the first internal electrode layer of the capacitance forming section: 12 μm Dielectric thickness of the first internal electrode layer of the current-carrying part: 6 μm Thickness of the first and second internal electrode layers: 0.6 μm Internal electrode structure First internal electrode layer Material: Ni Shape: See Figure 7 Number of sheets: See Table 1 Thickness: 0.6 μm Second internal electrode layer Material: Ni Shape: See Figure 8 Number of sheets: See Table 1 Thickness: 0.6 μm External electrode structure First and second external electrodes Base electrode layer: A baked layer containing conductive metal (Cu) and glass components · Plating layer: Two-layer structure of Ni plating layer and Sn plating layer Third and fourth external electrodes Base electrode layer: A baked layer containing conductive metal (Cu) and glass components · Plating layer: Two-layer structure of Ni plating layer and Sn plating layer

[0127] For each sample according to the example, capacitance, DC resistance measurement tests, and temperature rise measurements were performed when the number of first internal electrode layers in the current-carrying portion located in the first outer layer portion was increased. Note that when the space for arranging the first internal electrode layers in the current-carrying portion located in the first outer layer portion became small, the numbers of first internal electrode layers and second internal electrode layers in the capacitance forming portion were reduced so as not to increase the T dimension of the laminate.

[0128] The sample according to the comparative example is a three-terminal multilayer ceramic capacitor identical to the multilayer ceramic capacitor according to the example, except that the first outer layer does not have a conductive portion.

[0129] (2) DC resistance (Rdc) measurement test of the internal electrode layer Electrical resistance measurements were performed using the four-terminal DC resistance measurement method. Specifically, a DC current of 100 mA was applied between the first and second external electrodes of the sample multilayer ceramic capacitor, and the potential difference between the first and second external electrodes was measured to measure the DC resistance while minimizing the influence of contact resistance. Thirty samples were used for each test, and the average value for each sample was calculated. Generally, as the DC resistance value increases, the temperature rise when a DC current flows increases, which can lead to problems with reduced high-temperature load reliability of the multilayer ceramic capacitor.

[0130] (3) Heat generation characteristics test The temperature rise value was measured by measuring the temperature generated by each sample of multilayer ceramic capacitor when a direct current was passed through it, and the temperature rise value was calculated by subtracting the room temperature from that value to obtain ΔT. The temperature rise was measured by placing a pair of electrodes on the surface of each sample chip. Five samples were used for each test, and the average value for each test was calculated. Alternatively, the temperature rise could be measured by using a thermal camera to measure the heat generation temperature of each sample chip.

[0131] (4) Evaluation criteria The evaluation criteria for the experimental results for each sample were as follows: In the heat generation characteristic test, if the temperature rise value ΔT is 40°C or more, it is marked as "×" as a failure. . When the temperature rise ΔT is less than 40°C, and the capacitance value is If the rate was 80% or more, it was considered good and marked with a "Good". In addition, when the temperature rise value ΔT is less than 40°C and the capacitance value is the same as that of the comparative example, On the other hand, if it was less than 80%, it was rated as "△".

[0132] (5) Results Table 1 shows the measurement results of the capacitance, heat generation characteristic test, and DC resistance measurement test when the number of first internal electrode layers (A) of the capacitance forming portion, the number of second internal electrode layers (B) of the capacitance forming portion, and the number of first internal electrode layers (C) of the current-carrying portion are changed, and the evaluation results based on these measurement results.

[0133] Table 1 also shows the ratio (C / (A+B)) of the number of first internal electrode layers in the current-carrying portion to the total number of first internal electrode layers and second internal electrode layers in the capacitance-forming portion, and the ratio (C / A) of the number of first internal electrode layers in the current-carrying portion to the number of first internal electrode layers in the capacitance-forming portion.

[0134] [Table 1]

[0135] According to Table 1, it was confirmed that the first internal electrode layers were arranged in the current-carrying portions of the samples of Examples 1 to 8, and that the value of the direct current resistance (Rdc) decreased as the number of first internal electrode layers in the current-carrying portions increased. As a result, it was confirmed that it was possible to reduce the heat generation amount of the multilayer ceramic capacitors that were the samples of each Example.

[0136] Furthermore, it was confirmed that increasing the number of first internal electrode layers arranged in the current-carrying section can reduce the temperature rise value as mentioned above, but maintaining the size of the multilayer ceramic capacitor requires reducing the total number of internal electrode layers in the capacitance forming section, resulting in a decrease in the capacitance value.

[0137] As a result of the above, it was found that a good sample that can achieve both a reduction in temperature rise and the acquisition of capacitance values ​​can be obtained when the ratio (C / (A+B)) of the total number of first internal electrode layers and second internal electrode layers arranged in the capacitance forming section to the number of first internal electrode layers in the current-carrying section is 0.03 or more and 1.04 or less.

[0138] It was also found that a good sample that can achieve both a reduction in temperature rise and the acquisition of capacitance values ​​can be obtained when the ratio (C / A) of the number of first internal electrode layers in the current-carrying section to the total number of first internal electrode layers arranged in the capacitance forming section is 0.07 or more and 2.17 or less.

[0139] On the other hand, in the comparative example sample, since no current-carrying parts are provided, the conductivity between the internal electrode layer and the external electrode decreases, which increases the DC resistance (Rdc) and the amount of heat generated, and it became clear that the temperature rise of the multilayer ceramic capacitor exceeds 40°C.

[0140] From the above results, it was revealed that in the samples of the multilayer ceramic capacitors according to Examples 1 to 8, the DC resistance (Rdc) can be reduced by having a conductive portion in the first outer layer portion, and as a result, the amount of heat generated by the multilayer ceramic capacitor can be reduced, thereby suppressing temperature rise.

[0141] As described above, the embodiment of the present invention has been disclosed in the above description, but the present invention is not limited to this. In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position, arrangement, etc. without departing from the scope of the technical idea and purpose of the present invention, and these modifications are included in the present invention.

[0142] <1> a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, the laminate having a first surface and a second surface facing each other in a lamination direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the lamination direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the lamination direction and the first direction; a first external electrode disposed on the third surface; a second external electrode disposed on the fourth surface; a third external electrode disposed on the fifth surface; a fourth external electrode disposed on the sixth surface; A multilayer ceramic capacitor comprising: The plurality of internal electrode layers are a first internal electrode layer exposed on the third surface and the fourth surface; a second internal electrode layer exposed on the fifth surface and the sixth surface; and The laminate is a capacitance forming portion in which the first internal electrode layer and the second internal electrode layer face each other to form a capacitance; a first outer layer portion located between the first surface and the capacitance generating portion; a second outer layer portion located between the second surface and the capacitance generating portion; and the capacitance forming portion is disposed at the center in the stacking direction, the first outer layer portion is disposed on a non-mounting substrate side, A multilayer ceramic capacitor, wherein one or more current-carrying portions on which the first internal electrode layers are arranged are arranged in the first outer layer portion.

[0143] <2> a thickness in the stacking direction of the dielectric portion located between the first surface and the current-carrying portion is smaller than a thickness in the stacking direction of the second outer layer portion; <1> The multilayer ceramic capacitor according to claim 1.

[0144] <3> a ratio of the total number of the first internal electrode layers arranged in the current-carrying portion to the total number of the first internal electrode layers and the second internal electrode layers arranged in the capacitance forming portion is 0.03 or more and 1.04 or less; <1> or <2> The multilayer ceramic capacitor according to claim 1.

[0145] <4> a ratio of the total number of the first internal electrode layers arranged in the current-carrying portion to the total number of the first internal electrode layers arranged in the capacitance forming portion is 0.07 or more and 2.17 or less; <1> Or <3> 10. The multilayer ceramic capacitor according to claim 9, wherein

[0146] <5> the current-carrying portion is disposed within a range of up to 1 / 5 of the stacking direction of the stacked body from the first surface; <1> Or <4> 10. The multilayer ceramic capacitor according to claim 9, wherein

[0147] <6> a thickness of the dielectric layer of the current-carrying portion in the stacking direction is smaller than a thickness of the dielectric layer of the capacitance-forming portion in the stacking direction; <1> Or <5> 10. The multilayer ceramic capacitor according to claim 9, wherein

[0148] <7> The number of the first internal electrode layers arranged in the current-carrying portion is 1 to 26. <1> Or <6> 10. The multilayer ceramic capacitor according to claim 9, wherein

[0149] <8> a mounting board; a multilayer ceramic capacitor mounted on the mounting substrate; Equipped with The multilayer ceramic capacitor <1> Or <7> The multilayer ceramic capacitor according to any one of the preceding claims, The mounting board is A core material of the substrate; a first connecting conductor connected to the first external electrode disposed on the core material; a second connecting conductor connected to the second external electrode disposed on the core material; a third connecting conductor connected to the third external electrode disposed on the core material; a fourth connecting conductor connected to the fourth external electrode disposed on the core material; and The multilayer ceramic capacitor is mounted so that the second surface faces the mounting substrate. [Explanation of symbols]

[0150] 10 Multilayer ceramic capacitors 12 Laminate 12a First Side 12b Second Side 12c First Side 12d Second Side 12e First Side 12f Second Floor 14 Dielectric layer 16 Internal electrode layer 16a First internal electrode layer 16b Second internal electrode layer 18 Capacity forming part 20a First outer layer 20b Second outer layer 21 Electrical part 22 Dielectric part 23a, 23b W gap 24a, 24b L-gap 25a first opposing portion 25b second opposing portion 26a First drawer 26b Second drawer 27a First extension 27b Second extension 30 External electrode 30a First outer electrode 30b Second external electrode 30c Third external electrode 30d Fourth external electrode 30c1 first covering portion 30c2 first folded portion 30c3 Second fold 30d1 Second coating part 30d2 Third fold 30d3 Fourth fold 32 Base electrode layer 32a First base electrode layer 32b Second base electrode layer 32c Third base electrode layer 32d Fourth base electrode layer 34 plating layer 34a First plating layer 34b Second plating layer 34c Third plating layer 34d Fourth plating layer 50 Mounting board 51 Core material of the board 51a PCB mounting surface 52 Conductor Land 52a First conductor land 52b Second conductive land 52c Third Conductor Land 52d Fourth Conductor Land 54 Bonding material 100 Mounting structure of multilayer ceramic capacitor x stacking direction y primary direction z second direction L is the dimension of the multilayer ceramic capacitor in the first direction W is the dimension in the second direction of the multilayer ceramic capacitor T Dimension in the lamination direction of a multilayer ceramic capacitor l Dimension of the laminate in the first direction w is the dimension of the laminate in the second direction t Dimension of laminate in the stacking direction

Claims

1. a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, the laminate having a first surface and a second surface facing each other in a lamination direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the lamination direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the lamination direction and the first direction; a first external electrode disposed on the third surface; a second external electrode disposed on the fourth surface; a third external electrode disposed on the fifth surface; a fourth external electrode disposed on the sixth surface; A multilayer ceramic capacitor comprising: The plurality of internal electrode layers are a first internal electrode layer exposed on the third surface and the fourth surface; a second internal electrode layer exposed on the fifth surface and the sixth surface; and The laminate is a capacitance forming portion in which the first internal electrode layer and the second internal electrode layer face each other to form a capacitance; a first outer layer portion located between the first surface and the capacitance generating portion; a second outer layer portion located between the second surface and the capacitance generating portion; and the capacitance forming portion is disposed at the center in the stacking direction, the first outer layer portion is disposed on a non-mounting substrate side, a current-carrying portion in which one or more first internal electrode layers are arranged is disposed in the first outer layer portion;

2. 2. The multilayer ceramic capacitor according to claim 1, wherein a thickness in the lamination direction of the dielectric portion located between the first surface and the current-carrying portion is smaller than a thickness in the lamination direction of the second outer layer portion.

3. 3. The multilayer ceramic capacitor according to claim 1, wherein a ratio of the total number of the first internal electrode layers arranged in the current-carrying portion to the total number of the first internal electrode layers and the second internal electrode layers arranged in the capacitance forming portion is 0.03 or more and 1.04 or less.

4. 3. The multilayer ceramic capacitor according to claim 1, wherein a ratio of the total number of the first internal electrode layers arranged in the current-carrying portion to the total number of the first internal electrode layers arranged in the capacitance forming portion is 0.07 or more and 2.17 or less.

5. 3. The multilayer ceramic capacitor according to claim 1, wherein the current-carrying portion is disposed within a range of up to 1 / 5 of the distance from the first surface in the stacking direction of the laminate.

6. 3. The multilayer ceramic capacitor according to claim 1, wherein the thickness of the dielectric layer of the current-carrying portion in the stacking direction is smaller than the thickness of the dielectric layer of the capacitance-forming portion in the stacking direction.

7. 3. The multilayer ceramic capacitor according to claim 1, wherein the number of the first internal electrode layers arranged in the current-carrying portion is 1 to 26.

8. a mounting board; a multilayer ceramic capacitor mounted on the mounting substrate; Equipped with The multilayer ceramic capacitor is the multilayer ceramic capacitor according to claim 1, The mounting board is A core material of the substrate; a first connecting conductor connected to the first external electrode disposed on the core material; a second connecting conductor connected to the second external electrode disposed on the core material; a third connecting conductor connected to the third external electrode disposed on the core material; a fourth connecting conductor connected to the fourth external electrode disposed on the core material; and The multilayer ceramic capacitor is mounted so that the second surface faces the mounting substrate.

Images