Semiconductor device

Abstract

To increase the capacitance of a capacitor.SOLUTION: The semiconductor device 10 includes a semiconductor substrate 21, trenches 30, insulating layers 40, and electrode portions 50. The semiconductor substrate 21 includes a first substrate surface 211 and a second substrate surface 212 opposite to the first substrate surface 211. The trench 30 is recessed from the first substrate surface 211 toward the second substrate surface 212 and has a width in a plan view. The insulating layer 40 is arranged on the inner surface 301 of the trench 30. The electrode portion 50 is provided inside the trench 30 and is surrounded with the insulating layer 40. The electrode portion 50 has conductivity. The trench 30 includes a first trench portion 31 and a second trench portion 32. The first trench portion 31 has a first widthwise side W11 in the widthwise direction of the trench 30. The second trench portion is arranged at a position different from the first trench portion 31 in the Z-axis direction. The second trench portion 32 has a second widthwise W11 larger than the first widthwise W12 in the widthwise direction of the trench 30.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Patent document 1 discloses a chip capacitor comprising a substrate, a first conductive film formed on the substrate, a dielectric film disposed on the first conductive film and on the substrate, and a second conductive film disposed on the dielectric film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2017-195321

[0004] [overview] In a semiconductor device including a capacitor, there is a demand for increasing the capacitance of the capacitor.

[0005] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor substrate including a first substrate surface and a second substrate surface opposite the first substrate surface, a trench recessed from the first substrate surface toward the second substrate surface and having a width when viewed in a thickness direction of the semiconductor substrate, an insulating layer disposed on an inner surface of the trench, and a conductive electrode portion disposed within the trench and surrounded by the insulating layer, wherein the trench includes a first trench portion having a first width in a width direction of the trench, and a second trench portion disposed at a different position in the thickness direction from the first trench portion and having a second width in the width direction that is greater than the first width. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view of an exemplary semiconductor device according to one embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an enlarged portion of FIG. [Figure 3]FIG. 3 is a schematic cross-sectional view of the semiconductor device taken along line F3-F3 in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view showing an enlarged portion of FIG. [Figure 5] 5A to 5C are schematic cross-sectional views illustrating exemplary manufacturing steps for the semiconductor device of FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 18] FIG. 18 is a schematic plan view showing a semiconductor device of a comparative example. [Figure 19] FIG. 19 is a schematic cross-sectional view of the semiconductor device of the comparative example of FIG. [Figure 20] FIG. 20 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 21] FIG. 21 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 22] FIG. 22 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 23] FIG. 23 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 24] FIG. 24 is a schematic cross-sectional view of the semiconductor device of FIG. [Figure 25] FIG. 25 is a schematic cross-sectional view showing a semiconductor device according to a modified example. [Figure 26] FIG. 26 is a schematic cross-sectional view showing a semiconductor device according to a modified example. [Figure 27] FIG. 27 is a schematic cross-sectional view showing a semiconductor device according to a modified example. [Figure 28] FIG. 28 is a schematic cross-sectional view showing a semiconductor device according to a modified example.

[0007] [Detailed explanation] Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure. Terms such as "first," "second," and "third" in the present disclosure are used merely to distinguish between objects and do not rank the objects.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] <Embodiment> A semiconductor device 10 according to an embodiment will be described with reference to FIGS. FIG. 1 is a schematic plan view of a semiconductor device 10. FIG. 2 is a schematic plan view showing an enlarged portion of FIG. 1. FIG. 3 is a schematic cross-sectional view of the semiconductor device 10 taken along line F3-F3 in FIG. 2. FIG. 4 is a schematic cross-sectional view showing an enlarged portion of FIG. 3. The term "plan view" used in the present disclosure refers to viewing the semiconductor device 10 in the Z-axis direction of the XYZ axes shown in FIG. 1.

[0010] As shown in FIG. 1, the semiconductor device 10 has a rectangular flat plate shape with its thickness direction in the Z-axis direction. The semiconductor device 10 includes a device front surface 101 and a device back surface 102 opposite the device front surface 101 in the Z-axis direction. The semiconductor device 10 also includes multiple device side surfaces 103, 104, 105, and 106 connecting the device front surface 101 and the device back surface 102. The device side surfaces 103 to 106 are perpendicular to the Z-axis direction and face either the X-axis direction or the Y-axis direction, which are perpendicular to each other. In one example, the device side surfaces 103 and 104 extend along the YZ plane and form both end surfaces in the X-axis direction. The device side surfaces 105 and 106 extend along the XZ plane and form both end surfaces in the Y-axis direction.

[0011] The semiconductor device 10 includes, for example, a chip-shaped integrated circuit (IC) device. The semiconductor device 10 may be referred to as a small scale IC (SSI), a middle scale IC (MSI), a large scale IC (LSI), a very large scale IC (VLSI), an ultra large scale IC (ULSI), or the like, depending on the number of integrated circuit elements.

[0012] In one example, the semiconductor device 10 includes a plurality of device regions 11. Adjacent device regions 11 are spaced apart in the X-axis direction or the Y-axis direction. The device regions 11 are spaced apart from the device side surfaces 103 to 106. The number, arrangement, and shape of the device regions 11 included in the semiconductor device 10 may be changed as appropriate. The semiconductor device 10 may include at least one device region 11.

[0013] The device region 11 may be a region including functional devices of the semiconductor device 10. The functional devices include circuit elements such as transistors, capacitors, diodes, resistors, etc. In one example, the device region 12 includes a capacitor 13.

[0014] The semiconductor device 10 may include a plurality of electrode pads exposed on the device surface 101. The plurality of electrode pads are used to supply power to functional devices of the semiconductor device 10 and to input and output signals.

[0015] (Schematic configuration of the capacitor) The capacitor 13 is composed of a semiconductor substrate 21, at least one trench 30 provided in the semiconductor substrate 21, and an insulating layer 40 and an electrode portion 50 disposed in the trench 30. In order to make the capacitor 13 easier to understand, in Figures 1 and 2, the first trench portion 31 of the trench 30, the insulating layer 40, and the electrode portion 50 are shown by solid lines, and the second trench portion 32 is shown by dashed lines.

[0016] In one example, the semiconductor device 10 includes three trenches 30. The three trenches 30 are arranged in the X-axis direction in a plan view. Each trench 30 extends in the Y-axis direction in a plan view.

[0017] (Configuration of a semiconductor device related to a capacitor) 3 and 4, the semiconductor substrate 21 includes a first substrate surface 211 and a second substrate surface 212 opposite to the first substrate surface 211. The second substrate surface 212 of the semiconductor substrate 21 may constitute the device back surface 102 of the semiconductor device 10. The semiconductor substrate 21 includes a plurality of substrate side surfaces that constitute a portion of each of the device side surfaces 103 to 106. The substrate side surfaces connect the first substrate surface 211 and the second substrate surface 212.

[0018] The semiconductor substrate 21 has a thickness T11 in the Z-axis direction. The thickness T11 of the semiconductor substrate 21 may be 100 μm or more and 500 μm or less. The semiconductor substrate 21 may be made of a material containing Si (silicon). For example, the semiconductor substrate 21 may be a silicon substrate. The semiconductor substrate 21 may include an epitaxial layer. The semiconductor substrate 21 may contain impurities or may not contain impurities. The impurities may be impurities of a first conductivity type. For example, the semiconductor substrate 21 may be a silicon substrate containing impurities of the first conductivity type. The first conductivity type may be, for example, p-type. The resistivity of the semiconductor substrate 21 may be 5 mΩ·cm or more and 100 mΩ·cm or less by introducing p-type impurities.

[0019] The semiconductor substrate 21 may be made of a compound semiconductor. Examples of compound semiconductors include III-V compound semiconductors, IV-IV compound semiconductors, and alloy semiconductors using these semiconductors. III-V compound semiconductors are, for example, Ga-containing semiconductors such as GaAs and GaN. IV-IV compound semiconductors are, for example, Si-containing semiconductors such as SiC and SiGe.

[0020] The semiconductor device 10 may include a surface insulating layer 22. The surface insulating layer 22 may cover the first substrate surface 211 of the semiconductor substrate 21. In one example, the surface insulating layer 22 covers the entire first substrate surface 211 of the semiconductor substrate 21. In one example, the surface insulating layer 22 may include a first insulating layer 23 and a second insulating layer 24. The first insulating layer 23 is made of a material containing at least one of SiO2 (silicon oxide), SiN (silicon nitride), SiON (silicon oxynitride), and Al2O3 (aluminum oxide). In one example, the first insulating layer 23 is made of SiN. The second insulating layer 24 is made of a material containing at least one of SiO2, SiN, SiON, and Al2O3. In one example, the second insulating layer 24 is made of SiO2. The surface insulating layer 22 may have a single-layer structure. Alternatively, the surface insulating layer 22 may be made of three or more insulating layers.

[0021] The semiconductor device 10 may include a conductive portion 25. The conductive portion 25 may include an insulating layer and a wiring layer. The insulating layer may be composed of multiple insulating films. The multiple insulating films may be referred to as interlayer insulating films. The wiring layer may include multiple layer wirings, via conductors connecting the layer wirings, pad electrodes for external connection, etc. The wiring layer connects functional devices in the device region 11 shown in Figure 1. The capacitor 13 is connected to the functional device by the wiring layer. A surface 251 of the conductive portion 25 may constitute the device surface 101 of the semiconductor device 10.

[0022] The semiconductor device 10 includes a trench 30 provided in a semiconductor substrate 21. The trench 30 is recessed from a first substrate surface 211 toward a second substrate surface 212 of the semiconductor substrate 21. The trench 30 has a width W1A in a plan view, that is, when viewed in the thickness direction of the semiconductor substrate 21. In one example, the trenches 30 are arranged so that the width W1A is the length in the X-axis direction. The widths W1A of the multiple trenches 30 may be the same. The trenches 30 extend in the Y-axis direction. The trenches 30 have a length L1A in the Y-axis direction. In one example, the length L1A of the trench 30 may be the length of the first trench portion 31 in the Y-axis direction. The length L1A of the trench 30 may also be the length of the second trench portion 32 in the Y-axis direction. The lengths L1A of the multiple trenches 30 may be the same. The multiple trenches 30 are formed by removing a portion of the semiconductor substrate 21.

[0023] The trench 30 includes an inner surface 301 provided in the semiconductor substrate 21. The semiconductor device 10 includes an insulating layer 40 disposed on the inner surface 301 of the trench 30. The insulating layer 40 has insulating properties. For example, the insulating layer 40 may be made of a material containing Si. For example, the insulating layer 40 may be an oxide film such as SiO2. The insulating layer 40 may be a SiN film. The insulating layer 40 may be an SiO2 / SiN stacked film or an SiO2 / SiN / SiO2 stacked film. The insulating layer 40 may be an ON film or an ONO film, or a stacked film thereof. The insulating layer 40 may be an insulating film made of a high-dielectric material (high-k material).

[0024] The electrode portion 50 is provided in the trench 30. The electrode portion 50 is surrounded by the insulating layer 40. The electrode portion 50 is conductive. For example, the electrode portion 50 may be made of polysilicon. Impurities may be added to the polysilicon. The electrode portion 50 may be made of a conductive layer of polysilicon to which no impurities have been added, and a conductive layer of polysilicon to which impurities have been added. The impurities added to the polysilicon may be p-type impurities or n-type impurities.

[0025] The electrode portion 50 faces the inner surface 301 of the trench 30 with the insulating layer 40 sandwiched therebetween. It can be said that the electrode portion 50 faces the semiconductor substrate 21 with the insulating layer 40 sandwiched therebetween. The capacitor 13 is composed of the insulating layer 40, and the electrode portion 50 and the semiconductor substrate 21 which face each other with the insulating layer 40 sandwiched therebetween.

[0026] (Trench configuration) The trench 30 includes a first trench portion 31 and a second trench portion 32. The second trench portion 32 is disposed at a different position from the first trench portion 31 in the Z-axis direction.

[0027] 3 and 4, the trench 30 includes four first trench portions 31A, 31B, 31C, and 31D and four second trench portions 32A, 32B, 32C, and 32D. The number of first trench portions 31 may be changed to any number greater than or equal to one, as appropriate. The number of second trench portions 32 may be changed to any number greater than or equal to one, as appropriate.

[0028] In the following description, when the first trench portions 31A, 31B, 31C, and 31D are not distinguished from one another, they will simply be referred to as the first trench portion 31. Similarly, in the following description, when the second trench portions 32A, 32B, 32C, and 32D are not distinguished from one another, they will simply be referred to as the second trench portion 32.

[0029] 4, the first trenches 31A to 31D and the second trenches 32A to 32D are alternately arranged in the Z-axis direction. The first trenches 31A to 31D and the second trenches 32A to 32D are connected to each other in the Z-axis direction.

[0030] The first trench portion 31A extends from the first substrate surface 211 of the semiconductor substrate 21 toward the second substrate surface 212 of the semiconductor substrate 21. The second trench portion 32A extends from the first trench portion 31A toward the second substrate surface 212 of the semiconductor substrate 21. The first trench portion 31B extends from the second trench portion 32A toward the second substrate surface 212 of the semiconductor substrate 21. The second trench portion 32B extends from the first trench portion 31B toward the second substrate surface 212 of the semiconductor substrate 21. The first trench portion 31C extends from the second trench portion 32B toward the second substrate surface 212 of the semiconductor substrate 21. The second trench portion 32C extends from the first trench portion 31C toward the second substrate surface 212 of the semiconductor substrate 21. The first trench portion 31D extends from the second trench portion 32C toward the second substrate surface 212 of the semiconductor substrate 21. The second trench portion 32D extends from the first trench portion 31D toward the second substrate surface 212 of the semiconductor substrate 21.

[0031] The first trench portion 31A opens to the first substrate surface 211 of the semiconductor substrate 21. This first trench portion 31A may be referred to as a surface trench portion. The first trench portion 31B is disposed between two second trench portions 32A, 32B arranged in the Z direction. This first trench portion 31B may be referred to as an intermediate trench portion. The first trench portion 31C is disposed between two second trench portions 32B, 32C arranged in the Z direction. This first trench portion 31C may be referred to as an intermediate trench portion. The first trench portion 31D is disposed between two second trench portions 32C, 32D arranged in the Z direction. This first trench portion 31D may be referred to as an intermediate trench portion.

[0032] The first trench portions 31A, 31B, 31C, and 31D extend in the Z-axis direction. The first trench portions 31A, 31B, 31C, and 31D have first lengths D11A, D11B, D11C, and D11D in the Z-axis direction. In one example, the first lengths D11A to D11D are equal to one another. At least one of the first lengths D11A to D11D of the first trench portions 31A to 31D may be different from the others. The first lengths D11A to D11D of the first trench portions 31A to 31D may be different from one another.

[0033] The first trench portions 31A, 31B, 31C, and 31D have first widths W11A, W11B, W11C, and W11D, respectively, in the X-axis direction, which is the width direction of the trench 30. In one example, the first widths W11A to W11D are equal to one another. At least one of the first widths W11A to W11D of the first trench portions 31A to 31D may be different from the others. The first widths W11A to W11D of the first trench portions 31A to 31D may be different from one another. The first width W11 of the first trench portion 31 may be represented by the maximum value of the first widths W11A to W11D of the multiple first trench portions 31A to 31D. Note that the first width W11 of the first trench portion 31 may be represented by the average value of the first widths W11A to W11D of the multiple first trench portions 31A to 31D.

[0034] The second trench portions 32A, 32B, 32C, and 32D extend in the Z-axis direction. The second trench portions 32A, 32B, 32C, and 32D have second lengths D12A, D12B, D12C, and D12D in the Z-axis direction. In one example, the second lengths D12A to D12D are equal to one another. At least one of the second lengths D12A to D12D of the second trench portions 32A to 32D may be different from the others. The second lengths D12A to D12D of the second trench portions 32A to 32D may be different from one another.

[0035] The second trench portions 32A, 32B, 32C, and 32D have second widths W12A, W12B, W12C, and W12D, respectively, in the X-axis direction, which is the width direction of the trench 30. In one example, the second widths W12A to W12D are equal to one another. At least one of the second widths W12A to W12D of the second trench portions 32A to 32D may be different from the others. The second widths W12A to W12D of the second trench portions 32A to 32D may be different from one another.

[0036] The second width W12 of the second trench portion 32 may be represented by the maximum value of the second widths W12A to W12D of the multiple second trench portions 32A to 32D. Alternatively, the second width W12 of the second trench portion 32 may be represented by the average value of the second widths W12A to W12D of the multiple second trench portions 32A to 32D. It can be said that the second trench portion 32 has a second width W12 that is larger than the first width W11 of the first trench portion 31 in the X-axis direction.

[0037] The inner surface 321 of the second trench portion 32 includes side surfaces 322 facing each other in the X-axis direction, a top surface 323 extending in the X-axis direction from the upper end of the side surface 322, and a bottom surface 324 extending in the X-axis direction from the lower end of the side surface 322. The area between the side surface 322 and the top surface 323 may be curved so as to be convex toward the outside of the second trench portion 32. The area between the side surface 322 and the bottom surface 324 may be curved so as to be convex toward the outside of the second trench portion 32.

[0038] The trench 30 has a step surface between the first trench portion 31 and the second trench portion 32. More specifically, in the second trench portions 32A to 32D, the top surface 323 and the bottom surface 324 face each other in the Z-axis direction. In the second trench portions 32A to 32D, the top surface 323 of the second trench portion 32 connects the side surface 322 of the second trench portion 32 to the inner surface 311 of the first trench portion 31. The top surface 323 of the second trench portion 32 forms a step surface between the second trench portion 32 and the first trench portion 31. In the second trench portions 32A to 32C, the bottom surface 324 of the second trench portion 32 connects the side surface 322 of the second trench portion 32 to the inner surface 311 of the first trench portion 31. The bottom surface 324 of the second trench portion 32 forms a step surface between the second trench portion 32 and the first trench portion 31 .

[0039] In a plan view, a distance L21A from the inner surface 311 of the first trench portion 31A to the side surface 322 of the second trench portion 32A may correspond to a second length D12A of the second trench portion 32A in the Z-axis direction. The distance L21A may be equal to the second length D12A. The distance L21A may also be different from the second length D12A.

[0040] In a plan view, a distance L21B from the inner surface 311 of the first trench portion 31B to the side surface 322 of the second trench portion 32B may correspond to a second length D12B of the second trench portion 32B in the Z-axis direction. The distance L21B may be equal to the second length D12B. The distance L21B may also be different from the second length D12B.

[0041] In a plan view, a distance L21C from the inner surface 311 of the first trench portion 31C to the side surface 322 of the second trench portion 32C may correspond to a second length D12C of the second trench portion 32C in the Z-axis direction. The distance L21C may be equal to the second length D12C. The distance L21C may also be different from the second length D12C.

[0042] In a plan view, a distance L21D from the inner surface 311 of the first trench portion 31D to the side surface 322 of the second trench portion 32D may correspond to a second length D12D of the second trench portion 32D in the Z-axis direction. The distance L21D may be equal to the second length D12D. The distance L21D may also be different from the second length D12D.

[0043] (insulating layer) The insulating layer 40 includes a first insulating layer 41 covering the inner surface 311 of the first trench portion 31 and a second insulating layer 42 covering the inner surface 321 of the second trench portion 32. The thickness of the first insulating layer 41 may be equal to the thickness of the second insulating layer 42. The thickness of the first insulating layer 41 may be different from the thickness of the second insulating layer 42.

[0044] The first trench portion 31A, which is a surface trench portion, opens to the first substrate surface 211 of the semiconductor substrate 21. The surface insulating layer 22 provided on the first substrate surface 211 of the semiconductor substrate 21 includes an opening 223 that communicates with the trench 30. The insulating layer 40 may include a protruding portion 43 that is arranged in the opening 223 of the surface insulating layer 22.

[0045] (electrode part) The electrode portion 50 includes a first electrode portion 51 in the first trench portion 31 and a second electrode portion 52 in the second trench portion 32. The first electrode portion 51 and the second electrode portion 52 are electrically connected to each other. The electrode portion 50 may include a connection portion 53 disposed in the opening 223 of the surface insulating layer 22. The connection portion 53 is surrounded by the protruding portion 43 of the insulating layer 40 in a plan view. The connection portion 53 is exposed from the surface insulating layer 22. A wiring member such as a via wiring (not shown) is electrically connected to the connection portion 53. The electrode portion 50 is electrically connected to a circuit element in the semiconductor device 10 by the connection portion 53.

[0046] (cavity) A cavity 35 (seam) is provided in the second trench portion 32. The cavity 35 is surrounded by the second electrode portion 52. The cavity 35 can be said to be a region inside the insulating layer 42 of the second trench portion 32 that is not filled with the electrode portion 50. Therefore, the electrode portion 50 disposed in the second trench portion 32 can be said to have a hollow shape.

[0047] 3, the trenches 30 are spaced apart in the X-axis direction. The spacing between the arranged trenches 30 may be represented by a distance L31 between two adjacent first trench portions 31 in the X-axis direction, which is the arrangement direction. The spacing between the trenches 30 may be represented by a distance L32 between two adjacent second trench portions 32 in the X-axis direction. The distance L32 between two adjacent second trench portions 32 in the X-axis direction is smaller than the second widths W12 (W12A to W12D) of the second trench portions 32.

[0048] (Method of manufacturing a semiconductor device) Next, an example of a method for manufacturing the semiconductor device 10 shown in FIGS. 1 to 4 will be described. 5 to 17 are schematic cross-sectional views showing exemplary manufacturing processes for the semiconductor device 10. FIGS. 5 to 17 correspond to the cross-sectional structure of the semiconductor device 10 shown in FIG. 4. FIGS. 5 to 17 show the range for creating a configuration related to one trench 30. For ease of understanding, in FIGS. 5 to 17, components that are similar to the final components of the semiconductor device 10 are denoted by the same reference numerals as in FIG. 4.

[0049] 5, the method for manufacturing the semiconductor device 10 includes preparing a semiconductor substrate 21. The semiconductor substrate 21 may be, for example, a silicon wafer containing impurities of a first conductivity type. The semiconductor substrate 21 includes a first substrate surface 211 and a second substrate surface 212 opposite to the first substrate surface 211.

[0050] The method for manufacturing the semiconductor device 10 includes forming a surface insulating layer 22 on the first substrate surface 211 of the semiconductor substrate 21. The surface insulating layer 22 includes an opening 223 that exposes the first substrate surface 211 of the semiconductor substrate 21 at a position where a trench 30 (see FIG. 4) is to be formed.

[0051] The surface insulating layer 22 may be made of a material containing Si. The surface insulating layer 22 may have a multi-layer structure. The surface insulating layer 22 may be made of a single layer. In one example, the surface insulating layer 22 includes a first insulating layer 23 and a second insulating layer 24 stacked in this order from the first substrate surface 211 of the semiconductor substrate 21. The first insulating layer 23 and the second insulating layer 24 may be insulating films. The first insulating layer 23 may be a SiN film, and the second insulating layer 24 may be a SiO2 film.

[0052] 6 to 12, the method for manufacturing the semiconductor device 10 includes forming the trench 30. The trench 30 includes a plurality of first trench portions 31A to 31D and second trench portions 32A to 32D.

[0053] First, the formation of the first trench portion 31A and the second trench portion 32A will be described. As shown in FIG. 6, the method for manufacturing the semiconductor device 10 includes forming a first trench portion 31A. The first trench portion 31A is formed by deep etching of the semiconductor substrate 21. In the deep etching, isotropic etching of Si using F radicals and anisotropic etching are alternately repeated. A protective film 801 can be formed on the inner surface 311 of the first trench portion 31A by deep etching. This protective film 801 is formed, for example, by conformal CVD using a CF-based gas.

[0054] As shown in FIGS. 7 and 8, the manufacturing method for the semiconductor device 10 includes forming the second trench portion 32A. The second trench portion 32A is formed by, for example, isotropic etching. The second trench portion 32A is formed below the first trench portion 31A by performing isotropic etching of Si using, for example, F radicals on the portion of the semiconductor substrate 21 exposed from the first trench portion 31A. By the isotropic etching, the semiconductor substrate 21 is etched from the lower end of the first trench portion 31A in the Z-axis direction, as well as in the X-axis and Y-axis directions. This forms the second trench portion 32A having a second width W12 larger than the first width W11 of the first trench portion 31A.

[0055] As shown in FIG. 9, the method for manufacturing the semiconductor device 10 includes forming an oxide film 802 on the inner surface 311 of the first trench portion 31A and the inner surface 321 of the second trench portion 32A. First, the protective film 801 (see FIG. 8) on the inner surface 311 of the first trench portion 31A is removed. Next, an oxide film 802 is formed on the inner surface 311 of the first trench portion 31A and the inner surface 321 of the second trench portion 32A. The oxide film 802 is formed by, for example, thermal oxidation of Si.

[0056] As shown in Fig. 10, the method for manufacturing the semiconductor device 10 includes forming an oxide film 803. This oxide film 803 is obtained by depositing a silicon oxide film on the oxide film 802 shown in Fig. 9. The silicon oxide film can be formed by a plasma CVD method using TEOS (tetra ethoxy silane) as a raw material, for example. The silicon oxide film may be a low pressure (LP)-TEOS oxide film.

[0057] 11, the method for manufacturing the semiconductor device 10 includes forming an opening 804 in the oxide film 803, exposing the semiconductor substrate 21. The opening 804 is formed by removing, by etching, a portion of the oxide film 803 covering the inner surface 321 of the second trench portion 32A. The opening 804 is formed by isotropically etching the portion of the oxide film 803 covering the inner surface 321 of the second trench portion 32A that covers the bottom surface 324 of the second trench portion 32A.

[0058] 12, the method for manufacturing the semiconductor device 10 includes forming a plurality of first trenches 31B-31D and a plurality of second trenches 32B-32D. The plurality of first trenches 31B-31D can be formed in the same manner as the first trench 31A. The plurality of second trenches 32B-32D can be formed in the same manner as the second trench 32A. That is, the first trenches 31B-31D and the second trenches 32B-32D are formed by alternately repeating the formation of the first trench 31A and the formation of the second trench 32A described above.

[0059] In this way, the trench 30 is formed. 13, the method for manufacturing the semiconductor device 10 includes removing the oxide film 803. The oxide film 803 can be removed by, for example, HF (hydrofluoric acid).

[0060] 14, the method for manufacturing the semiconductor device 10 includes forming an insulating layer 40 on the inner surface 301 of the trench 30. The insulating layer 40 may be made of a material containing Si. For example, the insulating layer 40 may be an oxide film containing Si. The insulating layer 40 may be formed by, for example, thermal oxidation of Si.

[0061] 15 and 16, the method for manufacturing the semiconductor device 10 includes forming a conductive layer 805. The conductive layer 805 is made of polysilicon. In one example, the conductive layer 805 may include a first polysilicon layer 806 and a second polysilicon layer 807. In FIG. 16, a dashed line is partially shown to distinguish the first polysilicon layer 806 from the second polysilicon layer 807.

[0062] As shown in FIG. 15 , a first polysilicon layer 806 is formed on the inner surface 401 of the insulating layer 40. The first polysilicon layer 806 may be non-doped polysilicon with no impurities added. The first polysilicon layer 806 may be formed by a CVD method. The first polysilicon layer 806 is formed so as to cover the upper surface 221 of the surface insulating layer 22. Next, a second polysilicon layer 807 is formed. The second polysilicon layer 807 may be doped polysilicon with impurities added. The second polysilicon layer 807 may be formed by a CVD method. The second polysilicon layer 807 is formed so as to fill the inside of the first trench portion 31. This forms a conductive layer 805. The conductive layer 805 is formed so as to cover the upper surface 221 of the surface insulating layer 22.

[0063] 17, the manufacturing method of the semiconductor device 10 includes forming the electrode portion 50. The electrode portion 50 is formed by removing a portion 808 on the upper surface 221 of the surface insulating layer 22 of the conductive layer 805 shown in FIG. 16. The portion 808 on the upper surface 221 of the surface insulating layer 22 is removed by, for example, a CMP (Chemical Mechanical Polishing) method.

[0064] (Comparative Example) Fig. 18 is a schematic plan view showing a portion of a semiconductor device 10X of a comparative example. Fig. 19 corresponds to the schematic plan view of the semiconductor device 10X shown in Fig. 2. Fig. 19 is a schematic cross-sectional view of the semiconductor device 10X of Fig. 18. Fig. 19 corresponds to the schematic cross-sectional view of the semiconductor device 10X shown in Fig. 3. In the semiconductor device 10X of the comparative example shown in Figs. 18 and 19, the same names and symbols are used for components corresponding to those of the semiconductor device 10X shown in Figs. 1 to 4.

[0065] The semiconductor device 10X of the comparative example includes multiple trenches 30X. The multiple trenches 30X are spaced apart in the X-axis direction. Each trench 30X extends in the Y-axis direction. Each trench 30X has a width W1X in the X-axis direction. The trench 30X has a substantially constant width W1X from the opening end of the trench 30X to the bottom of the trench 30X.

[0066] The electrode portion 50X disposed in the trench 30X faces the inner surface 301X of the trench 30X, i.e., the wall portion 213X of the semiconductor substrate 21X, with the insulating layer 40X sandwiched therebetween. The electrode portion 50X faces the wall portion 213X of the semiconductor substrate 21X with the insulating layer 40X sandwiched therebetween, thereby forming the capacitor 13X of the comparative example.

[0067] <Operation of the embodiment> As shown in FIGS. 3 and 4 , the semiconductor device 10 includes a semiconductor substrate 21, a trench 30, an insulating layer 40, and an electrode portion 50. The semiconductor substrate 21 includes a first substrate surface 211 and a second substrate surface 212 opposite the first substrate surface 211. The trench 30 is recessed from the first substrate surface 211 toward the second substrate surface 212 and has a width W1A in a planar view. The insulating layer 40 is disposed on an inner surface 301 of the trench 30. The electrode portion 50 is disposed within the trench 30 and surrounded by the insulating layer 40. The electrode portion 50 is conductive. The trench 30 includes a first trench portion 31 and a second trench portion 32. The first trench portion 31 has a first width W11 in the width direction of the trench 30. The second trench portion 32 is disposed at a different position in the Z-axis direction from the first trench portion 31. The second trench portion 32 has a second width W12 in the width direction of the trench 30 that is larger than the first width W11.

[0068] The electrode portion 50 disposed in the trench 30 faces the inner surface 301 of the trench 30, i.e., the wall portion 213 of the semiconductor substrate 21, with the insulating layer 40 sandwiched between them. The wall portion 213 of the semiconductor substrate 21 and the electrode portion 50 facing each other with the insulating layer 40 sandwiched between them form a capacitor 13.

[0069] The trench 30 includes a first trench portion 31 and a second trench portion 32 having a second width W12 that is larger than the first width W11 of the first trench portion 31. The inner surface 301 of the trench 30 is wider than the inner surface 301X of the trench 30X of the comparative example. Therefore, the capacitance of the capacitor 13 formed by the insulating layer 40 and the electrode portion 50 disposed in the trench 30 can be increased.

[0070] <Effects of the embodiment> As described above, the semiconductor device 10 of this embodiment provides the following advantages. (1) The semiconductor device 10 includes a semiconductor substrate 21, a trench 30, an insulating layer 40, and an electrode portion 50. The semiconductor substrate 21 includes a first substrate surface 211 and a second substrate surface 212 opposite the first substrate surface 211. The trench 30 is recessed from the first substrate surface 211 toward the second substrate surface 212 and has a width W1A in a planar view. The insulating layer 40 is disposed on an inner surface 301 of the trench 30. The electrode portion 50 is provided within the trench 30 and surrounded by the insulating layer 40. The electrode portion 50 is conductive. The trench 30 includes a first trench portion 31 and a second trench portion 32. The first trench portion 31 has a first width W11 in the width direction of the trench 30. The second trench portion is disposed at a different position in the Z-axis direction from the first trench portion 31. The second trench portion 32 has a second width W12 in the width direction of the trench 30 that is larger than the first width W11.

[0071] The electrode portion 50 disposed in the trench 30 faces the inner surface 301 of the trench 30, i.e., the wall portion 213 of the semiconductor substrate 21, with the insulating layer 40 sandwiched between them. The wall portion 213 of the semiconductor substrate 21 and the electrode portion 50 facing each other with the insulating layer 40 sandwiched between them form a capacitor 13. The capacitance of this capacitor 13 can be increased.

[0072] (2) The second trench portion 32 has a second width W12 that is larger than the first width W11 of the first trench portion 31. Because the second width W12 of the second trench portion 32 is larger than the first width W11 of the first trench portion 31, the area of ​​the inner surface 301 of the trench 30 is larger. Therefore, the area of ​​the inner surface 301 of the trench 30, i.e., the capacitance of the capacitor 13, can be increased in accordance with the second width W12 of the second trench portion 32.

[0073] (3) The trench 30 includes a plurality of first trench portions 31 and a plurality of second trench portions 32. The plurality of first trench portions 31 and the plurality of second trench portions 32 are arranged alternately in the thickness direction of the semiconductor substrate 21. Therefore, the area of ​​the inner surface 301 of the trench 30, i.e., the capacitance of the capacitor 13, can be increased according to the number of second trench portions 32.

[0074] <Example of change> The above embodiment can be modified, for example, as follows: The above embodiment and each of the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, parts common to the above embodiment will be assigned the same reference numerals as in the above embodiment, and their description will be omitted.

[0075] 20 is a schematic plan view showing a modified semiconductor device A10. This semiconductor device A10 includes two first trenches 30AA, 30AB and two second trenches 30BA, 30BB. When viewed from the Z-axis direction, the first trenches 30AA, 30AB extend in a first direction. The first direction may be the Y-axis direction, for example. When viewed from the Z-axis direction, the second trenches 30BA, 30BB extend in a second direction intersecting the first direction. The second direction may be a direction perpendicular to the first direction. The second direction may be the Y-axis direction.

[0076] The first trenches 30AA, 30AB and the second trenches 30BA, 30BB each include four first trench portions 31 and four second trench portions 32. Note that the first trenches 30AA, 30AB and the second trenches 30BA, 30BB may each include at least one first trench portion 31 and at least one second trench portion 32.

[0077] In the semiconductor device A10 shown in FIG. 20, the first trenches 30AA, 30AB and the second trenches 30BA, 30BB are connected to each other. The first trenches 30AA and 30AB include first ends 61A and 61B in the Y-axis direction and second ends 62A and 62B opposite the first ends 61A and 61B. The second trenches 30BA and 30BB include first ends 63A and 63B in the X-axis direction and second ends 64A and 64B opposite the first ends 63A and 63B. The first end 61A of the first trench 30AA is connected to the first end 63A of the second trench 30BA, and the second end 62A of the first trench 30AA is connected to the first end 63B of the second trench 30BB. The first end 61B of the first trench 30AB is connected to the second end 64A of the second trench 30BA, and the second end 62B of the first trench 30AB is connected to the second end 64B of the second trench 30BB. As a result, the first trenches 30AA, 30AB and the second trenches 30BA, 30BB form a rectangular frame shape when viewed from the Z-axis direction.

[0078] The first trenches 30AA, 30AB and the second trenches 30BA, 30BB may be spaced apart from each other. For example, both of the two second trenches 30BA, 30BB may be spaced apart from the first trenches 30AA, 30AB. Alternatively, the second trench 30BB may be spaced apart from the first trenches 30AA, 30AB, and the second trench 30BA may be connected to the first trenches 30AA, 30AB.

[0079] 21 is a schematic plan view showing a modified semiconductor device A11, which includes three first trenches 30AA, 30AB, and 30AC and two second trenches 30BA and 30BB.

[0080] The first trenches 30AA, 30AB, 30AC and the second trenches 30BA, 30BB each include four first trench portions 31 and four second trench portions 32. Note that the first trenches 30AA, 30AB, 30AC and the second trenches 30BA, 30BB may each include at least one first trench portion 31 and at least one second trench portion 32.

[0081] When viewed from the Z-axis direction, the first trenches 30AA, 30AB, and 30AC extend in the Y-axis direction. The first trenches 30AA, 30AB, and 30AC include first ends 61A, 61B, and 61C in the Y-axis direction and second ends 62A, 62B, and 62C opposite the first ends 61A, 61B, and 61C. The second ends 62A and 62B of the first trenches 30AA and 30AB are connected to the second trench 30BA. The first ends 61B and 61C of the first trenches 30AB and 30AB are connected to the second trench 30BB.

[0082] 22 is a schematic plan view showing a semiconductor device A12 of a modified example. The semiconductor device A12 includes a plurality of trenches 30. The plurality of trenches 30 are arranged spaced apart in the X-axis direction and spaced apart in the Y-axis direction. In one example, each trench 30 extends in the Y-axis direction in plan view.

[0083] The multiple trenches 30 are arranged at a first interval in the Y-axis direction. The first interval may be represented by a distance L42 between two second trench portions 32 adjacent to each other in the Y-axis direction. The first interval may be represented by a distance L41 between two first trench portions 31 adjacent to each other in the Y-axis direction.

[0084] The multiple trenches 30 are arranged at second intervals in the X-axis direction. The second intervals may be represented by the distance L32 between two second trench portions 32 adjacent to each other in the X-axis direction. The second intervals may be represented by the distance L31 between two first trench portions 31 adjacent to each other in the X-axis direction.

[0085] Each trench 30 has a length L1A in the Y-axis direction. The first trench portion 31 has a length L11 in the Y-axis direction. The second trench portion 32 has a length L12 in the Y-axis direction. In one example, the length L1A of the trench 30 in the Y-axis direction may be represented by the length L12 of the second trench portion 32 in the Y-axis direction. A distance L42 represented as a first interval between two trenches 30 adjacent to each other in the Y-axis direction is smaller than the length L12 of the second trench portion 32.

[0086] Each trench 30 includes four first trench portions 31 and four second trench portions 32. Note that each trench 30 may include at least one first trench portion 31 and at least one second trench portion 32.

[0087] Fig. 23 is a schematic plan view showing a semiconductor device A13 of a modified example, and Fig. 24 is a schematic cross-sectional view of the semiconductor device A13 of Fig. 23. The semiconductor device A13 includes a trench 70 provided in a semiconductor substrate 21.

[0088] The trench 70 includes a first trench portion 71 and a second trench portion 72. The first trench portion 71 includes four first trench portions 71 and four second trench portions 72. The four first trench portions 71 and the four second trench portions 72 are alternately arranged in the Z-axis direction. The four first trench portions 71 and the four second trench portions 72 are connected in the Z-axis direction. The number of first trench portions 71 may be changed to any number greater than or equal to one, as appropriate. The number of second trench portions 72 may be changed to any number greater than or equal to one, as appropriate.

[0089] The first trench portions 71 that open to the first substrate surface 211 of the semiconductor substrate 21 can be called surface trench portions. In the Z-axis direction, the first trench portions 71 between the second trench portions 72 can be called intermediate trench portions.

[0090] The first trench portion 71 extends in the Z-axis direction and includes three holes 73 arranged in the width direction, which is the X-axis direction here. The number of holes 73 may be two, or four or more. 23, the multiple holes 73 are spaced apart in the X-axis direction. The multiple holes 73 may be arranged at equal intervals. In one example, the multiple holes 73 are arranged with a distance L51 between two adjacent holes 73 in the X-axis direction. When viewed from the Z-axis direction, they extend in the Y-axis direction. The multiple holes 73 include a first hole 731 and a second hole 732 arranged at both ends of the arrangement in the X-axis direction.

[0091] The second trench portion 72 includes a first side surface 721 and a second side surface 722 that face each other in the X-axis direction. The second trench portion 72 includes an upper surface 723 closer to the first substrate surface 211 of the semiconductor substrate 21, and a bottom surface 724 closer to the second substrate surface 212 of the semiconductor substrate 21. The upper surface 723 and the bottom surface 724 form a step surface between the second trench portion 72 and the first trench portion 71. The portions between the side surfaces 721, 722 and the upper surface 723 may be curved so as to be convex toward the outside of the second trench portion 72. The portions between the side surfaces 721, 722 and the bottom surface 724 may be curved so as to be convex toward the outside of the second trench portion 72.

[0092] It can be said that the first trench portion 71 (hole portion 73) closer to the first substrate surface 211 of the semiconductor substrate 21 than the second trench portion 72 opens to the upper surface 723 of the second trench portion 72. It can be said that the first trench portion 71 (hole portion 73) closer to the second substrate surface 212 of the semiconductor substrate 21 than the second trench portion 72 opens to the bottom surface of the second trench portion 72. Therefore, the second trench portion 72 spans the multiple hole portions 73. The second trench portion 72 and the multiple hole portions 73 are in communication with each other.

[0093] The first side surface 721 of the second trench portion 72 is located on the opposite side of the first hole portion 731 from the second hole portion 732. The second side surface 722 of the second trench portion 72 is located on the opposite side of the second hole portion 732 from the first hole portion 731. In other words, the first side surface 721 and the second side surface 722 of the second trench portion 72 are located at positions sandwiching the three holes 73 of the first trench portion 71 in the X-axis direction in plan view. The second width W22 of the second trench portion 72 is larger than the first width W21 of the first trench portion 71 including the three holes 73.

[0094] In a plan view, the distance L52 from the first hole 731 to the first side surface 721 of the second trench portion 72 may be equal to the distance L53 from the second hole 732 to the second side surface 722 of the second trench portion 72. In a plan view, the distance L51 between the holes 73 is less than twice the distance L52 from the first hole 731 to the first side surface 721 of the second trench portion 72. The distance L51 between the holes 73 may be equal to or greater than the distance L52 from the first hole 731 to the first side surface 721 of the second trench portion 72.

[0095] 25 is a schematic cross-sectional view showing a modified semiconductor device A14. In this semiconductor device A14, the first trench portions 31A-31D may be provided so that their first widths W11A-W11D are different from one another. In the semiconductor device A14, the first trench portions 31A-31D are provided so that their first widths W11A-W11D decrease from the first substrate surface 211 toward the second substrate surface 212 of the semiconductor substrate 21.

[0096] 26 is a schematic cross-sectional view showing a modified semiconductor device A15. In this semiconductor device A15, the second trench portions 32A-32D may be provided so that their second widths W12A-W12D are different from one another. In the semiconductor device A15, the second trench portions 32A-32D are provided so that their second widths W12A-W12D decrease from the first substrate surface 211 toward the second substrate surface 212 of the semiconductor substrate 21.

[0097] 27 is a schematic cross-sectional view showing a modified semiconductor device A16. In this semiconductor device A16, the second trench portions 32A-32D may be provided so that their second widths W12A-W12D are different from one another. In the semiconductor device A16, the second trench portions 32A-32D are provided so that their second widths W12A-W12D increase from the first substrate surface 211 toward the second substrate surface 212 of the semiconductor substrate 21.

[0098] FIG. 28 is a schematic cross-sectional view showing a semiconductor device A17 according to a modified example. In this semiconductor device A17, each of the first trench portions 31A to 31D includes a plurality of irregularities 312 on its inner surface 311. The plurality of irregularities 312 is arranged from the first substrate surface 211 to the second substrate surface 212 of the semiconductor substrate 21. The plurality of irregularities 312 extends along the XY plane. The plurality of irregularities 312 extends in stripes along the XY plane. It can be said that the plurality of irregularities 312 extends along the circumferential direction of the first trench portion 31. The first trench portions 31A to 31D may be formed by deep etching. The plurality of irregularities 312 may be formed by isotropic etching in the deep etching method.

[0099] The first width W11A of the first trench portion 31A may vary within the first trench portion 31A in the Z-axis direction. For example, the first trench portion 31A may be provided such that the first width W11A gradually decreases from the first substrate surface 211 to the second substrate surface 212 of the semiconductor substrate 21 in the Z-axis direction. The first trench portion 31A may be provided such that the first width W11A gradually increases from the first substrate surface 211 to the second substrate surface 212 of the semiconductor substrate 21 in the Z-axis direction. The first width W11A of the first trench portion 31A at the center in the Z-axis direction may be larger or smaller than the first width W11A at the upper and lower ends of the first trench portion 31A.

[0100] Similarly to the first trench portion 31A, the first trench portions 31B to 31D may also be provided so that the first widths W11B to W11D are different within each of the first trench portions 31B to 31D.

[0101] Furthermore, the shapes of some of the first trench portions 31A to 31D may be different. For example, the first trench portion 31A may be provided so that the first width W11A gradually decreases from the first substrate surface 211 to the second substrate surface 212, and the first trench portion 31B may be provided so that the first width W11A gradually increases from the first substrate surface 211 to the second substrate surface 212. Furthermore, the first trench portion 31A may be provided so that the first width W11A is constant from the first substrate surface 211 to the second substrate surface 212, and the first trench portion 31B may be provided so that the first width W11A gradually increases from the first substrate surface 211 to the second substrate surface 212.

[0102] The term "on" as used in this disclosure includes both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0103] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (for example, the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described in this disclosure being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0104] <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0105] [Appendix 1] a semiconductor substrate (21) including a first substrate surface (211) and a second substrate surface (212) opposite to the first substrate surface (211); a trench (30) recessed from the first substrate surface (211) toward the second substrate surface (212) and having a width when viewed in the thickness direction (Z) of the semiconductor substrate (21); an insulating layer (40) disposed on the inner surface of the trench (30); a conductive electrode portion (50) provided in the trench (30) and surrounded by the insulating layer (40); Including, The trench (30) is a first trench portion (31) having a first width (W11) in the width direction of the trench (30); a second trench portion (32) disposed at a position different from that of the first trench portion (31) in the thickness direction (Z) and having a second width (W12) in the width direction that is larger than the first width (W11); 10. A semiconductor device comprising:

[0106] [Appendix 2] The trench (30) has a step surface between the first trench portion (31) and the second trench portion (32). 2. The semiconductor device of claim 1.

[0107] [Appendix 3] The first trench portion (31) and the second trench portion (32) are provided in plurality, The plurality of first trench portions (31) and the plurality of second trench portions (32) are alternately arranged in the thickness direction (Z). 10. The semiconductor device according to claim 1 or 2.

[0108] [Appendix 4] The first trench portion (31) is a surface trench portion (31A) opening to the first substrate surface (211); an intermediate trench portion (31B to 31D) between two of the second trench portions (32) arranged in the thickness direction (Z); Including, The length of the surface trench portion (31A) in the thickness direction (Z) is equal to the length of the intermediate trench portions (31B to 31D). 4. The semiconductor device according to claim 3.

[0109] [Appendix 5] the first widths (W11B to W11D) of the intermediate trench portions (31B to 31D) are narrower than the first width (W11A) of the surface trench portion; 5. The semiconductor device according to claim 4.

[0110] [Appendix 6] The length of the second trench portion (32) in the thickness direction (Z) is greater than the length of the intermediate trench portion; 6. The semiconductor device according to claim 4 or 5.

[0111] [Appendix 7] the inner surface of the first trench portion (31) includes a plurality of projections and recesses extending from the first substrate surface (211) to the second substrate surface (212); The plurality of irregularities extend along the circumferential direction of the first trench portion (31). 7. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0112] [Appendix 8] The second trench portion (32) includes side surfaces (322) facing each other in the width direction, When viewed from the thickness direction (Z), the distance from the inner surface of the first trench portion (31) to the side surface (322) of the second trench portion (32) is equal to the depth of the second trench portion (32) in the thickness direction (Z). 8. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0113] [Appendix 9] The plurality of second trench portions (32) are provided such that the distances (W11A to W11D) between the side surfaces (322) are different from one another. 9. The semiconductor device according to claim 8.

[0114] [Appendix 10] The plurality of second trench portions (32) are provided such that distances (W11A to W11D) between the side surfaces (322) become smaller from the first substrate surface (211) toward the second substrate surface (212). 10. The semiconductor device according to claim 9.

[0115] [Appendix 11] The plurality of second trench portions (32) are provided such that distances (W11A to W11D) between the side surfaces (322) increase from the first substrate surface (211) toward the second substrate surface (212). 10. The semiconductor device according to claim 9.

[0116] [Appendix 12] The trench (30) extends in a length direction intersecting the width direction when viewed from the thickness direction (Z). 12. The semiconductor device according to claim 1.

[0117] [Appendix 13] The trenches (30) are arranged in a plurality at intervals in the width direction (X), a distance (L32) between two adjacent second trench portions (32) in the width direction (X) is smaller than the second width (W12); 13. The semiconductor device according to claim 1.

[0118] [Appendix 14] The trenches (30) are arranged in a length direction intersecting the width direction (X) when viewed from the thickness direction (Z). 14. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0119] [Appendix 15] The first trench portion (31) includes a plurality of holes (73) extending in the thickness direction (Z) and arranged in the width direction (X), The second trench portion (32) extends in the width direction (X) and straddles the plurality of hole portions (73), and the second trench portion (32) and the plurality of hole portions (73) are in communication with each other. 15. The semiconductor device according to any one of claims 1 to 14.

[0120] [Appendix 16] The plurality of holes (73) include a first hole (731) and a second hole (732) arranged at both ends in the width direction (X), The second trench portion (32) includes a first side surface (721) and a second side surface (722) facing each other in the width direction (X), the first side surface (721) of the second trench portion (32) is located on the opposite side of the first hole portion (731) from the second hole portion (732); The second side surface (722) of the second trench portion (32) is located on the opposite side of the second hole portion (732) from the first hole portion (731). 16. The semiconductor device according to claim 15.

[0121] [Appendix 17] a distance (L51) between the plurality of holes (73) is smaller than twice the distance (L52) from the first hole (731) to the first side surface (721); 17. The semiconductor device according to claim 16.

[0122] [Appendix 18] a cavity (35) disposed within the second trench portion (32) and surrounded by the electrode portion (50); 18. The semiconductor device according to any one of claims 1 to 17.

[0123] [Appendix 19] The trench (30) is provided in plurality, The plurality of trenches include, when viewed from the thickness direction (Z), first trenches (30AA, 30AB) extending in a first direction and second trenches (30BA, 30BB) extending in a second direction intersecting the first direction. 19. The semiconductor device according to any one of claims 1 to 18.

[0124] [Appendix 20] The first trenches (30AA, 30AB) and the second trenches (30BA, 30BB) are connected to each other. 20. The semiconductor device according to claim 19.

[0125] [Appendix 21] the first trench and the second trench are spaced apart from each other; 20. The semiconductor device according to claim 19.

[0126] [Appendix 22] A semiconductor substrate (21) including a first substrate surface (211) and a second substrate surface (212) opposite to the first substrate surface (211) is etched to form a first trench portion (31) having a first width (W11) as viewed in a thickness direction (Z) of the semiconductor substrate (21); forming a second trench portion (32) having a second width (W12) larger than the first width (W11) of the first trench portion (31) when viewed in the thickness direction (Z) by isotropically etching the semiconductor substrate (21) through the first trench portion (31); forming an insulating layer (40) on the inner surfaces of the first trench portion (31) and the second trench portion (32); forming conductive electrode portions (50) in the first trench portion (31) and the second trench portion (32) and surrounded by the corresponding insulating layer (40); A method for manufacturing a semiconductor device, comprising:

[0127] [Appendix 23] a first etching step of forming the first trench portion (31) by deep etching the semiconductor substrate (21); a second etching step of forming the second trench portion (32) by isotropic etching the semiconductor substrate (21); 23. A method for manufacturing a semiconductor device according to claim 22, comprising:

[0128] [Appendix 24] The first etching step and the second etching step are alternately repeated to form a trench including a plurality of the first trench portions (31) and a plurality of the second trench portions (32). 24. A method for manufacturing a semiconductor device according to claim 23.

[0129] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0130] 10, A10 to A17 Semiconductor device 11,12 Device Area 13 Capacitor 21 Semiconductor substrate 211 First board surface 212 Second board surface 22 Surface insulating layer 23 First insulating layer 24 Second insulating layer 25 Conductive part 30 Trench 30AA, 30AB, 30AC First Trench 30BA, 30BB Second trench 31, 31A to 31D First trench section 32, 32A to 32D Second trench section 35 Cavity 40 insulating layer 41 First insulating layer 42 Second insulating layer 42 Insulating layer 43 Protruding part 50 Electrode section 51 1st electrode part 52 2nd electrode part 53 Connection 70 Trench 71 First Trench Section 72 Second Trench Section 73 Hole 213 Wall section 221 Top surface 223 Aperture 251 Surface 301 Inside 311 Inside 312 Unevenness 321 Inside 322 Side 323 Top surface 324 bottom 401 Inside 721 Side 721 1st side 722 Side 722 Second side 723 Top surface 724 bottom 731 1st hole 732 2nd hole D11A~D11D First length D12A~D12D Second length L11, L12, L1A length L21A~L21D distance L31,L32 distance L41,L42 distance L51~L53 distance T11 Thickness W1A width W11, W11A~W11D First width W12, W12A~W12D Second width W21 1st width W22 2nd width

Claims

1. a semiconductor substrate including a first substrate surface and a second substrate surface opposite the first substrate surface; a trench recessed from the first substrate surface toward the second substrate surface and having a width when viewed in a thickness direction of the semiconductor substrate; an insulating layer disposed on the inner surface of the trench; a conductive electrode portion provided in the trench and surrounded by the insulating layer; Including, The trench is a first trench portion having a first width in a width direction of the trench; a second trench portion disposed at a position different from that of the first trench portion in the thickness direction and having a second width in the width direction that is larger than the first width; 10. A semiconductor device comprising:

2. the trench has a step surface between the first trench portion and the second trench portion; The semiconductor device of claim 1.

3. a plurality of the first trench portions and a plurality of the second trench portions are provided; the plurality of first trench portions and the plurality of second trench portions are alternately arranged in the thickness direction; The semiconductor device according to claim 1 .

4. The first trench portion is a surface trench portion opening to the first substrate surface; an intermediate trench portion between two of the second trench portions arranged in the thickness direction; Including, The length of the surface trench portion in the thickness direction is equal to the length of the intermediate trench portion. The semiconductor device according to claim 3 .

5. the first width of the intermediate trench portion is narrower than the first width of the surface trench portion; The semiconductor device according to claim 4 .

6. The length of the second trench portion in the thickness direction is greater than the length of the intermediate trench portion. The semiconductor device according to claim 4 .

7. an inner surface of the first trench portion includes a plurality of projections and recesses extending from the first substrate surface toward the second substrate surface; The plurality of projections and recesses extend along the circumferential direction of the first trench portion. The semiconductor device according to claim 1 .

8. the second trench portion includes side surfaces opposing each other in the width direction, When viewed from the thickness direction, a distance from an inner surface of the first trench portion to the side surface of the second trench portion is equal to a depth of the second trench portion in the thickness direction. The semiconductor device according to claim 1 .

9. The plurality of second trench portions are provided such that distances between the side surfaces are different from one another. The semiconductor device according to claim 8 .

10. the plurality of second trench portions are provided such that the distance between the side surfaces decreases from the first substrate surface toward the second substrate surface; The semiconductor device according to claim 9 .

11. the plurality of second trench portions are provided such that the distance between the side surfaces increases from the first substrate surface toward the second substrate surface; The semiconductor device according to claim 9 .

12. The trench extends in a length direction intersecting with the width direction when viewed from the thickness direction. The semiconductor device according to claim 1 .

13. The trenches are arranged in a plurality at intervals in the width direction, a distance between two of the second trench portions adjacent to each other in the width direction is smaller than the second width; The semiconductor device according to claim 1 .

14. The trenches are arranged in a length direction intersecting the width direction when viewed from the thickness direction. The semiconductor device according to claim 1 .

15. the first trench portion includes a plurality of holes extending in the thickness direction and arranged in the width direction, the second trench portion extends in the width direction and straddles the plurality of hole portions, and the second trench portion and the plurality of hole portions are in communication with each other. The semiconductor device according to claim 1 .

16. the plurality of holes include a first hole and a second hole arranged at both ends in the width direction, the second trench portion includes a first side surface and a second side surface facing each other in the width direction, the first side surface of the second trench portion is located on an opposite side of the first hole portion from the second hole portion, the second side surface of the second trench portion is located on the opposite side of the second hole portion from the first hole portion; The semiconductor device according to claim 15.

17. The distance between the plurality of holes is less than twice the distance from the first hole to the first side surface. The semiconductor device according to claim 16.

18. a cavity disposed in the second trench portion and surrounded by the electrode portion; The semiconductor device according to claim 1 .

19. A plurality of the trenches are provided, The plurality of trenches include, when viewed from the thickness direction, a first trench extending in a first direction and a second trench extending in a second direction intersecting the first direction. The semiconductor device according to claim 1 .

20. the first trench and the second trench are connected to each other; 20. The semiconductor device according to claim 19.

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