Wiring board and method for manufacturing wiring board

Abstract

To provide a wiring board capable of improving connection reliability.SOLUTION: The interconnect substrate 10 includes the insulating layer 42 that covers the interconnect layer 41, the interconnect layer 43A that is stacked on the upper surface of the insulating layer 42 and is electrically connected to the interconnect layer 41, and the insulating layer 444648 that is stacked on the upper surface of the insulating layer 42. The interconnect substrate 10 includes the cavity 43A, which is formed in the insulating layer 444648 to expose the upper surface and the side surface of the interconnect layer 40X, and the surface-processed layer 80, which covers the upper surface and the side surface of the interconnect layer 40X exposed from the cavity 43A. The interconnect substrate 10 includes the electronic part 60 disposed in the cavity 40X and mounted on the surface-processed layer 80, and the insulating layer 49 that fills the cavity 40X and covers the electronic part 60. The side surface of the interconnection layer 43A is formed as the first roughened surface R1. The upper surface of the interconnection layer 43A is formed as a second roughened face R1 having a roughness larger than that of the first roughened face R2.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a wiring board and a method for manufacturing a wiring board. [Background technology]

[0002] Conventionally, wiring boards with built-in electronic components have been known (see, for example, Patent Document 1). One proposed wiring board of this type has electronic components mounted on conductive pads exposed at the bottom of cavities formed in multiple insulating layers, and a filled insulating layer formed to fill the cavities and cover the electronic components. Such wiring boards are manufactured, for example, by the following manufacturing method. First, conductive pads are formed, and a protective material is formed to cover the conductive pads. Then, multiple insulating layers are laminated to cover the conductive pads and the protective material. Next, predetermined regions of the multiple insulating layers are removed to form cavities that expose the protective material, and the protective material is then removed to expose the conductive pads. Next, electronic components are mounted on the conductive pads, and a filled insulating layer is formed to fill the cavities and cover the electronic components. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-80677 Summary of the Invention [Problem to be solved by the invention]

[0004] In the above wiring board, it is desired to improve the reliability of the connection between the conductive pads exposed at the bottom of the cavity and the electronic components. [Means for solving the problem]

[0005] According to one aspect of the present invention, a semiconductor device includes a first wiring layer, a first insulating layer covering the first wiring layer, a second wiring layer stacked on an upper surface of the first insulating layer and electrically connected to the first wiring layer, N insulating layers (N is a natural number greater than or equal to 1) including the second insulating layer stacked on an upper surface of the first insulating layer, a cavity formed in the N insulating layers and formed to expose an upper surface and a side surface of the second wiring layer, a surface treatment layer covering an upper surface and a side surface of the second wiring layer exposed from the cavity, an electronic component disposed in the cavity and mounted on the surface treatment layer, a filled insulating layer filling the cavity and covering the electronic component, and a third wiring layer stacked on an upper surface of the filled insulating layer and electrically connected to the electronic component, wherein the side surface of the second wiring layer is formed as a first roughened surface, and the upper surface of the second wiring layer is formed as a second roughened surface having a surface roughness greater than that of the first roughened surface. [Effects of the Invention]

[0006] According to one aspect of the present invention, an effect is achieved in that connection reliability can be improved. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic cross-sectional view showing a wiring board according to the first embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view showing an enlarged portion of the wiring board of the first embodiment. [Figure 3] 3A to 3C are schematic cross-sectional views illustrating a method for manufacturing the wiring board of the first embodiment. [Figure 4] 4A to 4C are schematic cross-sectional views illustrating a method for manufacturing the wiring board of the first embodiment. [Figure 5] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing the wiring board of the first embodiment. [Figure 6] 6A to 6C are schematic cross-sectional views illustrating a method for manufacturing the wiring board of the first embodiment. [Figure 7] 7A to 7C are schematic cross-sectional views illustrating a method for manufacturing the wiring board of the first embodiment. [Figure 8]8A to 8C are schematic cross-sectional views illustrating a method for manufacturing the wiring board of the first embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a method for manufacturing the wiring board of the first embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a method for manufacturing the wiring board of the first embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a method for manufacturing the wiring board of the first embodiment. [Figure 12] 12A to 12C are schematic cross-sectional views illustrating a method for manufacturing the wiring board of the first embodiment. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a method for manufacturing the wiring board of the first embodiment. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a method for manufacturing the wiring board of the first embodiment. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a method for manufacturing the wiring board of the first embodiment. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a method for manufacturing the wiring board of the first embodiment. [Figure 17] FIG. 17 is a schematic cross-sectional view showing an enlarged portion of the wiring board according to the second embodiment. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a method for manufacturing the wiring board of the second embodiment. [Figure 19] FIG. 19 is a schematic cross-sectional view showing a method for manufacturing the wiring board of the second embodiment. [Figure 20] FIG. 20 is a schematic cross-sectional view showing a method for manufacturing the wiring board of the second embodiment. [Figure 21] FIG. 21 is a schematic cross-sectional view showing a method for manufacturing the wiring board of the second embodiment. [Figure 22] FIG. 22 is a schematic cross-sectional view showing a method for manufacturing the wiring board of the second embodiment. [Figure 23] FIG. 23 is a schematic cross-sectional view showing a method for manufacturing the wiring board of the second embodiment. [Figure 24] FIG. 24 is a schematic cross-sectional view showing a method for manufacturing the wiring board of the second embodiment. [Figure 25]FIG. 25 is a schematic cross-sectional view showing a method for manufacturing the wiring board of the second embodiment. [Figure 26] FIG. 26 is a schematic cross-sectional view showing a method for manufacturing the wiring board of the second embodiment. [Figure 27] FIG. 27 is a schematic cross-sectional view showing a method for manufacturing the wiring board of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, each embodiment will be described with reference to the accompanying drawings. For convenience, the accompanying drawings may show characteristic portions enlarged to make the features easier to understand, and the dimensional ratios of each component may differ from one drawing to another. Furthermore, in cross-sectional views, the hatching of some components is shown with a matte finish, and the hatching of some components is omitted, to make the cross-sectional structure of each component easier to understand.

[0009] (First embodiment) The first embodiment will be described below with reference to Figures 1 to 16. In this specification, "plan view" refers to viewing an object from the vertical direction (up and down in the figure) as in Figure 1, and "planar shape" refers to the shape of an object viewed from the vertical direction as in Figure 1. In addition, the "up and down direction" and "left and right direction" in this specification refer to directions in which the direction in which the symbols indicating each component in each figure can be correctly read is taken as the normal position.

[0010] (Overall configuration of wiring board 10) 1, the wiring board 10 includes a core substrate 20, a wiring structure 30, a wiring structure 40, a cavity 40X formed in the wiring structure 40, and one or more electronic components 60 (one in this embodiment) disposed in the cavity 40X. The wiring board 10 includes an underfill resin 65, a solder resist layer 70, and external connection terminals 90. The wiring board 10 is a wiring board incorporating the electronic components 60. The wiring structure 30 and the solder resist layer 70 are disposed on one side of the core substrate 20, and the wiring structure 40 and the external connection terminals 90 are disposed on the other side of the core substrate 20.

[0011] 1 will be referred to as the lower side or one side, and the external connection terminals 90 side will be referred to as the upper side or the other side. Also, in this embodiment, for convenience, the surface of each portion facing the solder resist layer 70 will be referred to as the one side or lower side, and the surface facing the external connection terminals 90 will be referred to as the other side or upper side. However, the wiring board 10 can be used upside down or positioned at any angle.

[0012] For example, a so-called glass epoxy substrate, in which glass cloth is impregnated with a thermosetting insulating resin such as an epoxy resin, can be used as the core substrate 20. For example, a substrate, in which a woven or nonwoven fabric made of glass fiber, carbon fiber, aramid fiber, or the like is impregnated with a thermosetting insulating resin such as an epoxy resin, can also be used as the core substrate 20. Note that glass cloth and the like are omitted from the drawings.

[0013] The core substrate 20 has a plurality of through holes 20X formed therein, penetrating the core substrate 20 in the thickness direction. The planar shape of the through holes 20X can be any shape and any size. For example, the planar shape of the through holes 20X can be a circle with a diameter of about 50 μm to 200 μm.

[0014] A through electrode 21 is formed inside the through hole 20X, penetrating the core substrate 20 in the thickness direction. The through electrode 21 is formed, for example, to fill the through hole 20X. The material of the through electrode 21 can be, for example, copper (Cu) or a copper alloy.

[0015] (Configuration of wiring structure 30) The wiring structure 30 is laminated on the lower surface of the core substrate 20. The wiring structure 30 of this embodiment has a structure in which a wiring layer 31, an insulating layer 32, a wiring layer 33, an insulating layer 34, a wiring layer 35, an insulating layer 36, a wiring layer 37, an insulating layer 38, and a wiring layer 39 are laminated in this order on the lower surface of the core substrate 20.

[0016] The wiring layers 31, 33, 35, 37, and 39 may be made of, for example, copper or a copper alloy. The thickness of each of the wiring layers 31, 33, 35, 37, and 39 may be, for example, approximately 8 μm to 35 μm. The line / space (L / S) of the wiring layers 31, 33, 35, 37, and 39 may be, for example, approximately 10 μm / 10 μm to 50 μm / 50 μm. Here, the "line" in "line / space" refers to the wiring width, and the "space" refers to the spacing between adjacent wirings (wiring spacing). For example, if the line / space is described as 10 μm / 10 μm to 50 μm / 50 μm, this means that the wiring width is 10 μm to 50 μm, and the wiring spacing between adjacent wirings is 10 μm to 50 μm. Note that the wiring width and the wiring spacing do not necessarily have to be equal.

[0017] The insulating layers 32, 34, 36, and 38 are insulating layers whose main component is a non-photosensitive resin. The insulating layers 32, 34, 36, and 38 may be made mainly of a thermosetting non-photosensitive resin such as an epoxy resin, an imide resin, a phenol resin, or a cyanate resin. The thickness of each of the insulating layers 32, 34, 36, and 38 may be, for example, approximately 35 μm to 100 μm.

[0018] The wiring layer 31 is laminated on the lower surface of the core substrate 20. The wiring layer 31 is electrically connected to the through electrodes 21. The insulating layer 32 is formed on the lower surface of the core substrate 20 so as to cover the wiring layer 31. The wiring layer 33 is laminated on the lower surface of the insulating layer 32. The wiring layer 33 is electrically connected to the wiring layer 31 through via wiring that penetrates the insulating layer 32 in the thickness direction.

[0019] The insulating layer 34 is formed on the lower surface of the insulating layer 32 so as to cover the wiring layer 33. The wiring layer 35 is laminated on the lower surface of the insulating layer 34. The wiring layer 35 is electrically connected to the wiring layer 33 through via wiring that penetrates the insulating layer 34 in the thickness direction. The insulating layer 36 is formed on the lower surface of the insulating layer 34 so as to cover the wiring layer 35. The wiring layer 37 is laminated on the lower surface of the insulating layer 36. The wiring layer 37 is electrically connected to the wiring layer 35 through via wiring that penetrates the insulating layer 36 in the thickness direction. The insulating layer 38 is formed on the lower surface of the insulating layer 36 so as to cover the wiring layer 37. The wiring layer 39 is laminated on the lower surface of the insulating layer 38. The wiring layer 39 is electrically connected to the wiring layer 37 through via wiring that penetrates the insulating layer 38 in the thickness direction.

[0020] (Configuration of solder resist layer 70) The solder resist layer 70 is an outermost insulating layer provided on the outermost layer (here, the lowest layer) of the wiring board 10. The solder resist layer 70 is formed on the lower surface of the wiring structure 30, specifically on the lower surface of the insulating layer 38 formed on the lowest layer of the wiring structure 30, so as to cover the lowermost wiring layer 39. The solder resist layer 70 is an insulating layer whose main component is a photosensitive resin. The material of the solder resist layer 70 can be, for example, a photosensitive insulating resin whose main component is a phenolic resin or a polyimide resin. The solder resist layer 70 may contain a filler such as silica or alumina.

[0021] Openings 70X are formed in the solder resist layer 70 to expose portions of the lower surface of the lowermost wiring layer 39 as external connection pads P1. The external connection pads P1 are adapted to be connected to external connection terminals used when mounting the wiring board 10 on a mounting board such as a motherboard.

[0022] A surface treatment layer 71 is formed, if necessary, on the wiring layer 39 exposed through the opening 70X. Examples of the surface treatment layer 71 include an Au layer, a Ni layer / Au layer (a metal layer formed by laminating a Ni layer and an Au layer in this order), and a Ni layer / Pd layer / Au layer (a metal layer formed by laminating a Ni layer, a Pd layer, and an Au layer in this order). The Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or an Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy. The Au layer, Ni layer, and Pd layer may be, for example, a metal layer formed by electroless plating (electroless plated metal layer). Alternatively, the surface treatment layer 71 may be an OSP (organic solderability preservative) film formed by applying an anti-oxidation treatment such as an OSP treatment to the surface of the external connection pad P1. For example, an organic coating of an azole compound or an imidazole compound may be used as the OSP film. The wiring layer 39 exposed from the opening 70X (or, if the surface treatment layer 71 is formed on the wiring layer 39, the surface treatment layer 71) itself may be used as an external connection terminal.

[0023] The external connection pads P1 and the openings 70X may have any shape and size in plan view, and may have a circular shape with a diameter of, for example, about 200 μm to 300 μm in plan view.

[0024] (Configuration of wiring structure 40) The wiring structure 40 is laminated on the upper surface of the core substrate 20. The wiring structure 40 of this embodiment has a structure in which a wiring layer 41, an insulating layer 42, a wiring layer 43, an insulating layer 44, a wiring layer 45, an insulating layer 46, a wiring layer 47, an insulating layer 48, an insulating layer 49, a wiring layer 50, an insulating layer 51, and a wiring layer 52 are laminated in this order on the upper surface of the core substrate 20.

[0025] Copper or a copper alloy, for example, can be used as the material for the wiring layers 41, 43, 45, 47, 50, and 52. The thickness of each of the wiring layers 41, 43, 45, 47, 50, and 52 can be, for example, approximately 10 μm to 30 μm. The line / space of the wiring layers 41, 43, 45, 47, 50, and 52 can be, for example, approximately 10 μm / 10 μm to 50 μm / 50 μm.

[0026] The insulating layers 42, 44, 46, 48, 49, and 51 are insulating layers whose main component is, for example, a non-photosensitive resin. The insulating layers 42, 44, 46, 48, 49, and 51 can be made mainly of, for example, a thermosetting non-photosensitive resin such as an epoxy resin, an imide resin, a phenolic resin, or a cyanate resin. The insulating layer 51 may also be made mainly of a photosensitive resin, similar to the solder resist layer 70. In this case, the material of the insulating layer 51 can be, for example, a photosensitive insulating resin whose main component is a phenolic resin, a polyimide resin, or the like.

[0027] The wiring layer 41 is laminated on the upper surface of the core substrate 20. The wiring layer 41 is electrically connected to the wiring layer 31 via the through electrodes 21. The insulating layer 42 is formed on the upper surface of the core substrate 20 so as to cover the wiring layer 41. The thickness from the upper surface of the wiring layer 41 to the upper surface of the insulating layer 42 can be, for example, about 25 μm to 40 μm.

[0028] The wiring layer 43 is stacked on the upper surface of the insulating layer 42. The wiring layer 43 is electrically connected to the wiring layer 41 through via wiring that penetrates the insulating layer 42 in the thickness direction. The wiring layer 43 has a wiring layer 43A and a wiring layer 43B. The wiring layer 43A is provided at a position that overlaps with the cavity 40X in a planar view. The wiring layer 43B is provided at a position that does not overlap with the cavity 40X in a planar view.

[0029] The insulating layer 44 is formed on the upper surface of the insulating layer 42 so as to cover the wiring layer 43. The thickness from the upper surface of the wiring layer 43 to the upper surface of the insulating layer 44 can be, for example, about 30 μm to 60 μm.

[0030] The wiring layer 45 is laminated on the upper surface of the insulating layer 44. The wiring layer 45 is electrically connected to the wiring layer 43 through via wiring that penetrates the insulating layer 44 in the thickness direction. The wiring layer 45 is provided at a position that does not overlap with the cavity 40X in a plan view.

[0031] The insulating layer 46 is formed on the upper surface of the insulating layer 44 so as to cover the wiring layer 45. The thickness from the upper surface of the wiring layer 45 to the upper surface of the insulating layer 46 can be, for example, about 30 μm to 60 μm.

[0032] The wiring layer 47 is laminated on the upper surface of the insulating layer 46. The wiring layer 47 is electrically connected to the wiring layer 45 through via wiring that penetrates the insulating layer 46 in the thickness direction. The wiring layer 47 is provided at a position that does not overlap with the cavity 40X in a plan view.

[0033] The insulating layer 48 is formed on the upper surface of the insulating layer 46 so as to cover the wiring layer 47. The thickness from the upper surface of the wiring layer 47 to the upper surface of the insulating layer 48 can be, for example, about 25 μm to 40 μm.

[0034] The cavity 40X is formed in the insulating layers 44, 46, and 48. The cavity 40X is formed so as to be recessed from the top surface of the insulating layer 48 to a position halfway through the thickness of the insulating layer 44. The cavity 40X is formed so as to expose the top surface and side surfaces of the wiring layer 43A. More specifically, the cavity 40X is formed so as to expose the entire top surface of the wiring layer 43A and to expose a portion of the side surface of the wiring layer 43A. The cavity 40X is formed to correspond to the electronic component 60 to be built in. That is, the cavity 40X is formed at the mounting position of the electronic component 60.

[0035] As shown in FIG. 2, the cavity 40X of this embodiment is configured by a through hole 48X penetrating the insulating layer 48 in the thickness direction, a through hole 46X penetrating the insulating layer 46 in the thickness direction, and a recess 44X formed in the upper surface of the insulating layer 44, which are all connected to each other. For example, the inner wall surfaces of the through hole 48X, the through hole 46X, and the recess 44X are formed so as to be continuous with each other. The through hole 48X, the through hole 46X, and the recess 44X are formed, for example, coaxially with each other. That is, the central axes of the through hole 48X, the through hole 46X, and the recess 44X are aligned in plan view. The bottom surface of the recess 44X, i.e., the bottom surface of the cavity 40X, is located midway in the thickness direction of the insulating layer 44. The bottom surface of the cavity 40X is located below the upper surface of the wiring layer 43A. In other words, the upper part of the wiring layer 43A is formed so as to protrude above the bottom surface of the cavity 40X. The thickness from the upper surface of the insulating layer 42 to the bottom surface of the cavity 40X can be, for example, about 3 μm to 8 μm.

[0036] The cavity 40X is formed, for example, in a tapered shape in FIG. 2 such that the opening width narrows from the upper side (the upper surface side of the insulating layer 48) to the lower side (the core substrate 20 side). That is, the cavity 40X is formed such that the upper opening is wider than the lower opening. The space surrounded by the inner wall surface and the bottom surface of the cavity 40X, i.e., the internal space of the cavity 40X, serves as a housing space for housing the electronic component 60. Thus, in the wiring board 10 of this example, the three insulating layers 44, 46, and 48 stacked on the lowest insulating layer 42 of the wiring structure 40 serve as insulating layers for forming the cavity. Note that, in FIG. 2, the insulating layer 51, the wiring layer 52, and the external connection terminals 90 are not shown for the sake of simplicity.

[0037] The wiring layer 43A exposed from the cavity 40X has the electronic component 60 mounted thereon. The wiring layer 43A functions as an electronic component mounting pad for electrically connecting to the electronic component 60.

[0038] Here, the side surface of the wiring layer 43A is formed on the first roughened surface R1. The upper surface of the wiring layer 43A is formed on the second roughened surface R2, which has a surface roughness greater than that of the first roughened surface R1. In this way, the upper surface of the wiring layer 43A is formed on a roughened surface having a surface roughness greater than that of the side surface of the wiring layer 43A. Note that, for example, both the portion of the side surface of the wiring layer 43A covered by the insulating layer 44 and the portion exposed from the cavity 40X are formed on the first roughened surface R1. In other words, the side surface of the wiring layer 43A in the portion covered by the insulating layer 44 and the side surface of the wiring layer 43A in the portion exposed from the cavity 40X have approximately the same roughness. The surface roughness of the first roughened surface R1 can be, for example, approximately 80 nm to 130 nm in surface roughness Ra value. The surface roughness of the second roughened surface R2 can be, for example, approximately 250 nm to 450 nm in surface roughness Ra value. Here, the surface roughness Ra value is a type of numerical value that represents surface roughness, and is called the arithmetic mean roughness. Specifically, it is the arithmetic mean of the absolute values ​​of the height that changes within the measurement area, measured from the surface, which is the average line.

[0039] The top surface and side surface of the wiring layer 43B are formed on the first roughened surface R1. Thus, the top surface and side surface of the wiring layer 43B have the same degree of roughness. The top surface and side surface of the wiring layer 43B are formed on a roughened surface having a surface roughness smaller than that of the top surface of the wiring layer 43A, i.e., the second roughened surface R2.

[0040] A surface treatment layer 80 is formed on the surface of the wiring layer 43A exposed from the cavity 40X. The surface treatment layer 80 is formed to cover the entire upper surface of the wiring layer 43A and to cover the entire side surfaces of the wiring layer 43A exposed from the cavity 40X. The surface treatment layer 80 may be a metal layer such as an Au layer, a Ni layer / Au layer, or a Ni layer / Pd layer / Au layer, or an OSP film.

[0041] The surface treatment layer 80 of this embodiment has a structure in which a first metal layer 81 and a second metal layer 82 are stacked. The first metal layer 81 is formed so as to cover the entire surface of the wiring layer 43A exposed from the cavity 40X. The material of the first metal layer 81 is preferably, for example, a conductive material that has higher adhesion to the wiring layer 43B than the metal constituting the second metal layer 82. The first metal layer 81 of this embodiment is a Ni layer. The second metal layer 82 is formed so as to cover the entire upper surface of the first metal layer 81 and the entire side surface of the first metal layer 81. The second metal layer 82 of this embodiment is an Au layer. The thickness of the first metal layer 81 can be, for example, approximately 1 μm to 9 μm. The thickness of the second metal layer 82 can be, for example, approximately 10 nm to 90 nm.

[0042] The top surfaces and side surfaces of the wiring layers 41, 45, 47, 50, and 52 other than the wiring layer 43 are formed as roughened surfaces similar to the first roughened surface R1. However, in each drawing, for the sake of simplicity, the top surfaces and side surfaces of the wiring layers 41, 45, 47, 50, and 52 are illustrated as smooth surfaces.

[0043] (Configuration of electronic component 60) Here, the electronic component 60 has a main body 61, a first electrode 62 provided on the lower surface of the main body 61, and a second electrode 63 provided on the upper surface of the main body 61. The electronic component 60 of this embodiment has a plurality of first electrodes 62 provided on the lower surface of the main body 61 and a plurality of second electrodes 63 provided on the upper surface of the main body 61. The electronic component 60 is, for example, flip-chip mounted on the wiring layer 43A exposed from the cavity 40X. Specifically, the first electrode 62 of the electronic component 60 is electrically connected to a surface treatment layer 80 formed on the surface of the wiring layer 43A exposed from the cavity 40X. More specifically, the first electrode 62 is electrically connected to the surface treatment layer 80 via a bonding member 64. As a result, the electronic component 60 is electrically connected to the wiring layer 43A via the first electrode 62, the bonding member 64, and the surface treatment layer 80.

[0044] The electronic component 60 may be, for example, a semiconductor element, a quartz crystal oscillator, or a chip component. Examples of the chip component include a chip capacitor, a chip resistor, and a chip inductor. The electronic component 60 built into the wiring substrate 10 is not limited to one type, and multiple types of electronic components 60 may be built into the wiring substrate 10.

[0045] The main body 61 is formed, for example, in the shape of a rectangular parallelepiped. The thickness of the main body 61 can be set, for example, to about 50 μm to 100 μm. The main body 61 is formed, for example, from silicon (Si) or silicon carbide (SiC).

[0046] The first electrode 62 and the second electrode 63 may be made of a metal such as aluminum (Al) or copper (Cu), or an alloy containing at least one metal selected from these metals.

[0047] The multiple first electrodes 62 are provided so as to face the multiple wiring layers 43A, respectively. Each first electrode 62 is formed, for example, so as to protrude downward from the lower surface of the main body portion 61. The thickness of the first electrode 62 can be, for example, approximately 2 μm to 20 μm. Note that each first electrode 62 may be formed so as to be embedded in the main body portion 61.

[0048] Each second electrode 63 is formed, for example, so as to protrude upward from the upper surface of the main body 61. The upper surface of each second electrode 63 is provided, for example, on the same plane as the upper surface of the insulating layer 48. The thickness of each second electrode 63 can be, for example, approximately 2 μm to 20 μm. Note that each second electrode 63 may be formed so as to be embedded in the main body 61.

[0049] (Configuration of joining member 64) The bonding member 64 is bonded to, for example, the first electrode 62 and also to the surface treatment layer 80. The bonding member 64 electrically connects the first electrode 62 and the surface treatment layer 80. For example, a solder layer can be used as the bonding member 64. For example, tin (Sn)-silver (Ag)-based, Sn-Cu-based, or Sn-Ag-Cu-based lead (Pb)-free solder can be used as the material for the solder layer. The thickness of the bonding member 64 can be, for example, approximately 5 μm to 30 μm.

[0050] (Composition of underfill resin 65) An underfill resin 65 is formed between the electronic component 60 and the bottom surface of the cavity 40X. The underfill resin 65 is formed so as to fill the gap between the lower surface of the main body 61 of the electronic component 60 and the bottom surface of the cavity 40X. The underfill resin 65 is formed so as to seal the first electrode 62, the bonding member 64, and the surface treatment layer 80. The underfill resin 65 can be made of an insulating resin such as an epoxy resin, for example.

[0051] (Configuration of wiring structure 40) The insulating layer 49 is a filling insulating layer that fills the cavity 40X. The insulating layer 49 is formed to cover the upper surface of the insulating layer 48 and to fill the cavity 40X to cover the electronic component 60. The insulating layer 49 is formed to cover the underfill resin 65. For example, the insulating layer 49 is formed to cover the entire side surface of the underfill resin 65. For example, the insulating layer 49 is formed to cover the entire bottom surface of the cavity 40X exposed from the underfill resin 65. For example, the insulating layer 49 is formed to cover the entire inner wall surface of the cavity 40X exposed from the underfill resin 65. For example, the insulating layer 49 is formed to cover the entire electronic component 60 exposed from the underfill resin 65. For example, the insulating layer 49 is formed to cover the side and upper surface of the main body portion 61 exposed from the underfill resin 65. For example, the insulating layer 49 is formed to cover the side and upper surface of the second electrode 63.

[0052] The insulating layer 49 is formed, for example, so as to cover the entire upper surface of the insulating layer 48. A through hole VH1 is formed at a required location in the insulating layers 48, 49, penetrating the insulating layers 48, 49 in the thickness direction to expose a portion of the upper surface of the wiring layer 47. A through hole VH2 is formed at a required location in the insulating layer 49, penetrating the insulating layer 49 in the thickness direction to expose a portion of the upper surface of the second electrode 63. The through holes VH1, VH2 are formed, for example, in a tapered shape whose diameter (opening width) decreases from the upper side (the upper surface side of the insulating layer 49) to the lower side (the core substrate 20 side) in FIG. 2. The through holes VH1, VH2 are formed in an inverted truncated cone shape, with the opening diameter at the lower opening end being smaller than the opening diameter at the upper opening end. The thickness from the upper surface of the insulating layer 48 to the upper surface of the insulating layer 49 can be, for example, approximately 15 μm to 45 μm.

[0053] The wiring layer 50 is formed on the upper surface of the insulating layer 49. The wiring layer 50 has a wiring pattern electrically connected to the wiring layer 47 via via wiring filled in the through hole VH1, for example. The wiring layer 50 has a wiring pattern electrically connected to the second electrode 63 via via wiring filled in the through hole VH2, for example. The wiring layer 50 is formed integrally with the via wiring filled in the through hole VH1 or the through hole VH2, for example. The wiring layer 50 may be routed on the upper surface of the insulating layer 49 in a planar direction (specifically, a direction perpendicular to the stacking direction of the wiring substrate 10 in a cross-sectional view). Furthermore, the wiring layer 50 connected to the wiring layer 47 and the wiring layer 50 connected to the second electrode 63 may be electrically connected to each other by the wiring layer 50 routed in this manner.

[0054] 1, insulating layer 51 is formed on the upper surface of insulating layer 49 so as to cover wiring layer 50. Insulating layer 51 is the outermost insulating layer provided on the outermost layer (here, the uppermost layer) of wiring board 10. The thickness from the upper surface of wiring layer 50 to the upper surface of insulating layer 51 can be, for example, approximately 25 μm to 40 μm.

[0055] The wiring layer 52 is laminated on the upper surface of the insulating layer 51. The wiring layer 52 is electrically connected to the wiring layer 50 through via wiring that penetrates the insulating layer 51 in the thickness direction. The wiring layer 52 is, for example, the outermost layer (here, the uppermost layer) of the wiring board 10. The wiring layer 52 functions as, for example, an electronic component mounting pad for electrically connecting to an electronic component (not shown) such as a semiconductor element.

[0056] If necessary, a surface treatment layer may be formed on the surface (top and side surfaces, or only the top surface) of the wiring layer 52. As the surface treatment layer, a metal layer such as an Au layer, a Ni layer / Au layer, or a Ni layer / Pd layer / Au layer, or an OSP film can be used.

[0057] For example, external connection terminals 90 are provided on the upper surface of the wiring layer 52. For example, solder balls can be used as the external connection terminals 90. For example, Sn-Ag based, Sn-Cu based, or Sn-Ag-Cu based Pb-free solder can be used as the material for the solder balls.

[0058] (Method of manufacturing wiring board 10) Next, a method for manufacturing the wiring board 10 will be described. Here, a method for manufacturing the structure of the wiring board 10 shown in Fig. 2 will be described in detail. For ease of explanation, the parts that will ultimately become the components of the wiring board 10 will be described using the reference numerals of the final components.

[0059] 3, a structure is formed that includes a core substrate 20, a through electrode 21, and a wiring layer 41 formed on the upper surface of the core substrate 20. This structure can be manufactured by a known manufacturing method, and therefore a detailed description thereof will be omitted here.

[0060] Next, in the step shown in FIG. 4, an insulating layer 42 that covers the wiring layer 41 is formed on the upper surface of the core substrate 20. When a resin film is used as the insulating layer 42, for example, the resin film is laminated on the upper surface of the core substrate 20. Then, while pressing the resin film, it is heat-treated at a temperature equal to or higher than the curing temperature (for example, about 130°C to 200°C) to harden it, thereby forming the insulating layer 42. As the resin film, for example, a thermosetting resin film mainly composed of an epoxy resin can be used. When a liquid or paste insulating resin is used as the insulating layer 42, the liquid or paste insulating resin is applied to the upper surface of the core substrate 20 by a spin coating method or the like. Then, the applied insulating resin is heat-treated at a temperature equal to or higher than the curing temperature to harden it, thereby forming the insulating layer 42. As the liquid or paste insulating resin, for example, a thermosetting resin mainly composed of an epoxy resin can be used.

[0061] Next, through holes 42X are formed in predetermined locations of the insulating layer 42 so as to expose portions of the upper surface of the wiring layer 41. The through holes 42X can be formed by laser processing using, for example, a CO2 laser, a UV-YAG laser, or the like.

[0062] Next, in the case where the through holes 42X are formed by laser processing, a desmearing process is performed to remove resin smears adhering to the exposed surface of the wiring layer 41 exposed at the bottom of the through holes 42X. The desmearing process in this step may be, for example, a wet desmearing process using a potassium permanganate solution or the like.

[0063] 5, a seed layer 91 is formed to cover the entire upper surface of the insulating layer 42 and the entire inner surface of the through hole 42X. The seed layer 91 can be formed by, for example, sputtering or electroless plating. For example, when forming the seed layer 91 by sputtering, first, titanium (Ti) is deposited by sputtering on the upper surface of the insulating layer 42 and the inner surface of the through hole 42X to form a Ti layer so as to cover the upper surface of the insulating layer 42 and the inner surface of the through hole 42X. Then, copper is deposited by sputtering on the Ti layer to form a Cu layer. This allows the seed layer 91 to have a two-layer structure (Ti layer / Cu layer). When forming the seed layer 91 by electroless plating, for example, the seed layer 91 made of a Cu layer (single-layer structure) can be formed by electroless copper plating.

[0064] Next, a resist layer 100 having an opening pattern 100X at a predetermined location is formed on the seed layer 91. The opening pattern 100X is formed so as to expose a portion of the seed layer 91 corresponding to the formation region of the wiring layer 43 (see FIG. 2). The resist layer 100 may be made of, for example, a material that is resistant to the electrolytic plating process in the subsequent step. For example, the resist layer 100 may be made of a photosensitive dry film resist or a liquid photoresist (e.g., a dry film resist or liquid resist such as a novolac resin or an acrylic resin). When a photosensitive dry film resist is used, a dry film is laminated on the upper surface of the seed layer 91 by thermocompression bonding, and the dry film is patterned by photolithography to form the resist layer 100 having the opening pattern 100X. When a liquid photoresist is used, the resist layer 100 can also be formed through the same process.

[0065] 6, using the resist layer 100 as a plating mask, electrolytic plating is performed on the seed layer 91, utilizing the seed layer 91 as a plating power supply layer. That is, electrolytic plating, in this case, Cu electrolytic plating, is performed on the upper surface of the seed layer 91 exposed from the opening pattern 100X of the resist layer 100. This process forms a metal layer 92 that fills the through holes 42X inside the seed layer 91 and a metal layer 93 provided inside the opening pattern 100X.

[0066] Next, in the process shown in FIG. 7, the resist layer 100 shown in FIG. 6 is removed with an alkaline remover (for example, an organic amine-based remover, caustic soda, acetone, ethanol, or the like). 8, unnecessary seed layer 91 is removed by etching using metal layer 93 as an etching mask. In this step, via wiring filling through hole 42X is formed by seed layer 91 and metal layer 92 formed inside through hole 42X, and wiring layer 43 composed of seed layer 91 and metal layer 93 is formed on the upper surface of insulating layer 42. At this time, wiring layer 43 has wiring layer 43A provided at a position overlapping with cavity 40X (see FIG. 2) formed in a later step in a planar view, and wiring layer 43B provided at a position not overlapping with cavity 40X in a planar view.

[0067] Next, the wiring layers 43A and 43B are subjected to a roughening treatment. This roughening treatment forms the entire upper surface and entire side surface of the wiring layer 43A into a first roughened surface R1, and also forms the entire upper surface and entire side surface of the wiring layer 43B into a first roughened surface R1. That is, in this step, the upper surface of the wiring layer 43A is formed into a first roughened surface R1, which has a surface roughness smaller than that of the second roughened surface R2 shown in FIG. 2. The roughening treatment can be performed by, for example, blackening, etching, blasting, or the like.

[0068] Next, in the step shown in FIG. 9, the same steps as those shown in FIGS. 4 to 8 are performed to laminate an insulating layer 44 and a wiring layer 45 on the upper surface of the insulating layer 42. 10, steps similar to those shown in FIGS. 4 to 8 are performed to laminate an insulating layer 46 and a wiring layer 47 on the upper surface of the insulating layer 44. Furthermore, an insulating layer 48 that covers the wiring layer 47 is laminated on the upper surface of the insulating layer 46. At this time, the insulating layer 48 is formed so as to cover the entire upper surface and entire side surfaces of the wiring layer 47.

[0069] 11, a cavity 40X is formed recessed from the upper surface of the insulating layer 48 toward the insulating layer 42 so as to expose the upper and side surfaces of the wiring layer 43A. Specifically, a through hole 48X is formed through the insulating layer 48 in the thickness direction, a through hole 46X is formed in communication with the through hole 48X and is formed through the insulating layer 46 in the thickness direction, and a recess 44X is formed in communication with the through hole 46X and is recessed from the upper surface of the insulating layer 44. That is, the cavity 40X is formed so as to penetrate the insulating layers 48 and 46 in the thickness direction and to be recessed to a position midway in the thickness direction of the insulating layer 44. The cavity 40X is formed so as to expose a portion of the side surface of the wiring layer 43A, specifically, the side surface at the upper part of the wiring layer 43A. However, the cavity 40X is formed so that the bottom surface of the cavity 40X is located above the upper surface of the seed layer 91. That is, the cavity 40X is formed so that the thickness between the bottom surface of the cavity 40X and the upper surface of the insulating layer 42 is greater than the thickness of the seed layer 91. In other words, the depth of the cavity 40X is set so that the insulating layer 44 remains thicker than the seed layer 91. As a result, even if a portion of the unnecessary seed layer 91 is not removed and remains in the step shown in FIG. 8, the remaining unnecessary seed layer 91 can be covered with the insulating layer 44. Therefore, it is possible to preferably prevent the remaining unnecessary seed layer 91 from being exposed in the cavity 40X.

[0070] Here, the cavity 40X can be formed by a laser processing method using, for example, a CO2 laser or a UV-YAG laser. In this laser processing method, a laser beam is irradiated onto the upper surface of the wiring layer 43A. This laser beam irradiation further roughens the upper surface of the wiring layer 43A. That is, the laser processing increases the roughness of the upper surface of the wiring layer 43A. As a result, after this process, i.e., after roughening by the laser processing method, the upper surface of the wiring layer 43A is formed into a second roughened surface R2 having a surface roughness greater than that of the first roughened surface R1. By this process, the upper surface of the wiring layer 43A and the side surface of the wiring layer 43A are formed into roughened surfaces having different surface roughnesses.

[0071] Next, in the step shown in FIG. 12, a surface treatment layer 80 is formed on the surface of the wiring layer 43A exposed from the cavity 40X. The surface treatment layer 80 is formed to cover the entire side surface of the wiring layer 43A exposed from the cavity 40X and the entire upper surface of the wiring layer 43A. The surface treatment layer 80 can be formed by, for example, an electroless plating method. More specifically, first, a first metal layer 81 (Ni layer) is formed by an electroless plating method (electroless Ni plating here) to cover the entire surface of the wiring layer 43A exposed from the cavity 40X. Next, a second metal layer 82 (Au layer) is formed by an electroless plating method (electroless Au plating here) to cover the entire surface of the first metal layer 81. Here, in this step, if unnecessary seed layer 91 that was not removed in the step shown in FIG. 8 is exposed in the cavity 40X, a plating film will be deposited on the surface of the remaining unnecessary seed layer 91. There is a risk that adjacent wiring layers 43A may be short-circuited due to the unintentionally deposited plating film. In contrast, in the present embodiment, the depth of the cavity 40X is set so that the insulating layer 44 remains thicker than the seed layer 91. Therefore, even if unnecessary seed layer 91 remains, the unnecessary seed layer 91 can be covered with the insulating layer 44. This makes it possible to prevent the unintentional deposition of a plating film and to prevent short-circuit defects caused by the plating film.

[0072] 13 to 16, the seed layer 91 and the metal layers 92 and 93 are omitted, and the wiring layer 43 is illustrated as a single layer. 13, an electronic component 60 having a main body 61, a first electrode 62, and a second electrode 63 is prepared. Next, the electronic component 60 is mounted on a surface treatment layer 80 in the cavity 40X. Specifically, the first electrode 62 of the electronic component 60 is bonded to the surface treatment layer 80 formed on the surface of the wiring layer 43A via a bonding member 64. For example, if the bonding member 64 is a solder layer, a suitable flux (not shown) is applied to the surface treatment layer 80, and the surface treatment layer 80 and the first electrode 62 are aligned with the bonding member 64 sandwiched therebetween. Then, a reflow process is performed at a temperature of approximately 230°C to 260°C. This melts the bonding member 64, which is a solder layer, and electrically connects the surface treatment layer 80 and the first electrode 62 via the bonding member 64. Then, an underfill resin 65 is filled between the bottom surface of the cavity 40X and the lower surface of the main body 61 of the electronic component 60 and hardened.

[0073] 14, a process similar to that shown in FIG. 4 is performed to form an insulating layer 49 that covers the upper surface of the insulating layer 48 and fills the cavity 40X. The insulating layer 49 is formed so as to cover the entire side surfaces of the underfill resin 65 and the entire surface of the electronic component 60 that is exposed from the underfill resin 65.

[0074] 15, a process similar to that shown in Fig. 4 is performed to form through-holes VH1 at predetermined locations of the insulating layers 48, 49, penetrating the insulating layers 48, 49 in the thickness direction and exposing part of the upper surface of the wiring layer 47. Furthermore, a through-hole VH2 is formed at predetermined locations of the insulating layer 49, penetrating the insulating layer 49 in the thickness direction and exposing part of the upper surface of the second electrode 63.

[0075] 16, by performing steps similar to those shown in FIGS. 5 to 8, via wiring is formed to fill the through hole VH1, and a wiring layer 50 electrically connected to the wiring layer 47 through the via wiring is laminated on the upper surface of the insulating layer 49. Furthermore, via wiring is formed to fill the through hole VH2, and a wiring layer 50 electrically connected to the second electrode 63 through the via wiring is laminated on the upper surface of the insulating layer 49.

[0076] The above manufacturing steps can be used to manufacture the structure shown in Fig. 2. Thereafter, the insulating layer 51, the wiring layer 52, and the like shown in Fig. 1 are formed, thereby manufacturing the wiring board 10 of this embodiment.

[0077] (Operation and effect of the first embodiment) Next, the effects of the first embodiment will be described. (1-1) The wiring board 10 has a wiring layer 41, an insulating layer 42 that covers the wiring layer 41, and a wiring layer 43A that is laminated on the upper surface of the insulating layer 42 and is electrically connected to the wiring layer 41. The wiring board 10 has N insulating layers 44, 46, and 48 (three in this example) including an insulating layer 44 that is laminated on the upper surface of the insulating layer 42, and a cavity 40X that is formed in the N insulating layers 44, 46, and 48 and that exposes the upper and side surfaces of the wiring layer 43A. The wiring board 10 has a surface treatment layer 80 that covers the upper and side surfaces of the wiring layer 43A that are exposed from the cavity 40X, and an electronic component 60 that is disposed in the cavity 40X and mounted on the surface treatment layer 80. The wiring substrate 10 includes an insulating layer 49 that fills the cavity 40X and covers the electronic component 60, and a wiring layer 50 that is laminated on the upper surface of the insulating layer 49 and electrically connected to the electronic component 60. The side surface of the wiring layer 43A is formed as a first roughened surface R1. The upper surface of the wiring layer 43A is formed as a second roughened surface R2 that has a surface roughness greater than that of the first roughened surface R1.

[0078] According to this configuration, the side and top surfaces of the wiring layer 43A are roughened. The surface treatment layer 80 is then formed to cover the roughened side and top surfaces of the wiring layer 43A. This increases the contact area between the side and top surfaces of the wiring layer 43A and the surface treatment layer 80 compared to when the side and top surfaces of the wiring layer 43A are smooth, thereby improving adhesion between the wiring layer 43A and the surface treatment layer 80. This effectively prevents the surface treatment layer 80 from peeling off from the wiring layer 43A, improving the connection reliability between the wiring layer 43A and the surface treatment layer 80. As a result, the connection reliability between the wiring layer 43A and the electronic component 60 through the surface treatment layer 80 can be improved.

[0079] (1-2) Furthermore, the upper surface of the wiring layer 43A is formed as a second roughened surface R2 having a surface roughness greater than that of the side surface of the wiring layer 43A. This increases the contact area between the upper surface of the wiring layer 43A and the surface treatment layer 80, thereby further improving the adhesion between the upper surface of the wiring layer 43A and the surface treatment layer 80. This more effectively prevents the surface treatment layer 80 from peeling off from the wiring layer 43A.

[0080] (1-3) In a conventional method for manufacturing a wiring board, conductive pads are formed, a protective material is formed to cover the conductive pads, and then multiple insulating layers are laminated to cover the conductive pads and the protective material. Subsequently, a predetermined region of the multiple insulating layers is removed to form a cavity that exposes the protective material, and the protective material is then removed to expose the conductive pads. In this manufacturing method, the conductive pads are covered with the protective material when the cavity is formed, so the surfaces of the conductive pads are not roughened. Therefore, the surfaces of the conductive pads are formed smooth. Therefore, when a surface treatment layer is formed on the surface of such a conductive pad, the adhesion between the conductive pad and the surface treatment layer is reduced, which can easily lead to the problem of the surface treatment layer peeling off from the conductive pad.

[0081] In contrast, in the manufacturing method of the wiring substrate 10 of this embodiment, a protective material covering the wiring layer 43A is not formed. Furthermore, after the wiring layer 43A is roughened, N insulating layers 44, 46, and 48, including the insulating layer 44 that covers the wiring layer 43A, are formed. Furthermore, a laser processing method is used to form cavities 40X that expose the top and side surfaces of the wiring layer 43A in the insulating layers 44, 46, and 48. In this manufacturing method, the roughening process performed before forming the insulating layer 44 allows the top and side surfaces of the wiring layer 43A to be formed into a first roughened surface R1. Furthermore, the laser processing method allows the top surface of the wiring layer 43A to be formed into a second roughened surface R2, which has a surface roughness greater than that of the first roughened surface R1. This increases the contact area between the side and top surfaces of the wiring layer 43A and the surface processing layer 80 compared to when the side and top surfaces of the wiring layer 43A are smooth, thereby improving adhesion between the wiring layer 43A and the surface processing layer 80.

[0082] (1-4) The wiring layer 43B is stacked on the upper surface of the insulating layer 42 and is provided at a position that does not overlap the cavity 40X in a planar view. The side and upper surfaces of the wiring layer 43B are formed as a first roughened surface R1. In this configuration, the upper surface of the wiring layer 43A is formed as a roughened surface with a greater surface roughness than the side and upper surfaces of the wiring layer 43B, which are provided on the same plane as the wiring layer 43A. This further increases the contact area between the upper surface of the wiring layer 43A and the surface treatment layer 80, thereby further improving the adhesion between the upper surface of the wiring layer 43A and the surface treatment layer 80. This more effectively prevents the surface treatment layer 80 from peeling off from the wiring layer 43A.

[0083] (1-5) The cavity 40X is formed so as to recess from the top surface of the uppermost insulating layer 48 of the N insulating layers 44, 46, 48 to a position halfway in the thickness direction of the insulating layer 44. The cavity 40X is formed so as to expose a part of the side surface of the wiring layer 43A. The bottom surface of the cavity 40X is provided above the top surface of the seed layer 91.

[0084] 8, even if a portion of the unnecessary seed layer 91 remains without being removed, the remaining unnecessary seed layer 91 can be covered with the insulating layer 44. Therefore, the remaining unnecessary seed layer 91 can be suitably prevented from being exposed in the cavity 40X. Therefore, when the surface treatment layer 80 is formed, it is possible to prevent a plating film from being unintentionally deposited from the remaining unnecessary seed layer 91, and to prevent short-circuit defects caused by the plating film.

[0085] (Second embodiment) The second embodiment will be described below with reference to Figures 17 to 27. The wiring board 10A of this embodiment differs from the first embodiment in the structure of the cavity 40Y of the wiring structure 40 and the surface treatment layer 80. The following description will focus on the differences from the first embodiment. Note that the same components as those shown in Figures 1 to 16 above are denoted by the same reference numerals, and detailed description of each element will be omitted.

[0086] (Configuration of wiring structure 40) As shown in Fig. 17, a cavity 40Y is formed in the wiring structure 40. In this embodiment, the cavity 40Y is formed in the insulating layers 42, 44, 46, and 48. The cavity 40Y is formed so as to be recessed from the upper surface of the insulating layer 48 to a position halfway in the thickness direction of the insulating layer 42. The cavity 40Y is formed so as to expose the entire upper surface of the wiring layer 43A and the entire side surface of the wiring layer 43A. The cavity 40Y is formed to correspond to the electronic component 60 to be built in.

[0087] The cavity 40Y is configured by a through hole 48X penetrating the insulating layer 48 in the thickness direction, a through hole 46X penetrating the insulating layer 46 in the thickness direction, a through hole 44Y penetrating the insulating layer 44 in the thickness direction, and a recess 42Y formed in the upper surface of the insulating layer 42, which are all connected to each other. For example, the inner wall surfaces of the through holes 48X, 46X, 44Y, and recess 42Y are formed so as to be continuous with each other. The through holes 48X, 46X, 44Y, and recess 42Y are formed, for example, coaxially with each other. That is, the central axes of the through holes 48X, 46X, 44Y, and recess 42Y are aligned in plan view.

[0088] The bottom surface of the recess 42Y, i.e., the bottom surface of the cavity 40Y, is located at a midpoint in the thickness direction of the insulating layer 42. The bottom surface of the cavity 40Y is located below the lower surface of the wiring layer 43A. The bottom surface of the cavity 40Y is located above the upper surface of the wiring layer 41. The depth of the recess 42Y, i.e., the depth from the upper surface of the insulating layer 42 to the bottom surface of the recess 42Y, can be, for example, approximately 3 μm to 8 μm.

[0089] The recess 42Y is provided, for example, at a position that overlaps with the through-hole 44Y in a plan view but does not overlap with the wiring layer 43A in a plan view. That is, the recess 42Y is not formed in a portion of the upper surface of the insulating layer 42 that overlaps with the wiring layer 43A in a plan view. In other words, the insulating layer 42 has a protrusion 42A that protrudes upward from the bottom surface of the recess 42Y in a portion that overlaps with the wiring layer 43A in a plan view.

[0090] 2. That is, the cavity 40Y is formed so that the upper opening is wider than the lower opening. The side surface of the protrusion 42A is formed so as to extend perpendicular to the upper surface of the insulating layer 42.

[0091] The space surrounded by the inner wall surface and the bottom surface of cavity 40Y, i.e., the internal space of cavity 40Y, serves as an accommodating space for accommodating electronic component 60. In this manner, in wiring board 10A of the present example, four insulating layers 42, 44, 46, and 48 stacked on core substrate 20 serve as insulating layers for forming the cavity. Note that, in FIG. 17, for simplification of the drawing, insulating layer 51, wiring layer 52, and external connection terminal 90 shown in FIG. 1 are omitted.

[0092] The side surfaces of the wiring layer 43A are formed on a first roughened surface R1. The top surface of the wiring layer 43A is formed on a second roughened surface R2 having a surface roughness greater than that of the first roughened surface R1. The entire side surfaces and the entire top surface of the wiring layer 43A are exposed from the cavity 40Y.

[0093] A surface treatment layer 80 is formed on the surface of the wiring layer 43A exposed from the cavity 40Y. The surface treatment layer 80 of this embodiment has a structure in which a first metal layer 81 and a second metal layer 82 are stacked.

[0094] The first metal layer 81 is formed to cover the entire upper surface of the wiring layer 43A and to cover the entire side surface of the wiring layer 43A. The first metal layer 81 is formed, for example, to cover a part of the side surface of the protruding portion 42A of the insulating layer 42. The first metal layer 81 is formed to continuously cover the side surface of the protruding portion 42A, the side surface of the wiring layer 43A, and the upper surface of the wiring layer 43A.

[0095] The second metal layer 82 is formed so as to cover the entire surface of the first metal layer 81. The second metal layer 82 is formed so as to cover the entire upper surface of the first metal layer 81, cover the entire side surfaces of the first metal layer 81, and cover the entire lower surface of the first metal layer 81. The second metal layer 82 is formed so as to continuously cover the upper surface of the first metal layer 81, the side surfaces of the first metal layer 81, and the lower surface of the first metal layer 81.

[0096] (Configuration of electronic component 60) The electronic component 60 is flip-chip mounted on the wiring layer 43A exposed from the cavity 40Y. Specifically, the first electrode 62 of the electronic component 60 is electrically connected to a surface treatment layer 80 formed on the surface of the wiring layer 43A exposed from the cavity 40Y. More specifically, the first electrode 62 is electrically connected to the surface treatment layer 80 via a bonding member 64. As a result, the electronic component 60 is electrically connected to the wiring layer 43A via the first electrode 62, the bonding member 64, and the surface treatment layer 80.

[0097] (Composition of underfill resin 65) An underfill resin 65 is formed between the electronic component 60 and the bottom surface of the cavity 40Y. The underfill resin 65 is formed so as to fill the gap between the lower surface of the main body 61 of the electronic component 60 and the bottom surface of the cavity 40Y. The underfill resin 65 is formed so as to seal the first electrode 62, the bonding member 64, and the surface treatment layer 80. The underfill resin 65 is formed so as to cover the entire side surface of the protrusion 42A exposed from the surface treatment layer 80.

[0098] (Configuration of wiring structure 40) The insulating layer 49 is a filling insulating layer that fills the cavity 40Y. The insulating layer 49 is formed to cover the upper surface of the insulating layer 48 and to fill the cavity 40Y to cover the electronic component 60. The insulating layer 49 is formed, for example, to cover the entire side surface of the underfill resin 65. The insulating layer 49 is formed, for example, to cover the entire bottom surface of the cavity 40Y that is exposed from the underfill resin 65. The insulating layer 49 is formed, for example, to cover the entire inner wall surface of the cavity 40Y that is exposed from the underfill resin 65. The insulating layer 49 is formed, for example, to cover the entire electronic component 60 that is exposed from the underfill resin 65.

[0099] (Method of Manufacturing Wiring Board 10A) Next, a method for manufacturing wiring board 10A will be described. For ease of explanation, the parts that will ultimately become the components of wiring board 10A will be denoted by the reference numerals of the final components.

[0100] 18, the structure shown in FIG. 18 is formed by performing the same steps as those shown in FIGS. 3 to 6. That is, first, an insulating layer 42 that covers the wiring layer 41 and has through holes 42X is formed on the upper surface of the core substrate 20, and a seed layer 91 that continuously covers the upper surface of the insulating layer 42 and the inner surfaces of the through holes 42X is formed. Thereafter, a resist layer 100 having an opening pattern 100X is formed on the seed layer 91, and electrolytic plating is performed using the resist layer 100 as a plating mask. This forms a metal layer 92 that fills the through holes 42X inside the seed layer 91, and a metal layer 93 provided inside the opening pattern 100X.

[0101] Next, in the step shown in FIG. 19, the resist layer 100 shown in FIG. 18 is removed with an alkaline remover (for example, an organic amine-based remover, caustic soda, acetone, ethanol, or the like).

[0102] 20, unnecessary seed layer 91 is removed by etching using metal layer 93 as an etching mask. In this step, via wiring filling through hole 42X is formed by seed layer 91 and metal layer 92 formed inside through hole 42X, and wiring layer 43 composed of seed layer 91 and metal layer 93 is formed on the upper surface of insulating layer 42. At this time, wiring layer 43 has wiring layer 43A provided at a position overlapping with cavity 40Y (see FIG. 17) formed in a later step in a planar view, and wiring layer 43B provided at a position not overlapping with cavity 40Y in a planar view.

[0103] Next, the wiring layers 43A and 43B are subjected to a roughening treatment. This roughening treatment forms the entire upper surface and entire side surfaces of the wiring layer 43A into a first roughened surface R1, and also forms the entire upper surface and entire side surfaces of the wiring layer 43B into a first roughened surface R1. That is, in this step, the upper surface of the wiring layer 43A is formed into a first roughened surface R1, which has a surface roughness smaller than that of the second roughened surface R2 shown in FIG. 17. The roughening treatment can be performed by, for example, blackening, etching, blasting, or the like.

[0104] 21, steps similar to those shown in FIGS. 4 to 8 are performed to stack an insulating layer 44, a wiring layer 45, an insulating layer 46, a wiring layer 47, and an insulating layer 48 on the upper surface of the insulating layer 42. At this time, the insulating layer 48 is formed so as to cover the entire upper surface and the entire side surfaces of the wiring layer 47.

[0105] 22, a cavity 40Y is formed recessed from the top surface of the insulating layer 48 toward the core substrate 20 so that the entire top and side surfaces of the wiring layer 43A are exposed. Specifically, a through hole 48X is formed through the insulating layer 48, a through hole 46X is formed through the insulating layer 46 and communicates with the through hole 48X, a through hole 44Y is formed through the insulating layer 44 and communicates with the through hole 46X, and a recess 42Y is formed through the through hole 44Y and recessed from the top surface of the insulating layer 42. That is, the cavity 40Y is formed so as to penetrate the multiple insulating layers 48, 46, and 44 in the thickness direction and to recess to a position midway through the insulating layer 42 in the thickness direction. In this manner, the cavity 40Y is formed so as to recess from the top surface of the insulating layer 42 toward the core substrate 20. As a result, even if a portion of the unnecessary seed layer 91 remains unremoved in the process shown in FIG. 20, the remaining unnecessary seed layer 91 can be removed by laser processing in this process.

[0106] Here, the cavity 40Y can be formed by a laser processing method using, for example, a CO2 laser or a UV-YAG laser. In this laser processing method, a laser beam is irradiated onto the upper surface of the wiring layer 43A. This laser beam irradiation further roughens the upper surface of the wiring layer 43A. That is, the laser processing increases the roughness of the upper surface of the wiring layer 43A. As a result, the upper surface of the wiring layer 43A is formed into a second roughened surface R2 having a surface roughness greater than that of the first roughened surface R1.

[0107] 23, a surface treatment layer 80 is formed on the surface of the wiring layer 43A exposed from the cavity 40Y. The surface treatment layer 80 is formed to cover the entire side surface of the wiring layer 43A and the entire upper surface of the wiring layer 43A. The surface treatment layer 80 can be formed by, for example, electroless plating. More specifically, first, a first metal layer 81 (Ni layer) is formed by electroless plating (electroless Ni plating here) to cover the entire surface of the wiring layer 43A exposed from the cavity 40Y. At this time, the first metal layer 81 is formed to cover, for example, a portion of the side surface of the protruding portion 42A of the insulating layer 42. Next, a second metal layer 82 (Au layer) is formed by electroless plating (electroless Au plating here) to cover the entire surface of the first metal layer 81, i.e., the entire upper surface, entire side surface, and entire lower surface of the first metal layer 81. In this step, since the remaining unnecessary seed layer 91 is suppressed as described above, it is possible to suitably suppress the unintentional deposition of a plating film due to the unnecessary seed layer 91. This makes it possible to suitably suppress the occurrence of short-circuit defects due to the unintentional deposition of a plating film.

[0108] 24 to 27, the seed layer 91 and the metal layers 92 and 93 are omitted, and the wiring layer 43 is illustrated as a single layer. 24, an electronic component 60 having a main body 61, a first electrode 62, and a second electrode 63 is prepared. Next, the electronic component 60 is mounted on the surface treatment layer 80 in the cavity 40Y. After that, underfill resin 65 is filled between the bottom surface of the cavity 40Y and the lower surface of the main body 61 of the electronic component 60, and is then cured.

[0109] 25, a process similar to that shown in FIG. 4 is performed to form an insulating layer 49 that covers the upper surface of the insulating layer 48 and fills the cavity 40Y. The insulating layer 49 is formed so as to cover the entire side surfaces of the underfill resin 65 and the entire surface of the electronic component 60 that is exposed from the underfill resin 65.

[0110] 26, a process similar to that shown in Fig. 4 is performed to form through-holes VH1 at predetermined locations of the insulating layers 48, 49, penetrating the insulating layers 48, 49 in the thickness direction and exposing part of the upper surface of the wiring layer 47. Furthermore, a through-hole VH2 is formed at predetermined locations of the insulating layer 49, penetrating the insulating layer 49 in the thickness direction and exposing part of the upper surface of the second electrode 63.

[0111] 27, by performing steps similar to those shown in FIGS. 5 to 8, via wiring is formed to fill the through hole VH1, and a wiring layer 50 electrically connected to the wiring layer 47 through the via wiring is laminated on the upper surface of the insulating layer 49. Furthermore, via wiring is formed to fill the through hole VH2, and a wiring layer 50 electrically connected to the second electrode 63 through the via wiring is laminated on the upper surface of the insulating layer 49.

[0112] The above manufacturing steps can manufacture the structure shown in Fig. 17. Thereafter, the insulating layer 51, the wiring layer 52, and the like shown in Fig. 1 are formed, thereby manufacturing the wiring board 10A of this embodiment.

[0113] (Operation and effect of the second embodiment) According to the second embodiment described above, in addition to the effects (1-1) to (1-4) of the first embodiment, the following effects can be achieved.

[0114] (2-1) The cavity 40Y is formed so as to recess from the upper surface of the uppermost insulating layer 48 of the N (here, three) insulating layers 44, 46, 48 to a position halfway in the thickness direction of the insulating layer 42. The cavity 40Y is formed so as to penetrate the insulating layer 44 in the thickness direction, and so as to expose the entire side surface of the wiring layer 43A.

[0115] 20 , even if a portion of the unnecessary seed layer 91 is not removed and remains on the upper surface of the insulating layer 42, the remaining unnecessary seed layer 91 can be removed by laser processing when forming the cavity 40Y. This makes it possible to preferably prevent unintentional deposition of a plating film due to the remaining unnecessary seed layer 91 when forming the surface treatment layer 80. This makes it possible to preferably prevent short-circuit defects caused by unintentional deposition of a plating film.

[0116] (2-2) The cavity 40Y has a recess 42Y recessed from the upper surface of the insulating layer 42. The recess 42Y is provided at a position that does not overlap the wiring layer 43A in a plan view. With this configuration, the recess 42Y is formed between two adjacent wiring layers 43A. This increases the creepage distance between the two adjacent wiring layers 43A, thereby effectively suppressing the occurrence of short circuits due to migration.

[0117] (Example of change) The above-described embodiments can be modified as follows: The above-described embodiments and the following modifications can be combined with each other within the scope of technical compatibility.

[0118] The structure of the wiring boards 10 and 10A in the above embodiments can be modified as appropriate. For example, the number and layout of wiring layers in the wiring structure 30 and the number of insulating layers can be modified and changed in various ways.

[0119] The solder resist layer 70 in each of the above embodiments may be omitted. The wiring structure 30 in each of the above embodiments may be omitted. For example, the number and layout of wiring layers in the wiring structure 40 and the number of insulating layers can be modified and changed in various ways.

[0120] In the wiring structure 40 of the first embodiment, the insulating layer for forming the cavity is configured with three insulating layers 44, 46, and 48. However, the invention is not limited to this, and the insulating layer for forming the cavity may be configured with one insulating layer, two insulating layers, or four or more insulating layers.

[0121] In the wiring structure 40 of the second embodiment, the insulating layer for forming the cavity is configured with four insulating layers 42, 44, 46, and 48. However, the invention is not limited to this, and the insulating layer for forming the cavity may be configured with one to three insulating layers, or may be configured with five or more insulating layers.

[0122] In the wiring structure 40 of each of the above embodiments, a metal pattern may be formed on the periphery of the bottom of the cavities 40X, 40Y. In this case, the metal pattern is exposed on the periphery of the bottom of the cavities 40X, 40Y.

[0123] In the wiring boards 10 and 10A of the above embodiments, the number of wiring layers and insulating layers stacked on the upper surface of the insulating layer 49 for filling the cavity is not particularly limited. Although the wiring boards 10 and 10A in the above embodiments are embodied as build-up wiring boards having a core substrate 20, the present invention is not limited to this. For example, the wiring boards 10 and 10A may be embodied as wiring boards in the form of coreless substrates that do not have a core substrate 20.

[0124] The number of electronic components 60 built into the wiring board 10, 10A in each of the above embodiments is not limited. For example, multiple electronic components 60 may be built into the wiring board 10, 10A. In this case, the same number of cavities 40X, 40Y as the number of built-in electronic components 60 may be formed, or multiple electronic components 60 may be arranged in one cavity 40X, 40Y.

[0125] In the above embodiments, the electronic component 60 having two types of electrodes, i.e., the first electrode 62 and the second electrode 63, is embedded in the wiring board 10, 10A, but this is not limiting. For example, an electronic component having three or more types of electrodes may be embedded in the wiring board 10, 10A.

[0126] The structure of the electronic component 60 in each of the above embodiments can be modified as appropriate. For example, the second electrode 63 may be omitted. In this case, the electronic component 60 has the first electrode 62 only on the lower surface of the main body 61.

[0127] In the above embodiments, the manufacturing method is embodied as a single-cavity (one-piece) manufacturing method, but the manufacturing method may be embodied as a multi-cavity manufacturing method. [Explanation of symbols]

[0128] 10,10A wiring board 40X, 40Y cavity 41 Wiring layer (1st wiring layer) 42 Insulating layer (first insulating layer) 42Y recess 43A Wiring layer (2nd wiring layer) 43B Wiring layer (4th wiring layer) 44 Insulation layer (second insulation layer) 45 Wiring layer (5th wiring layer) 46 Insulation layer (third insulation layer) 47 Wiring layer (6th wiring layer) 48 Insulation layer (4th insulation layer) 49 Insulation layer (filled insulation layer) 50 Wiring layer (3rd wiring layer) 60 Electronic Components 61 Main body 62 1st electrode 63 2nd electrode 64 Joint members 65 Underfill resin 80 Surface treatment layer 91 Seed Layer 93 Metal layer R1 First roughened surface R2 Second roughened surface

Claims

1. a first wiring layer; a first insulating layer covering the first wiring layer; a second wiring layer laminated on an upper surface of the first insulating layer and electrically connected to the first wiring layer; N insulating layers (N is a natural number equal to or greater than 1) including a second insulating layer stacked on an upper surface of the first insulating layer; a cavity formed in the N insulating layers so as to expose an upper surface and a side surface of the second wiring layer; a surface treatment layer that covers the upper surface and side surfaces of the second wiring layer exposed from the cavity; an electronic component disposed in the cavity and mounted on the surface treatment layer; a filled insulating layer that fills the cavity and covers the electronic component; a third wiring layer laminated on an upper surface of the filled insulating layer and electrically connected to the electronic component; a side surface of the second wiring layer is formed on a first roughened surface, a top surface of the second wiring layer formed as a second roughened surface having a surface roughness greater than that of the first roughened surface;

2. a fourth wiring layer laminated on an upper surface of the first insulating layer and electrically connected to the first wiring layer; the fourth wiring layer is provided at a position that does not overlap the cavity in a plan view, The wiring board according to claim 1 , wherein the side and top surfaces of the fourth wiring layer are formed on the first roughened surface.

3. the cavity is formed so as to be recessed from an upper surface of an uppermost insulating layer among the N insulating layers to a midpoint in a thickness direction of the second insulating layer, the cavity is formed so as to expose a part of a side surface of the second wiring layer, 2. The wiring board according to claim 1, wherein the surface treatment layer is formed so as to cover the entire upper surface of the second wiring layer and the entire side surface of the second wiring layer exposed from the cavity.

4. the second wiring layer has a seed layer formed on the upper surface of the first insulating layer and a metal layer formed on the upper surface of the seed layer; The wiring board according to claim 3 , wherein a bottom surface of the cavity is provided above an upper surface of the seed layer.

5. the cavity is formed so as to be recessed from an upper surface of an uppermost insulating layer among the N insulating layers to a midpoint in a thickness direction of the first insulating layer, the cavity is formed so as to penetrate the second insulating layer in a thickness direction and to expose the entire side surface of the second wiring layer, 2. The wiring board according to claim 1, wherein the surface treatment layer is formed so as to cover the entire upper surface of the second wiring layer and the entire side surfaces of the second wiring layer.

6. the cavity has a recess recessed from the top surface of the first insulating layer, The wiring board according to claim 5 , wherein the recess is provided at a position that does not overlap the second wiring layer in a plan view.

7. The wiring board is the second insulating layer laminated on the top surface of the first insulating layer so as to cover the fourth wiring layer; a fifth wiring layer laminated on an upper surface of the second insulating layer and electrically connected to the fourth wiring layer; a third insulating layer laminated on an upper surface of the second insulating layer so as to cover the fifth wiring layer; a sixth wiring layer laminated on an upper surface of the third insulating layer and electrically connected to the fifth wiring layer; a fourth insulating layer laminated on the upper surface of the third insulating layer so as to cover the sixth wiring layer, The wiring board according to claim 2 , wherein the N insulating layers include the second insulating layer, the third insulating layer, and the fourth insulating layer.

8. the electronic component has a main body, a first electrode provided on a lower surface of the main body, and a second electrode provided on an upper surface of the main body; the first electrode is electrically connected to the surface treatment layer via a bonding member; The wiring board according to claim 1 , wherein the third wiring layer is electrically connected to the second electrode.

9. an underfill resin that fills a gap between the bottom surface of the cavity and the electronic component; The wiring board according to claim 8 , wherein the filling insulating layer is formed so as to cover the entire side surface of the underfill resin.

10. forming a first wiring layer; forming a first insulating layer covering the first wiring layer; forming a second wiring layer electrically connected to the first wiring layer on the upper surface of the first insulating layer; a step of forming an upper surface and a side surface of the second wiring layer into a first roughened surface by a roughening treatment; forming an insulating layer of N layers (N is a natural number equal to or greater than 1) including a second insulating layer stacked on an upper surface of the first insulating layer so as to cover the second wiring layer; forming a cavity in the N insulating layers by a laser processing method, exposing an upper surface and a side surface of the second wiring layer, and roughening the upper surface of the second wiring layer; forming a surface treatment layer that covers the upper surface and side surfaces of the second wiring layer exposed from the cavity; mounting an electronic component on the surface treatment layer in the cavity; forming a filled insulating layer that fills the cavity and covers the electronic component; forming a third wiring layer electrically connected to the electronic component on the upper surface of the filled insulating layer; The method for manufacturing a wiring substrate, wherein the upper surface of the second wiring layer after being roughened by the laser processing method is formed into a second roughened surface having a surface roughness greater than that of the first roughened surface.

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