Recording apparatus

Abstract

To provide a technique which contributes to miniaturization of a circuit board.SOLUTION: A generation unit configured to generate a plurality of driving signals for driving the piezoelectric element, the generation unit including a plurality of digital-to-analog conversion units configured to convert a digital signal into an analog signal; And a selection unit configured to select a specific driving signal from the plurality of driving signals generated by the generation unit and output the selected driving signal to the recording unit, wherein in the generation unit, the control signal is shared by the plurality of digital-to-analog conversion units, and output signals are output from the plurality of digital-to-analog conversion units at different timings.SELECTED DRAWING: Figure 14

Description

[Technical Field]

[0001] The present disclosure relates to a recording device using a piezoelectric element. [Background technology]

[0002] In recent years, with the trend toward higher image quality in recording devices, it has become common to prepare multiple drive signals to be supplied to the recording head and stabilize the ejection performance by selectively using the multiple drive signals according to the ink characteristics, the state of the nozzles ejecting the ink, etc. For example, in a recording device that uses a piezoelectric element to eject ink using an inkjet method, a drive signal selection unit that selects one drive signal from multiple drive signals is located near the piezoelectric element, and the drive signal selected by the drive signal selection unit is applied to the piezoelectric element.

[0003] Patent Document 1 discloses a technology in which drive data, which is a digital signal that forms the basis of a drive signal, is converted into an analog signal in a drive circuit equipped with a digital-to-analog converter, and the voltage and current of the converted analog signal are amplified to obtain the drive signal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-158494 Summary of the Invention [Problem to be solved by the invention]

[0005] However, with the technology disclosed in Patent Document 1, in order to generate one drive signal, it is necessary to transmit multi-bit drive data to the drive circuits. For example, if the drive data is 10 bits and there are eight drive circuits, 80 (=10×8) signal lines are required between these drive circuits and the configuration that outputs the drive data. This increases the wiring area of ​​these signal lines on the circuit board, making it difficult to miniaturize the circuit board.

[0006] The present disclosure has been made in view of the above-mentioned problems, and aims to provide a technique that contributes to the miniaturization of circuit boards. [Means for solving the problem]

[0007] In order to achieve the above object, one embodiment of a recording device according to the present disclosure comprises a recording means that records by ejecting ink by driving a piezoelectric element, a generating means that has a plurality of digital-to-analog conversion units that convert digital signals to analog signals and generates a plurality of drive signals that drive the piezoelectric elements, a control means that outputs a control signal to the generating means for generating the drive signals and controls the generation of the drive signals by the generating means, and a selecting means that selects a specific drive signal from the plurality of drive signals generated by the generating means and outputs it to the recording means, wherein the generating means is characterized in that the control signal is shared by the plurality of digital-to-analog conversion units, and output signals are output at different times by the plurality of digital-to-analog conversion units. [Effects of the Invention]

[0008] According to the present disclosure, the number of signal lines is reduced, which can contribute to miniaturization of the circuit board. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic diagram of a recording apparatus. [Figure 2] FIG. 2 is a schematic configuration diagram of a chip unit. [Figure 3] FIG. 2 is a schematic diagram of a recording head. [Figure 4] FIG. 2 is a diagram showing wiring of a flexible electrical wiring board. [Figure 5] FIG. 3 is a diagram illustrating driving of a piezoelectric element. [Figure 6] FIG. 1 is a block diagram showing the configuration of a recording apparatus. [Figure 7] FIG. 2 is a block diagram showing the functional configuration of an image processing unit. [Figure 8]FIG. 2 is a schematic configuration diagram of a drive signal selection unit and a drive signal generation unit. [Figure 9] FIG. 4 is a diagram showing signals transmitted by the first serial communication. [Figure 10] FIG. 4 is a diagram showing the relationship between signals in the first serial communication and drive signals. [Figure 11] FIG. [Figure 12] FIG. 1 is a circuit diagram of a residual vibration detection circuit. [Figure 13] FIG. 2 is a circuit diagram of a drive signal generation circuit. [Figure 14] FIG. 2 is a diagram showing a detailed configuration of a drive signal generating unit. [Figure 15] FIG. 2 is a diagram for explaining the timing of a control signal of a DAC. [Figure 16] FIG. 2 is a diagram showing an example of an output waveform of a DAC. [Figure 17] 10 is a diagram showing the relationship between the output value of a DAC and time when the output waveform rises. [Figure 18] 10 is a diagram showing the relationship between the output value of a DAC and time when the output waveform falls. [Figure 19] FIG. 10 is a diagram showing a detailed configuration of a drive signal generating unit according to another embodiment. [Figure 20] FIG. 10 is a diagram for explaining the timing of a control signal of a DAC in another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] An example of an embodiment of a recording device will be described in detail below with reference to the accompanying drawings. Note that the following embodiment does not limit the present disclosure, and not all of the combinations of features described in the present embodiment are necessarily essential to the solutions of the present disclosure. Furthermore, the positions, shapes, and the like of components described in the embodiment are merely examples, and are not intended to limit the scope of the present disclosure to only those.

[0011] (First embodiment) A recording device according to a first embodiment will be described with reference to Figures 1 to 18. In the following description, a recording device that uses a full-line type recording head to record on a sheet (hereinafter referred to as a "recording medium") unwound from a roll will be described as an example of the recording device according to this embodiment.

[0012] <Recording device> Fig. 1 is a schematic diagram of a recording device according to this embodiment. Recording device 10 shown in Fig. 1 includes a housing 12, a holding unit 14 that holds a roll R formed by winding a sheet-like recording medium S, and a conveying unit 16 that conveys the recording medium S unwound from the roll R. Recording device 10 also includes a head unit 18 that records on the recording medium S conveyed by the conveying unit 16, and a scanner unit 20 that includes a line scanner 19 that reads an image recorded on the recording medium S by the head unit 18.

[0013] The head unit 18 is equipped with a full-line type recording head 22 capable of recording in an area corresponding to the length in the width direction (direction perpendicular to the paper surface of FIG. 1) of the recording medium S being transported. In this embodiment, four recording heads are provided: a recording head that ejects cyan ink, a recording head that ejects magenta ink, a recording head that ejects yellow ink, and a recording head that prints black ink. Note that the number of recording heads and the types of ink ejected from the recording heads are not limited to those described above.

[0014] The conveying unit 16 conveys the recording medium S in a conveying direction (see arrow in FIG. 1) by nipping the recording medium S with, for example, a conveying roller 16a driven by a motor and a driven roller 16b that is in pressure contact with the conveying roller 16a and driven by it. Ink is sequentially ejected from each recording head 22 of the head unit 18 onto the recording medium S conveyed by the conveying unit 16, and recording is performed.

[0015] <Recording head configuration> The recording head 22 is equipped with nozzles that eject ink. The recording head 22 is equipped with piezoelectric elements as ejection energy generating elements that eject ink from these nozzles. When ejecting ink, pressure is generated within the piezoelectric elements using the piezoelectric elements, and this pressure causes liquid in the pressure chambers to be ejected from nozzles formed at one end of the pressure chambers. Therefore, in the recording head 22, each piezoelectric element is equipped with an electrical contact and is connected to an integrated circuit that generates a drive signal, and ink is ejected by driving the piezoelectric elements with the drive signal. The configuration of the recording head 22 will be described below.

[0016] Fig. 2 is a schematic diagram of the chip unit 206 provided in the recording head 22. Fig. 3 is a schematic diagram of the recording head 22. Fig. 4 is a diagram showing the wiring in the flexible electrical wiring board 204, where (a) shows the first layer and (b) shows the second layer.

[0017] The chip unit 206 includes a piezoelectric element substrate 200, a drive signal selection unit 202, and a flexible electrical wiring substrate 204. The piezoelectric element substrate 200 includes piezoelectric elements, pressure chambers, and nozzles, and is configured to be able to eject ink. Since publicly known techniques can be used for the detailed configurations of the piezoelectric elements, pressure chambers, and nozzles, a detailed description thereof will be omitted. A method for driving the piezoelectric elements will be described later.

[0018] A first terminal 200a is provided near one end in the short side direction (the vertical direction in FIG. 2) of the piezoelectric element substrate 200, and a second terminal 200b is provided near the other end in the short side direction (see FIG. 2). The first terminal 200a and the second terminal 200b are each electrically connected to a terminal (not shown) provided on a drive signal selection unit 202 mounted on a flexible electrical wiring substrate 204.

[0019] The flexible electrical wiring board 204 includes a selection unit-side terminal 208, which is electrically connected to a wiring board-side terminal (not shown) provided on the drive signal selection unit 202. The flexible electrical wiring board 204 also includes a capacitor mounting section 210 that implements a power supply bypass capacitor for the drive signal selection unit 202, and a head substrate connection section 212 that connects to the head substrate 302 (see FIG. 3).

[0020] The printhead 22 includes four chip units 206 (see FIG. 3). Each chip unit 206 is electrically connected to a head substrate 302 via a head substrate connection section 212. The head substrate 302 includes, for example, a signal connection section 304 and a drive signal connection section 306 that are connected to a controller 600 (see FIG. 6) that controls the printing apparatus 10.

[0021] The flexible electrical wiring board 204 has a first layer formed on one surface of the base material (see FIG. 4(a)), and a second layer formed on the other surface of the base material (see FIG. 4(b)). The first layer of the flexible electrical wiring board 204 has a first drive signal wiring 402, a third drive signal wiring 404, a fifth drive signal wiring 406, and a seventh drive signal wiring 408 formed thereon, and these wirings have approximately the same wiring width (see FIG. 4(a)). The first drive signal wiring 402, the third drive signal wiring 404, the fifth drive signal wiring 406, and the seventh drive signal wiring 408 are arranged in this order in the width direction of the flexible electrical wiring board, which intersects with the extension direction of the flexible electrical wiring board 204. In this width direction, these drive signal wirings are arranged so as to be sandwiched between two drive signal return current wirings 410. Specifically, in the width direction, when the first drive signal wire 402 is used as a reference, the drive signal return current wire 410a is arranged on the opposite side of the third drive signal wire 404. In addition, in the width direction, when the seventh drive signal wire 408 is used as a reference, the drive signal return current wire 410b is arranged on the opposite side of the fifth drive signal wire 406.

[0022] The second layer of the flexible electrical wiring substrate 204 is formed with a second drive signal wiring 412, a fourth drive signal wiring 414, a sixth drive signal wiring 416, and an eighth drive signal wiring 418, all of which have approximately the same wiring width (see FIG. 4(b)). The second drive signal wiring 412, the fourth drive signal wiring 414, the sixth drive signal wiring 416, and the eighth drive signal wiring 418 are arranged in this order in the width direction of the flexible electrical wiring substrate 204. These signal wirings are arranged so as to be sandwiched between two drive signal return current wirings 420 in the width direction. Specifically, the drive signal return current wiring 420a is arranged on the opposite side of the fourth drive signal wiring 414 in the width direction when the second drive signal wiring 412 is used as a reference. The drive signal return current wiring 420b is arranged on the opposite side of the sixth drive signal wiring 416 in the width direction when the eighth drive signal wiring 418 is used as a reference.

[0023] <Piezoelectric element driving method and piezoelectric element driving signal> Next, we will explain the method of driving the piezoelectric element 502 and the drive signal applied to the piezoelectric element 502. Figure 5 is a diagram for explaining the driving of the piezoelectric element 502, where (a) shows the driving of the piezoelectric element 502 in four steps, and (b) shows the drive signal applied to the piezoelectric element.

[0024] The piezoelectric element 502 is driven in the following four steps, steps (1) to (4). That is, a series of operations from step (1) to step (4) described below constitutes one ejection operation (see FIG. 5(a)). Furthermore, a series of voltage changes of the voltage source 512 from step (1) to step (4) constitutes the waveform of the drive signal to be applied to the piezoelectric element 502 (see FIG. 5(b)).

[0025] Step (1): In the initial state, the pressure chamber 504 is filled with ink 506, and a high voltage is applied between the upper electrode 508 and the lower electrode 510 of the piezoelectric element 502 from the voltage source 512, causing the pressure chamber 504 to contract. Step (2): The pressure chamber 504 is expanded by reducing the voltage of the voltage source 512, and ink 506 is drawn into the expanded pressure chamber 504 via a flow path (not shown) that communicates with the pressure chamber 504. At this time, a sinusoidal pressure wave is generated in the pressure chamber 504 by the piezoelectric element 502. At this time, the meniscus in the nozzle 514 is drawn toward the pressure chamber 504. Step (3): The voltage of the voltage source 512 is increased in synchronization with the pressure wave generated in step (2), thereby contracting the pressure chamber 504 and ejecting the ink 506 from the nozzle 514 . Step (4): After step (3), mechanical vibration continues in the piezoelectric element 502. In order to cancel this mechanical vibration and bring the piezoelectric element 502 to a standstill, the voltage of the voltage source 512 is increased again.

[0026] <Configuration of recording device> Next, the configuration of the recording device 10 will be described, focusing on the control system. Fig. 6 is a block diagram showing the configuration of the recording device. Note that Fig. 6 mainly shows the configuration of the control system of the recording device 10, and therefore some components of the recording device 10 are omitted. Fig. 7 is a block diagram showing the functional configuration of the image processing unit 612.

[0027] The recording device 10 includes a control controller 600 that controls the overall operation of the recording device 10. The control controller 600 is connected to a host PC 602, and receives recording jobs output from the host PC 602, including recording instructions, image data to be recorded, and recording setting information. The control controller 600 includes a receiving I / F 604, a ROM 606, a RAM 608, a motor and sensor control unit 610, an image processing unit 612, a recording control unit 614, and a CPU 615.

[0028] A receiving I / F 604 transmits and receives data to and from the Host PC 602. A ROM 606 stores programs that operate the CPU 615. A RAM 608 is used to execute programs and also temporarily stores various data. A motor and sensor control unit 610 controls various motors and sensors in the recording device 10.

[0029] The image processing unit 612 performs image processing on image data included in a print job input from the Host PC 602 via the receiving I / F 604. Specifically, for example, the image processing unit 612 generates raster image data in bitmap format based on image data included in the input print job and expressed in a page description language. Furthermore, the image processing unit 612 converts the generated image data into image data for each ink color, such as CMYK, that can be processed by the print control unit 614, and outputs the converted image data.

[0030] The recording control unit 614 controls recording on the recording head 22 based on image data obtained by image processing by the image processing unit 612. The recording control unit 614 includes a drive signal control unit 616 and a drive signal selection information transmission unit 618. The drive signal control unit 616 outputs a control signal (drive data) for generating a drive signal to the drive signal generation unit 620. The drive signal selection information transmission unit 618 outputs drive signal selection information to the drive signal selection unit 202 by serial communication (referred to as first serial communication) using a predetermined transmission path. Serial communication refers to a communication method in which data is continuously transmitted and received one bit at a time using one or two transmission paths for transmitting and receiving data.

[0031] The drive signal generation unit 620 generates a plurality of drive signals based on the control signal output from the drive signal control unit 616, and outputs the generated drive signals to the drive signal selection unit 202. In this embodiment, the plurality of drive signals includes three types of drive signals (large ink droplet size, small ink droplet size, and no ink droplet ejection).

[0032] The drive signal selection unit 202 selects a drive signal to be output to the printhead 22 from among the multiple drive signals output from the drive signal generation unit 620, based on drive signal selection information output from the drive signal selection information transmission unit 618. The drive signal selected by the drive signal selection unit 202 is input to the piezoelectric element 502 corresponding to the nozzle 514 in the chip unit 206 of the printhead 22. As described above, when a voltage of the drive signal waveform is applied to the electrodes of the piezoelectric element 502, the piezoelectric element 502 between the electrodes is displaced, and the resulting energy causes ink to be ejected from the nozzle 514 (see FIG. 5).

[0033] The first serial communication establishes a connection between the drive signal selection information transmitter 618 and the drive signal selection unit 202, and the clk signal, data signal, and latch signal are transmitted from the drive signal selection information transmitter 618 to the drive signal selection unit 202. Specifically, information is transmitted on the data signal in synchronization with the clk, and information is transmitted in units of latch signals.

[0034] Further, the drive signal selection information transmitter 618 and the drive signal selector 202 are connected by a second serial communication that uses a transmission path different from the transmission path used for the first serial communication. The second serial communication is used for setting up the drive signal selector 202. Note that in this embodiment, a commonly known communication protocol such as SPI (Serial Peripheral Interface) is used for the second serial communication, but the communication method is not limited to this.

[0035] The recording head 22 includes nozzles 514 that eject ink and piezoelectric elements 502 that correspond to the nozzles. By inputting a drive signal to the piezoelectric elements 502, ink is ejected from the nozzles 514. In the following description, unless otherwise specified, the recording head 22 will be described as including 128 nozzles 514 and piezoelectric elements 502 that correspond to each nozzle 514, but the number of nozzles 514 may be any integer equal to or greater than two.

[0036] In the image processing unit 612, the image processing input unit 702 reads image data included in the print job stored in RAM 608 based on instructions from the CPU 615 and outputs it to the image generation unit 704 (see FIG. 7). The image generation unit 704 converts the received image data into CMYK four-channel image data at a resolution that can be printed by the print head 22, and outputs it to the output gradation correction processing unit 706. The output gradation correction processing unit 706 performs correction processing according to the ink output characteristics. The quantization processing 708 converts 8-bit to 16-bit gradation data into gradation data that can be expressed by the nozzles of the print head. Generally, N-value conversion is performed using an error diffusion method or a dither method, and the gradation is converted into 1-bit to 4-bit image data. The landing position deviation correction processing unit 710 shifts the data in pixel units to correct landing position deviation after the nozzles in units of image resolution. The image processing output unit 712 performs processing to output the image data that has undergone the above image processing to the RAM 608, and this image data is stored in the RAM 608.

[0037] <Outline of the configuration of the drive signal selection unit and drive signal generation unit> Next, we will explain the outline of the configuration of the drive signal selection unit 202 and the drive signal generation unit 620. Fig. 8 is a schematic diagram of the drive signal selection unit 202 and the drive signal generation unit 620. In the drive signal selection unit 202, data transmitted from the drive signal selection information transmission unit 618 via the first serial communication is received by a serial-to-parallel conversion unit 802, and is held in a data latch 804 starting from the input timing of the latch signal.

[0038] The drive signal generation unit 620 includes a plurality of digital-to-analog conversion units (hereinafter also referred to as "DACs (Digital to Analog Converters)") 806 and a plurality of drive signal generation circuits 808. The DACs 806 receive control signals from the drive signal control unit 616. The analog signals output from the DACs 806 are input to the drive signal generation circuits 808, which generate drive signals based on the input analog signals.

[0039] The drive signal generating circuit 808 outputs the generated drive signal to a switch group 810 provided in the drive signal selecting unit 202. The switch group 810 is provided for each of the piezoelectric elements 502 provided corresponding to each nozzle 514 provided in the recording head 22. The switch group 810 includes a plurality of switches SW x-y It is composed of SW x-y The "x" in SW corresponds to the nozzle number that identifies the nozzle 514. x-y The "y" in the above expression corresponds to a drive signal number that identifies the drive signal.

[0040] The switch group 810 selects a specific drive signal from the multiple drive signals output from the drive signal generation circuit 808 based on the decoded information of the decoder 812, and outputs the specific drive signal to the corresponding piezoelectric element 502. As described above, the print head 22 is equipped with a nozzle group including 128 nozzles 514, and piezoelectric elements 502 provided corresponding to each nozzle 514. For this reason, the drive signal selection unit 202 is provided with the same number of decoders 812 and switch groups 810 as the nozzles 514.

[0041] <First serial communication> Next, the first serial communication will be described. FIG. 9 shows the contents of the signal transmitted by the drive signal selection information transmission unit 618 via the first serial communication. As shown in FIG. 9, the data signal is transmitted in synchronization with the clk signal. The latch signal indicates the end of one transmission. The number of data signals does not need to be one; the number of data signals may be increased, taking into account the balance with the frequency of the clk signal, so as to enable ejection at a predetermined ink ejection frequency. Note that the "ink ejection frequency" refers to the number of times the recording head 22 ejects ink droplets per second.

[0042] In this embodiment, communication is performed so that data for one column, that is, data equivalent to the number of nozzles multiplied by the drive signal selection information (i.e., the number of drive signal types), can be transmitted between one latch signal and the next. For example, if there are four types of drive signals and 128 nozzles, 128 x 2 bits of data (meaning a selection from among four types of signals) are transmitted between latch signals. On the other hand, if there are four types of drive signals plus a switch for residual detection (described below), the sum of the number of drive signal types and the number of residual detection switches is 5 (= 4 + 1). Therefore, 128 x 3 bits of data (to select from five states) must be transmitted between latch signals.

[0043] <Timing chart of the drive signal selection section> Next, a timing chart of the drive signal selection unit will be described with reference to Fig. 10. Fig. 10 is a diagram showing the relationship between the data transmitted by the first serial communication and the drive signal. Drive signal selection information for one column is transferred between one latch signal and the next, and the received data is held in the data latch 804 (see Fig. 8) starting from the reception of the latch signal. Then, based on the data held in the data latch 804, one type of drive signal is selected from multiple types of drive signals and transmitted for each nozzle 514 (piezoelectric element 502).

[0044] For example, in the case of Figure 10, three types of drive signals are assumed. Therefore, in this case, there are three drive signal generation circuits 808 in Figure 8 (drive signal generation circuit 0, drive signal generation circuit 1, and drive signal generation circuit 2). Drive signals that can achieve desired ink droplet states, such as large ink droplet size, small ink droplet size, and no ink droplet ejection, are assigned to these three drive signal generation circuits 808. As shown in Figure 10, the drive signal that achieves the large ink droplet state is defined as "drive signal 0," the drive signal that achieves the small ink droplet state is defined as "drive signal 1," and the drive signal that achieves the no ink droplet ejection state is defined as "drive signal 2."

[0045] <Residual vibration detection circuit> Next, the residual vibration detection circuit will be described. Fig. 11 is a diagram showing the residual vibration voltage. Fig. 12 is a circuit diagram of the residual vibration detection circuit.

[0046] Among the switches included in the switch group 810 shown in FIG. x-0 From SW x-n (In this embodiment, x and n are each an integer value in the range of 0 to 127) is a switch for applying a drive signal to the piezoelectric element 502 corresponding to the nozzle x. x-z is a switch for supplying a residual vibration voltage generated in the piezoelectric element 502 due to the residual vibration after the piezoelectric element 502 is driven to a residual vibration detection circuit 814 (see FIG. 8).

[0047] As shown in FIG. 11, first, in section st1, a drive signal is applied to the piezoelectric element 502 to drive the piezoelectric element 502. After that, the switch is turned off to stop applying the drive signal to the piezoelectric element 502. Then, as shown in FIG. 11, in section st2, a voltage Amp-in appears in the piezoelectric element 502. This voltage Amp-in is generated when mechanical vibrations remaining in the piezoelectric element 502 are converted into voltage by the piezoelectric effect, and is called a "residual vibration voltage." By detecting and analyzing the residual vibration voltage, it is possible to detect abnormalities in each nozzle 514.

[0048] In the residual vibration detection circuit 814, the residual vibration voltage Amp-in is supplied to the non-inverting input terminal V+ of the operational amplifier OPAz via the switch SWx-z and the capacitor Ca (see FIG. 12). Also, in the residual vibration detection circuit 814, the non-inverting input terminal V+ of the operational amplifier OPAz is connected to a bias voltage Vbias via a resistor Rm. Meanwhile, the inverting input terminal V- of the operational amplifier OPAz is connected to the bias voltage Vbias via a resistor Rb. Also, the inverting input terminal V- of the operational amplifier OPAz is connected to the output terminal of the operational amplifier OPAz via a resistor Ra.

[0049] In this circuit configuration, the residual vibration voltage Amp-in is amplified to become a residual vibration detection voltage Vz in the residual vibration detection circuit 814. The residual vibration detection voltage Vz is expressed by the following equation.

[0050]

number

[0051] The residual vibration detection voltage Vz is output to the outside of the residual vibration detection circuit 814 (see FIG. 8). Thereafter, the residual vibration detection voltage Vz is converted into a digital signal by an analog-to-digital converter (not shown) and analyzed by a logical operation element (not shown).

[0052] <Drive signal generation circuit> Next, the drive signal generation circuit 808 will be described. Fig. 13 is a circuit diagram of the drive signal generation circuit 808. The drive signal generation circuit 808 is a so-called amplifier circuit, and amplifies the voltage and current of an analog signal 1304 supplied to a non-inverting input terminal V+ of an operational amplifier 1302. The drive signal generation circuit 808 includes Darlington-connected transistors 1306 and 1308 on the high side, Darlington-connected transistors 1310 and 1312 on the low side, and the operational amplifier 1302.

[0053] The transistors 1306 and 1308 are each npn transistors. The transistors 1310 and 1312 are each pnp transistors. The base terminal of the transistor 1308 and the base terminal of the transistor 1312 are each connected to the output terminal of the operational amplifier 1302 via a diode. The emitter terminal of the transistor 1306 and the emitter terminal of the transistor 1310 are each connected to the piezoelectric element 502 via a switch SWx-n (not shown in FIG. 13).

[0054] When an analog signal 1304 is input to the drive signal generation circuit 808, the voltage of the analog signal 1304 is amplified by the operational amplifier 1302. The current is then amplified by transistors 1306, 1308, and transistors 1310, 1312. The piezoelectric element 502 is then driven by the drive signal 1314, the voltage and current of which have been amplified by the drive signal generation circuit 808, causing ink to be ejected.

[0055] <Detailed configuration of the drive signal generation unit> Next, we will explain the detailed configuration of the drive signal generation unit 620. Fig. 14 is a diagram showing the detailed configuration of the drive signal generation unit 620. In the following explanation, we will explain an example in which eight drive signals are supplied to one recording head 22.

[0056] In the drive signal generation unit 620, four DACs 806 are arranged in parallel to generate eight drive signals for one recording head 22, and two drive signal generation circuits 808 are connected to each DAC 806, for a total of eight drive signal generation circuits 808. More specifically, the drive signal generation unit 620 includes DACs 806a, 806b, 806c, and 806d. In the following description and drawings, the DAC 806a will also be referred to as "DAC_0," the DAC 806b as "DAC_1," the DAC 806c as "DAC_2," and the DAC 806d as "DAC_3." In the drive signal generation unit 620, the drive signal generation circuits 808a and 808b are connected to the DAC 806a, and the drive signal generation circuits 808c and 808d are connected to the DAC 806b. Furthermore, drive signal generation circuits 808e and 808f are connected to the DAC 808c, and drive signal generation circuits 808g and 808h are connected to the DAC 808d.

[0057] The DAC806 is a circuit that converts a value set by a digital signal into an analog value and outputs it. Each DAC806 can output two analog signals, and it can receive input of DATA (a 10-bit parallel signal) for setting the output value, a selection signal A / B for selecting the setting of output signals OUT1 and OUT2, and a chip select signal CS. DATA, A / B, and CS will be output from the drive signal control unit 616. DATA and A / B are connected in parallel to DAC806a, 806b, 806c, and 806d. The drive signal generation unit 620 is configured to be able to control four DAC806s with a control signal for one DAC806.

[0058] CS is connected to each DAC806 individually. Specifically, CS0 is connected to DAC806a, CS1 is connected to DAC806b, CS2 is connected to DAC806c, and CS3 is connected to DAC806d. The output signals (OUT1, OUT2) from each DAC806 are input to the corresponding drive signal generation circuit 808 for each output signal. Specifically, OUT1 of DAC806a is input to drive signal generation circuit 808a, and OUT2 of DAC806a is input to drive signal generation circuit 808b. OUT1 of DAC806b is input to drive signal generation circuit 808c, and OUT2 of DAC806b is input to drive signal generation circuit 808d. OUT1 of DAC806c is input to drive signal generation circuit 808e, and OUT2 of DAC806c is input to drive signal generation circuit 808f. OUT1 of DAC806d is input to drive signal generation circuit 808g, and OUT2 of DAC806d is input to drive signal generation circuit 808h.

[0059] <Timing of DAC Control Signal> Next, the control signal timing of each DAC806 will be described. FIG. 15 is a diagram for explaining the control signal timing of DAC806. When A / B is at a high level, the DAC806 is set to output OUT1, and when A / B is at a low level, the DAC806 is set to output OUT2. At the rising edge of CS0, DAC806a (DAC_0 in the figure) latches the setting of DATA0. Also, at the rising edge of CS1, DAC806b (DAC_1 in the figure) latches the setting of DATA0. Further, at the rising edge of CS2, DAC806c (DAC_2 in the figure) latches the setting of DATA0. Furthermore, at the rising edge of CS3, DAC806d (DAC_3 in the figure) latches the setting of DATA0.

[0060] In this way, by sequentially setting the control signals of A / B, CS0, CS1, CS2, CS3, and DATA0, the output signals of each DAC806 are set in the following order. DAC806a·OUT1 → DAC806b·OUT1 → DAC806c·OUT1 → DAC806d·OUT1 → DAC806a·OUT2 → DAC806b·OUT2 → DAC806c·OUT2 → DAC806d·OUT2. After DAC806d·OUT2, it returns to DAC806a·OUT1, and the above-mentioned order is repeated. As a result, the timing of outputting the output signals from each DAC806 does not overlap. Note that the above order is an example, and the control signal timing of the DAC may be in an order different from the above.

[0061] <Output Control of DAC> Next, the output control of DAC806 will be described. FIG. 16 shows an example of the output waveform of the DAC. FIG. 17 is a diagram showing the relationship between the output value and time of each DAC806 when the output waveform in FIG. 16 is rising. FIG. 18 is a diagram showing the relationship between the output value and time of each DAC806 when the output waveform in FIG. 16 is falling. Note that in FIGS. 17 and 18, the dashed lines indicate the approximate curves of the DAC output values. In the description here, the case where each DAC is controlled so that OUT1 / OUT2 of each DAC806 all draw the output waveform shown in FIG. 16 will be described as an example.

[0062] As described above, the drive signal generation unit 620 is configured so that four DACs 806 are controlled by a control signal for one DAC 806. In other words, the drive signal generation unit 620 is configured so that the control signal output from the drive signal control unit 616 is shared by DACs 806a, 806b, 806c, and 806d. For this reason, the drive signal generation unit 620 switches the settings for each DAC 806 in sequence to form an output waveform as shown in FIG.

[0063] When the output waveform rises as shown at point A in FIG. 16, first, at timing (1) in FIG. 17(a), the output setting for OUT1 of DAC806a (DAC_0) is performed. Next, at timing (2) in FIG. 17(b), the output setting for OUT1 of DAC806b (DAC_1) is performed at an output value higher than the output value set immediately before at (1). Next, at timing (3) in FIG. 17(c), the output setting for OUT1 of DAC806c (DAC_2) is performed at an output value higher than the output value set immediately before at (2). Next, at timing (4) in FIG. 17(d), the output setting for OUT1 of DAC806d (DAC_3) is performed at an output value higher than the output value set immediately before at (3).

[0064] Next, at timing (5) in Figure 17(e), the OUT2 output of DAC 806a is set to an output value higher than the output value set immediately before at (4). Next, at timing (6) in Figure 17(f), the OUT2 output of DAC 806b is set to an output value higher than the output value set immediately before at (5). Next, at timing (7) in Figure 17(g), the OUT2 output of DAC 806c is set to an output value higher than the output value set immediately before at (6). Next, at timing (8) in Figure 17(h), the OUT2 output of DAC 806d is set to an output value higher than the output value set immediately before at (7).

[0065] Next, at timing (9) in Figure 17(a), the output of OUT1 of the DAC 806a is set to an output value higher than the output value set immediately before at (8). Similarly, thereafter, the output is set to a value higher than the output value set immediately before, in the order explained in the DAC control signal timing described above. In this way, when the output waveform rises, the output is set to a value higher than the output value set immediately before, by sequentially setting in the order of (1) to (40) in Figures 17(a) to (h).

[0066] Furthermore, when the output waveform is descending, as at point B in FIG. 16, first, at timing (1) in FIG. 18(a), the output setting for OUT1 of DAC806a (DAC_0) is made to be a lower output value than the output value set immediately before. Next, at timing (2) in FIG. 18(b), the output setting for OUT1 of DAC806b (DAC_1) is made to be a lower output value than the output value set immediately before at (1). Next, at timing (3) in FIG. 18(c), the output setting for OUT1 of DAC806c (DAC_2) is made to be a lower output value than the output value set immediately before at (2). Next, at timing (4) in FIG. 18(d), the output setting for OUT1 of DAC806d (DAC_3) is made to be a lower output value than the output value set immediately before at (3).

[0067] Next, at timing (5) in Figure 18(e), the OUT2 output of DAC 806a is set to an output value lower than the output value set immediately before at (4). Next, at timing (6) in Figure 18(f), the OUT2 output of DAC 806b is set to an output value lower than the output value set immediately before at (5). Next, at timing (7) in Figure 18(g), the OUT2 output of DAC 806c is set to an output value lower than the output value set immediately before at (6). Next, at timing (8) in Figure 18(h), the OUT2 output of DAC 806d is set to an output value lower than the output value set immediately before at (7).

[0068] Next, at timing (9) in FIG. 18(a), the output of OUT1 of the DAC 806a is set to an output value lower than the output value set immediately before at (8). Similarly, thereafter, the output is set to a value lower than the output value set immediately before, in the order explained in the DAC control signal timing described above. In this way, when the output waveform descends, the output is set to a value lower than the output value set immediately before, in the order of (1) to (40) in FIG. 18(a) to (h). Note that when the output waveform is constant, the output is set to the same output value as the output value set immediately before, in the order explained in the DAC control timing described above.

[0069] <Action and effect> As described above, in this embodiment, in a drive signal generation unit that generates multiple drive signals for one print head, a control signal for generating the drive signals is shared by multiple DACs, and each DAC outputs two output signals. This reduces the number of signal lines between the drive signal control unit that outputs the control signal and the drive signal generation unit that generates multiple drive signals based on the control signal compared to known techniques, making it possible to miniaturize the circuit board that includes the drive signal control unit and the drive signal generation unit. Furthermore, the reduction in signal lines simplifies the wiring on the circuit board, reducing manufacturing costs.

[0070] In addition, the output values ​​are set in sequence at different times for each DAC, so that when the output waveform is rising, the output value is set to a higher value than the output value set immediately before, and when the output waveform is falling, the output value is set to a lower value than the output value set immediately before. This reduces deviations in the output waveforms of each DAC output due to settings at different times.

[0071] (Second embodiment) Next, a recording device according to a second embodiment will be described with reference to Figures 19 and 20. In the following description, the same or corresponding components as those in the recording device according to the first embodiment will be denoted by the same reference numerals as those used in the first embodiment, and detailed description thereof will be omitted.

[0072] In the first embodiment described above, the drive signal generation unit 620 supplies multiple drive signals to one print head 22. In contrast, in the second embodiment, the drive signal generation unit supplies multiple drive signals to each of multiple print heads. The drive signal generation unit provided in the printing apparatus 10 according to this embodiment will be described in detail below.

[0073] <Detailed configuration of the drive signal generation unit> Fig. 19 is a diagram showing a detailed configuration of the drive signal generation unit 620 provided in the recording device 10 according to this embodiment. Note that the following explanation using Fig. 19 will be given taking as an example a case where eight drive signals are supplied to eight recording heads 22. Note that Fig. 19 shows the connection configuration of input signals to the DAC 806, and the output signals of each DAC and the drive signal generation circuit are not shown.

[0074] In this embodiment, 32 DACs 806 are arranged in the drive signal generation unit 620 to generate eight drive signals for each of the eight print heads 22. Specifically, eight groups are provided, each consisting of four DACs 806a, 806b, 806c, and 806d. In other words, one group is provided corresponding to one print head 22.

[0075] More specifically, the first group G1 includes DAC_0 as DAC806a, DAC_1 as DAC806b, DAC_2 as DAC806c, and DAC_3 as DAC806d. The second group G2 includes DAC_4 as DAC806a, DAC_5 as DAC806b, DAC_6 as DAC806c, and DAC_7 as DAC806d. The third group G3 includes DAC_8 as DAC806a, DAC_9 as DAC806b, DAC_10 as DAC806c, and DAC_11 as DAC806d. The fourth group G4 includes DAC_12 as DAC806a, DAC_13 as DAC806b, DAC_14 as DAC806c, and DAC_15 as DAC806d. The fifth group G5 includes DAC_16 as DAC806a, DAC_17 as DAC806b, DAC_18 as DAC806c, and DAC_19 as DAC806d. The sixth group G6 includes DAC_20 as DAC806a, DAC_21 as DAC806b, DAC_22 as DAC806c, and DAC_23 as DAC806d. The seventh group G7 includes DAC_24 as DAC806a, DAC_25 as DAC806b, DAC_26 as DAC806c, and DAC_27 as DAC806d. The eighth group G8 includes DAC_28 as DAC806a, DAC_29 as DAC806b, DAC_30 as DAC806c, and DAC_31 as DAC806d.

[0076] Although not shown in the figure, two drive signal generation circuits 808 are connected to each DAC, and each DAC outputs OUT1 or OUT2 to the respective drive signal generation circuits 808.

[0077] Also, for DATA, it is connected in parallel to the four DACs in each group. Specifically, DATA0 is connected to DAC_0, DAC_1, DAC_2, DAC_3 of the first group G1. DATA1 is connected to DAC_4, DAC_5, DAC_6, DAC_7 of the second group G2. DATA2 is connected to DAC_8, DAC_9, DAC_10, DAC_11 of the third group G3. DATA3 is connected to DAC_12, DAC_13, DAC_14, DAC_15 of the fourth group G4. DATA4 is connected to DAC_16, DAC_17, DAC_18, DAC_19 of the fifth group G5. DATA5 is connected to DAC_20, DAC_21, DAC_22, DAC_23 of the sixth group G6. DATA6 is connected to DAC_24, DAC_25, DAC_26, DAC_27 of the seventh group G7. DATA7 is connected to DAC_28, DAC_29, DAC_30, DAC_31 of the eighth group G8. For A / B, it is connected to all the DAC806.

[0078] CS is connected to the corresponding DAC in each group. Specifically, CS0 is connected to the DAC that is set first in each group. That is, CS0 is connected to DAC_0, DAC_4, DAC_8, DAC_12, DAC_16, DAC_20, DAC_24, DAC_28. CS1 is connected to the DAC that is set second in each group. That is, CS1 is connected to DAC_1, DAC_5, DAC_9, DAC_13, DAC_17, DAC_21, DAC_25, DAC_29. CS2 is connected to the DAC that is set third in each group. That is, CS2 is connected to DAC_2, DAC_6, DAC_10, DAC_14, DAC_18, DAC_22, DAC_26, DAC_30. CS3 is connected to the DAC that is set fourth in each group. That is, CS3 is connected to DAC_3, DAC_7, DAC_11, DAC_15, DAC_19, DAC_23, DAC_27, DAC_31.

[0079] <DAC Control Signal Timing> Next, we will explain the control signal timing of the DAC 806. Figure 20 is a diagram explaining the control timing of the DAC 806. When A / B is at a high level, the DAC 806 is set to output OUT1, and when A / B is at a low level, the DAC 806 is set to output OUT2.

[0080] At the rising edge of CS0, DAC_0 latches the DATA0 setting, DAC_4 latches the DATA1 setting, DAC_8 latches the DATA2 setting, DAC_12 latches the DATA3 setting, DAC_16 latches the DATA4 setting, DAC_20 latches the DATA5 setting, DAC_24 latches the DATA6 setting, and DAC_28 latches the DATA7 setting. At the rising edge of CS1, DAC_1 latches the DATA0 setting, DAC_5 latches the DATA1 setting, DAC_9 latches the DATA2 setting, DAC_13 latches the DATA3 setting, DAC_17 latches the DATA4 setting, DAC_21 latches the DATA5 setting, DAC_25 latches the DATA6 setting, and DAC_29 latches the DATA7 setting.

[0081] At the rising edge of CS2, DAC_2 latches the DATA0 setting, DAC_6 latches the DATA1 setting, DAC_10 latches the DATA2 setting, DAC_14 latches the DATA3 setting, DAC_18 latches the DATA4 setting, DAC_22 latches the DATA5 setting, DAC_26 latches the DATA6 setting, and DAC_30 latches the DATA7 setting. At the rising edge of CS3, DAC_3 latches the DATA0 setting, DAC_7 latches the DATA1 setting, DAC_11 latches the DATA2 setting, DAC_15 latches the DATA3 setting, DAC_19 latches the DATA4 setting, DAC_23 latches the DATA5 setting, DAC_27 latches the DATA6 setting, and DAC_31 latches the DATA7 setting.

[0082] In this way, for each of the 32 DAC806s, by sequentially setting the control signals of A / B, CS0, CS1, CS2, CS3, and DATA0~7, in each of the eight groups, the output signals of each DAC806 are set in the following order. DAC806a·OUT1 → DAC806b·OUT1 → DAC806c·OUT1 → DAC806d·OUT1 → DAC806a·OUT2 → DAC806b·OUT2 → DAC806c·OUT2 → DAC806d·OUT2. After DAC806d·OUT2, it returns to DAC806a·OUT1, and the above-mentioned order is repeated. As a result, in each group, the timing of outputting the output signal from each DAC806 does not overlap. Note that the above order is just an example, and the timing of the control signal of the DAC may be in an order different from the above-mentioned order.

[0083] <Output Control of DAC> Regarding the output control of DAC806, for each of the groups G1~G8, the output values of the four DAC806a, 806b, 806c, and 806d are set in the same manner as the output control of the DAC described in the first embodiment above. For the specific description of the output control of the DAC in each group, since it is the same as that in the first embodiment above, the description is omitted.

[0084] <Function and Effect> As described above, in this embodiment, in the drive signal generation unit that generates a plurality of drive signals for a plurality of recording heads, the control signal for generating the drive signal is shared by a plurality of DACs corresponding to each recording head. Also, output settings are sequentially performed at different timings among the plurality of DACs corresponding to one recording head. When the output waveform rises, the output value is set higher than the output value set immediately before, and when the output waveform falls, the output value is set lower than the output value set immediately before. As a result, the same function and effect as in the first embodiment are achieved.

[0085] (Other Embodiments) Note that the above-described embodiment may be modified as shown in the following (1) to (3).

[0086] (1) In the above embodiment, the recording device 10 is configured to record on a sheet-like recording medium unwound from a roll R, but this is not limited to this and the recording device 10 may be configured to record on a recording medium of a predetermined size stored in a cassette or the like.

[0087] (2) In the above embodiment, each DAC can output two analog signals and two drive signal generation circuits are connected to each DAC, but this is not limited to this. Each DAC may be capable of outputting three or more analog signals and three or more drive signal generation circuits may be connected to each DAC.

[0088] (3) The above embodiment and the various forms shown in (1) and (2) above may be combined as appropriate.

[0089] The disclosure of the above embodiment includes the following configurations and methods. (Configuration 1) a recording means for ejecting ink by driving a piezoelectric element to record; a generating means for generating a plurality of drive signals for driving the piezoelectric element, the drive signals including a plurality of digital-to-analog converters for converting digital signals into analog signals; a control unit that outputs a control signal to the generating unit for generating the drive signal and controls the generating unit to generate the drive signal; a selection means for selecting a specific drive signal from the plurality of drive signals generated by the generation means and outputting the selected drive signal to the recording means; In the generating means, the control signal is shared among the plurality of digital-to-analog conversion units; A recording apparatus characterized in that the output signals are output at different timings from the plurality of digital-to-analog converters. (Configuration 2) 2. The recording device according to claim 1, wherein each of the plurality of digital-to-analog converters outputs a plurality of analog signals. (Configuration 3) 3. The recording device according to configuration 2, wherein the plurality of digital-to-analog conversion sections share a selection signal for selecting an analog signal output. (Configuration 4) The recording device according to any one of configurations 1 to 3, wherein when the output value from the digital-to-analog conversion unit is increased, the generation means sets the output value output from the digital-to-analog conversion unit to an output value higher than the output value set immediately before. (Configuration 5) 5. The recording device according to any one of configurations 1 to 4, wherein when the output value from the digital-to-analog conversion unit is lowered, the generation means sets the output value output from the digital-to-analog conversion unit to an output value lower than the output value set immediately before. (Configuration 6) The recording means is provided in plurality, In the generating means, a predetermined number of digital-to-analog converters are connected to each of the plurality of recording means; 2. The recording device according to claim 1, wherein the control signal is shared for each group formed by the predetermined number of digital-to-analog conversion units. [Explanation of symbols]

[0090] 22 Recording head 202 drive signal selection unit 616 Drive signal control section 620 Drive signal generation unit 806 Digital-to-analog converter (DAC)

Claims

1. a recording means for ejecting ink by driving a piezoelectric element to record; a generating means for generating a plurality of drive signals for driving the piezoelectric element, the drive signals including a plurality of digital-to-analog converters for converting digital signals into analog signals; a control unit that outputs a control signal to the generating unit for generating the drive signal and controls the generating unit to generate the drive signal; a selection means for selecting a specific drive signal from the plurality of drive signals generated by the generation means and outputting the selected drive signal to the recording means; In the generating means, the control signal is shared among the plurality of digital-to-analog conversion units; A recording apparatus characterized in that the output signals are output at different timings from the plurality of digital-to-analog converters.

2. 2. The recording apparatus according to claim 1, wherein each of said plurality of digital-to-analog converters outputs a plurality of analog signals.

3. 3. The recording apparatus according to claim 2, wherein the plurality of digital-to-analog converters share a selection signal for selecting an analog signal output.

4. The recording device according to claim 1, characterized in that, when the output value from the digital-to-analog conversion unit is increased, the generation means sets the output value output from the digital-to-analog conversion unit to an output value higher than the output value set immediately before.

5. The recording device according to claim 1, characterized in that, when the output value from the digital-to-analog conversion unit is lowered, the generation means sets the output value output from the digital-to-analog conversion unit to an output value lower than the output value set immediately before.

6. The recording means is provided in plurality, In the generating means, a predetermined number of digital-to-analog converters are connected to each of the plurality of recording means; 2. The recording apparatus according to claim 1, wherein the control signal is shared by each group formed by the predetermined number of digital-to-analog conversion units.

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