Wired circuit board

Abstract

To provide a wiring circuit board capable of suppressing generation of burrs in a solder plating layer even when the surface of the solder plating layer is rubbed.SOLUTION: A wired circuit substrate 1 includes a circuit pattern 13 having terminals 131A, and a solder plating layer 15 disposed on the terminals 131A. The arithmetic average height Sa of the S1 of the solder plating layer 15 is 1.3 μm or less.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a printed circuit board. [Background technology]

[0002] BACKGROUND ART Conventionally, there has been known a wired circuit board that includes a conductor layer having terminals, a metal protective layer disposed on the surface of the terminals, and a conductive member disposed on the metal protective layer (see, for example, Patent Document 1 below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-029294 Summary of the Invention [Problem to be solved by the invention]

[0004] In the wired circuit board described in Patent Document 1, if the surface of the conductive member is rubbed, the surface of the conductive member may be scraped off, possibly resulting in burrs. An example of a case in which the surface of the conductive member is rubbed is when multiple sheets having wired circuit boards are stacked and transported.

[0005] The present invention provides a wired circuit board that can prevent burrs from being formed on a solder plating layer even when the surface of the solder plating layer is rubbed. [Means for solving the problem]

[0006] The present invention [1] includes a wired circuit board comprising a circuit pattern having terminals and a solder plating layer disposed on the terminals, wherein the arithmetic mean height Sa of the surface of the solder plating layer is 1.3 μm or less.

[0007] The present invention [2] includes the wired circuit board according to the above [1], wherein the arithmetic mean height Sa is 0.8 μm or less.

[0008] The present invention [3] includes the wired circuit board of [1] or [2] above, in which the terminal has a conductor layer made of copper and a coating layer that coats the conductor layer, the coating layer has a surface layer, and the solder plating layer is disposed on the surface layer and contains tin and silver.

[0009] The present invention [4] includes the wired circuit board according to the above [3], wherein the silver content in the solder plating layer is 1% by mass or more and less than 20% by mass.

[0010] The present invention [5] includes the wired circuit board according to the above [4], wherein the tin content in the solder plating layer is more than 80 mass %.

[0011] The present invention [6] includes the wired circuit board according to the above [3] or [4], wherein the surface layer is made of gold.

[0012] The present invention [7] comprises the wired circuit board of any one of the above [1] to [6], wherein the width of the terminal is 30 μm or less.

[0013] The present invention [8] includes the wired circuit board of any one of the above [1] to [7], further comprising a metal support layer and an insulating layer arranged on one side of the metal support layer in the thickness direction of the metal support layer, and the circuit pattern is arranged on one side of the insulating layer in the thickness direction. [Effects of the Invention]

[0014] According to the wired circuit board of the present invention, the arithmetic mean height Sa of the surface of the solder plating layer is 1.3 μm or less.

[0015] Therefore, even if the surface of the solder plating layer is rubbed, the surface of the solder plating layer can be prevented from being scraped off.

[0016] As a result, even if the surface of the solder plating layer is rubbed, the generation of burrs on the solder plating layer can be suppressed.

[0017] Furthermore, since the arithmetic mean height Sa of the surface of the solder plating layer is small, the thickness and volume of the solder plating layer can be made uniform. [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 1 is a plan view of a printed circuit board according to one embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view of the printed circuit board shown in FIG. 1 taken along the line AA. [Figure 3] Fig. 3A shows a first insulating layer forming step in the method for producing the wired circuit board shown in Fig. 2. Fig. 3B shows a pattern forming step following Fig. 3A. Fig. 3C shows a second insulating layer forming step following Fig. 3B. [Figure 4] Fig. 4A shows the opening formation step following Fig. 3C, Fig. 4B shows the coating layer formation step following Fig. 4A, and Fig. 4C shows the solder plating layer formation step following Fig. 4B. [Figure 5] FIG. 5 is an explanatory diagram illustrating a modified example of the printed circuit board. DETAILED DESCRIPTION OF THE INVENTION

[0019] 1. Wiring circuit board As shown in Fig. 1, the wired circuit board 1 extends in the length direction and width direction. In this embodiment, the wired circuit board 1 has a substantially rectangular shape. However, the shape of the wired circuit board 1 is not limited to this embodiment. The wired circuit board 1 may be a flexible wired circuit board or a circuit-equipped suspension board.

[0020] As shown in FIG. 2, the wired circuit board 1 includes a metal support layer 11, a first insulating layer 12, a circuit pattern 13, a second insulating layer 14, and a solder plating layer 15.

[0021] (1) Metal support layer The metal support layer 11 supports the first insulating layer 12, the circuit pattern 13, and the second insulating layer 14. Examples of materials for the metal support layer 11 include stainless steel and copper alloys. The metal support layer 11 has an opening 11A.

[0022] The opening 11A is disposed at one end in the length direction of the wired circuit board 1. The opening 11A extends in the width direction.

[0023] (2) First insulating layer The first insulating layer 12 is disposed on one side of the metal support layer 11 in the thickness direction of the metal support layer 11. The thickness direction is perpendicular to the length direction and width direction. The first insulating layer 12 is disposed on one surface of the metal support layer 11 in the thickness direction. The first insulating layer 12 is disposed between the metal support layer 11 and the circuit pattern 13 in the thickness direction. The first insulating layer 12 insulates the metal support layer 11 from the circuit pattern 13. Examples of resins include polyimide, maleimide, epoxy resin, polybenzoxazole, and polyester. Preferably, the first insulating layer 12 is made of polyimide. As shown in FIG. 1, the first insulating layer 12 has an opening 12A.

[0024] The opening 12A is disposed at one end in the length direction of the wired circuit board 1. The opening 12A extends in the width direction. The entire opening 12A communicates with the opening 11A of the metal support layer 11 (see FIG. 2).

[0025] (3) Circuit pattern 2, circuit pattern 13 is disposed on one side of first insulating layer 12 in the thickness direction. Circuit pattern 13 is disposed on one surface of first insulating layer 12 in the thickness direction. Circuit pattern 13 is disposed on the opposite side of first insulating layer 12 from metal support layer 11 in the thickness direction. The shape of circuit pattern 13 is not limited.

[0026] 1, the circuit pattern 13 has a plurality of terminals 131A and 131B, a plurality of terminals 132A and 132B, and a plurality of wirings 133A and 133B. Note that the number of terminals and the number of wirings are not limited.

[0027] (3-1) Terminals 131A, 131B The terminals 131A and 131B are arranged at one end of the wired circuit board 1 in the length direction. When the wired circuit board 1 is a suspension board with circuit, the terminals 131A and 131B are, for example, magnetic head connection terminals that are electrically connected to a magnetic head. In this embodiment, the terminals 131A and 131B are aligned in the width direction. The terminal 131B is arranged at a distance from the terminal 131A in the width direction. Each of the terminals 131A and 131B has, for example, a square land shape.

[0028] The width W (dimension in the width direction) of the terminal 131A is, for example, 30 μm or less, preferably 25 μm or less. If the width W of the terminal 131A is less than the above upper limit, it becomes difficult to form a solder layer on the terminal 131A by printing.

[0029] The width W of the terminal 131A is, for example, 5 μm or more, or preferably 15 μm or more.

[0030] As shown in FIG. 2, terminal 131A is disposed on one side of first insulating layer 12 in the thickness direction. Terminal 131A is disposed on one surface of first insulating layer 12 in the thickness direction. Specifically, one end of terminal 131A in the length direction is disposed within opening 12A (see FIG. 1) of first insulating layer 12. The other end of terminal 131A in the length direction is disposed on one surface of first insulating layer 12. Terminal 131A has a conductor layer 1311 and a covering layer 1312.

[0031] The conductor layer 1311 is made of copper.

[0032] The covering layer 1312 covers the surface of the conductor layer 1311. The covering layer 1312 is made of a metal different from that of the conductor layer 1311. The covering layer 1312 may be a single layer or multiple layers. The covering layer 1312 has a surface layer 1312A. The surface layer 1312A is made of, for example, gold. The surface layer 1312A is, for example, a gold-plated layer. The covering layer 1312 preferably has an intermediate layer 1312B. The intermediate layer 1312B is disposed between the conductor layer 1311 and the surface layer 1312A. The intermediate layer 1312B is made of a metal different from that of the conductor layer 1311 and the surface layer 1312A. The intermediate layer 1312B is preferably made of nickel. The intermediate layer 1312B is, for example, a nickel-plated layer.

[0033] The thickness T1 of the coating layer 1312 is, for example, 0.1 μm or more, preferably 0.2 μm or more, and for example, 5 μm or less, preferably 4 μm or less.

[0034] Furthermore, thickness T11 of surface layer 1312A is equal to or smaller than thickness T1 of coating layer 1312. When coating layer 1312 is made up of intermediate layer 1312B and surface layer 1312A, thickness T11 of surface layer 1312A is smaller than thickness T1 of coating layer 1312. When coating layer 1312 does not have intermediate layer 1312B and is made up of only surface layer 1312A, thickness T11 of surface layer 1312A is the same as thickness T1 of coating layer 1312. Thickness T11 of surface layer 1312A is, for example, 0.1 μm or more, preferably 0.2 μm or more, and for example, 4 μm or less, preferably 2 μm or less.

[0035] (3-2) Terminals 132A, 132B 1, the terminals 132A and 132B are arranged at the other end of the wired circuit board 1 in the length direction. In this embodiment, the terminals 132A and 132B are aligned in the width direction. The terminal 132B is arranged apart from the terminal 132A in the width direction. Each of the terminals 132A and 132B has, for example, a square land shape.

[0036] Terminal 132A is disposed on one side of first insulating layer 12 in the thickness direction. Terminal 132A is disposed on one surface of first insulating layer 12 in the thickness direction. Like terminal 131A, terminal 132A also has a conductor layer 1311 and a covering layer 1312.

[0037] The description of the terminal 132B is the same as the description of the terminal 132A, so the description of the terminal 132B will be omitted.

[0038] (3-3) Wiring One end of the wiring 133A is connected to the terminal 131 A. The other end of the wiring 133A is connected to the terminal 132 A. The wiring 133A electrically connects the terminal 131A and the terminal 132A.

[0039] One end of the wiring 133B is connected to the terminal 131 B. The other end of the wiring 133B is connected to the terminal 132 B. The wiring 133B electrically connects the terminal 131 B and the terminal 132B.

[0040] The wirings 133A and 133B are made of copper.

[0041] (4) Second insulating layer As shown in FIG. 2, the second insulating layer 14 is disposed on the first insulating layer 12 in the thickness direction. The second insulating layer 14 covers the circuit pattern 13. More specifically, the second insulating layer 14 covers the wirings 133A and 133B. The second insulating layer 14 does not cover the terminals 131A, 131B, 132A, and 132B. The second insulating layer 14 is made of a resin. Examples of resins include polyimide, maleimide, epoxy resin, polybenzoxazole, and polyester.

[0042] (5) Solder plating layer The solder plating layer 15 is disposed on the terminal 131A. The solder plating layer 15 is also disposed on the terminal 131B (see FIG. 1). The solder plating layer 15 is disposed on one side of the terminal 131A in the thickness direction. The solder plating layer 15 is disposed on one surface of the terminal 131A in the thickness direction. The solder plating layer 15 is disposed on the surface layer 1312A. The solder plating layer 15 is disposed away from the conductor layer 1311 in the thickness direction. The solder plating layer 15 contacts the coating layer 1312 but does not contact the conductor layer 1311.

[0043] The thickness T2 of the solder plating layer 15 is thicker than the thickness T1 of the coating layer 1312. The thickness T2 of the solder plating layer 15 is thicker than the thickness T11 of the surface layer 1312A. The thickness T2 of the solder plating layer 15 is, for example, 10 μm or more, or preferably 15 μm or more, and for example, 100 μm or less, or preferably 50 μm or less.

[0044] The ratio (T2 / T11) of the thickness T2 of the solder plating layer 15 to the thickness T11 of the surface layer 1312A of the coating layer 1312 is in the range of, for example, 10 or more, or preferably 20 or more, and for example, 300 or less, or preferably 100 or less.

[0045] If the ratio (T2 / T11) is less than the lower limit, when the surface layer 1312A of the coating layer 1312 is a gold-plated layer, the ratio of gold (surface layer 1312A) to tin in the solder-plated layer 15 becomes excessively high, resulting in an excessive rise in the melting temperature of the solder-plated layer 15. In this regard, if the ratio (T2 / T11) is equal to or greater than the lower limit, when the surface layer 1312A of the coating layer 1312 is a gold-plated layer, the rise in the melting temperature of the solder-plated layer 15 can be suppressed.

[0046] The solder plating layer 15 has a surface S1 and a contact surface S2 in the thickness direction.

[0047] The surface S1 is one surface in the thickness direction of the solder plating layer 15. The surface S1 is located on the opposite side of the contact surface S2 from the terminal 131A in the thickness direction.

[0048] The contact surface S2 is the other surface in the thickness direction of the solder plating layer 15. The contact surface S2 is disposed between the surface S1 and the terminal 131A in the thickness direction. The contact surface S2 comes into contact with the coating layer 1312 of the terminal 131A.

[0049] The arithmetic mean height Sa of the surface S1 of the solder plating layer 15 is 1.3 μm or less, preferably 0.8 μm or less. When the arithmetic mean height Sa of the surface S1 of the solder plating layer 15 is equal to or less than the above upper limit, scraping of the surface S1 of the solder plating layer 15 can be suppressed even when the surface S1 of the solder plating layer 15 is rubbed. As a result, the generation of burrs on the solder plating layer 15 can be suppressed. Furthermore, because the arithmetic mean height Sa of the surface S1 of the solder plating layer 15 is small, the thickness T2 of the solder plating layer 15 and the volume of the solder plating layer 15 can be made uniform.

[0050] There is no lower limit for the arithmetic mean height Sa of the surface S1 of the solder plating layer 15. The arithmetic mean height Sa of the surface S1 of the solder plating layer 15 is, for example, 0.1 μm or more. The arithmetic mean height Sa of the surface S1 of the solder plating layer 15 may be 0.

[0051] The arithmetic mean height Sa is defined in ISO 25178 and is measured by the method described in the examples below.

[0052] The solder plating layer 15 contains tin and silver. The solder plating layer 15 may contain a metal other than tin and silver. Examples of metals other than tin and silver include lead, copper, bismuth, indium, and zinc. The solder plating layer 15 is preferably made of a tin-silver alloy. In other words, the solder plating layer 15 is preferably made of tin and silver.

[0053] The melting temperature of the solder plating layer 15 is, for example, 200°C to 350°C, preferably 220°C to 300°C, and more preferably 220°C to 235°C.

[0054] The solder plating layer 15 has a Vickers hardness of, for example, 1 HV or more, or preferably 2 HV or more, and for example, 30 HV or less, or preferably 20 HV or less.

[0055] The tin content in the solder plating layer 15 is, for example, more than 80 mass %, preferably 85 mass % or more. When the tin content in the solder plating layer 15 is equal to or greater than the above lower limit, the melting properties of the solder plating layer 15 can be ensured.

[0056] The tin content in the solder plating layer 15 is, for example, 99 mass % or less, or preferably 98 mass % or less.

[0057] The tin content in the solder plating layer 15 is measured by the method described in the examples below.

[0058] The silver content in the solder plating layer 15 is lower than the tin content in the solder plating layer 15. The silver content in the solder plating layer 15 is, for example, 1 mass % or more, preferably 2 mass % or more. When the silver content in the solder plating layer 15 is equal to or more than the above lower limit, the arithmetic mean height Sa of the surface of the solder plating layer 15 can be reduced.

[0059] The silver content in the solder plating layer 15 is, for example, less than 20 mass %, preferably 15 mass % or less, and more preferably 10 mass % or less. When the silver content in the solder plating layer 15 is equal to or less than the upper limit, a decrease in the melting property of the solder plating layer 15 can be suppressed.

[0060] The silver content in the solder plating layer 15 can be measured by, for example, atomic absorption spectrometry.

[0061] 2. Manufacturing method of printed circuit board Next, a method for manufacturing the above-mentioned wired circuit board 1 will be described.

[0062] The method for manufacturing the wired circuit board 1 includes a first insulating layer forming process (see FIG. 3A), a pattern forming process (see FIG. 3B), a second insulating layer forming process (see FIG. 3C), an opening forming process (see FIG. 4A), a coating layer forming process (see FIG. 4B), a solder plating layer forming process (see FIG. 4C), and an exterior processing process (see FIG. 2).

[0063] (1) First insulating layer formation process As shown in FIG. 3A, in the first insulating layer forming step, a first insulating layer 12 is formed on a substrate M. The first insulating layer forming step is performed by roll-to-roll processing. That is, the first insulating layer 12 is formed on the substrate M pulled out from a first roll. The substrate M on which the first insulating layer 12 has been formed is taken up onto a second roll. The substrate M is made of the same material as the metal support layer 11 described above. Of the first insulating layer 12 formed in the first insulating layer forming step, the thickness of a first portion 121 in which an opening 12A (see FIG. 2) is formed is thinner than the thickness of a second portion 122 in which the opening 12A is not formed.

[0064] More specifically, in the first insulating layer forming step, first, a solution (varnish) of a photosensitive resin is applied onto the substrate M and dried to form a coating film of the photosensitive resin.

[0065] Next, the photosensitive resin coating is exposed and developed. The photosensitive resin coating is subjected to gradational exposure using, for example, a photomask having a light-shielding portion, a fully transparent portion, and a semi-transparent portion. The light-shielding portion faces the portion of the photosensitive resin coating where the first insulating layer 12 will not be formed. The semi-transparent portion faces the portion of the photosensitive resin coating where the first portion 121 will be formed. The fully transparent portion faces the portion of the photosensitive resin coating where the second portion 122 will be formed. The gradational exposure results in a first insulating layer 12 having the first portion 121 and the second portion 122.

[0066] The first portion 121 may be formed thinner than the second portion 122 by etching the first insulating layer 12.

[0067] (2) Pattern formation process The patterning step is performed after the first insulating layer formation step, and is performed by roll-to-roll.

[0068] As shown in Fig. 3B, in the pattern formation process, a conductive pattern 20 is formed on the first insulating layer 12. The conductive pattern 20 has conductive layers 1311 for the terminals 131A, 131B, 132A, and 132B, and wirings 133A and 133B. The conductive pattern 20 is made of copper. The conductive pattern 20 does not have a covering layer 1312.

[0069] More specifically, in the pattern forming step, a seed layer is first formed on one surface of the first insulating layer 12 and one surface of the substrate M in the thickness direction. The seed layer is formed by, for example, sputtering. Examples of materials for the seed layer include chromium, copper, nickel, titanium, and alloys thereof.

[0070] Next, a plating resist is attached to one surface in the thickness direction of the base material M. The plating resist covers the first insulating layer 12.

[0071] Next, the plating resist is exposed to light and developed, which removes the plating resist from the area where the conductive pattern 20 is to be formed, exposing the seed layer in the area where the conductive pattern 20 is to be formed. On the other hand, the plating resist remains in the area where the conductive pattern 20 is not to be formed.

[0072] Next, the conductive pattern 20 is formed on the exposed seed layer by electrolytic plating. After the electrolytic plating is completed, the plating resist is stripped off, and the seed layer exposed by the stripping of the plating resist is removed by etching.

[0073] (3) Second insulating layer formation process The second insulating layer forming step is performed after the pattern forming step, and is performed by roll-to-roll.

[0074] As shown in FIG. 3C, in the second insulating layer forming step, a second insulating layer 14 is formed on the first insulating layer 12.

[0075] More specifically, in the second insulating layer forming step, first, a photosensitive resin solution (varnish) is applied onto the conductive pattern 20, the first insulating layer 12, and the base material M, and then dried to form a photosensitive resin coating.

[0076] Next, the photosensitive resin coating is exposed to light and developed, thereby forming the second insulating layer 14 on the first insulating layer 12.

[0077] (4) Opening formation process The opening forming step is performed after the second insulating layer forming step, and is performed by roll-to-roll.

[0078] As shown in FIG. 4A, in the opening forming step, openings 11A are formed in the base material M, and openings 12A are formed in the first insulating layer 12.

[0079] More specifically, in the opening forming step, an etching resist is attached to the other surface of the base material M in the thickness direction.

[0080] Next, the etching resist is exposed to light and developed, whereby the etching resist is removed from the portion where the opening 11A is to be formed, exposing the substrate M in the portion where the opening 11A is to be formed. On the other hand, the etching resist remains in the portion where the opening 11A is not to be formed.

[0081] Next, the base material M exposed from the etching resist is etched to form the opening 11 A. By forming the opening 11 A in the base material M, the first insulating layer 12 is exposed in the opening 11 A.

[0082] Next, the first insulating layer 12 exposed in the opening 11A is etched. By etching the first insulating layer 12 exposed in the opening 11A, an opening 12A is formed in the first insulating layer 12.

[0083] (5) Covering layer formation process The coating layer forming step is performed after the opening forming step, and is performed by roll-to-roll.

[0084] As shown in FIG. 4B, in the coating layer forming step, a coating layer 1312 is formed on the conductor layer 1311.

[0085] More specifically, in the coating layer forming step, first, plating resists are attached to one surface of the base material M in the thickness direction and the other surface of the base material M in the thickness direction.

[0086] Next, the plating resist is exposed and developed, whereby the plating resist covering the terminals 131A, 131B, 132A, and 132B is removed, exposing the terminals 131A, 131B, 132A, and 132B.

[0087] Next, for example, electroless nickel plating and electroless gold plating are carried out in sequence to form coating layers 1312 consisting of intermediate layers 1312B (nickel-plated layers) and surface layers 1312A (gold-plated layers) on each of the terminals 131A, 131B, 132A, and 132B.

[0088] Intermediate layer 1312B (nickel plated layer) may be formed by electrolytic nickel plating, and surface layer 1312A (gold plated layer) may be formed by electrolytic gold plating.

[0089] After the coating layer forming step is completed, the plating resist is stripped off.

[0090] (6) Solder plating layer formation process The solder plating layer forming step is performed after the coating layer forming step, and is performed in a roll-to-roll manner.

[0091] As shown in FIG. 4C, in the solder plating layer forming step, a solder plating layer 15 is formed on the coating layer 1312.

[0092] Specifically, in the solder plating layer forming step, first, a plating resist is attached to one surface of the substrate M in the thickness direction. Next, a plating resist is attached to the other surface of the substrate M in the thickness direction. Note that, instead of the plating resist, an insulating low-adhesion film may be attached to the other surface of the substrate M in the thickness direction.

[0093] Next, the plating resist is exposed to light and developed, whereby the plating resist is removed from the portion where the solder plating layer 15 is to be formed, exposing one surface of each of the terminals 131A and 131B in the thickness direction.

[0094] Next, a solder plating layer 15 is formed on each of the coating layers 1312 of the exposed terminals 131A and 131B by electrolytic plating or electroless plating.

[0095] The solder plating solution used in the solder plating layer formation process is prepared by mixing a tin (Sn) element solution and a silver (Ag) element solution with a free acid solution in a ratio sufficient to obtain the desired solder plating layer. The solder plating solution may contain known additives in addition to the tin (Sn) element solution and the silver (Ag) element solution. The proportion of tin and the proportion of silver in the solder plating layer 15 can be adjusted by changing the ratio of the tin (Sn) element solution to the silver (Ag) element solution. When the solder plating layer 15 is formed by electroplating, the proportion of tin and the proportion of silver in the solder plating layer 15, and the arithmetic mean height Sa of the surface S1 of the solder plating layer 15 can be adjusted by changing the current density.

[0096] After the solder plating layer formation process is completed, the plating resist is peeled off.

[0097] (7) External shape processing process The outer shaping process is carried out after the solder plating layer formation process and is performed on a roll-to-roll basis.

[0098] As shown in FIG. 4C and FIG. 2, in the contour processing step, the substrate M is etched to form the metal support layer 11.

[0099] In this way, the above-described wired circuit board 1 is obtained.

[0100] 3. Effects According to the wired circuit board 1, the arithmetic mean height Sa of the surface S1 of the solder plating layer 15 is 1.3 μm or less.

[0101] Therefore, even if the surface S1 of the solder plating layer 15 is rubbed, the surface S1 of the solder plating layer 15 can be prevented from being scraped off.

[0102] As a result, even if the surface S1 of the solder plating layer 15 is rubbed, the occurrence of burrs on the solder plating layer 15 can be suppressed.

[0103] Furthermore, since the arithmetic mean height Sa of the surface S1 of the solder plated layer 15 is small, the thickness T2 of the solder plated layer 15 and the volume of the solder plated layer 15 can be made uniform.

[0104] 4. Variations In the modified example, the same components as those in the above-described embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

[0105] (1) As shown in Fig. 5, one end of terminal 131A in the length direction may be disposed on one edge of opening 12A in the length direction. In other words, terminal 131A may be disposed across opening 12A.

[0106] (2) The metal support layer 11 does not necessarily have to have the opening 11A. The first insulating layer 12 does not necessarily have to have the opening 12A.

[0107] (3) The wired circuit board 1 does not necessarily have to have the metal support layer 11.

[0108] (4) The steps of the method for producing the wired circuit board 1 are not limited to being performed by roll-to-roll. Each step may be performed on the substrate M in sheet form. [Example]

[0109] The present invention will be described in more detail below with reference to examples and comparative examples. It should be noted that the present invention is not limited to these examples and comparative examples. The specific numerical values ​​of the blending ratios (content ratios), physical property values, parameters, etc. used in the following description can be substituted with the upper limit (a numerical value defined as "equal to or less than") or lower limit (a numerical value defined as "equal to or more than" or "exceeding") of the corresponding blending ratios (content ratios), physical property values, parameters, etc. described in the "Description of the Invention" above.

[0110] 1. Manufacturing of printed circuit boards (1) Example 1 A photosensitive polyimide solution (varnish) was applied to a stainless steel substrate and dried to form a photosensitive polyimide coating.

[0111] Next, the photosensitive polyimide coating was exposed to light and developed to form a first insulating layer on the substrate (first insulating layer forming step, see FIG. 3A).

[0112] Next, a conductor pattern made of copper was formed on the first insulating layer by electrolytic plating (pattern forming step, see FIG. 3B).

[0113] Next, a second insulating layer was formed on the first insulating layer in the same manner as the first insulating layer (second insulating layer forming step, see FIG. 3C).

[0114] Next, openings were formed in the base material and the first insulating layer by etching (opening forming step, see FIG. 4A).

[0115] Next, electrolytic nickel plating and electrolytic gold plating were carried out in this order to form a coating layer consisting of a nickel plating layer and a gold plating layer on the conductor layer of the terminal (coating layer forming step, see FIG. 4B).

[0116] Next, a solder plating solution was prepared by mixing the tin element solution and the silver element solution with the free acid solution, and a solder plating layer was formed on the gold plating layer of the coating layer by electroplating at the current density shown in Table 1 (solder plating layer formation process, see Figure 4C).

[0117] Next, the substrate was shaped by etching to obtain an assembly sheet having a plurality of wiring circuit boards.

[0118] (2) Examples 2 to 4 and Comparative Example An assembly sheet having a plurality of wiring circuit boards was obtained in the same manner as in Example 1, except that electrolytic plating was performed at the current density shown in Table 1 in the solder plating layer forming step.

[0119] 2. Measurement of the arithmetic mean height Sa of the solder plating layer surface One wiring circuit board was selected from the assembly sheet obtained in Example 1, and the arithmetic mean height Sa of the surface of the solder plating layer was measured for each of the 10 terminals of the wiring circuit board using a laser microscope (manufactured by Keyence Corporation).

[0120] The maximum value of the measured arithmetic mean height Sa was taken as the arithmetic mean height Sa of the wired circuit board obtained in Example 1.

[0121] Furthermore, in the assembly sheets obtained in Examples 2 to 4 and the Comparative Example, the arithmetic mean height Sa of the wired circuit board was measured in the same manner as in Example 1.

[0122] The arithmetic mean height Sa obtained is shown in Table 1.

[0123] 3. Shaking test Ten of the assembly sheets obtained in Example 1 were stacked in a container with the metal support layer and the solder plating layer facing each other. When placed in the container, the ten assembly sheets were stacked vertically.

[0124] Next, the sample was shaken horizontally at a frequency of 80 Hz for 15 minutes.

[0125] After shaking, 60 wiring circuit boards were selected from the assembly sheet and examined with an optical microscope to see whether burrs had formed on the solder plating layer.

[0126] Furthermore, in the same manner as in Example 1, it was confirmed whether or not burrs had occurred on the solder plating layer of the assembly sheets obtained in each of Examples 2 to 4 and the comparative example.

[0127] The evaluation was carried out according to the following evaluation criteria.

[0128] A: The burr rate is 1% or less.

[0129] B: The burr occurrence rate is more than 1% and less than 5%.

[0130] C: Burr occurrence rate exceeds 5%.

[0131] [Table 1] [Explanation of symbols]

[0132] 1 Wiring circuit board 11 Metal support layer 12 First insulating layer (insulating layer) 13 Circuit Pattern 131A terminal 1311 Conductor layer 1312 Covering layer 1312A Surface layer 15 Solder plating layer S1 Solder plating layer surface

Claims

1. a circuit pattern having terminals; a solder plating layer disposed on the terminal; Equipped with The solder plating layer has an arithmetic mean surface height Sa of 1.3 μm or less.

2. 2. The wired circuit board according to claim 1, wherein the arithmetic mean height Sa is 0.8 [mu]m or less.

3. the terminal has a conductor layer made of copper and a coating layer that coats the conductor layer, The coating layer has a surface layer, The printed circuit board according to claim 1 , wherein the solder plating layer is disposed on the surface layer and contains tin and silver.

4. 4. The wired circuit board according to claim 3, wherein the silver content in the solder plating layer is 1% by mass or more and less than 20% by mass.

5. 5. The printed circuit board according to claim 4, wherein the solder plating layer has a tin content of more than 80 mass %.

6. The printed circuit board according to claim 3 , wherein the surface layer is made of gold.

7. 2. The printed circuit board according to claim 1, wherein the terminals have a width of 30 [mu]m or less.

8. a metal support layer; an insulating layer disposed on one side of the metal support layer in a thickness direction of the metal support layer; Furthermore, The printed circuit board according to claim 1 , wherein the circuit pattern is disposed on one side of the insulating layer in the thickness direction.

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