Signal transmission device, electronic device, and vehicle

Abstract

The signal transmission device has room for further consideration regarding drive control of the switch to be driven.SOLUTION: The signal transmission device 200X includes a transmission-side circuit 410, a reception-side circuit 420, an insulating circuit 430, and a protection circuit 440 configured to monitor the SAT voltage of the switch SW1 during on-periods Ton and Tson of the switch SW1. The reception-side circuit 420 includes a first drive circuit 426, a second drive circuit 502, and a drive control circuit 429. The protection circuit 440 starts to monitor the SAT voltage after the first blank period SW1 elapses from the start point of the transition period of the drive object switch TB1 when the first drive circuit 426 is enabled and the second drive circuit 502 is disabled, and starts to monitor the SAT voltage after the second blank period TB1 longer than the first blank period TB2 elapses from the start point when the first drive circuit 426 is disabled and the second drive circuit 502 is disabled.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The invention disclosed herein relates to a signaling device, an electronic device, and a vehicle. [Background technology]

[0002] BACKGROUND ART Signal transmission devices that transmit pulse signals while insulating input and output have been used in a variety of applications (such as power supply devices or motor drive devices).

[0003] As an example of the related prior art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2017-188903

[0005] [overview] The signal transmission device disclosed in Patent Document 1 leaves room for further consideration regarding drive control of the switch to be driven.

[0006] The signal transmission device disclosed in this specification includes a transmitter circuit, a receiver circuit, an isolation circuit, and a protection circuit. The transmitter circuit is configured to output a first internal signal and a second internal signal that pulse-drive in response to a first input signal. The receiver circuit is configured to output a drive signal in response to the first internal signal and the second internal signal to drive and control a switch to be driven. The isolation circuit is configured to transmit the first internal signal and the second internal signal while providing insulation between the transmitter circuit and the receiver circuit. The protection circuit is configured to monitor the SAT voltage of the switch to be driven during an on-period of the switch to be driven. The transmitter circuit drives at least one of the first internal signal and the second internal signal in response to a second input signal different from the first input signal, at a specific period different from the period of the first input signal. The receiving circuit includes a first drive circuit configured, when the receiving circuit is enabled, to generate a drive signal based on the first input signal to drive and control the switch to be driven, a second drive circuit configured, when the receiving circuit is enabled, to generate a drive signal to drive the switch to be driven slower than the first drive circuit to drive the switch to be driven, and a drive control circuit configured, when the receiving circuit is enabled, to detect that the period of at least one of the first internal signal and the second internal signal is a specific period, to disable the first drive circuit and enable the second drive circuit.The protection circuit is a signal transmission device that, based on the first input signal and the second input signal, starts monitoring the SAT voltage after a first blanking period has elapsed from the start of a transition period from an OFF state to an ON state or an ON state to an OFF state of the switch to be driven when the first drive circuit is enabled and the second drive circuit is disabled, and starts monitoring the SAT voltage after a second blanking period longer than the first blanking period has elapsed from the start of the transition period from an OFF state to an ON state or an ON state to an OFF state when the first drive circuit is disabled and the second drive circuit is disabled.

[0007] The electronic device disclosed in this specification includes a signal transmission device having the above-described configuration, a control circuit configured to generate a first input signal and a second input signal, and a drive target switch.

[0008] The vehicle disclosed in this specification is equipped with the electronic device having the above-described configuration. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing the basic configuration of a signal transmission device. [Figure 2] FIG. 2 is a diagram showing the basic structure of a transformer chip. [Figure 3] FIG. 3 is a perspective view of a semiconductor device used as a two-channel transformer chip. [Figure 4] FIG. 4 is a plan view of the semiconductor device shown in FIG. [Figure 5] FIG. 5 is a plan view showing a layer in which a low potential coil is formed in the semiconductor device of FIG. [Figure 6] FIG. 6 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 8] FIG. 8 is an enlarged view (isolation structure) of region XIII shown in FIG. [Figure 9] FIG. 9 is a diagram schematically illustrating an example of the layout of a transformer chip. [Figure 10] FIG. 10 is a diagram showing the basic configuration of an electronic device 400 in which the signal transmitter 200 and the signal transmitter L are mounted. [Figure 11] FIG. 11 is a diagram showing the internal configuration of a signal transmission device 200X according to the present disclosure. [Figure 12] FIG. 12 is a diagram showing the detailed configuration of the logic circuits 416 and 429. [Figure 13] FIG. 13 is a timing chart showing the timing of drive control of the drive target switch SW1 using the signal transmission device 200X. [Figure 14] FIG. 14 is a table showing the setting states of the first blanking period TB1 and the second blanking period TB2. [Figure 15] FIG. 15 is a block diagram showing an implementation example of a signal transmission device 200X of the present disclosure. [Figure 16]FIG. 16 is a diagram showing a vehicle A equipped with an electronic device 400. As shown in FIG.

[0010] [Detailed explanation] <Signal transmission device (basic configuration)> 1 is a diagram showing the basic configuration of a signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 200p to the secondary circuit system 200s while insulating the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system) and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is configured by sealing a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0011] The controller chip 210 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC1 (for example, up to 7 V with respect to GND1). The controller chip 210 has integrated therein, for example, a pulse transmission circuit 211 and buffers 212 and 213.

[0012] The pulse transmitting circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmitting circuit 211 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputting a single or multiple transmission pulses), and when it notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. That is, the pulse transmitting circuit 211 pulse-drives either the transmission pulse signals S11 or S21 in response to the logic level of the input pulse signal IN.

[0013] The buffer 212 receives the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).

[0014] The buffer 213 receives the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).

[0015] The driver chip 220 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC2 (for example, up to 30 V with respect to GND2). The driver chip 220 has buffers 221 and 222, a pulse receiving circuit 223, and a driver 224 integrated therein.

[0016] The buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically, the transformer 231) and outputs the result to the pulse receiving circuit 223.

[0017] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically, the transformer 232) and outputs the result to the pulse receiving circuit 223.

[0018] The pulse receiving circuit 223 generates the output pulse signal OUT by driving the driver 224 in response to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 so that the output pulse signal OUT rises to a high level in response to the pulse driving of the received pulse signal S12, and the output pulse signal OUT falls to a low level in response to the pulse driving of the received pulse signal S22. In other words, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT in response to the logic level of the input pulse signal IN. Note that an RS flip-flop, for example, can be suitably used as the pulse receiving circuit 223.

[0019] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223 .

[0020] The transformer chip 230 provides DC insulation between the controller chip 210 and the driver chip 220 using transformers 231 and 232, and outputs transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 as reception pulse signals S12 and S22, respectively, to the pulse reception circuit 223. In this specification, "DC-insulated" means that the objects to be insulated are not connected by a conductor.

[0021] More specifically, the transformer 231 outputs a reception pulse signal S12 from the secondary coil 231s in response to a transmission pulse signal S11 input to the primary coil 231p, while the transformer 232 outputs a reception pulse signal S22 from the secondary coil 232s in response to a transmission pulse signal S21 input to the primary coil 232p.

[0022] In this way, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to the rise signal and fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0023] In addition, the signal transmission device 200 of this configuration example has an independent transformer chip 230 equipped with only transformers 231 and 232, in addition to the controller chip 210 and the driver chip 220, and these three chips are sealed in a single package.

[0024] With this configuration, the controller chip 210 and the driver chip 220 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), thereby enabling reduction in manufacturing costs.

[0025] The signal transmission device 200 can be suitably used, for example, in a power supply device or a motor drive device for on-board equipment mounted in a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs) / plug-in hybrid vehicles (PHVs), or xEVs such as fuel cell electric vehicles (FCEVs) / FCVs (fuel cell electric vehicles)).

[0026] <Transformer chip (basic structure)> Next, the basic structure of transformer chip 230 will be described. Fig. 2 is a diagram showing the basic structure of transformer chip 230. In transformer chip 230 shown in this figure, transformer 231 includes primary coil 231p and secondary coil 231s that face each other in the vertical direction. Transformer 232 includes primary coil 232p and secondary coil 232s that face each other in the vertical direction.

[0027] The primary coils 231p and 232p are both formed on a first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed on a second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is disposed directly above the primary coil 231p and faces the primary coil 231p. The secondary coil 232s is disposed directly above the primary coil 232p and faces the primary coil 232p.

[0028] The primary coil 231p is laid spirally, starting from a first end connected to the internal terminal X21, so as to surround the periphery of the internal terminal X21 in a clockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. Meanwhile, the primary coil 232p is laid spirally, starting from a first end connected to the internal terminal X23, so as to surround the periphery of the internal terminal X23 in a counterclockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. The internal terminals X21, X22, and X23 are linearly arranged in the order shown in the figure.

[0029] The internal terminal X21 is connected to the external terminal T21 on the second layer 230b via a conductive wiring Y21 and a via Z21. The internal terminal X22 is connected to the external terminal T22 on the second layer 230b via a conductive wiring Y22 and a via Z22. The internal terminal X23 is connected to the external terminal T23 on the second layer 230b via a conductive wiring Y23 and a via Z23. The external terminals T21 to T23 are arranged linearly and are used for wire bonding with the controller chip 210.

[0030] The secondary coil 231s is laid in a spiral shape, starting from a first end connected to the external terminal T24 and surrounding the external terminal T24 in a counterclockwise direction, with a second end corresponding to the end point connected to the external terminal T25. Meanwhile, the secondary coil 232s is laid in a spiral shape, starting from a first end connected to the external terminal T26 and surrounding the external terminal T26 in a clockwise direction, with a second end corresponding to the end point connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure, and are used for wire bonding with the driver chip 220.

[0031] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, and are DC-insulated from the primary coils 231p and 232p, respectively. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-insulated from the controller chip 210 by the transformer chip 230.

[0032] <Transformer chip (2-channel type)> FIG. 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device 5 shown in FIG. 3. FIG. 5 is a plan view showing a layer in which a low-potential coil 22 (corresponding to the primary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 6 is a plan view showing a layer in which a high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is an enlarged view of region XIII shown in FIG. 7, showing an isolation structure 130.

[0033] 3 to 7, semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. Semiconductor chip 41 includes at least one of silicon, a wide bandgap semiconductor, and a compound semiconductor.

[0034] The wide bandgap semiconductor is a semiconductor with a bandgap greater than that of silicon (approximately 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or greater. The wide bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0035] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may also be an epitaxial substrate having a layered structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0036] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0037] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0038] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0039] The insulating side walls 53A to 53D include a first insulating side wall 53A, a second insulating side wall 53B, a third insulating side wall 53C, and a fourth insulating side wall 53D. The insulating side walls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip side walls 44A to 44D. Specifically, the insulating side walls 53A to 53D are formed flush with the chip side walls 44A to 44D. The insulating side walls 53A to 53D form ground surfaces that are flush with the chip side walls 44A to 44D.

[0040] The insulating layer 51 has a multilayer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and a plurality of (11 in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The top insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 also has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0041] Each of the multiple interlayer insulating layers 57 has a stacked structure including a first insulating layer 58 on the side of the bottom insulating layer 55 and a second insulating layer 59 on the side of the top insulating layer 56. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, approximately 0.3 μm).

[0042] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, approximately 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0043] The total thickness DT of the insulating layers 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of stacked interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0044] The semiconductor device 5 includes a first functional device 45 formed on an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (corresponding to the aforementioned transformers). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed inside the insulating layer 51 at intervals from the insulating side walls 53A to 53D. The multiple transformers 21 are formed at intervals in the first direction X.

[0045] Specifically, the multiple transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating side wall 53C side toward the insulating side wall 53D side in a plan view. The multiple transformers 21A to 21D each have a similar structure. The following description will be given using the structure of the first transformer 21A as an example. The description of the structure of the first transformer 21A applies mutatis mutandis to the structures of the second transformer 21B, third transformer 21C, and fourth transformer 21D, and will be omitted.

[0046] 5 to 7, the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed in an insulating layer 51. The high-potential coil 23 is formed in the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in a region sandwiched between a lowermost insulating layer 55 and an uppermost insulating layer 56 (i.e., a plurality of interlayer insulating layers 57).

[0047] The low-potential coil 22 is formed on the side of the lowest insulating layer 55 (semiconductor chip 41) within the insulating layer 51, and the high-potential coil 23 is formed on the side of the highest insulating layer 56 (insulating main surface 52) relative to the low-potential coil 22 within the insulating layer 51. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 sandwiched between them. The low-potential coil 22 and the high-potential coil 23 may be disposed in any desired locations. Furthermore, it is sufficient that the high-potential coil 23 faces the low-potential coil 22 with one or more interlayer insulating layers 57 sandwiched between them.

[0048] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57) is adjusted appropriately depending on the dielectric strength and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed on the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. In this embodiment, the high-potential coil 23 is formed on the first interlayer insulating layer 57 counting from the top insulating layer 56 side.

[0049] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 that is wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape that extends in an elliptical shape (oval shape) in a plan view. The portion that forms the innermost periphery of the first spiral portion 26 defines a first inner region 66 that is elliptical in a plan view.

[0050] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0051] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the shapes shown in Fig. 5 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0052] The low-potential coil 22 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a layered structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0053] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape that extends in an elliptical (oval) shape in a planar view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 that is elliptical in a planar view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0054] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. The number of turns of the second helical portion 29 preferably exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26 or may be equal to the number of turns of the first helical portion 26.

[0055] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0056] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0057] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in Fig. 6 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the second spiral portion 29.

[0058] The high-potential coil 23 is preferably formed from the same conductive material as the low-potential coil 22. That is, like the low-potential coil 22, the high-potential coil 23 preferably includes a barrier layer and a main body layer.

[0059] 4, the semiconductor device 5 includes a plurality of (12 in this figure) low potential terminals 11 and a plurality of (12 in this figure) high potential terminals 12. The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0060] The plurality of low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the plurality of low potential terminals 11 are formed in an area on the insulating sidewall 53B side at intervals in the second direction Y from the plurality of transformers 21A to 21D, and are arranged at intervals in the first direction X.

[0061] The plurality of low potential terminals 11 include a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E, and a sixth low potential terminal 11F. In this embodiment, two of each of the plurality of low potential terminals 11A to 11F are formed. The number of the plurality of low potential terminals 11A to 11F is arbitrary.

[0062] The first low potential terminal 11A faces the first transformer 21A in the second direction Y in plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in plan view.

[0063] The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

[0064] The fifth low potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). The sixth low potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low potential coil 22) and the first outer end 25 of the fourth transformer 21D (low potential coil 22).

[0065] The plurality of high potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the plurality of low potential terminals 11. Specifically, the plurality of high potential terminals 12 are formed in an area on the insulating sidewall 53A side at intervals from the plurality of low potential terminals 11 in the second direction Y, and are arranged at intervals in the first direction X.

[0066] The multiple high potential terminals 12 are each formed in an area close to the corresponding transformer 21A to 21D in a plan view. The high potential terminals 12 being close to the transformers 21A to 21D means that the distance between the high potential terminal 12 and the transformer 21 in a plan view is less than the distance between the low potential terminal 11 and the high potential terminal 12.

[0067] Specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D along the first direction X in a plan view. More specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0068] The plurality of high potential terminals 12 include a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E, and a sixth high potential terminal 12F. In this embodiment, two of each of the plurality of high potential terminals 12A to 12F are formed. The number of the plurality of high potential terminals 12A to 12F is arbitrary.

[0069] The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in a plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in a plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in a plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in a plan view. The fifth high potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0070] The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

[0071] The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).

[0072] 5 to 7, the semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34, each formed in an insulating layer 51. In this embodiment, a plurality of first low potential wirings 31, a plurality of second low potential wirings 32, a plurality of first high potential wirings 33, and a plurality of second high potential wirings 34 are formed.

[0073] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. The first low-potential wiring 31 and the second low-potential wiring 32 also fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all of the low-potential coils 22 of the transformers 21A to 21D to the same potential.

[0074] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. The first high-potential wiring 33 and the second high-potential wiring 34 also fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 21A to 21D to the same potential.

[0075] The plurality of first low potential wirings 31 are electrically connected to the corresponding low potential terminals 11A-11D and the first inner ends 24 of the corresponding transformers 21A-21D (low potential coils 22), respectively. The plurality of first low potential wirings 31 have the same structure. In the following, the structure of the first low potential wiring 31 connected to the first low potential terminal 11A and the first transformer 21A will be described as an example. The description of the structure of the first low potential wiring 31 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first low potential wirings 31, and will not be repeated here.

[0076] The first low-potential wiring 31 includes a through wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (multiple in this embodiment) pad plug electrodes 76, and one or more (multiple in this embodiment) substrate plug electrodes 77.

[0077] The through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0078] The through wiring 71 penetrates the multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this embodiment, the through wiring 71 is formed in the region of the insulating layer 51 between the lowermost insulating layer 55 and the uppermost insulating layer 56. The through wiring 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0079] In this embodiment, the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0080] The first electrode layer 78 forms the upper end of the through wiring 71. The second electrode layer 79 forms the lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0081] The plurality of wiring plug electrodes 80 are embedded in the plurality of interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be electrically connected to one another, and electrically connect the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 each have a planar area that is less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0082] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating the interlayer insulating layers 57.

[0083] The low-potential connecting wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) in the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connecting wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The low-potential connecting wiring 72 preferably has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connecting wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0084] The lead-out wiring 73 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead-out wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the lower end of the through wiring 71. The second end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the low-potential connecting wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0085] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 71 and the lead-out wiring 73, and is electrically connected to first ends of the through wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 72 and the lead-out wiring 73, and is electrically connected to second ends of the low potential connection wiring 72 and the lead-out wiring 73.

[0086] The plurality of pad plug electrodes 76 are formed in the uppermost insulating layer 56 in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71, and are electrically connected to the upper ends of the low potential terminal 11 and the through wiring 71, respectively. The plurality of substrate plug electrodes 77 are formed in the lowermost insulating layer 55 in a region between the semiconductor chip 41 and the drawing wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first ends of the drawing wiring 73, and are electrically connected to the semiconductor chip 41 and the first ends of the drawing wiring 73, respectively.

[0087] 6 and 7, the plurality of first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A-12D and the second inner ends 27 of the corresponding transformers 21A-21D (high-potential coils 23), respectively. The plurality of first high-potential wirings 33 each have a similar structure. In the following, the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A will be described as an example. The description of the structure of the first high-potential wiring 33 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first high-potential wirings 33, and will not be repeated here.

[0088] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (multiple in this embodiment) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrode 82 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the high-potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0089] The high-potential connecting wire 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connecting wire 81 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The high-potential connecting wire 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connecting wire 81 is formed spaced apart from the low-potential connecting wire 72 in a plan view and does not face the low-potential connecting wire 72 in the normal direction Z. This increases the insulation distance between the low-potential connecting wire 72 and the high-potential connecting wire 81, thereby increasing the dielectric strength voltage of the insulating layer 51.

[0090] The plurality of pad plug electrodes 82 are formed in the uppermost insulating layer 56 in a region between the high potential terminal 12 (first high potential terminal 12A) and the high potential connecting wiring 81, and are electrically connected to the high potential terminal 12 and the high potential connecting wiring 81. The plurality of pad plug electrodes 82 each have a plane area smaller than the plane area of ​​the high potential connecting wiring 81 in a plan view.

[0091] Referring to FIG. 7, it is preferable that the distance D1 between the low potential terminal 11 and the high potential terminal 12 exceeds the distance D2 between the low potential coil 22 and the high potential coil 23 (D2 < D1). The distance D1 preferably exceeds the total thickness DT of the plurality of interlayer insulating layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the withstand voltage insulation to be achieved.

[0092] Referring to FIGS. 6 and 7, the semiconductor device 5 includes a dummy pattern 85 embedded in the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view.

[0093] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from that of the high potential coil 23 and the low potential coil 22 and is independent of the transformers 21A to 21D. That is, the dummy pattern 85 does not function as the transformers 21A to 21D. The dummy pattern 85 is formed as a shield conductor layer that shields the electric field between the low potential coil 22 and the high potential coil 23 in the transformers 21A to 21D and suppresses the electric field concentration with respect to the high potential coil 23. In this form, the dummy pattern 85 is routed with a line density equal to the line density of the high potential coil 23 per unit area. That the line density of the dummy pattern 85 is equal to the line density of the high potential coil 23 means that the line density of the dummy pattern 85 falls within the range of ±20% of the line density of the high potential coil 23.

[0094] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. Note that the dummy pattern 85 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low-potential coil 22.

[0095] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The shorter the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z, the more electric field concentration on the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be further appropriately suppressed. The dummy pattern 85 includes multiple dummy patterns with different electrical states. The dummy pattern 85 may include a high-potential dummy pattern.

[0096] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 22 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0097] Dummy patterns 85 include floating dummy patterns formed in an electrically floating state within insulating layer 51 so as to be positioned around transformers 21A to 21D.

[0098] In this embodiment, the floating dummy pattern is routed in a dense line shape so as to partially cover and partially expose the area around the high-potential coil 23 in a plan view. The floating dummy pattern may be formed to have ends or to have no ends.

[0099] The depth position of the floating dummy pattern inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed.

[0100] The number of floating lines is arbitrary and can be adjusted depending on the electric field to be relaxed. The floating dummy pattern may be made up of a plurality of floating lines.

[0101] 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region above the first main surface 42 of the semiconductor chip 41, and is covered with an insulating layer 51 (lowermost insulating layer 55). In FIG. 7, the second functional device 60 is simply shown by a dashed line drawn on the surface layer portion of the first main surface 42.

[0102] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring, and is electrically connected to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has a structure similar to that of the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. The high-potential wiring has a structure similar to that of the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. A detailed description of the low-potential wiring and high-potential wiring related to the second functional device 60 will be omitted.

[0103] The second functional device 60 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The second functional device 60 may include circuitry in which any two or more of the passive devices, the semiconductor rectifying device, and the semiconductor switching device are selectively combined. The circuitry may form part or all of an integrated circuit.

[0104] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifying device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0105] 5 to 7, the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape at a distance from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 prevents moisture and cracks from entering the device region 62 from the outer region 63.

[0106] The device region 62 is a region including the first functional device 45 (plurality of transformers 21), the second functional device 60, plural low potential terminals 11, plural high potential terminals 12, first low potential wiring 31, second low potential wiring 32, first high potential wiring 33, second high potential wiring 34, and dummy patterns 85. The outer region 63 is a region outside the device region 62.

[0107] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path leading to the device region 62.

[0108] The seal conductor 61 is formed in a strip shape along the insulating side walls 53 to 53D in plan view. In this embodiment, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. As a result, the seal conductor 61 defines a quadrangular (specifically, rectangular) device region 62 in plan view. The seal conductor 61 also defines a quadrangular (specifically, rectangular) outer region 63 surrounding the device region 62 in plan view.

[0109] Specifically, the seal conductor 61 has an upper end on the insulating principal surface 52 side, a lower end on the semiconductor chip 41 side, and a wall extending in a wall shape between the upper and lower ends. In this embodiment, the upper end of the seal conductor 61 is formed at a distance from the insulating principal surface 52 toward the semiconductor chip 41 and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed at a distance from the semiconductor chip 41 toward the upper end.

[0110] Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the plurality of low potential terminals 11 and the plurality of high potential terminals 12. Furthermore, the seal conductor 61 faces the first functional device 45 (plurality of transformers 21), the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85 in the insulating layer 51 in a direction parallel to the insulating principal surface 52. The seal conductor 61 may face a part of the second functional device 60 in the insulating layer 51 in a direction parallel to the insulating principal surface 52.

[0111] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (in this embodiment, a plurality) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end portion of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end portion of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed from the same conductive material as the low-potential coil 22. In other words, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0112] The multiple seal plug conductors 64 are embedded in the multiple interlayer insulating layers 57, respectively, and are each formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in plan view. The multiple seal plug conductors 64 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be connected to each other. The number of stacked multiple seal plug conductors 64 matches the number of stacked multiple interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0113] As long as a single annular seal conductor 61 is formed by an assembly of a plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end shape. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture and cracks penetrating into the device region 62, it is preferable that the plurality of seal plug conductors 64 be formed in an endless (annular) shape.

[0114] The plurality of seal via conductors 65 are respectively formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the lowermost insulating layer 55. The plurality of seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductor 64. The plurality of seal via conductors 65 have a planar area smaller than the planar area of ​​the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or larger than the planar area of ​​the seal plug conductor 64.

[0115] The width of the shield conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the shield conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the shield conductor 61 is defined as the width in a direction perpendicular to the direction in which the shield conductor 61 extends.

[0116] 7 and 8, the semiconductor device 5 further includes an isolation structure 130 that is interposed between the semiconductor chip 41 and the seal conductor 61 and electrically isolates the seal conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 is made of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0117] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0118] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41, and extends in a strip shape along the seal conductor 61 in plan view. In this embodiment, the isolation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. The isolation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion where the lower end portion (seal via conductor 65) of the seal conductor 61 bites in toward the semiconductor chip 41. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0119] The isolation structure 130 includes an inner end 130A on the device region 62 side, an outer end 130B on the outer region 63 side, and a main body 130C between the inner end 130A and the outer end 130B. The inner end 130A defines the region in which the second functional device 60 is formed (i.e., the device region 62) in plan view. The inner end 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0120] The outer end 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end 130B may be formed in the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0121] The main body 130C has a flat surface extending substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 can take various forms in addition to the field insulating film 131.

[0122] 7, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating principal surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may also be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating principal surface 52.

[0123] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. The first inorganic insulating layer 141 preferably contains USG (undoped silicate glass), which is silicon oxide without added impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength voltage on the high-potential coil 23 can be increased.

[0124] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable to form the first inorganic insulating layer 141 thicker than the second inorganic insulating layer 142.

[0125] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass), which are examples of silicon oxide. In this case, however, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the dielectric strength voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure made of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0126] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61, and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed in an area outside the seal conductor 61. The plurality of low potential pad openings 143 expose the plurality of low potential terminals 11, respectively. The plurality of high potential pad openings 144 expose the plurality of high potential terminals 12, respectively. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the low potential terminals 11. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the high potential terminals 12.

[0127] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0128] The thickness of the organic insulating layer 145 preferably exceeds the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably equal to or greater than 2 μm and equal to or less than 10 μm. Furthermore, the thickness of the organic insulating layer 145 is preferably equal to or greater than 5 μm and equal to or less than 50 μm. These structures can prevent the inorganic insulating layer 140 and the organic insulating layer 145 from becoming thicker, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 can appropriately increase the dielectric strength voltage on the high-potential coil 23.

[0129] The organic insulating layer 145 includes a first portion 146 covering the region on the low potential side and a second portion 147 covering the region on the high potential side. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 sandwiched therebetween. The first portion 146 has a plurality of low potential terminal openings 148 that expose a plurality of low potential terminals 11 (low potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have an overlap portion that rises onto the periphery (overlap portion) of the low potential pad opening 143.

[0130] The second portion 147 is formed at a distance from the first portion 146, and exposes the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose the plurality of high-potential terminals 12 (high-potential pad openings 144), respectively. The second portion 147 may have an overlapping portion that rises onto the periphery (overlapping portion) of the high-potential pad opening 144.

[0131] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the plurality of high-potential coils 23, the plurality of high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121.

[0132] The embodiments of the present invention can be implemented in other forms. In the above-described embodiment, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form in which only the second functional device 60 is provided without the first functional device 45 may be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0133] That is, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the high potential terminal 12 and the seal conductor 61. Furthermore, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the low potential terminal 11 and the seal conductor 61.

[0134] In the above embodiment, an example was described in which the second functional device 60 was formed. However, the second functional device 60 is not necessarily required, and may be removed.

[0135] In the above embodiment, an example was described in which the dummy pattern 85 was formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0136] In the above embodiment, an example has been described in which the first functional device 45 is a multi-channel type that includes multiple transformers 21. However, a first functional device 45 that is a single-channel type that includes a single transformer 21 may also be employed.

[0137] <Transformer arrangement> 9 is a plan view (top view) schematically showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the aforementioned semiconductor device 5). The transformer chip 300 in this figure has a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0138] In the transformer chip 300, pads a1 and b1 are connected to one end of a secondary coil L1s that forms a first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of a secondary coil L2s that forms a second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0139] Furthermore, pads a3 and b3 are connected to one end of a secondary coil L3s that forms the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of a secondary coil L4s that forms the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0140] Note that the primary coils forming the first transformer 301, the primary coils forming the second transformer 302, the primary coils forming the third transformer 303, and the primary coils forming the fourth transformer 304 are not shown in this figure. However, the primary coils basically have the same configuration as the secondary coils L1s to L4s, and are arranged directly below the secondary coils L1s to L4s, respectively, so as to face the secondary coils L1s to L4s.

[0141] That is, pads a5 and b5 are connected to one end of the primary coil forming first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Also, pads a6 and b6 are connected to one end of the primary coil forming second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0142] Pads a7 and b7 are connected to one end of the primary coil forming third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Pads a8 and b8 are connected to one end of the primary coil forming fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0143] However, the pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are led out from the inside of the transformer chip 300 to the surface through vias (not shown).

[0144] Of the multiple pads, pads a1 to a8 correspond to first current supply pads, pads b1 to b8 correspond to first voltage measurement pads, pads c1 to c4 correspond to second current supply pads, and pads d1 to d4 correspond to second voltage measurement pads.

[0145] Therefore, with the transformer chip 300 of this configuration example, the series resistance component of each coil can be accurately measured during the defective product inspection. Therefore, it is possible to not only reject defective products in which a break occurs in each coil, but also to appropriately reject defective products in which an abnormal resistance value occurs in each coil (for example, a short circuit between coils), thereby making it possible to prevent defective products from being released onto the market.

[0146] For the transformer chip 300 that has passed the above-mentioned defective product inspection, the above-mentioned plurality of pads may be used as a means for connecting the primary chip and the secondary chip (for example, the above-mentioned controller chip 210 and driver chip 220).

[0147] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 may be connected to the signal input or output terminals of the secondary chip, respectively, and pads c1 and d1, and pads c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0148] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 may be connected to the signal input or output terminals of the primary chip, respectively, and pads c3 and d3, and pads c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0149] Here, the first transformer 301 to the fourth transformer 304 are arranged in a manner that couples them in the respective signal transmission directions, as shown in Fig. 9. Referring to this figure, for example, the first transformer 301 and the second transformer 302 that transmit signals from the primary-side chip to the secondary-side chip are connected as a first pair by a first guard ring 305. Also, for example, the third transformer 303 and the fourth transformer 304 that transmit signals from the secondary-side chip to the primary-side chip are connected as a second pair by a second guard ring 306.

[0150] The reason for such coupling is to ensure a withstand voltage between the primary coil and the secondary coil when the primary coil and the secondary coil that respectively form the first transformer 301 to the fourth transformer 304 are stacked in the vertical direction of the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0151] The first guard ring 305 and the second guard ring 306 may be connected to a low impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0152] In the transformer chip 300, pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p. Pads c4 and d4 are shared between the corresponding primary coils. This configuration reduces the number of pads, making it possible to miniaturize the transformer chip 300.

[0153] 9, the primary coil and secondary coil forming each of the first transformer 301 to the fourth transformer 304 are preferably wound in a rectangular shape (or a track shape with rounded corners) in a plan view of the transformer chip 300. This configuration increases the area where the primary coil and secondary coil overlap, thereby improving the transmission efficiency of the transformer.

[0154] Of course, the transformer arrangement in this figure is merely an example, and the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to all semiconductor devices in which coils are integrated on a semiconductor chip.

[0155] <About Electronic Devices 400> The above-described signal transmission device 200 can be used in the electronic device 400. The electronic device 400 will now be described in detail.

[0156] Fig. 10 is a diagram showing the basic configuration of an electronic device 400 equipped with a signal transmission device 200X. The electronic device 400 of this configuration example is a type of motor drive device that converts DC power supplied from an in-vehicle battery (not shown) into AC power to drive a motor M. The motor M is a three-phase motor that is rotationally driven in accordance with three-phase drive voltages input from three-phase half-bridge output stages (see Fig. 15 described later). Note that Fig. 10 shows only one phase of the three-phase half-bridge output stages.

[0157] As shown in FIG. 10, the electronic device 400 of this configuration example includes an ECU (Electronic Control Unit) 2, a pair of signal transmission devices 200X, and a plurality of discrete components (drive target switches SW1 and SW2, resistors R1 to R42, and a capacitor C1).

[0158] A first terminal of capacitor C1 is connected to the collector of switch SW1 to be driven and to the terminal to which first motor drive voltage VD1 is applied. A second terminal of capacitor C1 is connected to the emitter of switch SW2 to be driven and to the terminal to which second motor drive voltage VD2 is applied. Capacitor C1 smoothes and stabilizes the DC voltage (= the voltage between the terminals to which first motor drive voltage VD1 and second motor drive voltage VD2 are applied) that fluctuates in accordance with fluctuations in power consumption of motor M.

[0159] The ECU2 is a means for performing overall electrical control of the electronic device 400 and the vehicle A (see FIG. 16 described later) in which the electronic device 400 is mounted. The ECU2 switches the signal levels of the input signals INH and INL between a high level (based on VCC1) and a low level (based on VEE1) to drive the switches SW1 and SW2 to be driven. The ECU2 also sets the logic level of the discharge signal ACD (external signal) to a high level (based on VCC1, first logic level) or a low level (based on VEE1, second logic level) depending on whether or not to execute the discharge function of the capacitor C1 (details of which will be described later).

[0160] The signal transmission device 200X is a semiconductor integrated circuit device and corresponds to the signal transmission device 200 described above.

[0161] The signal transmission device 200X has terminals (in accordance with this figure, a first external terminal T1, a second external terminal T2, a third external terminal T3, a fourth external terminal T4, a fifth external terminal T5, and a sixth external terminal T6) as means for communicating with the outside.

[0162] The first external terminal T1 receives an input signal INH from the ECU 2. The second external terminal T2 receives a discharge signal ACD from the ECU 2. The third external terminal T3 is connected to a first end of the resistor R1. The fourth external terminal T4 is connected to a first end of the resistor R2.

[0163] The fifth external terminal T5 is connected to the second end of the resistor R. The sixth external terminal T6 is connected to the second end of the resistor R2. The second end of the resistor R1, together with the second end of the resistor R2, is connected to the gate of the switch SW1 to be driven.

[0164] The switches to be driven SW1 and SW2 are IGBTs. The collector of the switch to be driven SW1 is connected to a terminal to which a first motor drive voltage VD1 is applied. The emitter of the switch to be driven SW1 is connected to a collector of the switch to be driven SW2. The emitter of the switch to be driven SW2 is connected to a terminal to which a second motor drive voltage VD2 is applied.

[0165] The switches SW1 and SW2 to be driven constitute a half-bridge output stage. An output voltage VOUT is output from a connection node between the switches SW1 and SW2 to be driven. An application terminal of the output voltage VOUT is connected to a motor M to be driven by the electronic device 400.

[0166] For ease of explanation, the connection node between the collector of the switch SW1 to be driven and the application terminal of the first motor drive voltage VD1 is referred to as node n1, and the connection node between the emitter of the switch SW1 to be driven and the collector of the switch SW2 to be driven (= the output terminal of the output voltage VOUT) is referred to as node n2.

[0167] Each signal transmitter 200X generates drive voltages Vgh and Vgl according to the input signal INH and the discharge signal ACD, and controls the drive of the switches SW1 and SW2 to be driven by the drive voltages Vgh and Vgl.

[0168] The switch to be driven SW1 has a drive voltage Vgh input to its gate, and turns on / off according to the drive voltage Vgh. Specifically, when the drive voltage Vgh exceeds the on-threshold voltage of the switch to be driven SW1, the switch to be driven SW1 turns on, and as the voltage value of the drive voltage Vgh increases, the on-resistance of the switch to be driven SW1 decreases. On the other hand, when the drive voltage Vgh falls below the on-threshold voltage of the switch to be driven SW1, the switch to be driven SW1 turns off, and no current flows between the emitter and collector.

[0169] Similarly, the switch SW2 to be driven has a drive voltage Vgl input to its gate, and turns on / off according to the drive voltage Vgl. Specifically, when the drive voltage Vgl exceeds the on-threshold voltage of the switch SW2 to be driven, the switch SW2 to be driven turns on, and as the voltage value of the drive voltage Vgl increases, the on-resistance of the switch SW2 to be driven decreases. On the other hand, when the drive voltage Vgl falls below the on-threshold voltage of the switch SW2 to be driven, the switch SW2 to be driven turns off, and no current flows between the emitter and collector.

[0170] <About the soft turn-off function of the signal transmission device 200X> The signal transmission device 200X has a soft turn-on / off function. Soft turn-on is a turn-on operation in which the slew rate of the rising edge of the gate voltage is slower than the slew rate of a normal turn-on. During soft turn-on, the transition time from the on state to the off state is relatively long. Conversely, soft turn-off is a turn-off operation in which the slew rate of the falling edge of the gate voltage is slower than that during a normal turn-off. During soft turn-off, the transition time from the on state to the off state is relatively long.

[0171] When the switches SW1 and SW2 to be driven are soft turned on or soft turned off, the signal transmission device 200X places the third external terminal T3 and the fourth external terminal T4 in a high impedance state. When soft turning on is performed, the signal transmission device 200X outputs a soft turn-on signal Son from the fifth external terminal T5 in this state. As a result, the drive voltages Vgh and Vgl become equivalent to the soft turn-on signal Son.

[0172] To softly turn off the drive target switches SW1 and SW2, the signal transmission device 200X similarly outputs a soft turn-off signal Soff from the sixth external terminal T6 in the above state. As a result, the drive voltages Vgh and Vgl correspond to the soft turn-off signal Soff. The soft turn-off signal Soff turns off at a relatively gentle slew rate from high level (based on VCC2, described below) to low level (based on VEE2, described below). In response to this soft turn-off signal Soff, the drive target switch SW1 turns off more slowly than in a normal turn-off.

[0173] <Capacitor discharge function using soft turn-off function> The electronic device 400 has a function of extracting (discharging) the charge from the capacitor C1 at any timing such as during a protection operation. When this discharge function is executed, the ECU2 raises the discharge signal ACD to a high level. This causes each signal transmission device 200X to perform a predetermined operation to control the drive target switches SW1 and SW2 and discharge the capacitor C1. When this discharge function is executed, the signal transmission device 200X controls the drive target switches SW1 and SW2, for example, as follows:

[0174] The signal transmission device 200X controls the drive target switches SW1 and SW2 so that two states are alternately repeated: a state (first state) in which the drive target switch SW1 is turned off and on and the drive target switch SW2 is soft-turned off, and a state (second state) in which the drive target switch SW1 is soft-turned off and the drive target switch SW2 is soft-turned on. Then, a period occurs between the first state and the second state in which both the drive target switches SW1 and SW2 are on. At this period, current flows from capacitor C1. This reduces the amount of charge in capacitor C1. This discharge amount (the magnitude of the flowing current) is smaller than when both the drive target switches SW1 and SW2 are fully on and the capacitor C1 is discharged. This prevents the drive target switches SW1 and SW2 and capacitor C1 from being damaged by overcurrent.

[0175] <About the Signal Transmission Device 200X> Next, the signal transmission device 200X will be described in detail. Fig. 11 is a diagram showing the internal configuration of the signal transmission device 200X according to the present disclosure. As shown in Fig. 11, the signal transmission device 200X is configured to transmit a gate drive signal from a primary circuit system (VCC1-VEE1) to a secondary circuit system (VCC2-VEE2) while insulating the primary circuit system from the secondary circuit system.

[0176] The primary power supply terminal Tv1 is a power supply terminal for the primary circuit system (= the controller chip 410 described later). The primary circuit system receives a supply voltage VCC1 via the primary power supply terminal Tv1. The secondary power supply terminal Tv2 is a power supply terminal for the secondary circuit system (= the driver chip 420 described later). The secondary circuit system receives a supply voltage VCC2 via the secondary power supply terminal Tv2. Gate

[0177] The signal transmission device 200X includes a controller chip 410 (transmitting circuit), a driver chip 420 (receiving circuit), and a transformer chip 430 (insulating circuit). The signal transmission device 200X is configured by sealing the controller chip 410, the driver chip 420, and the transformer chip 430 in one package.

[0178] The controller chip 410 corresponds to the primary circuit system 200p mentioned above. The controller chip 410 is a controller chip on which a controller having a function of generating each signal is integrated. The controller chip 410 is driven by receiving a power supply voltage VCC1. The controller chip 410 generates a first internal signal S1 and a second internal signal S2 based on an input signal INH and a discharge signal ACD.

[0179] The controller chip 410 includes a logic circuit 416 , a first transmitting circuit 411 , and a second transmitting circuit 412 .

[0180] The logic circuit 416 receives the power supply voltage VCC1, the input signal INH, and the discharge signal ACD, and generates a first internal signal S1 and a second internal signal S2 that are pulse-driven at a predetermined period in response to the input signal INH and the discharge signal ACD.

[0181] The first transmitting circuit 411 and the second transmitting circuit 412 receive a first internal signal S1 and a second internal signal S2 as inputs from the logic circuit 416. The first transmitting circuit 411 transmits the input first internal signal S1 to the driver chip 420 (more specifically, a first receiving circuit 421 described later) via the transformer chip 430 (more specifically, a first transformer 431 described later). The second transmitting circuit 412 transmits the input second internal signal S2 to the driver chip 420 (more specifically, a second receiving circuit 422 described later) via the transformer chip 430 (more specifically, a second transformer 432 described later).

[0182] The driver chip 420 corresponds to the secondary circuit system 200s described above. The driver chip 420 is a driver chip in which a driver for controlling the drive of the switch SW1 to be driven is integrated.

[0183] The driver chip 420 is driven by receiving a power supply voltage VCC2. The driver chip 420 generates a drive voltage Vgh in response to the received first internal signal S1 and second internal signal S2, and controls the drive of the drive target switch SW1. The detailed configuration of the driver chip 420 will be described later.

[0184] The transformer chip 430 is a transformer chip in which multiple transformers (first transformer 431 to fifth transformer 435 described later) are integrated. The transformer chip 430 transmits the first internal signal S1 and the second internal signal S2 while providing DC insulation between the controller chip 410 and the driver chip 420.

[0185] A detailed description will be given of the configuration of the driver chip 420. The driver chip 420 has a first receiving circuit 421, a second receiving circuit 422, a logic circuit 429, a first driving circuit 426, and a second driving circuit 502.

[0186] The first receiving circuit 421 receives the first internal signal S1 from the first transmitting circuit 411 via the first transformer 431. The first receiving circuit 421 inputs the received first internal signal S1 to the logic circuit 429.

[0187] The second receiving circuit 422 receives the second internal signal S2 from the second transmitting circuit 412 via the second transformer 432. The second receiving circuit 422 inputs the received second internal signal S2 to the logic circuit 429.

[0188] The logic circuit 429 generates a first drive control signal S4 and second drive control signals S5a, S5b based on the input first internal signal S1 and second internal signal S2. The logic circuit 429 inputs the first drive control signal S4 and the second drive control signals S5a, S5b to the first drive circuit 426 (more specifically, the driver circuit 501). The logic circuit 429 also inputs the second drive control signal S5a to the soft turn-on control circuit 502a. The logic circuit 429 also inputs the second drive control signal S5b to the soft turn-off control circuit 502b.

[0189] The logic circuit 429 is also configured to be able to detect whether the first internal signal S1 and the second internal signal S2 are pulse-driven at a specific period (details of which will be described later). Specifically, the logic circuit 429 monitors the drive period of the first internal signal S1 and the second internal signal S2 received by the second receiving circuit 422, and detects whether this drive period is the specific period.

[0190] The logic circuit 429 outputs the first drive control signal S4 according to the first internal signal S1 and the second internal signal S2, when the first internal signal S1 and the second internal signal S2 are driven at a normal cycle. At this time, the logic circuit 429 sets the second drive control signals S5a and S5b to a low level.

[0191] When the logic circuit 429 detects that at least one of the first internal signal S1 and the second internal signal S2 is pulse-driven at a specific period, the logic circuit 429 sets the second drive control signals S5a and S5b to high level. A more detailed configuration of the logic circuit 429 will be described later.

[0192] The first drive circuit 426 switches between an enabled state and an disabled state in response to the second drive control signals S5a and S5b. The enabled state of the first drive circuit 426 refers to a state in which the first drive circuit 426 controls the voltages at the third external terminal T3 and the fourth external terminal T4 to drive and control the drive target switch SW1. The disabled state of the first drive circuit 426 refers to a state in which the third external terminal T3 and the fourth external terminal T4 are set to a high impedance state, and the drive target switch SW1 is driven and controlled by a soft turn-on control circuit 502a and a soft turn-off control circuit 502b, which will be described later.

[0193] The first drive circuit 426 is enabled when both second drive control signals S5a and S5b are at low level, and disabled when at least one of the second drive control signals S5a and S5b is at high level.

[0194] The first drive circuit 426 includes a driver circuit 501, a transistor P1, and a transistor N1. The driver circuit 501 outputs drive signals GH and GL based on the input first drive control signal S4 and second drive control signals S5a and S5b.

[0195] The transistor P1 is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The transistor N1 is an N-channel MOSFET. The source of the transistor P1 is connected to the secondary power supply terminal Tv2. The drains of the transistors P1 and N1 are both connected to the third external terminal T3. The source of the transistor N1 is connected to an application terminal of a reference voltage VEE2. The reference voltage VEE2 is lower than the power supply voltage VCC2. The gates of the transistors P1 and N1 are connected to the driver circuit 501.

[0196] The transistor P1 receives a drive signal GH at its gate and is turned on / off by the drive signal GH. The transistor N1 receives a drive signal GL at its gate and is turned on / off by the drive signal GL. In the disabled state described above, the first drive circuit 426 outputs the drive signals GH and GL to turn off both the transistors P1 and N1.

[0197] When the transistor P1 is turned on, a high-level (=VCC2 level) voltage is supplied to the third external terminal T3. When the transistor P1 is turned off, the third external terminal T3 enters a high-impedance state. When the transistor N1 is turned on, a low-level (=VEE2 level) voltage is supplied to the fourth external terminal T4. When the transistor N1 is turned off, the fourth external terminal T4 enters a high-impedance state.

[0198] When the first drive circuit 426 is enabled, it turns on one of the transistors P1 and N1 and turns off the other, thereby supplying a predetermined voltage (high level or low level) to one of the third external terminal T3 and the fourth external terminal T4, and putting the other into a high impedance state.

[0199] The drive voltage Vgh changes depending on the states of the third external terminal T3 and the fourth external terminal T4. For example, when the transistor P1 is turned on and the transistor N1 is turned off, the power supply voltage VCC2 is supplied to the third external terminal T3 and the fourth external terminal T4 is in a high-impedance state. At this time, the drive voltage Vgh becomes high level. Also, for example, when the transistor P1 is turned off and the transistor N1 is turned on, the third external terminal T3 is in a high-impedance state and the reference voltage VEE2 is supplied to the fourth external terminal T4. At this time, the drive voltage Vgh becomes low level.

[0200] When the first drive circuit 426 is in an inactive state, the first drive circuit 426 turns off the transistor P1 and the transistor N1, so that the third external terminal T3 and the fourth external terminal T4 are in a high impedance state.

[0201] When the second drive circuit 502 is enabled, it generates the drive voltage Vgh so as to turn on and off the drive target switch SW1 slower than the first drive circuit 426. "Slower than the first drive circuit 426" has the following meaning: the second drive circuit 502 generates the drive voltage Vgh so as to transition the drive target switch SW1 from the on state to the off state (soft turn-off operation) or from the off state to the on state (soft turn-on operation) slower than the first drive circuit 426 transitions the drive target switch SW1 from the on state to the off state (off operation) or from the off state to the on state (on operation). Specifically, this is as follows.

[0202] The second drive circuit 502 includes a soft turn-on control circuit 502a and a soft turn-off control circuit 502b. The soft turn-on control circuit 502a switches between an enabled state and an disabled state in response to the second drive control signal S5a. The soft turn-off control circuit 502b switches between an enabled state and an disabled state in response to the second drive control signal S5b.

[0203] The soft turn-on control circuit 502a is in an inactive state when the second drive control signal S5a is at a low level, and is in an active state when the second drive control signal S5a is at a high level.

[0204] When the soft turn-on control circuit 502a is in an enabled state, it supplies the soft turn-on signal Son to the fifth external terminal T5. On the other hand, when the soft turn-on control circuit 502a is in an disabled state, it does not supply the soft turn-on signal Son to the fifth external terminal T5. More specifically, this is as follows.

[0205] The soft turn-on control circuit 502a includes a signal generating circuit 503a and a switch SW3a. The signal generating circuit 503a generates a soft turn-on signal Son. The signal generating circuit 503a is connected to a first terminal of the switch SW3a. A second terminal of the switch SW3a is connected to a fifth external terminal T5.

[0206] The switch SW3a is controlled to be turned on and off based on the second drive control signal S5a. The above-mentioned soft turn-on control circuit 502a is in an enabled state when the switch SW3a is on. The above-mentioned soft turn-on control circuit 502a is in an disabled state when the switch SW3a is off. Specifically, this is as follows.

[0207] When the second drive control signal S5a is at a high level, the switch SW3a is turned on. At this time, the signal generating circuit 503a is brought into a conductive state with the fifth external terminal T5, and the soft turn-on signal Son is supplied to the fifth external terminal T5. On the other hand, when the second drive control signal S5a is at a low level, the switch SW3a is turned off, the signal generating circuit 503a is brought into a non-conductive state with the fifth external terminal T5, and the soft turn-on signal Son is no longer supplied to the fifth external terminal T5.

[0208] The soft turn-off control circuit 502b is in an inactive state when the second drive control signal S5b is at a low level, and is in an active state when the second drive control signal S5b is at a high level. When the soft turn-off control circuit 502b is in an active state, it supplies a soft turn-off signal Soff to the sixth external terminal T6. On the other hand, when the soft turn-off control circuit 502b is in an inactive state, it does not supply the soft turn-off signal Soff to the sixth external terminal T6. More specifically, this is as follows.

[0209] The soft turn-off control circuit 502b includes a signal generating circuit 503b and a switch SW3b. The signal generating circuit 503b generates a soft turn-off signal Soff. The signal generating circuit 503b is connected to a first terminal of the switch SW3b. A second terminal of the switch SW3b is connected to a sixth external terminal T6.

[0210] The switch SW3b is controlled to be turned on and off based on the second drive control signal S5b. The above-mentioned soft turn-off control circuit 502b is in an enabled state when the switch SW3b is on. The above-mentioned soft turn-off control circuit 502b is in an disabled state when the switch SW3b is off. Specifically, this is as follows.

[0211] When the second drive control signal S5b is at a high level, the switch SW3b is turned on. At this time, the signal generating circuit 503b is brought into a conductive state with the sixth external terminal T6, and the soft turn-off signal Soff is supplied to the sixth external terminal T6. On the other hand, when the second drive control signal S5b is at a low level, the switch SW3b is turned off, the signal generating circuit 503b is brought into a non-conductive state with the sixth external terminal T6, and the soft turn-off signal Soff is no longer supplied to the sixth external terminal T6.

[0212] The above-described discharge function is executed as follows: First, an example of control of the switch SW1 to be driven when the switch SW1 to be driven is soft turned off and the switch SW2 to be driven is soft turned on will be described.

[0213] In this case, the first drive circuit 426 is disabled and the third external terminal T3 is set to a high impedance state. At this time, the soft turn-on control circuit 502a is enabled and the soft turn-off control circuit 502b is disabled. As a result, the soft turn-on signal Son is supplied from the fifth external terminal T5 to the gate of the drive target switch SW1. The drive voltage Vgh at this time corresponds to the soft turn-on signal Son.

[0214] At this time, in the signal transmission device 200X connected to the switch SW2 to be driven, the soft turn-on control circuit 502a is disabled and the soft turn-off control circuit 502b is enabled (not shown). As a result, a soft turn-off signal Soff is supplied to the gate of the switch SW2 to be driven (not shown). The drive voltage Vgl at this time corresponds to the soft turn-off signal Soff. As a result, a current flows from the capacitor C1, and the charge is extracted.

[0215] Conversely, an example of control of the switch SW1 to be driven when the switch SW1 to be driven is soft turned on while the switch SW2 to be driven is soft turned off will be described.

[0216] In this case, the first drive circuit 426 is disabled and the third external terminal T3 is set to a high impedance state. At this time, the soft turn-on control circuit 502a is disabled and the soft turn-off control circuit 502b is enabled. As a result, the soft turn-off signal Soff is supplied from the sixth external terminal T6 to the gate of the drive target switch SW1. The drive voltage Vgh at this time corresponds to the soft turn-off signal Soff.

[0217] At this time, in the signal transmission device 200X connected to the switch SW2 to be driven, the soft turn-on control circuit 502a is enabled and the soft turn-off control circuit 502b is disabled (not shown). As a result, the soft turn-on signal Son is supplied to the gate of the switch SW2 to be driven (not shown). The drive voltage Vgl at this time corresponds to the soft turn-on signal Son. As a result, a current flows from the capacitor C1, and the charge is extracted.

[0218] <Detailed configuration of logic circuits 416 and 429> Next, a more detailed configuration of the logic circuits 416 and 429 will be described. Fig. 12 is a diagram showing the detailed configuration of the logic circuits 416 and 429. As shown in Fig. 12, the logic circuit 416 includes an edge detection circuit 450, a clock circuit 451, a D flip-flop 452, and a pulse generation circuit 453.

[0219] The edge detection circuit 450 is connected to the first external terminal T1. The edge detection circuit 450 receives the input signal INH via the first external terminal T1 and generates an edge detection signal S6. When the edge detection circuit 450 detects either a rising edge or a falling edge of the input signal INH, it generates a single pulse in the edge detection signal S6 after a predetermined time has elapsed since the detection (e.g., 50 ns has elapsed since the detection).

[0220] The clock circuit 451 receives the edge detection signal S6, generates a clock signal CLK according to the edge detection signal S6, and inputs the clock signal CLK to the pulse generation circuit 453. Specifically, the clock circuit 451 generates the clock signal CLK so as to pulse drive at a predetermined cycle from the timing of the pulse edge generated in the edge detection signal S6.

[0221] The D flip-flop 452 receives the discharge signal ACD at its input terminal (D), the edge detection signal S6 at its input terminal (CK), and the reset signal RST at its reset terminal (R). The D flip-flop 452 outputs a control signal S7 corresponding to the discharge signal ACD and the edge detection signal S6 from its output terminal (Q). Specifically, this is as follows.

[0222] When a pulse is generated in the edge detection signal S6, the D flip-flop 452 sets the logic level of the discharge signal ACD to the input terminal (D) at the timing of the pulse edge (e.g., rising edge) of the edge detection signal S6. As a result, the D flip-flop 452 makes the logic level of the control signal S7 the same as the logic level of the input terminal (D).

[0223] In other words, even if the discharge signal ACD rises from low to high, the control signal S7 is maintained at low until a pulse is generated in the edge detection signal S6 (until the edge detection circuit 450 detects the rising edge or falling edge of the input signal INH). That is, when a pulse is generated in the edge detection signal S6 while the discharge signal ACD is high (until the edge detection circuit 450 detects the rising edge or falling edge of the input signal INH), the control signal S7 rises to high.

[0224] The reset signal RST is generated by ECU2. ECU2 raises the reset signal RST from low level to high level at any timing when the discharge function is not being executed. When the reset signal RST rises to high level, the logic level set at the input terminal (D) is reset (to low level).

[0225] The pulse generating circuit 453 receives the clock signal CLK and the control signal S7 and generates the first internal signal S1 and the second internal signal S2 according to the clock signal CLK and the control signal S7. The pulse generating circuit 453 pulses one of the first internal signal S1 and the second internal signal S2 at a normal period or a specific period in accordance with the clock signal CLK and the control signal S7, and maintains the other at a low level. Specifically, this is as follows.

[0226] When the input signal INH is at a high level and the control signal S7 is at a low level (= when the discharge signal ACD is at a low level), the pulse generating circuit 453 pulses the first internal signal S1 at a normal period based on the clock signal CLK and maintains the second internal signal S2 at a low level.

[0227] When the input signal INH is at a low level and the control signal S7 is at a low level, the pulse generating circuit 453 pulses the second internal signal S2 at a normal period based on the clock signal CLK, and maintains the first internal signal S1 at a low level.

[0228] When the control signal S7 is at a high level, the pulse generating circuit 453 pulses one of the first internal signal S1 and the second internal signal S2 at a specific period, and maintains the other at a low level.

[0229] When the edge detection circuit 450 detects a rising edge of the input signal INH and the control signal S7 rises to a high level, the input signal INH and the discharge signal ACD are at a high level, and the pulse generation circuit 453 pulses the first internal signal S1 at a specific period and maintains the second internal signal S2 at a low level.

[0230] Conversely, when the edge detection circuit 450 detects a falling edge of the input signal INH and the control signal S7 rises to a high level, the input signal INH is at a low level, the discharge signal ACD is at a high level, and the pulse generation circuit 453 pulses the second internal signal S2 at a specific period and maintains the first internal signal S1 at a low level.

[0231] The normal period is a predetermined period (e.g., 100 ns) that is set in advance to correspond to the on / off period of the drive target switch SW1 in normal (i.e., when the discharge function is not executed) conditions. The specific period is a period (e.g., 25 ns) that is shorter than the normal period.

[0232] The pulse generating circuit 453 starts pulse driving of the first internal signal S1 or the second internal signal S2 at a specific cycle, and then after a predetermined pulse stop time Td has elapsed, the pulse generating circuit 453 sets both the first internal signal S1 and the second internal signal S2 to a low level. The pulse stop time Td is set to be longer than a second time Tb (described later) but shorter than the sum of the second time Tb and a third time Tc. The pulse stop time Td is also set to be shorter than the third time Tc. For example, the pulse stop time Td can be set to 0.5 μs (see FIG. 13 described later).

[0233] Next, a detailed description will be given of the configuration of the logic circuit 429. As shown in FIG.

[0234] The driver control circuit 454 generates a first drive control signal S4 in response to the first internal signal S1 and the second internal signal S2.

[0235] The detection circuit 455 is configured to monitor the first internal signal S1 and the second internal signal S2 and detect whether either the first internal signal S1 or the second internal signal S2 is pulse-driven at a specific period. The detection circuit 455 generates a detection signal S8 according to the detection result.

[0236] The discharge control circuit 460 generates the second drive control signal S5a and the second drive control signal S5b according to the first internal signal S1, the second internal signal S2, and the detection signal S8. Detailed configurations of the driver control circuit 454, the detection circuit 455, and the discharge control circuit 460 are as follows.

[0237] The driver control circuit 454 includes an RS flip-flop 456 and an AND gate AG1.

[0238] The RS flip-flop 456 receives the first internal signal S1 at its set input terminal (S) from the first receiving circuit 421. The RS flip-flop 456 receives the second internal signal S2 at its reset input terminal (R) from the second receiving circuit 422. The RS flip-flop 456 outputs a control signal S9 corresponding to the first internal signal S1 and the second internal signal S2 from its output terminal (Q).

[0239] The AND gate AG1 receives a control signal S9 at a first input terminal and an inverted signal S15 (described later) at a second input terminal, and outputs a first drive control signal S4 according to the control signal S9 and the inverted signal S15.

[0240] The detection circuit 455 includes OR gates OG1 and OG2, a NOR gate NG1, a first timer circuit 457, a second timer circuit 458, a third timer circuit 459 (mask circuit), and an RS flip-flop 461.

[0241] The OR gate OG1 receives the first internal signal S1 at its first input terminal from the first receiving circuit 421. The OR gate OG1 receives the second internal signal S2 at its second input terminal from the second receiving circuit 422. The OR gate OG1 outputs a monitoring signal S10 corresponding to the first internal signal S1 and the second internal signal S2 from its output terminal. More specifically, this is as follows.

[0242] The OR gate OG1 sets the monitoring signal S10 to a high level when at least one of the first internal signal S1 and the second internal signal S2 is at a high level, and sets the monitoring signal S10 to a low level when both the first internal signal S1 and the second internal signal S2 are at a low level.

[0243] The first timer circuit 457 receives the monitor signal S10 and outputs a first timer signal S11 corresponding to the monitor signal S10. Specifically, the first timer circuit 457 raises the logic level of the first timer signal S11 from low to high in synchronization with the rising edge of the monitor signal S10. Furthermore, when a predetermined first time Ta (see FIG. 13 described later) has elapsed from the timing of the rising edge of the first timer signal S11, the first timer circuit 457 lowers the logic level of the first timer signal S11 from high to low.

[0244] The first time Ta is set to be shorter than the normal period and longer than the specific period. For example, if the normal period is set to 100 ns and the specific period is set to 25 ns, the first time Ta can be set to be greater than 25 ns but less than 100 ns (e.g., 40 ns).

[0245] The OR gate OG2 receives the first timer signal S11 at its first input terminal. The OR gate OG2 receives the UVLO signal output from the constant voltage lockout circuit UVLO at its second input terminal. The OR gate OG2 outputs a control signal S12 from its output terminal in response to the UVLO signal and the first timer signal S11. More specifically, this is as follows.

[0246] When the power supply voltage falls below a predetermined lower limit voltage, the constant voltage lockout circuit UVLO places the function of the detection circuit 455 in a standby state (=temporarily stopped) to prevent the detection circuit 455 from malfunctioning. As long as the power supply voltage VCC2 does not fall below the lower limit voltage, the constant voltage lockout circuit UVLO basically outputs a low-level output signal. In other words, as long as the power supply voltage VCC2 does not fall below the lower limit voltage, the OR gate OG2 outputs a control signal S12 having the same logic level as the first timer signal S11.

[0247] The second timer circuit 458 receives the control signal S12 and outputs a second timer signal S13 according to the control signal S12. Specifically, the second timer circuit 458 operates as follows.

[0248] The second timer circuit 458 is configured to be able to detect whether the duration of the high level of the control signal S12 (= the time from the timing when the first timer signal S11 rises to the high level to the next time when the first timer signal S11 falls to the low level) exceeds a predetermined second time Tb (first period). The second timer circuit 458 outputs a second timer signal S13 according to the detection result.

[0249] Specifically, the second timer circuit 458 keeps the logic level of the second timer signal S13 at a low level until the duration of the high level of the control signal S12 reaches a second time Tb. On the other hand, when the duration of the high level of the control signal S12 reaches the second time Tb, the second timer circuit 458 keeps the logic level of the second timer signal S13 at a high level and maintains the logic level of the second timer signal S13 at a high level until the control signal S12 falls to a low level. The second time Tb is set to a time (e.g., 200 ns) longer than the first time Ta.

[0250] The RS flip-flop 461 receives the second timer signal S13 at its set input terminal (S). The RS flip-flop 461 receives the control signal S14 (described later) at its reset input terminal (R). The RS flip-flop 461 outputs a detection signal S8 from its output terminal (Q) and outputs an inverted signal S15 from its inverted output terminal (-Q) in response to the second timer signal S13 and the control signal S14. The inverted signal S15 is a signal whose logical level is inverted from that of the detection signal S8.

[0251] The third timer circuit 459 receives the inverted signal S15 as input, and outputs a third timer signal S16 corresponding to the inverted signal S15. Specifically, this is as follows.

[0252] In response to the input of the high-level inverted signal S15, the third timer circuit 459 sets the third timer signal S16 to a low level. The third timer circuit 459 also sets the third timer signal S16 to a high level from the timing when the inverted signal S15 falls to a low level until a predetermined third time Tc (second period) has elapsed. After the third time Tc has elapsed, the third timer circuit 459 sets the third timer signal S16 to a low level again.

[0253] The NOR gate NG1 receives the supervisory signal S10 at its first input terminal and the third timer signal S16 at its second input terminal. The NOR gate NG1 outputs a control signal S14 in response to the supervisory signal S10 and the third timer signal S16. Specifically, this is as follows.

[0254] While the third timer signal S16 is maintained at a low level, the NOR gate NG1 pulses the control signal S14 so that its logical level is the inverse of that of the monitoring signal S10. That is, during this time, the control signal S14 is pulsed at a specific period. While the third timer signal S16 is maintained at a high level, the NOR gate NG1 maintains the control signal S14 at a low level, regardless of the logical level of the monitoring signal S10.

[0255] Therefore, while the third timer circuit 459 maintains the third timer signal S16 at a low level, the RS flip-flop 461 receives the low-level second timer signal S13 as input to its set input terminal (S) and the specific periodic pulse-driven control signal S14 as input to its reset input terminal (R). That is, during this time, the RS flip-flop 461 alternately holds and resets the logical level of the output terminal (Q), and continues to maintain the detection signal S8 at a low level.

[0256] Meanwhile, while the third timer circuit 459 maintains the third timer signal S16 at a high level, the RS flip-flop 461 receives the high-level second timer signal S13 as input to its set input terminal (S) and the low-level control signal S14 as input to its reset input terminal (R). That is, during this time, the RS flip-flop 461 alternates between holding and setting the logic level of its output terminal (Q), thereby maintaining the detection signal S8 at a high level. In this way, by the third timer circuit 459 maintaining the third timer signal S16 at a high level, the logic level of the detection signal S8 does not change even if the monitoring signal S10 is pulse-driven.

[0257] In other words, the third timer circuit 459 masks the monitoring signal S10 when the detection signal S8 is at a high level (= when the detection circuit 455 detects that the pulse period of the first internal signal S1 or the second internal signal S2 is a specific period). As a result, when the detection signal S8 is at a high level, fluctuations in the logic level of the first internal signal S1 or the second internal signal S2 are not transmitted to the AND gate AG1 and the AND gates AG2 and AG3 (described later). This prevents both of the second drive control signals S5a and S5b from falling to a low level when the detection signal S8 is at a high level.

[0258] The discharge control circuit 460 includes an inverter IV1 and AND gates AG2 and AG3. The inverter IV1 receives a control signal S9 as input and outputs a control signal S17 whose logical level is the inverse of that of the control signal S9.

[0259] The AND gate AG2 receives the control signal S17 at a first input terminal and the detection signal S8 at a second input terminal, and outputs a second drive control signal S5a according to the control signal S17 and the detection signal S8.

[0260] The AND gate AG3 receives the control signal S9 at a first input terminal and the detection signal S8 at a second input terminal, and outputs a second drive control signal S5b according to the detection signal S8 and the control signal S9.

[0261] <Internal control during soft turn-on> Next, the internal control when the signal transmission device 200X softly turns on the drive target switch SW1 will be described. Note that the following describes an example of control during soft turn-on, in which the edge detection circuit 450 detects a rising edge of the input signal INH and the control signal S7 falls to low level (= the first internal signal S1 pulses at a specific period and the second internal signal S2 is maintained at low level).

[0262] Fig. 13 is a timing chart showing the timing of drive control of the drive target switch SW1 using the signal transmission device 200X. From top to bottom, Fig. 13 shows the discharge signal ACD, the input signal INH, the first internal signal S1, the second internal signal S2, the first timer signal S11, the second timer signal S13, the third timer signal S16, the detection signal S8, the control signal S9, and the drive voltage Vgh.

[0263] In FIG. 13, the period from time t1 to time t2 is a period during which the switch SW1 to be driven is normally turned on / off. More specifically, the period before time t1 is the on period Ton of the switch SW1 to be driven. The period from time t1 to time t2 is the off period Toff of the switch SW1 to be driven. The period from time t2 to time t6 is a period during which the above-mentioned discharge function is executed, and is the soft turn-on period Tson of the switch SW1 to be driven (= the period during which the switch SW1 to be driven is softly turned on). The period from time t7 onwards is the normal off period Toff after the discharge function has ended.

[0264] The ECU 2 maintains the discharge signal ACD at a low level from a predetermined timing (not shown) until time t2 arrives, and also maintains the input signal INH at a high level from a predetermined timing (not shown) until time t1 arrives.

[0265] Until time t1, the logic circuit 416 receives the low-level input signal INH and pulse-drives the first internal signal S1 high at a normal period (100 ns in this diagram) while maintaining the second internal signal S2 at a low level.

[0266] Furthermore, until time t1, the RS flip-flop 456 receives the first internal signal S1, which is pulse-driven at a normal cycle, at its set terminal (S), and the second internal signal S2, which is maintained at a low level, at its reset terminal (R). Therefore, the RS flip-flop 456 maintains the control signal S9 at a high level until time t1 arrives.

[0267] Furthermore, until time t1, the OR gate OG1 receives the first internal signal S1, which is pulsed at a normal cycle, at its first input terminal, and the second internal signal S2, which is maintained at a low level, at its second input terminal. Therefore, until time t1 arrives, the OR gate OG1 pulses the monitoring signal S10 (not shown) so as to be synchronized with the pulse driving of the first internal signal S1.

[0268] Furthermore, until time t1, the first timer circuit 457 raises the first timer signal S11 from low level to high level in synchronization with the pulse timing of the monitoring signal S10 (= the pulse timing of the first internal signal S1). Then, the first timer signal S11 is maintained at high level until the first time Ta (40 ns in accordance with the figure) has elapsed since the first timer signal S11 was raised to high level. When the first time Ta has elapsed since the first timer signal S11 rose to high level, the first timer signal S11 is again lowered to low level. Therefore, before time t1, the first timer signal S11 is a pulse signal having a pulse width of the first time Ta.

[0269] Furthermore, until time t1, the second timer circuit 458 receives an input of the first timer signal S11 having a pulse width of the first time Ta and sets the second timer signal S13 to low level. In other words, until time t1, the second timer circuit 458 maintains the second timer signal S13 at low level because the duration of the high level of the first timer signal S11 is the first time Ta and has not yet reached the second time Tb (200 ns in accordance with this diagram).

[0270] Furthermore, until time t1, the RS flip-flop 461 receives a low-level second timer signal S13 at its set input terminal (S). Therefore, until time t1 arrives, the RS flip-flop 461 maintains the detection signal S8 at a low level, regardless of the logic level of the control signal S14 input to its reset input terminal (R). Furthermore, the inverted signal S15 is maintained at a high level (not shown).

[0271] Furthermore, until time t1, the AND gate AG1 receives the control signal S9 maintained at a high level at its first input terminal and the inverted signal S15 maintained at a high level at its second input terminal, so that the AND gate AG1 maintains the first drive control signal S4 at a high level.

[0272] Furthermore, until time t1, inverter IV1 receives the control signal S9 maintained at a high level and maintains the control signal S17 at a low level (not shown). Therefore, AND gate AG2 receives the control signal S17 maintained at a low level at its first input terminal and the detection signal S8 maintained at a low level at its second input terminal. As a result, AND gate AG2 maintains the second drive control signal S5a at a low level until time t1.

[0273] Furthermore, until time t1, the AND gate AG3 receives the control signal S9 maintained at a high level at its first input terminal and the detection signal S8 maintained at a low level at its second input terminal, so that the AND gate AG3 maintains the second drive control signal S5b at a low level until time t1.

[0274] As described above, until time t1, the first drive control signal S4 is maintained at a high level, and the second drive control signals S5a and S5b are maintained at a low level. Then, until time t1 arrives, transistor P1 is on, transistor N1 is off, and switches SW3a and SW3b are off. That is, power supply voltage VCC2 is supplied from the third external terminal T3. Therefore, until time t1, the drive voltage Vgh remains at a high level. Therefore, as described above, the period before time t1 is the on period Ton of the switch SW1 to be driven.

[0275] Until time t1, the third timer circuit 459 receives the inverted signal S15 at a high level and maintains the third timer signal S16 at a low level.

[0276] At time t1, the ECU 2 drops the input signal INH to low while maintaining the discharge signal ACD at low level, and then maintains the logic levels of the discharge signal ACD and the input signal INH until time t2 arrives.

[0277] Between time t1 and time t2, the logic circuit 416 receives a low-level input signal INH and a low-level discharge signal ACD, which causes the logic circuit 416 to maintain the first internal signal S1 at a low level and pulse-drive the second internal signal S2 at a normal cycle.

[0278] Furthermore, from time t1 to time t2, the RS flip-flop 456 receives the first internal signal S1 maintained at a low level as input to its set terminal (S) and the second internal signal S2 pulse-driven at a normal period as input to its reset terminal (R). Therefore, the RS flip-flop 456 is triggered by the pulse edge (rising edge) generated in the second internal signal S2 at time t1 to cause the control signal S9 to fall to a low level (i.e., reset). The RS flip-flop 456 then maintains the control signal S9 at a low level from time t1 until the next pulse edge of the first internal signal S1 is detected (i.e., the on-period of the switch SW1 to be driven arrives) (not shown).

[0279] Furthermore, from time t1 to time t2, the OR gate OG1 receives the first internal signal S1 maintained at a low level at its first input terminal and the second internal signal S2 pulsed at a normal cycle at its second input terminal, so that from time t1 to time t2, the OR gate OG1 pulses the monitoring signal S10 (not shown) in synchronization with the pulse driving of the second internal signal S2.

[0280] Furthermore, from time t1 to time t2, the first timer circuit 457 raises the first timer signal S11 from low level to high level in synchronization with the pulse timing of the monitoring signal S10 (= the pulse timing of the second internal signal S2). Then, the first timer signal S11 is maintained at high level until the first time Ta (40 ns in accordance with the figure) has elapsed since the first timer signal S11 was raised to high level. When the first time Ta has elapsed since the first timer signal S11 rose to high level, the first timer signal S11 is again lowered to low level. Therefore, from time t1 to time t2, the first timer signal S11 is a pulse signal having a pulse width of the first time Ta.

[0281] Furthermore, from time t1 to time t2, the second timer circuit 458 receives an input of the first timer signal S11 having a pulse width of the first time Ta and sets the second timer signal S13 to low level. In other words, the second timer circuit 458 maintains the second timer signal S13 at low level because the duration of the high level of the first timer signal S11 is the first time Ta and has not yet reached the second time Tb (200 ns in accordance with this diagram).

[0282] Furthermore, between time t1 and time t2, the RS flip-flop 461 receives a low-level second timer signal S13 at its set input terminal (S). Therefore, regardless of the logic level of the control signal S14 input to its reset input terminal (R), the RS flip-flop 461 maintains the detection signal S8 at a low level. Therefore, the inverted signal S15 is maintained at a high level (not shown).

[0283] Furthermore, from time t1 to time t2, the AND gate AG1 receives the control signal S9 maintained at a low level at its first input terminal and the inverted signal S15 maintained at a high level at its second input terminal, causing the AND gate AG1 to set the first drive control signal S4 to a low level (not shown).

[0284] Furthermore, from time t1 to time t2, inverter IV1 receives control signal S9 maintained at a low level and maintains control signal S17 at a high level (not shown). Therefore, AND gate AG2 receives control signal S17 maintained at a high level at its first input terminal and detection signal S8 maintained at a low level at its second input terminal. As a result, AND gate AG2 maintains second drive control signal S5a at a low level (not shown) until time t2 arrives.

[0285] Furthermore, from time t1 to time t2, the control signal S9 maintained at a low level is input to the first input terminal of the AND gate AG3, and the detection signal S8 maintained at a low level is input to the second input terminal of the AND gate AG3, so that the AND gate AG3 maintains the second drive control signal S5b at a low level (not shown).

[0286] As described above, the first drive control signal S4 and the second drive control signals S5a and S5b are maintained at a low level from time t1 to time t2. Then, until time t2 arrives, transistor P1 is off, transistor N1 is on, and switches SW3a and SW3b are off. Therefore, the reference voltage VEE2 is supplied from the fourth external terminal T4. Therefore, the drive voltage Vgh is at a low level from time t1 to time t2. Therefore, as described above, the period from time t1 to time t2 is the off period Toff of the switch SW1 to be driven.

[0287] During the period from time t1 to time t2, the third timer circuit 459 receives the inverted signal S15 at a high level and maintains the third timer signal S16 at a low level.

[0288] At time t2, the ECU2 raises the discharge signal ACD to a high level while maintaining the input signal INH at a low level. Then, at time t3, a predetermined time after time t2, the ECU2 raises the input signal INH to a high level while maintaining the discharge signal ACD at a low level. During the soft turn-on period Tson until time t6, the ECU2 maintains the logic levels of the discharge signal ACD and the input signal INH.

[0289] From time t3 until time t4a, when the pulse stop time Td has elapsed, the logic circuit 416 receives the input signal INH at a low level and the discharge signal ACD at a high level, and maintains the first internal signal S1 at a low level and pulses the second internal signal S2 at a specific cycle. When time t4a arrives, the logic circuit 416 maintains the first internal signal S1 at a low level and the second internal signal S2 at a low level.

[0290] Furthermore, from time t3 to time t4a, the RS flip-flop 456 receives the first internal signal S1 maintained at a low level as input to its set terminal (S), and receives the second internal signal S2, which pulses at a specific period, as input to its reset terminal (R). At time t3, the output terminal (Q) of the RS flip-flop 456 (= the logical level of the control signal S9) is set to a low level. Therefore, as described above, the RS flip-flop 456 maintains the control signal S9 at a low level until time t7, when the first internal signal S1 input to its set terminal (S) next pulses.

[0291] Between time t3 and time t4a, the OR gate OG1 receives the first internal signal S1 maintained at a low level at its first input terminal and the second internal signal S2 pulsed at a specific period at its second input terminal, so that between time t3 and time t4a, the OR gate OG1 pulses the monitoring signal S10 (not shown) in synchronization with the pulse driving of the second internal signal S2.

[0292] Furthermore, when time t3 arrives, the first timer circuit 457 raises the first timer signal S11 to high level in synchronization with the pulse timing of the monitoring signal S10 (= the pulse timing of the second internal signal S2). Between time t3 and time t4a, the second internal signal S2 is pulse-driven at a specific cycle shorter than the first time Ta. Therefore, the timing of the next pulse of the monitoring signal S10 arrives before the first time Ta has elapsed since the pulse timing of the monitoring signal S10. As a result, the first timer circuit 457 continues to maintain the first timer signal S11 at high level without lowering it to low level.

[0293] When the second time Tb has elapsed since time t3 and time t4 arrives, the second timer circuit 458 determines that the high-level duration of the first timer signal S11 has reached the second time Tb, and raises the second timer signal S13 to a high level. In other words, the second timer circuit 458 maintains the second timer signal S13 at a low level until time t4.

[0294] Between time t3 and time t4, the RS flip-flop 461 receives a low-level second timer signal S13 at its set input terminal (S). During this period, the RS flip-flop 461 receives a low-level third timer signal S16 at its reset input terminal (R). Therefore, between time t3 and time t4, the RS flip-flop 461 sets the detection signal S8 to a low level.

[0295] Between time t3 and time t4, the AND gate AG1 receives a low-level control signal S9 at its first input terminal and a low-level detection signal S8 at its second input terminal, causing the AND gate AG1 to set the first drive control signal S4 to a low level between time t3 and time t4.

[0296] Furthermore, from time t3 to time t4, the AND gate AG2 receives the high-level control signal S17 at its first input terminal and the low-level detection signal S8 at its second input terminal, so that the AND gate AG2 maintains the second drive control signal S5a at a low level from time t3 to time t4.

[0297] Furthermore, between time t3 and time t4, the AND gate AG3 receives the low-level control signal S9 at its first input terminal and the low-level detection signal S8 at its second input terminal, so that the AND gate AG3 maintains the second drive control signal S5b at a low level between time t3 and time t4.

[0298] Therefore, from time t3 to time t4, transistor P1 is turned off, transistor N1 is turned on, and switches SW3a and SW3b are turned off. As a result, the reference voltage VEE2 is supplied from the fourth external terminal T4. Therefore, the drive voltage Vgh is maintained at a low level.

[0299] At time t4a, when the pulse stop time Td described above has elapsed since time t3, the logic circuit 416 (more specifically, the pulse generating circuit 453) stops pulsing the second internal signal S2 and maintains the second internal signal S2 at a low level. Then, at time t4b, when a first time Ta has elapsed since time t4a, the first timer circuit 457 causes the first timer signal S11 to fall to a low level. Therefore, at time t4b, the second timer circuit 458 causes the second timer signal S13 to fall to a low level.

[0300] When the second timer signal S13 rises to a high level at time t4, the RS flip-flop 461 raises the detection signal S8 to a high level. At this time, the RS flip-flop 461 also lowers the inverted signal S15 to a low level. When the second timer signal S13 falls to a low level at time t4b, the low-level control signal S14 is input to the reset input terminal (R) of the RS flip-flop 461. Therefore, at time t4b, the RS flip-flop 461 maintains the detection signal S8 at a high level and the inverted signal S15 at a low level.

[0301] When the inverted signal S15 falls to a low level at time t4, the third timer circuit 459 receives the low-level inverted signal S15 and sets the third timer signal S16 to a high level. When a third time Tc has elapsed since time t4 and time t5 arrives, the third timer circuit 459 sets the third timer signal S16 to a low level.

[0302] Between time t4 and time t5, the NOR gate NG1 receives the high-level third timer signal S16 at its second input terminal. Therefore, between time t4 and time t5, the NOR gate NG1 maintains the control signal S14 at a low level, regardless of the logic level of the monitoring signal S10 input to its first input terminal. Therefore, the RS flip-flop 461 maintains the detection signal S8 at a high level even after time t4b while the control signal S14 is maintained at a low level.

[0303] Furthermore, from time t4 to time t7, the AND gate AG2 receives a high-level control signal S17 at its first input terminal and a high-level detection signal S8 at its second input terminal, causing the AND gate AG2 to set the second drive control signal S5a to a high level.

[0304] Furthermore, from time t4 to time t7, the AND gate AG3 receives the control signal S9 maintained at a low level at its first input terminal and the detection signal S8 maintained at a high level at its second input terminal, so that from time t4 to time t7, the AND gate AG3 maintains the second drive control signal S5b at a low level.

[0305] Between time t4 and time t7, the driver circuit 501 receives a high-level second drive control signal S5a and turns off the transistors P1 and N1 regardless of the logic level of the first drive control signal S4, so that between time t4 and time t7, the third external terminal T3 and the fourth external terminal T4 are in a high impedance state.

[0306] Furthermore, from time t4 to time t7, switch SW3b is turned on in response to the input of the high-level second drive control signal S5a. As a result, the soft turn-on signal Son is supplied from the sixth external terminal T6. Therefore, from time t4 to time t7, the drive voltage Vgh corresponds to the soft turn-on signal Son. That is, from time t4 to time t7, the drive voltage Vgh gradually increases at a predetermined slew rate (corresponding to the soft turn-on signal Son). Therefore, the period from time t4 to time t7 is the soft turn-on period Tson of the switch SW1 to be driven.

[0307] When time t6 arrives after a predetermined time has elapsed since time t5, the ECU 2 drops the discharge signal ACD to low level. Then, when time t7 arrives, the ECU 2 drops the input signal INH to low level while maintaining the discharge signal ACD at low level. After time t7, the input signal INH is maintained at low level until the next ON period Ton of the drive target switch SW1 arrives.

[0308] When the input signal INH falls to low level at time t7, the logic circuit 416 receives the input signal INH at low-high level and the discharge signal ACD at low level, and pulse-drives the second internal signal S2 at the normal cycle while maintaining the first internal signal S1 at low level. That is, the states of the first internal signal S1 and the second internal signal S2 become the same as they were from time t1 to time t2.

[0309] Therefore, from time t7 onwards, each signal is controlled in the same way as it was between time t1 and time t2. Specifically, this is as follows.

[0310] As described above, after time t7, the control signal S9 is maintained at a low level, and the monitoring signal S10 is pulse-driven to synchronize with the pulse drive of the second internal signal S2. Also, the first timer signal S11 is pulse-driven to have a pulse width of the first time Ta. Also, the second timer signal S13 is maintained at a low level, the detection signal S8 is maintained at a low level, and the inversion signal S15 is maintained at a high level. As a result, the first drive control signal S4 and the second drive control signals S5a and S5b are maintained at a low level.

[0311] Therefore, after time t7, similar to the period from time t1 to time t2, the drive voltage Vgh becomes a low level, which means the off period Toff of the drive target switch SW1.

[0312] During soft turn-off, when the edge detection circuit 450 detects the falling edge of the input signal INH, the control signal S7 is raised to a low level. In this case, the first internal signal S1 is pulse-driven at a specific period, and the second internal signal S2 is maintained at a low level. The internal control at this time is basically the same as the internal control during the above-described soft turn-on, but different in the following points.

[0313] When the above-described soft turn-on control is replaced with soft turn-off control, during the period from time t3 to time t4a described above, the first internal signal S1 that is pulse-driven at a specific period is input to the first input terminal, and the second internal signal S2 that is maintained at a low level is input to the second input terminal. Therefore, during the period from time t3 to time t4a, the OR gate OG1 pulse-drives the monitoring signal S10 to synchronize with the pulse drive of the first internal signal S1.

[0314] <Regarding the DESAT protection circuit> By the way, the electronic device 400 has a DESAT protection function for the drive target switch SW1. Hereinafter, the configuration regarding the DESAT protection function of the drive target switch SW1 will be described. Returning to FIG. 11, the electronic device 400 includes a resistor R3, a diode d5, and a capacitor C3 in addition to the above-described discrete components.

[0315] A first terminal of the resistor R3 is connected to an external terminal (more specifically, an eighth external terminal T8 described later) of the signal transmission device 200X. A second terminal of the resistor R3 is connected to the anode of the diode d5. A cathode of the diode d5 is connected to the node n1.

[0316] A first terminal of the capacitor C3 is connected to a first terminal of the resistor R3. A second terminal of the capacitor C3 is connected to the node n2, the first terminal of the capacitor C4, and the terminal to which the power supply voltage VCC2 is applied. A second terminal of the capacitor C4 is connected to the terminal to which the reference voltage VEE2 is applied. A low-pass filter is formed by the third external terminal T3, the capacitor C3, and the diode d5. A second terminal of the capacitor C4 is connected to the terminal to which the reference voltage VEE2 is applied.

[0317] In addition to the above-described configuration, the signal transmission device 200X includes a seventh external terminal T7 and an eighth external terminal T8. The seventh external terminal T7 and the eighth external terminal T8 are terminals for establishing electrical connection with the outside. The seventh external terminal T7 is provided on the controller chip 410. The eighth external terminal T8 is provided on the driver chip 420.

[0318] The controller chip 410 includes a third receiving circuit 413 and a fourth transmitting circuit 414 in addition to the above-mentioned configuration.

[0319] The third receiving circuit 413 is connected to the seventh external terminal T7. The third receiving circuit 413 receives the SAT monitoring signal Sdst from the third transmitting circuit 423 (described later) via a transformer chip 430 (more specifically, a third transformer 433). The third receiving circuit 413 inputs the input SAT monitoring signal Sdst to the ECU 2 via the seventh external terminal T7.

[0320] The fourth transmission circuit 414 is connected to the first external terminal T1. The fourth transmission circuit 414 receives an input of an input signal INH from the ECU 2 via the first external terminal T1. The fourth transmission circuit 414 transmits the input signal INH to the driver chip 420 (more specifically, a fourth reception circuit 424, which will be described later) via the transformer chip 430 (more specifically, a fourth transformer 434).

[0321] The driver chip 420 includes a third transmitting circuit 423, a fourth receiving circuit 424, and a DESAT protection circuit 440 in addition to the above-mentioned configuration.

[0322] The third transmission circuit 423 is connected to the DESAT protection circuit 440. The third transmission circuit 423 receives an input of the SAT monitoring signal Sdst from the DESAT protection circuit 440. The third transmission circuit 423 inputs the input SAT monitoring signal Sdst to the third reception circuit 413 via a transformer chip 430 (more specifically, a third transformer 433).

[0323] The fourth receiving circuit 424 is connected to the DESAT protection circuit 440. The fourth receiving circuit 424 receives the input signal INH from the fourth transmitting circuit 414 via the transformer chip 430 (more specifically, the fourth transformer 434). The fourth receiving circuit 424 inputs the input signal INH to the DESAT protection circuit 440.

[0324] The DESAT protection circuit 440 is connected to the third transmitting circuit 423, the fourth receiving circuit 424, and the eighth external terminal T8. As described above, the DESAT protection circuit 440 receives the input signal INH. As described above, the DESAT protection circuit 440 inputs the SAT monitoring signal Sdst to the third transmitting circuit 423.

[0325] The DESAT protection circuit 440 is a circuit that monitors the SAT (saturation) voltage of the switch SW1 to be driven and protects the switch SW1 from overcurrent and overvoltage. The SAT voltage is the base-emitter voltage of the switch SW1 to be driven while it is on.

[0326] The DESAT protection circuit 440 passes a predetermined monitor current Im between the collector and emitter of the switch SW1 to be driven while the switch SW1 is on. At this time, a voltage is generated across the resistor R3. The DESAT protection circuit 440 monitors the SAT voltage of the switch SW1 to be driven by detecting the voltage generated across the resistor R3 via the eighth external terminal T8.

[0327] The DESAT protection circuit 440 determines the on-period and off-period of the switch SW1 to be driven based on the logic level of the input signal INH. Specifically, when the input signal INH is at a high level, the DESAT protection circuit 440 determines that the switch SW1 to be driven is in an on-period and outputs the monitoring current Im. Conversely, when the input signal INH is at a low level, the DESAT protection circuit 440 determines that the switch SW1 to be driven is in an off-period and stops outputting the monitoring current Im.

[0328] The DESAT protection circuit 440 generates a SAT monitoring signal Sdst according to the monitoring state. As described above, the SAT monitoring signal Sdst is input to the ECU 2 via the third transmitting circuit 423, the third transformer 433, and the third receiving circuit 413.

[0329] The ECU2 controls the input signal INH and the discharge signal ACD in response to the SAT monitor signal Sdst. Specifically, when the collector-emitter voltage exceeds a predetermined voltage value, the ECU2 generates the input signal INH and the discharge signal ACD to turn off the switch SW1 to be driven. More specifically, this is as follows.

[0330] If the collector-emitter voltage does not exceed the predetermined voltage value, the DESAT protection circuit 440 maintains the SAT monitoring signal Sdst at a low level. If the collector-emitter voltage exceeds the predetermined voltage value, the DESAT protection circuit 440 raises the SAT monitoring signal Sdst to a high level.

[0331] When the SAT monitoring signal Sdst is at a low level, the ECU 2 generates an input signal INH and a discharge signal ACD so that the switch SW1 to be driven performs normal on / off operations, soft turn-on operations, or soft turn-off operations as described above. On the other hand, when the SAT monitoring signal Sdst is at a high level, the ECU 2 sets the input signal INH and the discharge signal ACD to a low level so that the switch SW1 to be driven is forced to be in an off state.

[0332] Therefore, when the SAT monitoring signal Sdst is at a high level, the first internal signal S1 and the second internal signal S2 maintained at a low level are input to the logic circuit 429. As a result, the first drive circuit 426 is in an effective state, and the soft turn-on control circuit 502a and the soft turn-off control circuit 502b are in an ineffective state. At this time, the drive signal GH becomes a high level and becomes the drive signal GL. Therefore, when the SAT monitoring signal Sdst becomes a high level, the switch SW1 to be driven turns off.

[0333] In this way, when the collector-emitter voltage exceeds a predetermined voltage value during the on-period of the switch SW1 to be driven, the switch SW1 to be driven turns off. Therefore, the switch SW1 to be driven is protected from overvoltage and overcurrent.

[0334] <Regarding the DESAT protection standby time> As described above, the DESAT protection circuit 440 outputs a monitoring current Im during the on-period of the switch SW1 to be driven. On the other hand, during the off-period of the switch SW1 to be driven, the collector-emitter of the switch SW1 to be driven is in a non-conducting state. Therefore, as described above, the DESAT protection circuit 440 stops outputting the monitoring current Im.

[0335] Here, the drive voltage Vgh rises from low to high at the timing when the input signal INH rises from low to high. More precisely, at this timing, the drive voltage Vgh makes a steep transition from low to high with a slight slew rate. Therefore, strictly speaking, the drive target switch SW1 transitions from the OFF state to the ON state after a predetermined transition time has elapsed since the input signal INH rose to high.

[0336] Let us assume that the DESAT protection circuit 440 starts operating when the input signal INH rises to a high level. In this case, the DESAT protection circuit 440 starts outputting the monitoring current Im while the driven switch SW1 is in the middle of transitioning from the OFF state to the ON state.

[0337] If the drive voltage Vgh does not exceed the on-threshold voltage of the switch SW1 at this point, there is no conduction between the collector and emitter of the switch SW1. If the switch SW1 outputs the monitoring current Im in this state, no current will flow through the switch SW1, and capacitor C3 will be unintentionally charged.

[0338] As a result, the voltage at the eighth external terminal T8 rises regardless of the SAT voltage of the drive target switch SW1, which causes the DESAT protection circuit 440 to erroneously detect an overvoltage state of the drive target switch SW1 even though the switch SW1 is not in an overvoltage state.

[0339] To prevent such false detection, the DESAT protection circuit 440 of the present disclosure provides a predetermined blanking period from the time when the input signal INH rises to a high level. During the blanking period, the switch SW1 to be driven is not turned on, and the DESAT protection circuit 440 waits.

[0340] The blanking period is set based on the general time it takes for the driving voltage Vgh to complete a transition from a low level to a high level, and is set to, for example, 50 ns to 600 ns.

[0341] <Considerations regarding blanking periods> As described above, the signal transmission device 200X of the present disclosure may soft-turn on the drive target switch SW1. In this case, since the drive target switch SW1 is in an on-period, the DESAT protection circuit 440 monitors the SAT voltage of the drive target switch SW1. However, as described above, the soft turn-on signal Son gradually rises at a relatively gentle slew rate. When the drive target switch SW1 switches from an off-period to a soft turn-on period, it takes longer for the drive voltage Vgh to complete its transition from low to high compared to when the drive target switch SW1 switches from a normal off-period to an on-period.

[0342] Even if the blanking period described above is set, the drive voltage Vgh may not exceed the on-threshold voltage of the switch SW1 when the blanking period elapses. This causes the DESAT protection circuit 440 to start outputting the monitoring current Im while the switch SW1 is in the off state. This can lead to the DESAT protection circuit 440 making an erroneous detection, as described above.

[0343] If the DESAT protection circuit 440 makes a false detection, the ECU 2 forcibly drops the input signal INH and the discharge signal ACD to low level while the driven switch SW1 is performing a soft turn-on operation, which turns off the driven switch SW1, preventing effective active discharge and preventing the charge from being properly drawn from the capacitor C1.

[0344] Therefore, the signal transmission device 200X of the present disclosure is configured to be able to suppress erroneous detection by the DESAT protection circuit 440. Specifically, this is as follows.

[0345] In addition to the above-described configuration, the controller chip 410 includes a fifth transmission circuit 415. The fifth transmission circuit 415 is connected to the second external terminal T2. The fifth transmission circuit 415 receives an input of a discharge signal ACD from the ECU 2 via the second external terminal T2. The fifth transmission circuit 415 inputs the input discharge signal ACD to the driver chip 420 (more specifically, a fifth reception circuit 425 described later) via the transformer chip 430 (more specifically, a fifth transformer 435 described later).

[0346] In addition to the above-described configuration, the driver chip 420 includes a fifth receiving circuit 425. The fifth receiving circuit 425 receives the discharge signal ACD from the fifth transmitting circuit 415 via the transformer chip 430 (more specifically, a fifth transformer 435, which will be described later). The fifth transmitting circuit 415 inputs the discharge signal ACD to the DESAT protection circuit 440.

[0347] As described above, the DESAT protection circuit 440 receives the discharge signal ACD from the fifth receiving circuit 425. Based on the input signal INH and the discharge signal ACD, the DESAT protection circuit 440 determines whether the drive target switch SW1 is in the soft turn-on period. Specifically, the determination is as follows.

[0348] When the input signal INH is at a high level and the discharge signal ACD is at a low level, the DESAT protection circuit 440 determines that the switch SW1 to be driven is in a normal on-period. At this time, the DESAT protection circuit 440 enters a standby state without outputting the monitoring current Im for the first blanking period TB1 from the time the input signal INH rises to a high level. After the first blanking period TB1 has elapsed, the DESAT protection circuit 440 outputs the monitoring current Im.

[0349] When the input signal INH is high and the discharge signal ACD is low, the DESAT protection circuit 440 determines that the switch SW1 is in the soft turn-on period. During this period, the DESAT protection circuit 440 enters a standby state without outputting the monitoring current Im for the second blanking period TB2 from the time the input signal INH rises to high. After the second blanking period TB2 has elapsed, the DESAT protection circuit 440 outputs the monitoring current Im.

[0350] When the input signal INH is at a low level, the DESAT protection circuit 440 determines that the switch SW1 to be driven is in an off period, and goes into a standby state without outputting the monitoring current Im, as described above.

[0351] The second blanking period TB2 is set to be longer than the first blanking period TB1. The second blanking period TB2 is set to be 1.5 times or more and 160 times or less the first blanking period TB1. For example, when the first blanking period TB1 is set to 1 ns to 600 ns, the second blanking period TB2 should be set to 1 μs to 8 μs. More preferably, the second blanking period TB2 is 10 times or more and 30 times or less the first blanking period TB1. Specifically, it is as follows.

[0352] Fig. 14 is a table showing the setting states of the first blanking period TB1 and the second blanking period TB2. For example, as shown in Fig. 14, suppose the first blanking period TB1 is set to No. 1, 200 ns. Also, suppose the second blanking period TB2 is set to 3 μs.

[0353] In this case, if the DESAT protection circuit 440 determines that the switch SW1 to be driven is in an on-period, the DESAT protection circuit 440 will enter a standby state without outputting the monitoring current Im for 200 ns from the time the input signal INH rises to a high level.

[0354] In this case, if the DESAT protection circuit 440 determines that the switch SW1 to be driven is in the soft turn-on period, the DESAT protection circuit 440 will enter a standby state without outputting the monitoring current Im for 3 μs from the time the input signal INH rises to high level.

[0355] As described above, the DESAT protection circuit 440 of the present disclosure enters a standby state during the second blanking period TB2, which is a relatively long period from the rising edge of the input signal INH, during soft turn-on of the switch SW1 to be driven. Therefore, as described above, the DESAT protection circuit 440 is prevented from outputting the monitoring current Im when the drive voltage Vgh does not exceed the on-threshold voltage of the switch SW1 to be driven. This prevents the DESAT protection circuit 440 from falsely detecting the soft turn-on of the switch SW1 to be driven.

[0356] <Modification> The present invention is not limited to the above-described embodiments and various modifications are possible without departing from the spirit of the present invention. For example, although the switch SW1 to be driven is described as an IGBT, this is not limiting. For example, the switch SW1 to be driven can be an N-channel or P-channel MOSFET. In this case, the meanings described in this specification, FIGS. 1 to 16, and the claims can be interpreted with the emitter and collector of the switch SW1 to be driven as the source and drain, respectively. In this case, the SAT voltage is understood to be the gate-source voltage during the ON period of the switch SW1 to be driven.

[0357] <Implementation example of the signal transmission device 200X of the present disclosure> Fig. 15 is a block diagram showing an implementation example of a signal transmission device 200X of the present disclosure. Fig. 16 is a diagram showing a vehicle A equipped with an electronic device 400. The electronic device 400 equipped with the signal transmission device 200X of the present disclosure can be suitably used in the vehicle A (see Fig. 16), which is an engine vehicle or an electric vehicle. The electronic device 400 can be suitably used as a motor drive device that controls the drive of a motor M mounted on the vehicle A.

[0358] As shown in FIG. 15, the motor M is a three-phase motor that is rotationally driven in accordance with three-phase drive voltages U / V / W input from three-phase (U phase / V phase / W phase) half-bridge output stages.

[0359] The electronic device 400 has three insulated gate drivers 1H(u / v / w), three insulated gate drivers 1L(u / v / w), three high-side switch elements SWH(u / v / w), three low-side switch elements SWL(u / v / w), an ECU2, and a capacitor C1.

[0360] The insulated gate drivers 1H(u / v / w) drive the high-side switch elements SWH(u / v / w) by generating an upper gate drive signal (corresponding to the aforementioned drive voltage Vgh) in response to an upper gate control signal INH (corresponding to the aforementioned input signal INH) input from the ECU 2 while insulating the ECU 2 from the high-side switch elements SWH(u / v / w).

[0361] The insulated gate drivers 1L(u / v / w) drive the low-side switch elements SWL(u / v / w) by generating a low-side gate drive signal (corresponding to the aforementioned drive voltage Vgh) in response to a low-side gate control signal INL (corresponding to the aforementioned input signal INL) input from the ECU2 while insulating the ECU2 from the low-side switch elements SWL(u / v / w).

[0362] The high-side switch elements SWH(u / v / w) are gate-driven by respective insulated gate drivers 1H(u / v / w), and are connected between the power supply terminal (= the terminal to which the first motor drive voltage VD1 is applied) and each phase input terminal of the motor M.

[0363] The low-side switch elements SWL(u / v / w) are gate-driven by respective insulated gate drivers 1L(u / v / w), and are connected between the input terminals of each phase of the motor M and the power system ground terminal (= the terminal to which the second motor drive voltage VD2 is applied).

[0364] In this figure, IGBTs are used as the high-side switch elements SWH(u / v / w) and the low-side switch elements SWL(u / v / w), but as mentioned above, SiC-MOSFETs or Si-MOSFETs can also be used instead of IGBTs.

[0365] The ECU 2 controls the rotational drive of the motor M by driving the high-side switch element SWH(u / v / w) and the low-side switch element SWL(u / v / w) via the isolated gate drivers 1H(u / v / w) and 1L(u / v / w). The ECU 2 also has a function to monitor the FLT1 terminal and the FLT2 terminal of each of the isolated gate drivers 1H(u / v / w) and 1L(u / v / w) and perform various safety controls.

[0366] A capacitor C1 (corresponding to the aforementioned capacitor C1) is provided to smooth the voltage between the application terminals of the first motor drive voltage VD1 and the second motor drive voltage VD2. Capacitor C1 stabilizes the DC voltage (= the voltage between the application terminals of the first motor drive voltage VD1 and the second motor drive voltage VD2) that fluctuates in accordance with fluctuations in the power consumption of the motor M.

[0367] Here, the aforementioned signal transmission device 200X can be suitably used as the insulated gate drivers 1H (u / v / w) and 1L (u / v / w), respectively. For example, the insulated gate driver 1H and the insulated gate driver 1L of one of the three phases (for example, the U phase in accordance with this figure) can be the aforementioned signal transmission device 200X.

[0368] When the aforementioned signal transmission device 200X is used as the insulated gate driver 1H(u / v / w), the drive target switch SW1 in FIG. 10 becomes the high-side switch element SWH(u / v / w) in FIG. 15. In this case, the node n1 shown in FIGS. 10 and 11 can be considered as the application terminal of the first motor drive voltage VD1 in FIG. 15. Furthermore, the node n2 shown in FIGS. 10 and 12 can be considered as the connection terminal with the motor M in FIG. 15.

[0369] Furthermore, when the aforementioned signal transmission device 200X is used as the insulated gate driver 1L(u / v / w), the drive target switch SW1 in FIG. 11 becomes the low-side switch element SWL(u / v / w) in FIG. 15. In this case, the node n1 shown in FIG. 11 can be considered as the connection terminal with the motor M in FIG. 15. Furthermore, the node n2 shown in FIG. 11 can be considered as the application terminal of the second motor drive voltage VD2 in FIG. 15. Furthermore, in this case, the input signal INH in FIG. 11 and the corresponding description above can be interpreted as the input signal INL.

[0370] <Additional Notes> The signal transmission device (200X) disclosed in the specification includes a transmitting circuit (410) configured to output a first internal signal (S1) and a second internal signal (S2) that are pulse-driven in response to first input signals (INH, INL), a receiving circuit (420) configured to output a drive voltage (Vgh) in response to the first internal signal (S1) and the second internal signal (S2) to drive and control a switch (SW1) to be driven, and a power supply (110) for transmitting the first internal signal (S1) and the second internal signal (S2) while isolating the transmitting circuit (410) from the receiving circuit (420). and a protection circuit (440) configured to monitor the SAT voltage of the switch (SW1) to be driven during an on-period (Ton, Tson) of the switch (SW1), wherein the transmitting circuit (410) drives at least one of a first internal signal (S1) and a second internal signal (S2) in a specific cycle different from the cycle of the first input signal (INH, INL) in response to a second input signal (ACD) different from the first input signal (INH, INL), and the receiving circuit (420) drives at least one of a first internal signal (S1) and a second internal signal (S2) in a specific cycle different from the cycle of the first input signal (INH, INL) in a state where the receiving circuit (420) is enabled. a first driving circuit (426) configured to generate a driving voltage (Vgh) based on the first internal signal (S1) and drive and control the switch (SW1) to be driven; a second driving circuit (502) configured to generate a driving voltage (Vgh) so as to drive the switch (SW1) to be driven slower than the first driving circuit (426) when the first driving circuit (426) is enabled, and drive and control the switch (SW1); and a second driving circuit (502) configured to detect that the period of at least one of the first internal signal (S1) and the second internal signal (S2) is a specific period, and to disable the first driving circuit (426) and to disable the second driving circuit ( and a drive control circuit (429) configured to enable a drive circuit (426) and a second drive circuit (502), and the protection circuit (440) starts monitoring the SAT voltage after a first blanking period (TB1) has elapsed from the start of a transition period from an OFF state to an ON state of the drive target switch (SW1) or a transition period from an ON state to an OFF state of the drive target switch (SW1) based on the first input signals (INH, INL) and the second input signal (ACD) when the first drive circuit (426) is enabled and the second drive circuit (502) is disabled, and when the first drive circuit (426) is disabled and the second drive circuit (502) is disabled,After a second blanking period (TB2) longer than the first blanking period (TB1) has elapsed from the start point, the SAT voltage starts to be monitored (first configuration).

[0371] In the signal transmission device (200X) according to the first configuration, the second blanking period (TB2) is 1.5 times or more and 160 times or less than the first blanking period (TB1) (second configuration).

[0372] In the signal transmission device (200X) according to the first or second configuration, the second drive circuit (502) includes a soft turn-on control circuit (502a) that, when enabled, generates a soft turn-on signal (Son) as a drive voltage (Vgh) that drives and controls the switch (SW1) to be driven so that the switch (SW1) is changed from an off state to an on state within a predetermined transition period, and a soft turn-off control circuit (502b) that, when enabled, generates a soft turn-off signal (Soff) as a drive voltage (Vgh) that drives and controls the switch (SW1) to be driven so that the switch (SW1) is changed from an on state to an off state within a predetermined transition period, and drives and controls the switch (SW1). The enabled state of the second drive circuit (502) is either a state in which the soft turn-on control circuit (502a) is enabled and the soft turn-off control circuit (502b) is disabled, or a state in which the soft turn-on control circuit (502a) is disabled and the soft turn-off control circuit (502b) is enabled (third configuration).

[0373] The electronic device (400) disclosed in the specification includes a signal transmission device (200X) according to any one of the first to third configurations, a control circuit (2) configured to generate a first input signal (INH, INL) and a second input signal (ACD), and a drive target switch (SW1) (fourth configuration).

[0374] In the electronic device (400) according to the fourth configuration, the protection circuit (440) generates a monitoring signal (Sdst) based on the monitoring result, and the control circuit (2) generates first input signals (INH, INL) based on the monitoring signal (Sdst) (fifth configuration).

[0375] In an electronic device (400) according to a fifth configuration, a protection circuit (440) generates a monitoring signal (Sdst) according to whether or not the SAT voltage exceeds a predetermined voltage value, and when a control circuit (2) determines based on the monitoring signal (Sdst) that the SAT voltage exceeds the voltage value, it generates first input signals (INH, INL) and a second input signal (ACD) so that the switch to be driven (SW1) is turned off (sixth configuration).

[0376] The vehicle (A) disclosed in the specification includes an electronic device (400) according to any one of the fourth and fifth configurations (seventh configuration). [Explanation of symbols]

[0377] 5. Semiconductor Devices 11, 11A~11F Low potential terminal 12, 12A~12F high potential terminal 21, 21A~21D Transformer 22 Low potential coil (primary coil) 23 High potential coil (secondary coil) 24 1st medial end 25 First outer end 26 1st spiral part 27 Second medial end 28 Second outer end 29 Second spiral part 31 1st low potential wiring 32 2nd low potential wiring 33 1st high potential wiring 34 2nd high potential wiring 41 Semiconductor chips 42 First main surface 43 Second main surface 44A~44D Chip sidewall 45 First Functional Device 51 Insulating layer 52 Main insulating surface 53A~53D Insulated sidewall 55 Bottom insulating layer 56 Top insulating layer 57 Interlayer insulation layer 58 First insulating layer 59 Second insulating layer 60 Second Function Device 61 Sealed conductor 62 Device Area 63 Outer area 64 Seal plug conductor 65 Seal via conductor 66 1st medial area 67 Second medial area 71 Through-wiring 72 Low-potential connection wiring 73 Lead Wiring 74 First connecting plug electrode 75 Second connecting plug electrode 76 Pad plug electrode 77 PCB plug electrode 78 1st electrode layer 79 Second electrode layer 80 Wiring plug electrode 81 High-potential connection wiring 82 Pad plug electrode 85 Dummy Pattern 86 High-potential dummy pattern 87 First high potential dummy pattern 88 Second high potential dummy pattern 89 First area 90 Second area 91 Third area 92 First connection part 93 First Pattern 94 Second Pattern 95 Third Pattern 96 First Outer Line 97 Second Outer Line 98 First Intermediate Line 99 First connecting line 100 slits 130 Separation structure 140 Inorganic insulating layer 141 First inorganic insulating layer 142 Second inorganic insulating layer 143 Low potential pad opening 144 High potential pad opening 145 Organic insulating layer 146 Part 1 147 Part 2 148 Low potential terminal opening 149 High potential terminal opening 200 Signal Transmission Device 200p primary circuit system 200s Secondary circuit system 210 Controller Chip (1st Chip) 211 Pulse transmitting circuit (pulse generator) 212, 213 buffer 220 Driver Chip (Second Chip) 221, 222 buffer 223 Pulse receiving circuit (RS flip-flop) 224 Driver 230 Transformer Chip (3rd Chip) 230a 1st wiring layer (lower layer) 230b 2nd wiring layer (upper layer) 231, 232 transformer 231p, 232p Primary coil 231s, 232s Secondary coil 300 Trans Chip 301 1st transformer 302 2nd transformer 303 Third Transformer 304 4th Transformer 305 1st Guard Ring 306 Second Guard Ring a1 to a8 pads (corresponding to the first current supply pads) b1~b8 pads (corresponding to the first voltage measurement pads) c1 to c4 pads (corresponding to the second current supply pads) d1~d4 pads (corresponding to the second voltage measurement pads) e1, e2 pads L1p, L2p Primary coil L1s, L2s, L3s, L4s Secondary coil T21, T22, T23, T24, T25, T26 external terminals X 1st direction X21, X22, X23 internal terminals Y Second direction Y21, Y22, Y23 wiring Z normal direction Z21, Z22, Z23 vias 200X Signal Transmitter 300 Trans Chip 301 1st transformer 302 2nd transformer 303 Third Transformer 304 4th Transformer 400 Electronic equipment 410 Controller chip (transmitting circuit) 411 First transmitting circuit 412 Second transmission circuit 413 3rd receiving circuit 414 4th transmission circuit 415 5th Transmission Circuit 416 Logic Circuits 420 driver chip (receiving circuit) 421 1st receiving circuit 422 Second receiving circuit 423 3rd transmission circuit 424 4th receiving circuit 425 5th Receiving Circuit 429 Logic Circuit (Drive Control Circuit) 430 Transformer chip (isolated circuit) 431 1st Trans 432 2nd Transformer 433 3rd Trans 434 4th Trans 435 5th Trans 440 DESAT protection circuit (protection circuit) 450 Edge detection circuit 451 Clock Circuit 452 D Flip-Flop 453 Pulse Generator Circuit 454 Driver control circuit 455 detection circuit 456 RS Flip-Flop 457 First timer circuit 458 Second timer circuit 459 Third timer circuit 460 Discharge control circuit 461 RS Flip-Flop 501 Driver Circuit 501 First drive circuit 502 Second driving circuit 502a Soft turn-on control circuit 502b Soft turn-off control circuit 503a, 503b signal generation circuit Vehicle A ACD discharge signal (second input signal) AG1~AG3 AND gate C1, C3 capacitors GH, GL drive signal INH, INL input signal (first input signal) IV1 Inverter Im monitoring current Medium motor NG1 NOR gate OG1, OG2 OR gates P1, N1 transistors R1~R3 ​​resistance RST Reset signal S1 1st internal signal S2 2nd internal signal S4 First drive control signal S5a, S5b Second drive control signal S6 Edge detection signal S7 Control Signal S8 detection signal S9 Control Signal S10 monitoring signal S11 First timer signal S12 control signal S13 Second timer signal S14 control signal S15 Inverted signal S16 Third timer signal S17 Control signal SW1, SW2 Drive target switch SW3a and SW3b switches SWH High-side switch element SWL Low-side switch element Sdst SAT monitoring signal (monitoring signal) Soff Soft turn-off signal Son soft turn-on signal T1 First external terminal T2 Second external terminal T3 Third external terminal T4 4th external terminal T5 5th external terminal T6 6th external terminal T7 7th external terminal T8 8th external terminal TB1 First blanking period TB2 Second blanking period Ta 1st time Tb 2nd Hour Tc 3rd hour Td Pulse stop time Toff Off period Ton On period Tson soft turn-on period Tv1 Primary side power supply terminal Tv2 Secondary power supply terminal U Drive voltage UVLO constant voltage malfunction prevention circuit VCC1 power supply voltage VCC2 power supply voltage VD1 First motor drive voltage VD2 Second motor drive voltage VEE2 reference voltage VOUT Output voltage Vgh drive voltage Vgh, Vgl drive voltage d5 diode n1 and n2 nodes

Claims

1. a transmitter circuit configured to output a first internal signal and a second internal signal that are pulse-driven in response to a first input signal; a receiving circuit configured to output a drive signal in response to the first internal signal and the second internal signal, and to drive and control the switch to be driven; an isolation circuit configured to transmit the first internal signal and the second internal signal while isolating the transmitting circuit from the receiving circuit; a protection circuit configured to monitor a SAT voltage of the switch to be driven during an ON period of the switch to be driven; Equipped with the transmitting circuit drives at least one of the first internal signal and the second internal signal in response to a second input signal different from the first input signal, at a specific cycle different from the cycle of the first input signal; The receiving side circuit includes: a first driving circuit configured to generate the driving signal based on the first input signal when the first driving circuit is enabled, and to drive and control the switch to be driven; a second driving circuit configured to generate the driving signal so as to drive the switch to be driven slower than the first driving circuit when the second driving circuit is enabled, and to drive and control the switch to be driven; a drive control circuit configured to detect that the period of at least one of the first internal signal and the second internal signal is the specific period, and to disable the first drive circuit and enable the second drive circuit; Equipped with The protection circuit, based on the first input signal and the second input signal, When the first drive circuit is enabled and the second drive circuit is disabled, the SAT voltage is monitored after a first blanking period has elapsed from the start of a transition period from an OFF state to an ON state or from an ON state to an OFF state of the switch to be driven, and When the first drive circuit is disabled and the second drive circuit is disabled, the signal transmission device starts monitoring the SAT voltage after a second blanking period that is longer than the first blanking period has elapsed from the starting point.

2. 2. The signal transmission device according to claim 1, wherein the second blanking period is 1.5 times or more and 160 times or less than the first blanking period.

3. The second drive circuit is a soft turn-on control circuit that generates, as a drive signal, a soft turn-on signal that drives and controls the switch to be driven so that the switch to be driven changes from an off state to an on state within a predetermined transition period while the soft turn-on control circuit is enabled; and a soft turn-off control circuit that generates, as a drive signal, a soft turn-off signal that drives and controls the switch to be driven so that the switch to be driven changes from an on state to an off state within a predetermined transition period while the soft turn-off control circuit is enabled; and Equipped with The state in which the second driving circuit is enabled is a state in which the soft turn-on control circuit is enabled and the soft turn-off control circuit is disabled; or the soft turn-on control circuit is disabled and the soft turn-off control circuit is enabled; 2. The signal transmission device according to claim 1, wherein the signal transmission device is any one of the following:

4. A signal transmission device according to any one of claims 1 to 3; a control circuit configured to generate the first input signal and the second input signal; the switch to be driven; An electronic device comprising:

5. the protection circuit generates a monitoring signal based on the monitoring result; The electronic device according to claim 4 , wherein the control circuit generates the first input signal based on the monitor signal.

6. the protection circuit generates the monitoring signal according to whether the SAT voltage exceeds a predetermined voltage value; 6. The electronic device according to claim 5, wherein the control circuit generates the first input signal and the second input signal so that the switch to be driven is turned off when it determines based on the monitoring signal that the SAT voltage exceeds the voltage value.

7. A vehicle comprising the electronic device according to claim 4.

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