Signal transmission device, electronic device, and vehicle

Abstract

The signal transmission device has room for further consideration regarding drive control of the switch to be driven.SOLUTION: The signal transmission device 200X includes a transmission circuit S2 for outputting a control signal 350x, a reception circuit 400x, and an insulating circuit 500. The receiving circuit 400x receives an external signal S1x. The receiving circuit 400x drives the drive object switch S1x based on the control signal S2 in a state in which the external signal SW10 is at a first logic level, and drives and controls the drive object switch S1x based on the external signal S2 regardless of the control signal S1x in a state in which the external signal SW10 is at a second logic level.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The invention disclosed herein relates to a signaling device, an electronic device, and a vehicle. [Background technology]

[0002] BACKGROUND ART Signal transmission devices that transmit pulse signals while insulating input and output have been used in a variety of applications (such as power supply devices or motor drive devices).

[0003] As an example of the related prior art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2017-188903

[0005] [overview] The signal transmission device disclosed in Patent Document 1 leaves room for further consideration regarding drive control of the switch to be driven.

[0006] The signal transmission device disclosed in this specification includes a transmitter circuit, a receiver circuit, and an isolation circuit. The transmitter circuit is configured to output a pulse-driving control signal in response to an input signal. The receiver circuit is configured to drive a switch to be driven in response to the control signal. The isolation circuit is configured to transmit the control signal while providing insulation between the transmitter circuit and the receiver circuit. The receiver circuit receives an input of an external signal separate from the input signal. The receiver circuit drives the switch to be driven based on the control signal when the external signal is at a first logic level that is equal to or lower than a first threshold voltage, and drives and controls the switch to be driven based on the external signal regardless of the control signal when the external signal is at a second logic level that is higher than the first threshold.

[0007] The present specification discloses an electronic device including the signal transmission device having the above-described configuration, a control circuit, an external signal generation circuit, and a drive target switch. The control circuit is configured to generate an input signal. The external signal generation circuit is configured to generate an external signal.

[0008] The vehicle disclosed in this specification is equipped with the electronic device having the above-described configuration. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing the basic configuration of a signal transmission device. [Figure 2] FIG. 2 is a diagram showing the basic structure of a transformer chip. [Figure 3] FIG. 3 is a perspective view of a semiconductor device used as a two-channel transformer chip. [Figure 4] FIG. 4 is a plan view of the semiconductor device shown in FIG. [Figure 5] FIG. 5 is a plan view showing a layer in which a low potential coil is formed in the semiconductor device of FIG. [Figure 6] FIG. 6 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 8] FIG. 8 is an enlarged view (isolation structure) of region XIII shown in FIG. [Figure 9] FIG. 9 is a diagram schematically illustrating an example of the layout of a transformer chip. [Figure 10] FIG. 10 is a diagram showing the configuration of an electronic device 400 in which the signal transmission device 200Y is mounted. [Figure 11] FIG. 11 is a diagram showing the configuration of a signal transmission device 200X of the present disclosure. [Figure 12] 12 is a diagram showing the configuration of the driver-side logic circuit 401x. As shown in FIG. [Figure 13]FIG. 13 is a table showing the correlation between the logic levels of the output signals S8 to S10, the determination result signals S7a to S7d, the high-side signal GH, the low-side signal GL, the terminal voltage VH, and the terminal voltage VL and the state of the drive target switch SW10. [Figure 14] FIG. 14 is a diagram showing the configuration of a vehicle A on which electronic device 400 is mounted.

[0010] [Detailed explanation] <Signal transmission device (basic configuration)> 1 is a diagram showing the basic configuration of a signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 200p to the secondary circuit system 200s while insulating the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system) and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is configured by sealing a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0011] The controller chip 210 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC1 (for example, up to 7 V with respect to GND1). The controller chip 210 has integrated therein, for example, a pulse transmission circuit 211 and buffers 212 and 213.

[0012] The pulse transmitting circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmitting circuit 211 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputting a single or multiple transmission pulses), and when it notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. That is, the pulse transmitting circuit 211 pulse-drives either the transmission pulse signals S11 or S21 in response to the logic level of the input pulse signal IN.

[0013] The buffer 212 receives the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).

[0014] The buffer 213 receives the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).

[0015] The driver chip 220 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC2 (for example, up to 30 V with respect to GND2). The driver chip 220 has buffers 221 and 222, a pulse receiving circuit 223, and a driver 224 integrated therein.

[0016] The buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically, the transformer 231) and outputs the result to the pulse receiving circuit 223.

[0017] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically, the transformer 232) and outputs the result to the pulse receiving circuit 223.

[0018] The pulse receiving circuit 223 generates the output pulse signal OUT by driving the driver 224 in response to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 so that the output pulse signal OUT rises to a high level in response to the pulse driving of the received pulse signal S12, and the output pulse signal OUT falls to a low level in response to the pulse driving of the received pulse signal S22. In other words, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT in response to the logic level of the input pulse signal IN. Note that an RS flip-flop, for example, can be suitably used as the pulse receiving circuit 223.

[0019] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223 .

[0020] The transformer chip 230 provides DC insulation between the controller chip 210 and the driver chip 220 using transformers 231 and 232, and outputs transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 as reception pulse signals S12 and S22, respectively, to the pulse reception circuit 223. In this specification, "DC-insulated" means that the objects to be insulated are not connected by a conductor.

[0021] More specifically, the transformer 231 outputs a reception pulse signal S12 from the secondary coil 231s in response to a transmission pulse signal S11 input to the primary coil 231p, while the transformer 232 outputs a reception pulse signal S22 from the secondary coil 232s in response to a transmission pulse signal S21 input to the primary coil 232p.

[0022] In this way, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to the rise signal and fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0023] In addition, the signal transmission device 200 of this configuration example has an independent transformer chip 230 equipped with only transformers 231 and 232, in addition to the controller chip 210 and the driver chip 220, and these three chips are sealed in a single package.

[0024] With this configuration, the controller chip 210 and the driver chip 220 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), thereby enabling reduction in manufacturing costs.

[0025] The signal transmission device 200 can be suitably used, for example, in a power supply device or a motor drive device for on-board equipment mounted in a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs) / plug-in hybrid vehicles (PHVs), or xEVs such as fuel cell electric vehicles (FCEVs) / FCVs (fuel cell electric vehicles)).

[0026] <Trans chip (basic structure)> Next, the basic structure of transformer chip 230 will be described. Fig. 2 is a diagram showing the basic structure of transformer chip 230. In transformer chip 230 shown in this figure, transformer 231 includes primary coil 231p and secondary coil 231s that face each other in the vertical direction. Transformer 232 includes primary coil 232p and secondary coil 232s that face each other in the vertical direction.

[0027] The primary coils 231p and 232p are both formed on a first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed on a second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is disposed directly above the primary coil 231p and faces the primary coil 231p. The secondary coil 232s is disposed directly above the primary coil 232p and faces the primary coil 232p.

[0028] The primary coil 231p is laid spirally, starting from a first end connected to the internal terminal X21, so as to surround the periphery of the internal terminal X21 in a clockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. Meanwhile, the primary coil 232p is laid spirally, starting from a first end connected to the internal terminal X23, so as to surround the periphery of the internal terminal X23 in a counterclockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. The internal terminals X21, X22, and X23 are linearly arranged in the order shown in the figure.

[0029] The internal terminal X21 is connected to the external terminal T21 on the second layer 230b via a conductive wiring Y21 and a via Z21. The internal terminal X22 is connected to the external terminal T22 on the second layer 230b via a conductive wiring Y22 and a via Z22. The internal terminal X23 is connected to the external terminal T23 on the second layer 230b via a conductive wiring Y23 and a via Z23. The external terminals T21 to T23 are arranged linearly and are used for wire bonding with the controller chip 210.

[0030] The secondary coil 231s is laid in a spiral shape, starting from a first end connected to the external terminal T24 and surrounding the external terminal T24 in a counterclockwise direction, with a second end corresponding to the end point connected to the external terminal T25. Meanwhile, the secondary coil 232s is laid in a spiral shape, starting from a first end connected to the external terminal T26 and surrounding the external terminal T26 in a clockwise direction, with a second end corresponding to the end point connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure, and are used for wire bonding with the driver chip 220.

[0031] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, and are DC-insulated from the primary coils 231p and 232p, respectively. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-insulated from the controller chip 210 by the transformer chip 230.

[0032] <Transformer chip (2-channel type)> FIG. 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device 5 shown in FIG. 3. FIG. 5 is a plan view showing a layer in which a low-potential coil 22 (corresponding to the primary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 6 is a plan view showing a layer in which a high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is an enlarged view of region XIII shown in FIG. 7, showing an isolation structure 130.

[0033] 3 to 7, semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. Semiconductor chip 41 includes at least one of silicon, a wide bandgap semiconductor, and a compound semiconductor.

[0034] The wide bandgap semiconductor is a semiconductor with a bandgap greater than that of silicon (approximately 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or greater. The wide bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0035] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may also be an epitaxial substrate having a layered structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0036] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0037] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0038] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0039] The insulating side walls 53A to 53D include a first insulating side wall 53A, a second insulating side wall 53B, a third insulating side wall 53C, and a fourth insulating side wall 53D. The insulating side walls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip side walls 44A to 44D. Specifically, the insulating side walls 53A to 53D are formed flush with the chip side walls 44A to 44D. The insulating side walls 53A to 53D form ground surfaces that are flush with the chip side walls 44A to 44D.

[0040] The insulating layer 51 has a multilayer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and a plurality of (11 in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The top insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 also has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0041] Each of the multiple interlayer insulating layers 57 has a stacked structure including a first insulating layer 58 on the side of the bottom insulating layer 55 and a second insulating layer 59 on the side of the top insulating layer 56. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, approximately 0.3 μm).

[0042] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, approximately 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0043] The total thickness DT of the insulating layers 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of stacked interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0044] The semiconductor device 5 includes a first functional device 45 formed on an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (corresponding to the aforementioned transformers). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed inside the insulating layer 51 at intervals from the insulating side walls 53A to 53D. The multiple transformers 21 are formed at intervals in the first direction X.

[0045] Specifically, the multiple transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating side wall 53C side toward the insulating side wall 53D side in a plan view. The multiple transformers 21A to 21D each have a similar structure. The following description will be given using the structure of the first transformer 21A as an example. The description of the structure of the first transformer 21A applies mutatis mutandis to the structures of the second transformer 21B, third transformer 21C, and fourth transformer 21D, and will be omitted.

[0046] 5 to 7, the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed in an insulating layer 51. The high-potential coil 23 is formed in the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in a region sandwiched between a lowermost insulating layer 55 and an uppermost insulating layer 56 (i.e., a plurality of interlayer insulating layers 57).

[0047] The low-potential coil 22 is formed on the side of the lowest insulating layer 55 (semiconductor chip 41) within the insulating layer 51, and the high-potential coil 23 is formed on the side of the highest insulating layer 56 (insulating main surface 52) relative to the low-potential coil 22 within the insulating layer 51. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 sandwiched between them. The low-potential coil 22 and the high-potential coil 23 may be disposed in any desired locations. Furthermore, it is sufficient that the high-potential coil 23 faces the low-potential coil 22 with one or more interlayer insulating layers 57 sandwiched between them.

[0048] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57) is adjusted appropriately depending on the dielectric strength and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed on the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. In this embodiment, the high-potential coil 23 is formed on the first interlayer insulating layer 57 counting from the top insulating layer 56 side.

[0049] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 that is wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape that extends in an elliptical shape (oval shape) in a plan view. The portion that forms the innermost periphery of the first spiral portion 26 defines a first inner region 66 that is elliptical in a plan view.

[0050] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0051] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the shapes shown in Fig. 5 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0052] The low-potential coil 22 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a layered structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0053] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape that extends in an elliptical (oval) shape in a planar view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 that is elliptical in a planar view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0054] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. The number of turns of the second helical portion 29 preferably exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26 or may be equal to the number of turns of the first helical portion 26.

[0055] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0056] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0057] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in Fig. 6 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the second spiral portion 29.

[0058] The high-potential coil 23 is preferably formed from the same conductive material as the low-potential coil 22. That is, like the low-potential coil 22, the high-potential coil 23 preferably includes a barrier layer and a main body layer.

[0059] 4, the semiconductor device 5 includes a plurality of (12 in this figure) low potential terminals 11 and a plurality of (12 in this figure) high potential terminals 12. The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0060] The plurality of low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the plurality of low potential terminals 11 are formed in an area on the insulating sidewall 53B side at intervals in the second direction Y from the plurality of transformers 21A to 21D, and are arranged at intervals in the first direction X.

[0061] The plurality of low potential terminals 11 include a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E, and a sixth low potential terminal 11F. In this embodiment, two of each of the plurality of low potential terminals 11A to 11F are formed. The number of the plurality of low potential terminals 11A to 11F is arbitrary.

[0062] The first low potential terminal 11A faces the first transformer 21A in the second direction Y in plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in plan view.

[0063] The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

[0064] The fifth low potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). The sixth low potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low potential coil 22) and the first outer end 25 of the fourth transformer 21D (low potential coil 22).

[0065] The plurality of high potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the plurality of low potential terminals 11. Specifically, the plurality of high potential terminals 12 are formed in an area on the insulating sidewall 53A side at intervals from the plurality of low potential terminals 11 in the second direction Y, and are arranged at intervals in the first direction X.

[0066] The multiple high potential terminals 12 are each formed in an area close to the corresponding transformer 21A to 21D in a plan view. The high potential terminals 12 being close to the transformers 21A to 21D means that the distance between the high potential terminal 12 and the transformer 21 in a plan view is less than the distance between the low potential terminal 11 and the high potential terminal 12.

[0067] Specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D along the first direction X in a plan view. More specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0068] The plurality of high potential terminals 12 include a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E, and a sixth high potential terminal 12F. In this embodiment, two of each of the plurality of high potential terminals 12A to 12F are formed. The number of the plurality of high potential terminals 12A to 12F is arbitrary.

[0069] The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in a plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in a plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in a plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in a plan view. The fifth high potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0070] The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

[0071] The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).

[0072] 5 to 7, the semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34, each formed in an insulating layer 51. In this embodiment, a plurality of first low potential wirings 31, a plurality of second low potential wirings 32, a plurality of first high potential wirings 33, and a plurality of second high potential wirings 34 are formed.

[0073] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. The first low-potential wiring 31 and the second low-potential wiring 32 also fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all of the low-potential coils 22 of the transformers 21A to 21D to the same potential.

[0074] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. The first high-potential wiring 33 and the second high-potential wiring 34 also fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 21A to 21D to the same potential.

[0075] The plurality of first low potential wirings 31 are electrically connected to the corresponding low potential terminals 11A-11D and the first inner ends 24 of the corresponding transformers 21A-21D (low potential coils 22), respectively. The plurality of first low potential wirings 31 have the same structure. In the following, the structure of the first low potential wiring 31 connected to the first low potential terminal 11A and the first transformer 21A will be described as an example. The description of the structure of the first low potential wiring 31 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first low potential wirings 31, and will not be repeated here.

[0076] The first low-potential wiring 31 includes a through wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (multiple in this embodiment) pad plug electrodes 76, and one or more (multiple in this embodiment) substrate plug electrodes 77.

[0077] The through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0078] The through wiring 71 penetrates the multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this embodiment, the through wiring 71 is formed in the region of the insulating layer 51 between the lowermost insulating layer 55 and the uppermost insulating layer 56. The through wiring 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0079] In this embodiment, the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0080] The first electrode layer 78 forms the upper end of the through wiring 71. The second electrode layer 79 forms the lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0081] The plurality of wiring plug electrodes 80 are embedded in the plurality of interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be electrically connected to one another, and electrically connect the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 each have a planar area that is less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0082] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating the interlayer insulating layers 57.

[0083] The low-potential connecting wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) in the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connecting wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The low-potential connecting wiring 72 preferably has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connecting wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0084] The lead-out wiring 73 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead-out wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the lower end of the through wiring 71. The second end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the low-potential connecting wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0085] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 71 and the lead-out wiring 73, and is electrically connected to first ends of the through wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 72 and the lead-out wiring 73, and is electrically connected to second ends of the low potential connection wiring 72 and the lead-out wiring 73.

[0086] The plurality of pad plug electrodes 76 are formed in the uppermost insulating layer 56 in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71, and are electrically connected to the upper ends of the low potential terminal 11 and the through wiring 71, respectively. The plurality of substrate plug electrodes 77 are formed in the lowermost insulating layer 55 in a region between the semiconductor chip 41 and the drawing wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first ends of the drawing wiring 73, and are electrically connected to the semiconductor chip 41 and the first ends of the drawing wiring 73, respectively.

[0087] 6 and 7, the plurality of first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A-12D and the second inner ends 27 of the corresponding transformers 21A-21D (high-potential coils 23), respectively. The plurality of first high-potential wirings 33 each have a similar structure. In the following, the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A will be described as an example. The description of the structure of the first high-potential wiring 33 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first high-potential wirings 33, and will not be repeated here.

[0088] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (multiple in this embodiment) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrode 82 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the high-potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0089] The high-potential connecting wire 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connecting wire 81 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The high-potential connecting wire 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connecting wire 81 is formed spaced apart from the low-potential connecting wire 72 in a plan view and does not face the low-potential connecting wire 72 in the normal direction Z. This increases the insulation distance between the low-potential connecting wire 72 and the high-potential connecting wire 81, thereby increasing the dielectric strength voltage of the insulating layer 51.

[0090] The plurality of pad plug electrodes 82 are formed in the uppermost insulating layer 56 in a region between the high potential terminal 12 (first high potential terminal 12A) and the high potential connecting wiring 81, and are electrically connected to the high potential terminal 12 and the high potential connecting wiring 81. The plurality of pad plug electrodes 82 each have a plane area smaller than the plane area of ​​the high potential connecting wiring 81 in a plan view.

[0091] Referring to FIG. 7, it is preferable that the distance D1 between the low-potential terminal 11 and the high-potential terminal 12 exceeds the distance D2 between the low-potential coil 22 and the high-potential coil 23 (D2 < D1). It is preferable that the distance D1 exceeds the total thickness DT of the plurality of interlayer insulating layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the withstand voltage insulation to be achieved.

[0092] Referring to FIGS. 6 and 7, the semiconductor device 5 includes a dummy pattern 85 embedded in the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view.

[0093] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from the high-potential coil 23 and the low-potential coil 22 and is independent of the transformers 21A to 21D. That is, the dummy pattern 85 does not function as the transformers 21A to 21D. The dummy pattern 85 is formed as a shield conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D and suppresses the electric field concentration on the high-potential coil 23. In this form, the dummy pattern 85 is routed with a line density equal to the line density of the high-potential coil 23 per unit area. That the line density of the dummy pattern 85 is equal to the line density of the high-potential coil 23 means that the line density of the dummy pattern 85 falls within the range of ±20% of the line density of the high-potential coil 23.

[0094] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. Note that the dummy pattern 85 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low-potential coil 22.

[0095] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The shorter the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z, the more electric field concentration on the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be further appropriately suppressed. The dummy pattern 85 includes multiple dummy patterns with different electrical states. The dummy pattern 85 may include a high-potential dummy pattern.

[0096] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 22 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0097] Dummy patterns 85 include floating dummy patterns formed in an electrically floating state within insulating layer 51 so as to be positioned around transformers 21A to 21D.

[0098] In this embodiment, the floating dummy pattern is routed in a dense line shape so as to partially cover and partially expose the area around the high-potential coil 23 in a plan view. The floating dummy pattern may be formed to have ends or to have no ends.

[0099] The depth position of the floating dummy pattern inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed.

[0100] The number of floating lines is arbitrary and can be adjusted depending on the electric field to be relaxed. The floating dummy pattern may be made up of a plurality of floating lines.

[0101] 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region above the first main surface 42 of the semiconductor chip 41, and is covered with an insulating layer 51 (lowermost insulating layer 55). In FIG. 7, the second functional device 60 is simply shown by a dashed line drawn on the surface layer portion of the first main surface 42.

[0102] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring, and is electrically connected to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has a structure similar to that of the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. The high-potential wiring has a structure similar to that of the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. A detailed description of the low-potential wiring and high-potential wiring related to the second functional device 60 will be omitted.

[0103] The second functional device 60 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The second functional device 60 may include circuitry in which any two or more of the passive devices, the semiconductor rectifying device, and the semiconductor switching device are selectively combined. The circuitry may form part or all of an integrated circuit.

[0104] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifying device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0105] 5 to 7, the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape at a distance from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 prevents moisture and cracks from entering the device region 62 from the outer region 63.

[0106] The device region 62 is a region including the first functional device 45 (plurality of transformers 21), the second functional device 60, plural low potential terminals 11, plural high potential terminals 12, first low potential wiring 31, second low potential wiring 32, first high potential wiring 33, second high potential wiring 34, and dummy patterns 85. The outer region 63 is a region outside the device region 62.

[0107] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path leading to the device region 62.

[0108] The seal conductor 61 is formed in a strip shape along the insulating side walls 53 to 53D in plan view. In this embodiment, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. As a result, the seal conductor 61 defines a quadrangular (specifically, rectangular) device region 62 in plan view. The seal conductor 61 also defines a quadrangular (specifically, rectangular) outer region 63 surrounding the device region 62 in plan view.

[0109] Specifically, the seal conductor 61 has an upper end on the insulating principal surface 52 side, a lower end on the semiconductor chip 41 side, and a wall extending in a wall shape between the upper and lower ends. In this embodiment, the upper end of the seal conductor 61 is formed at a distance from the insulating principal surface 52 toward the semiconductor chip 41 and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed at a distance from the semiconductor chip 41 toward the upper end.

[0110] Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the plurality of low potential terminals 11 and the plurality of high potential terminals 12. Furthermore, the seal conductor 61 faces the first functional device 45 (plurality of transformers 21), the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85 in the insulating layer 51 in a direction parallel to the insulating principal surface 52. The seal conductor 61 may face a part of the second functional device 60 in the insulating layer 51 in a direction parallel to the insulating principal surface 52.

[0111] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (in this embodiment, a plurality) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end portion of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end portion of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed from the same conductive material as the low-potential coil 22. In other words, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0112] The multiple seal plug conductors 64 are embedded in the multiple interlayer insulating layers 57, respectively, and are each formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in plan view. The multiple seal plug conductors 64 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be connected to each other. The number of stacked multiple seal plug conductors 64 matches the number of stacked multiple interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0113] As long as a single annular seal conductor 61 is formed by an assembly of a plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end shape. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture and cracks penetrating into the device region 62, it is preferable that the plurality of seal plug conductors 64 be formed in an endless (annular) shape.

[0114] The plurality of seal via conductors 65 are respectively formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the lowermost insulating layer 55. The plurality of seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductor 64. The plurality of seal via conductors 65 have a planar area smaller than the planar area of ​​the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or larger than the planar area of ​​the seal plug conductor 64.

[0115] The width of the shield conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the shield conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the shield conductor 61 is defined as the width in a direction perpendicular to the direction in which the shield conductor 61 extends.

[0116] 7 and 8, the semiconductor device 5 further includes an isolation structure 130 that is interposed between the semiconductor chip 41 and the seal conductor 61 and electrically isolates the seal conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 is made of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0117] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0118] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41, and extends in a strip shape along the seal conductor 61 in plan view. In this embodiment, the isolation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. The isolation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion where the lower end portion (seal via conductor 65) of the seal conductor 61 bites in toward the semiconductor chip 41. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0119] The isolation structure 130 includes an inner end 130A on the device region 62 side, an outer end 130B on the outer region 63 side, and a main body 130C between the inner end 130A and the outer end 130B. The inner end 130A defines the region in which the second functional device 60 is formed (i.e., the device region 62) in plan view. The inner end 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0120] The outer end 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end 130B may be formed in the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0121] The main body 130C has a flat surface extending substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 can take various forms in addition to the field insulating film 131.

[0122] 7, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating principal surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may also be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating principal surface 52.

[0123] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. The first inorganic insulating layer 141 preferably contains USG (undoped silicate glass), which is silicon oxide without added impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength voltage on the high-potential coil 23 can be increased.

[0124] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable to form the first inorganic insulating layer 141 thicker than the second inorganic insulating layer 142.

[0125] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass), which are examples of silicon oxide. In this case, however, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the dielectric strength voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure made of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0126] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61, and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed in an area outside the seal conductor 61. The plurality of low potential pad openings 143 expose the plurality of low potential terminals 11, respectively. The plurality of high potential pad openings 144 expose the plurality of high potential terminals 12, respectively. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the low potential terminals 11. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the high potential terminals 12.

[0127] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0128] The thickness of the organic insulating layer 145 preferably exceeds the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably equal to or greater than 2 μm and equal to or less than 10 μm. Furthermore, the thickness of the organic insulating layer 145 is preferably equal to or greater than 5 μm and equal to or less than 50 μm. These structures can prevent the inorganic insulating layer 140 and the organic insulating layer 145 from becoming thicker, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 can appropriately increase the dielectric strength voltage on the high-potential coil 23.

[0129] The organic insulating layer 145 includes a first portion 146 covering the region on the low potential side and a second portion 147 covering the region on the high potential side. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 sandwiched therebetween. The first portion 146 has a plurality of low potential terminal openings 148 that expose a plurality of low potential terminals 11 (low potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have an overlap portion that rises onto the periphery (overlap portion) of the low potential pad opening 143.

[0130] The second portion 147 is formed at a distance from the first portion 146, and exposes the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose the plurality of high-potential terminals 12 (high-potential pad openings 144), respectively. The second portion 147 may have an overlapping portion that rises onto the periphery (overlapping portion) of the high-potential pad opening 144.

[0131] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the plurality of high-potential coils 23, the plurality of high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121.

[0132] The embodiments of the present invention can be implemented in other forms. In the above-described embodiment, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form in which only the second functional device 60 is provided without the first functional device 45 may be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0133] That is, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the high potential terminal 12 and the seal conductor 61. Furthermore, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the low potential terminal 11 and the seal conductor 61.

[0134] In the above embodiment, an example was described in which the second functional device 60 was formed. However, the second functional device 60 is not necessarily required, and may be removed.

[0135] In the above embodiment, an example was described in which the dummy pattern 85 was formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0136] In the above embodiment, an example has been described in which the first functional device 45 is a multi-channel type that includes multiple transformers 21. However, a first functional device 45 that is a single-channel type that includes a single transformer 21 may also be employed.

[0137] <Transformer arrangement> 9 is a plan view (top view) schematically showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the aforementioned semiconductor device 5). The transformer chip 300 in this figure has a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0138] In the transformer chip 300, pads a1 and b1 are connected to one end of a secondary coil L1s that forms a first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of a secondary coil L2s that forms a second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0139] Furthermore, pads a3 and b3 are connected to one end of a secondary coil L3s that forms the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of a secondary coil L4s that forms the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0140] Note that the primary coils forming the first transformer 301, the primary coils forming the second transformer 302, the primary coils forming the third transformer 303, and the primary coils forming the fourth transformer 304 are not shown in this figure. However, the primary coils basically have the same configuration as the secondary coils L1s to L4s, and are arranged directly below the secondary coils L1s to L4s, respectively, so as to face the secondary coils L1s to L4s.

[0141] That is, pads a5 and b5 are connected to one end of the primary coil forming first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Also, pads a6 and b6 are connected to one end of the primary coil forming second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0142] Pads a7 and b7 are connected to one end of the primary coil forming third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Pads a8 and b8 are connected to one end of the primary coil forming fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0143] However, the pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are led out from the inside of the transformer chip 300 to the surface through vias (not shown).

[0144] Of the multiple pads, pads a1 to a8 correspond to first current supply pads, pads b1 to b8 correspond to first voltage measurement pads, pads c1 to c4 correspond to second current supply pads, and pads d1 to d4 correspond to second voltage measurement pads.

[0145] Therefore, with the transformer chip 300 of this configuration example, the series resistance component of each coil can be accurately measured during the defective product inspection. Therefore, it is possible to not only reject defective products in which a break occurs in each coil, but also to appropriately reject defective products in which an abnormal resistance value occurs in each coil (for example, a short circuit between coils), thereby making it possible to prevent defective products from being released onto the market.

[0146] For the transformer chip 300 that has passed the above-mentioned defective product inspection, the above-mentioned plurality of pads may be used as a means for connecting the primary chip and the secondary chip (for example, the above-mentioned controller chip 210 and driver chip 220).

[0147] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 may be connected to the signal input or output terminals of the secondary chip, respectively, and pads c1 and d1, and pads c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0148] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 may be connected to the signal input or output terminals of the primary chip, respectively, and pads c3 and d3, and pads c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0149] Here, the first transformer 301 to the fourth transformer 304 are arranged in a manner that couples them in the respective signal transmission directions, as shown in Fig. 9. Referring to this figure, for example, the first transformer 301 and the second transformer 302 that transmit signals from the primary-side chip to the secondary-side chip are connected as a first pair by a first guard ring 305. Also, for example, the third transformer 303 and the fourth transformer 304 that transmit signals from the secondary-side chip to the primary-side chip are connected as a second pair by a second guard ring 306.

[0150] The reason for such coupling is to ensure a withstand voltage between the primary coil and the secondary coil when the primary coil and the secondary coil that respectively form the first transformer 301 to the fourth transformer 304 are stacked in the vertical direction of the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0151] The first guard ring 305 and the second guard ring 306 may be connected to a low impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0152] In the transformer chip 300, pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p. Pads c4 and d4 are shared between the corresponding primary coils. This configuration reduces the number of pads, making it possible to miniaturize the transformer chip 300.

[0153] 9, the primary coil and secondary coil forming each of the first transformer 301 to the fourth transformer 304 are preferably wound in a rectangular shape (or a track shape with rounded corners) in a plan view of the transformer chip 300. This configuration increases the area where the primary coil and secondary coil overlap, thereby improving the transmission efficiency of the transformer.

[0154] Of course, the transformer arrangement in this figure is merely an example, and the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to all semiconductor devices in which coils are integrated on a semiconductor chip.

[0155] <About Electronic Devices 400> The above-described signal transmission device 200 can be used in an electronic device 400. Below, the electronic device 400, and a signal transmission device 200X and a signal transmission device 200Y corresponding to the signal transmission device 200 will be described. First, the signal transmission device 200Y will be described as a comparative example of the signal transmission device 200X of the present disclosure. Next, the signal transmission device 200X of the present disclosure will be described.

[0156] 10 is a diagram showing the configuration of an electronic device 400 equipped with a signal transmission device 200Y. The electronic device 400 of this configuration example is a type of motor drive device (not shown) that converts DC power supplied from an in-vehicle battery (not shown) into AC power to drive a motor.

[0157] As shown in FIG. 10, the electronic device 400 of this configuration example includes an ECU [Electronic Control Unit] 600, a drive-side ASC [Active Short Circuit] controller 700y, a signal transmission device 200Y, and a plurality of discrete components (in accordance with FIG. 10, a drive target switch SW10, resistors R1 to R3, a switch SW5, a diode d5, and capacitors C3 and C4).

[0158] The ECU 600 is a means for comprehensively performing electrical control of the electronic device 400 and the vehicle A (see FIG. 14 described later) in which the electronic device 400 is mounted. The ECU 600 generates input signals IN1 and IN2 and inputs them to the signal transmission device 200Y (more specifically, external terminals T1 and T2 described later).

[0159] The drive-side ASC controller 700y generates an ASC signal S1y and inputs it to the signal transmission device 200Y (more specifically, to the external terminal T3 described later). The ASC signal S1y is a digital signal that takes on two values: high level or low level. When executing the active short circuit function described later, the drive-side ASC controller 700y sets the ASC signal S1y to high level. Normally (when the active short circuit function is not executed), the driver chip 400y sets the ASC signal S1y to low level.

[0160] The signal transmission device 200Y is a gate driver circuit that drives and controls the switch SW10 to be driven. The signal transmission device 200Y receives input signals IN1 and IN2 and generates a drive voltage Vge. The signal transmission device 200Y will be described in detail later.

[0161] The switch SW10 to be driven is an IGBT (Insulated Gate Bipolar Transistor). The gate of the switch SW10 to be driven receives an input of a drive voltage Vge. The collector of the switch SW10 to be driven is connected to a predetermined node n1. The emitter of the switch SW10 to be driven is connected to a predetermined node n2.

[0162] The node n1 is connected to, for example, a terminal to which a high-side power supply voltage is applied (not shown), and the node n2 is connected to a terminal to which a low-side power supply voltage (=reference voltage VEE2) is applied.

[0163] The switch SW10 to be driven is turned on / off in accordance with the drive voltage Vge. Specifically, when the drive voltage Vge exceeds the on-threshold voltage of the switch SW10 to be driven, the switch SW10 to be driven is turned on. While the switch SW10 to be driven is on, an emitter-collector current corresponding to the voltage value of the drive voltage Vge flows. On the other hand, when the drive voltage Vge falls below the on-threshold voltage of the switch SW10 to be driven, the switch SW10 to be driven is turned off. At this time, no emitter-collector current flows.

[0164] Next, the configuration of the signal transmission device 200Y will be described in detail. The signal transmission device 200Y is configured to transmit a gate drive signal from a primary circuit system (VCC1-VEE1) to a secondary circuit system (VCC2-VEE2) while insulating the primary circuit system from the secondary circuit system.

[0165] The signal transmission device 200Y has terminals (in accordance with the figure, external terminals T1 to T9, a primary power supply terminal Tv1, and a secondary power supply terminal Tv2) as means for communicating with the outside.

[0166] The external terminal T1 receives an input signal IN1 from the ECU 600. The external terminal T2 receives an input signal IN2 from the ECU 600. The external terminal T3 receives an input of an ASC signal S1y from the drive-side ASC controller 700y.

[0167] The external terminal T4 is connected to a first terminal of the resistor R1. The external terminal T5 is connected to a first terminal of the resistor R2. The second terminals of the resistors R1 and R2 are connected to the gate of the switch SW10 to be driven.

[0168] The external terminal T6 is connected to a terminal to which a reference voltage VEE1 is applied, and the external terminal T7 is connected to a terminal to which a reference voltage VEE2 is applied.

[0169] The external terminal T8 is connected to a first terminal of the switch SW5. A second terminal of the switch SW5 is connected to the gate of the switch SW10 to be driven. The switch SW5 is configured to be able to switch its first terminal and second terminal between an electrically connected state (ON) and an electrically disconnected state (OFF). The switch SW5 is basically OFF except during a soft turn-on operation, which will be described later.

[0170] The external terminal T9 is connected to a first terminal of a capacitor C3 and a first terminal of a resistor R3. A second terminal of the resistor R3 is connected to an anode of a diode d1. A cathode of the diode d1 is connected to a node n1. A second terminal of the capacitor C3 is connected to a node n2, a first terminal of a capacitor C4, and a terminal to which a secondary power supply voltage Vcc2 is applied. A second terminal of the capacitor C4 is connected to a terminal to which a reference voltage VEE2 is applied.

[0171] The primary power supply terminal Tv1 is connected to a terminal to which a primary power supply voltage Vcc1 is applied, and the secondary power supply terminal Tv2 is connected to a terminal to which a secondary power supply voltage Vcc2 is applied.

[0172] When the switch SW5 is off, a drive voltage Vge is generated at the connection node between the resistors R1 and R2. In other words, the signal transmission device 200Y controls the voltages generated at the external terminals T4 and T5, thereby changing the drive voltage Vge and controlling the drive target switch SW10.

[0173] The primary power supply terminal Tv1 is a power supply terminal for the primary circuit system (= the controller chip 350y described later). The primary circuit system is supplied with a power supply voltage VCC1 via the primary power supply terminal Tv1. The secondary power supply terminal Tv2 is a power supply terminal for the secondary circuit system (= the driver chip 400y described later). The secondary circuit system is supplied with a secondary power supply voltage Vcc2 via the secondary power supply terminal Tv2.

[0174] The secondary power supply voltage Vcc2 is higher than the primary power supply voltage Vcc1. The reference voltage VEE1 is a constant voltage lower than the primary power supply voltage Vcc1. The reference voltage VEE2 is a constant voltage lower than the secondary power supply voltage Vcc2.

[0175] The signal transmission device 200Y includes a controller chip 350y, a driver chip 400y, and a transformer chip 500. The signal transmission device 200Y is a semiconductor integrated circuit device in which the controller chip 350y, the driver chip 400y, and the transformer chip 500 are sealed in one package.

[0176] The controller chip 350y corresponds to the primary circuit system 200p mentioned above. The controller chip 350y is a controller chip on which controllers having the function of generating each signal are integrated. The controller chip 350y is driven by the supply of a power supply voltage VCC1. The controller chip 350y generates a PWM (Pulse Width Modulation) signal S2 and a data signal Sd based on the input signals IN1 and IN2. Details of the controller chip 350y are as follows.

[0177] The controller chip 350y includes an SPI (Serial Peripheral Interface) controller 301, a register 352, a nonvolatile memory 353, and a controller-side logic circuit 354.

[0178] The SPI controller 351 receives an input signal IN2 from the ECU 600 via the external terminal T2. SPI communication is performed between the ECU 600 and the SPI controller 351. For ease of explanation, the external terminal T2 is illustrated as a single terminal in each drawing. However, the external terminal T2 can be understood to include multiple terminals, such as a chip select signal terminal, a clock signal terminal, a MOSI (Master Out Slave In) signal terminal, and a MISO (Master-In Slave-Out) signal terminal. The input signal IN2 includes predetermined setting values ​​and the like required for various operations of the signal transmission device 200Y.

[0179] The SPI controller 351 inputs a control signal S3 to the register 352 based on the input signal IN2. The control signal S3 includes the setting values ​​and the like included in the input signal IN2. The register 352 receives the input of the input signal IN2 and stores the setting values ​​and the like in a volatile manner. At this time, the register 352 can also store the setting values ​​and the like in a nonvolatile manner in the nonvolatile memory 353.

[0180] The register 352 can access the nonvolatile memory 353 in response to the control signal S3 and read predetermined information (such as the above-mentioned set values) from the nonvolatile memory 353. The register 352 generates a control signal S4 that includes the information read from the nonvolatile memory 353 and the above-mentioned set values ​​stored therein. The register 352 then inputs the control signal S4 to the controller-side logic circuit 354.

[0181] The controller-side logic circuit 354 receives an input of an input signal IN1 via an external terminal T1 and also receives an input of a control signal S4 from the register 352.

[0182] The controller-side logic circuit 354 generates a PWM signal S2 based on the input signal IN1, and also generates a data signal Sd based on the control signal S4.

[0183] The PWM signal S2 is a pulse-width modulated signal for controlling the drive of the switch SW10. The rising and falling edges of the PWM signal S2 determine the on / off timing of the switch SW10. The duty ratio of the PWM signal S2 also determines the on period of the switch SW10.

[0184] The data signal Sd is a signal including information included in the control signal S4 (information read by the register 352 from the nonvolatile memory 353, the above-mentioned set values, etc.) The data signal Sd is transmitted between the controller-side logic circuit 354 and the driver-side logic circuit 401y in accordance with serial communication.

[0185] The PWM signal S2 and the data signal Sd are each input from the controller-side logic circuit 354 to the transformer chip 500 (more specifically, to a primary winding, which will be described later).

[0186] The transformer chip 500 has a plurality of primary windings and a plurality of secondary windings (not shown). The transformer chip 500 establishes transmission and reception of signals between the controller chip 350y and the driver chip 400y via each primary winding and each secondary winding while providing DC insulation between the controller chip 350y and the driver chip 400y.

[0187] The primary winding of the transformer chip 500 is connected to the controller chip 350y, and the secondary winding of the transformer chip 500 is connected to the driver chip 400y.

[0188] The PWM signal S2 and the data signal Sd input to the primary winding of the transformer chip 500 are transmitted to the secondary winding and input to the driver chip 400y.

[0189] The driver chip 400y corresponds to the secondary circuit system 200s described above. The driver chip 400y integrates a driver for controlling the drive of the switch SW10 to be driven.

[0190] The driver chip 400y is driven by receiving the secondary power supply voltage Vcc2. The driver chip 400y controls the drive voltage Vge based on the input PWM signal S2. Specifically, this is as follows.

[0191] The driver chip 400y includes a driver-side logic circuit 401y, a register 402, an output stage 415, a non-volatile memory 403, a soft turn-on circuit 420, and a DESAT protection circuit 430.

[0192] The driver-side logic circuit 401y receives the PWM signal S2 as an input, and generates a high-side signal GH and a low-side signal GL according to the PWM signal S2.

[0193] Furthermore, the driver-side logic circuit 401y receives the data signal Sd, generates a control signal S5, and inputs it to the register 402. The control signal S5 includes predetermined information (such as the information described above) included in the data signal Sd. The register 402 receives the control signal S5 and volatilely stores the information included in the control signal S5 therein. At this time, the register 402 also causes the nonvolatile memory 403 to nonvolatilely store the information included in the control signal S5.

[0194] The register 402 can also access the nonvolatile memory 403 in response to the control signal S5 and read out predetermined information stored in the nonvolatile memory 403. The register 402 can volatilely store the information read out from the nonvolatile memory 403. The register 402 generates a control signal S6 so as to include the information stored therein, and inputs the control signal S6 to the driver-side logic circuit 401y at any timing.

[0195] The output stage 415 receives the high-side signal GH and the low-side signal GL as input. The output stage 415 drives the drive target switch SW10 based on the high-side signal GH and the low-side signal GL. Specifically, this is as follows.

[0196] The output stage 415 includes a high-side switch SWH and a low-side switch SWL. The high-side switch SWH is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The gate of the high-side switch SWH receives a high-side signal GH from the driver-side logic circuit 401y. The source of the high-side switch SWH is connected to the secondary-side power supply terminal Tv2. The drain of the high-side switch SWH is connected to the external terminal T4.

[0197] The low-side switch SWL is an N-channel MOSFET. The gate of the low-side switch SWL receives a low-side signal GL from the driver-side logic circuit 401y. The source of the low-side switch SWL is connected to an external terminal T5. The drain of the low-side switch SWL is connected to an external terminal T7.

[0198] For example, when the switch SW10 to be driven is turned on (when the drive voltage Vge is set to high level), the driver-side logic circuit 401y turns on the high-side switch SWH and turns off the low-side switch SWL. That is, the high-side signal GH and the low-side signal GL are set to low level. As a result, the secondary-side power supply voltage Vcc2 is supplied to the external terminal T4, and the drive voltage Vge becomes high level. Then, the switch SW10 to be driven is turned on.

[0199] Furthermore, for example, when the switch SW10 to be driven is turned off (when the drive voltage Vge is set to low level), the driver-side logic circuit 401y turns off the high-side switch SWH and turns on the low-side switch SWL. That is, the high-side signal GH and the low-side signal GL are set to high level. As a result, the reference voltage VEE2 is supplied to the external terminal T5, and the drive voltage Vge is set to low level. Then, the switch SW10 to be driven is turned off.

[0200] For example, when the drive target switch SW10 is to be put into the gate open state, the driver-side logic circuit 401y turns off the high-side switch SWH and the low-side switch SWL. That is, the high-side signal GH is set to a high level and the low-side signal GL is set to a low level. The gate of the drive target switch SW10 is set into a floating state (=high impedance state). This puts the drive target switch SW10 into the gate open state.

[0201] Normally, the driver-side logic circuit 401y receives the PWM signal S2 and generates the high-side signal GH and the low-side signal GL. On the other hand, when the active short-circuit function is executed, the driver-side logic circuit 401y ignores the PWM signal S2 and generates the high-side signal GH and the low-side signal GL based on the control signal S6. The active short-circuit function will be described in detail later.

[0202] The soft turn-on circuit 420 generates a soft turn-on voltage Vs. The soft turn-on voltage Vs is generated so that its voltage value gradually increases at a predetermined slew rate. The soft turn-on circuit 420 applies the soft turn-on voltage Vs to the external terminal T8.

[0203] The driver-side logic circuit 401y can supply a soft turn-on voltage Vs to the gate of the switch SW10 to be driven by opening the gate of the switch SW10 to be driven and turning on the switch SW5. When the soft turn-on voltage Vs is supplied to the gate of the switch SW10 to be driven, the switch SW10 to be driven is soft-turned on. The soft turn-on of the switch SW10 to be driven will be described in detail later.

[0204] The DESAT protection circuit 430 is a circuit that monitors the SAT (saturation) voltage of the switch SW10 to be driven and protects the switch SW10 from overcurrent and overvoltage. The SAT voltage is the base-emitter voltage during the ON period of the switch SW10 to be driven. The DESAT protection circuit 430 passes a predetermined current between the collector and emitter of the switch SW10 to be driven during the ON period. At this time, a voltage is generated across the resistor R3. By detecting this voltage, the DESAT protection circuit 430 monitors the SAT voltage of the switch SW10 to be driven.

[0205] The DESAT protection circuit 430 inputs a monitoring signal Sdst corresponding to the monitoring state to the ECU 600. The ECU 600 controls the PWM signal S2 in accordance with the monitoring signal Sdst. When the collector-emitter voltage exceeds a predetermined voltage value, the driver-side logic circuit 401y turns off the drive target switch SW10 based on the PWM signal S2.

[0206] <About soft turn-on> Soft turn-on refers to turning on the switch SW10 to be driven while increasing the gate voltage of the switch SW10 at a predetermined slew rate. In the soft turn-on operation, it takes a longer time for the gate voltage of the switch SW10 to exceed the threshold voltage than in the normal turn-on operation. After the gate voltage of the switch SW10 to be driven exceeds the threshold voltage, the on-resistance of the switch SW10 to be driven gradually decreases as the soft turn-on voltage Vs increases.

[0207] Incidentally, a capacitor (not shown) may be connected to node n1 or node n2 to smooth the DC voltage. During protection operation, etc., it is necessary to gradually extract charge from this smoothing capacitor. At this time, the switch SW10 to be driven is soft-turned on. As described above, the soft-turn-on operation gradually reduces the on-resistance of the switch SW10 to be driven. This allows charge to be gradually extracted from the smoothing capacitor.

[0208] <About the active short circuit function> The electronic device 400 has an active short circuit function. The signal transmission device 200Y supports the active short circuit function. The active short circuit function is a function for forcibly controlling the gate potential of the drive target switch SW10 by the driver chip 400y, independently of the controller chip 350y (and thus the ECU 600).

[0209] When the driver chip 400y does not execute the active short circuit function (normal state), the following occurs: In this case, a low-level ASC signal S1y is input from the drive-side ASC controller 700y to the driver-side logic circuit 401y via the external terminal T3.

[0210] When the ASC signal S1y is at a low level, the driver-side logic circuit 401y generates the high-side signal GH and the low-side signal GL based on the PWM signal S2 as described above.

[0211] On the other hand, when the driver chip 400y executes the active short circuit function, the following occurs: In this case, a high-level ASC signal S1y is input from the drive-side ASC controller 700y to the driver-side logic circuit 401y via the external terminal T3.

[0212] When the ASC signal S1y is at a high level, the driver-side logic circuit 401y ignores the PWM signal S2 and performs an active short-circuit function. Specifically, this is as follows.

[0213] When the driver-side logic circuit 401y receives a high-level ASC signal S1y, it ignores the PWM signal S2 and sets the switch SW10 to any state. The any state means that the switch SW10 is in an on state, an off state, or a gate-open state. Specifically, the states are as follows.

[0214] When the driver-side logic circuit 401y receives the high-level ASC signal S1y, it sets the high-side signal GH and the low-side signal GL to any voltage value, regardless of the PWM signal S2. The target values ​​for the voltage values ​​of the high-side signal GH and the low-side signal GL at this time are stored in the nonvolatile memory 403. The nonvolatile memory 403 stores a plurality of values ​​corresponding to the above-mentioned any states as the target values.

[0215] Therefore, when the driver-side logic circuit 401y receives the input of the high-level ASC signal S1y, it reads the target value from the nonvolatile memory 403 via the register 402. Then, the driver-side logic circuit 401y sets the voltage values ​​of the high-side signal GH and the low-side signal GL to the target values.

[0216] As described above, in the soft turn-on operation, it takes a relatively long time for the drive voltage Vge to exceed the threshold voltage of the switch SW10 to be driven. This may cause the DESAT protection circuit 430 for the switch SW10 to malfunction. Specifically, this is as follows.

[0217] As described above, in the soft turn-on operation, it takes a relatively long time for the drive voltage Vge to exceed the threshold voltage of the switch SW10 to be driven. Then, the DESAT protection circuit 430 may start monitoring the SAT voltage of the switch SW10 to be driven even when the drive voltage Vge has not yet exceeded the threshold voltage of the switch SW10 to be driven (i.e., the switch SW10 to be driven is in the OFF state). Specifically, when the switch SW10 to be driven is in the OFF state, the DESAT protection circuit 430 attempts to inject current between the collector and emitter of the switch SW10 to be driven.

[0218] However, because there is no conduction between the collector and emitter of the switch SW10 to be driven, no current flows. This causes capacitor C3 to be unintentionally charged. This causes the voltage at external terminal T9 to rise regardless of the SAT voltage of the switch SW10 to be driven.

[0219] This may cause the DESAT protection circuit 430 to erroneously detect that an overvoltage is occurring between the collector and emitter of the switch SW10 to be driven. If this erroneous detection occurs, the switch SW10 to be driven will be forcibly turned off, even though it is actually desirable to soft-turn on the switch SW10 to be driven.

[0220] Here, the active short circuit function described above can ignore the PWM signal S2 and set the switch SW10 to any state. For example, the active short circuit function can set the gate of the switch SW10 to an open state. In this case, even if the DESAT protection circuit 430 makes an erroneous detection, the driver-side logic circuit 401y can ignore the PWM signal S2 and forcibly set the switch SW10 to an open state.

[0221] In this state, the driver-side logic circuit 401y turns on the switch SW5, thereby forcibly soft-turning on the drive target switch SW10 even if the DESAT protection circuit 430 makes an erroneous detection.

[0222] <Considerations on omitting non-volatile memory> However, in recent years, due to reasons such as reducing the circuit area and reducing manufacturing costs, there has been a demand to omit the nonvolatile memory on the controller side (corresponding to the nonvolatile memory 353 described above) and the nonvolatile memory on the driver side (corresponding to the nonvolatile memory 403 described above).

[0223] If the nonvolatile memory 353 and the nonvolatile memory 403 were omitted, when the signal transmission device 200Y was started, various setting information related to the active short circuit function (e.g., the target values ​​of the high-side signal GH and the low-side signal GL for setting the drive target switch SW10 to the above-mentioned desired state) would need to be temporarily stored in the register 402 from the ECU 600 via the input signal IN2, the control signal S3, the control signal S4, the data signal Sd, and the control signal S5.

[0224] Now, let us assume that some kind of communication trouble occurs on the path from the ECU 600 to the register 402. Then, when the signal transmission device 200Y is started, it becomes impossible to temporarily store information on the settings related to the active short circuit function in the register 402. Then, the above-described active short circuit function becomes ineffective.

[0225] Therefore, even if the drive target switch SW10 can be controlled by the PWM signal S2, if the DESAT protection circuit 430 detects an error, the drive target switch SW10 cannot be placed in the gate-open state. This prevents the drive target switch SW10 from being soft-turned on. As a result, the charge cannot be extracted from the smoothing capacitor.

[0226] To address this problem, the signal transmission device 200X of the present disclosure can reduce the circuit area while preventing the active short circuit function from becoming ineffective. The signal transmission device 200X according to an embodiment of the present disclosure will be described in detail below. The signal transmission device 200X according to an embodiment of the present disclosure includes components common to the signal transmission device 200Y described above. Therefore, the common components are denoted by the same reference numerals and will not be described again.

[0227] <Regarding the signal transmission device 200X according to the embodiment of the present disclosure> Fig. 11 is a diagram showing the configuration of a signal transmission device 200X of the present disclosure. As shown in Fig. 11, the signal transmission device 200X can be mounted on an electronic device 400, similar to the previously described signal transmission device 200Y. Note that the drive-side ASC controller 700x of this configuration example is partially different in configuration from the previously described drive-side ASC controller 700y. First, the drive-side ASC controller 700x will be described.

[0228] The drive-side ASC controller 700x inputs an ASC signal S1x to an external terminal T3. The ASC signal S1x is a signal that switches to either a high level (second logic level) or a low level (first logic level). When executing the active short circuit function, the drive-side ASC controller 700x sets the ASC signal S1x to a high level.

[0229] The drive-side ASC controller 700x can arbitrarily change the voltage value of the high-level ASC signal S1x to a predetermined set value set in multiple stages. Specifically, the drive-side ASC controller 700x changes the voltage value of the high-level ASC signal S1x according to the state of the target switch SW10 to be driven by the active short circuit function.

[0230] For example, when the active short circuit function is used to turn off the drive target switch SW10, the voltage value of the ASC signal S1x is set to a first set value, which is higher than a first threshold voltage Vth1 (described later) and lower than a second threshold voltage Vth2 (described later).

[0231] Furthermore, for example, when the gate of the drive target switch SW10 is opened by the active short circuit function, the drive-side ASC controller 700x sets the ASC signal S1x to a second set value, which is higher than the second threshold voltage Vth2 and lower than a third threshold voltage Vth3 (described later).

[0232] Furthermore, for example, when the drive target switch SW10 is turned on by the active short circuit function, the drive-side ASC controller 700x sets the ASC signal S1x to a third set value, which is higher than the third threshold voltage Vth3.

[0233] During normal operation (when the active short circuit function is not executed), the drive-side ASC controller 700x sets the voltage value of the ASC signal S1x to a fourth set value (=low level). This fourth set value is lower than the first threshold voltage Vth1. Details of the first threshold voltage Vth1 to the third threshold voltage Vth3 will be described later.

[0234] Next, the signal transmission device 200X will be described. The signal transmission device 200X is a gate driver circuit that drives and controls the drive target switch SW10. The signal transmission device 200X receives an input signal IN1 from the ECU 600 and generates a drive voltage Vge. The signal transmission device 200X corresponds to the signal transmission device 200 described above.

[0235] The signal transmission device 200X is configured to transmit a gate drive signal from a primary circuit system (VCC1-VEE1) to a secondary circuit system (VCC2-VEE2) while insulating the primary circuit system from the secondary circuit system.

[0236] The signal transmission device 200X has terminals as means for communicating with the outside (in accordance with this figure, external terminals T1 to T9 equivalent to those previously mentioned, a primary power supply terminal Tv1, and a secondary power supply terminal Tv2).

[0237] The signal transmission device 200X controls the voltages generated at the external terminals T4 and T5 to change the drive voltage Vge and drive the drive target switch SW10. The internal configuration of the signal transmission device 200X will now be described.

[0238] The signal transmission device 200X includes a transformer chip 500 similar to that described above. In addition, the signal transmission device 200X includes a controller chip 350x and a driver chip 400x. The signal transmission device 200X is configured by sealing the controller chip 350x, the driver chip 400x, and the transformer chip 500 in a single package.

[0239] The controller chip 350x corresponds to the primary circuit system 200p described above, and includes an SPI controller 351, a register 352, and a controller-side logic circuit 354, which are the same as those described above.

[0240] The transformer chip 500 is configured to establish transmission and reception of signals between the controller chip 350x and the driver chip 400x while providing DC insulation between the controller chip 350x and the driver chip 400x.

[0241] The primary winding of the transformer chip 500 is connected to the controller chip 350x. The secondary winding of the transformer chip 500 is connected to the driver chip 400x. The PWM signal S2 input to the primary winding of the transformer chip 500 is transmitted to the secondary winding and input to the driver chip 400x.

[0242] The driver chip 400x corresponds to the secondary circuit system 200s described above. The driver chip 400x integrates a driver for controlling the drive of the switch SW10 to be driven.

[0243] The driver chip 400x is driven by receiving a secondary power supply voltage Vcc2 via a secondary power supply terminal Tv2. The driver chip 400x controls the drive voltage Vge based on the input PWM signal S2. Specifically, this is as follows.

[0244] Driver chip 400x includes the same output stage 415, resistor 402, soft turn-on circuit 420, and DESAT protection circuit 430 as described above. Additionally, driver chip 400x includes driver side logic circuit 401x.

[0245] The driver-side logic circuit 401x receives the PWM signal S2 as an input, and generates a high-side signal GH and a low-side signal GL according to the PWM signal S2.

[0246] Furthermore, the driver-side logic circuit 401x receives the data signal Sd, generates a control signal S5, and inputs it to the register 402. The control signal S5 includes predetermined information (such as the above information) included in the data signal Sd. The register 402 receives the control signal S5 and volatilely stores the information included in the control signal S5 therein.

[0247] The register 402 can also generate the control signal S6 so that it includes the information stored therein in response to the control signal S5. In this case, the register 402 inputs the control signal S6 to the driver-side logic circuit 401x at any timing.

[0248] The gate of the high-side switch SWH receives an input of a high-side signal GH from the driver-side logic circuit 401x, and the gate of the low-side switch SWL receives an input of a low-side signal GL from the driver-side logic circuit 401x.

[0249] For example, when the switch SW10 to be driven is turned on (when the drive voltage Vge is set to high level), the driver-side logic circuit 401x turns on the high-side switch SWH and turns off the low-side switch SWL. That is, the driver-side logic circuit 401x sets the high-side signal GH and the low-side signal GL to low level. As a result, the secondary-side power supply voltage Vcc2 is supplied to the external terminal T4, and the drive voltage Vge becomes high level. Then, the switch SW10 to be driven is turned on.

[0250] Furthermore, for example, when the switch SW10 to be driven is turned off (when the drive voltage Vge is set to low level), the driver-side logic circuit 401x turns off the high-side switch SWH and turns on the low-side switch SWL. That is, the driver-side logic circuit 401x sets the high-side signal GH and the low-side signal GL to high level. As a result, the reference voltage VEE2 is supplied to the external terminal T5, and the drive voltage Vge is set to low level. Then, the switch SW10 to be driven is turned off.

[0251] For example, when the drive target switch SW10 is to be put into the gate open state, the driver-side logic circuit 401x turns off the high-side switch SWH and the low-side switch SWL. That is, the high-side signal GH is set to high level and the low-side signal GL is set to low level. This puts the gate of the drive target switch SW10 into a floating state (=high impedance state). This puts the gate of the drive target switch SW10 into the gate open state.

[0252] Normally, the driver-side logic circuit 401x receives the PWM signal S2 and generates the high-side signal GH and the low-side signal GL. On the other hand, when the active short circuit function is executed, the driver-side logic circuit 401x ignores the PWM signal S2 and generates the high-side signal GH and the low-side signal GL based on the ASC signal S1x. The configuration related to the active short circuit function of the present disclosure will be described in detail below.

[0253] <Configuration of the active short circuit function> The signal transmission device 200X supports an active short circuit function. Specifically, the driver-side logic circuit 401x receives an input of an ASC signal S1x from the drive-side ASC controller 700x via an external terminal T3.

[0254] When the ASC signal S1x is at a low level (=when the voltage value of the ASC signal S1x is the fourth set value), the driver-side logic circuit 401x generates the high-side signal GH and the low-side signal GL based on the PWM signal S2 as described above.

[0255] On the other hand, when the ASC signal S1x is at a high level, the driver-side logic circuit 401x ignores the PWM signal S2 and generates the high-side signal GH and the low-side signal GL based on the ASC signal S1x.

[0256] The configuration of the driver-side logic circuit 401x regarding the active short circuit function will be described in detail. Fig. 12 is a diagram showing the configuration of the driver-side logic circuit 401x. As shown in Fig. 12, the driver-side logic circuit 401x includes an ASC signal determination circuit 404 and a drive control circuit 405.

[0257] Here, as described above, the drive-side ASC controller 700x sets the voltage value of the ASC signal S1x to one of the first to fourth set values. The ASC signal determination circuit 404 determines whether the voltage value of the ASC signal S1x exceeds each of a plurality of threshold voltages (first threshold voltage Vth1 to third threshold voltage Vth3). This determines which of the first to fourth set values ​​the voltage value of the ASC signal S1x is.

[0258] The ASC signal determination circuit 404 generates a determination result signal S7 according to the determination result and inputs it to the drive control circuit 405. The drive control circuit 405 performs the active short circuit function or operates normally without performing the function according to the determination result signal S7. Specifically, this is as follows.

[0259] If the active short circuit function is to be executed, the drive control circuit 405 ignores the PWM signal S2 and generates the high-side signal GH and the low-side signal GL based on the determination result signal S7. On the other hand, if the active short circuit function is not to be executed (=normal operating state), the drive control circuit 405 generates the high-side signal GH and the low-side signal GL based on the PWM signal S2.

[0260] A more detailed description will be given of the configuration of the ASC signal determination circuit 404. The ASC signal determination circuit 404 includes logic circuits 406-408, an OR gate 409, and NOR gates 410-412.

[0261] Each of the logic circuits 406 to 408 is a logic circuit that changes its output voltage depending on whether or not the input voltage exceeds a predetermined threshold voltage. For example, each of the logic circuits 406 to 408 can be a Schmitt trigger. Each of the input terminals of the logic circuits 406 to 408 is connected to an external terminal T3. Each of the output terminals of the logic circuits 406 to 408 is connected to an input terminal of an OR gate 409 and an input terminal of NOR gates 410 to 412, respectively.

[0262] The logic circuit 406 receives the ASC signal S1x and determines whether the ASC signal S1x exceeds the first threshold voltage Vth1. The logic circuit 406 generates an output signal S8 according to the determination result. Specifically, if the ASC signal S1x exceeds the first threshold voltage Vth1, the logic circuit 406 sets the output signal S8 to a high level. Conversely, if the ASC signal S1x is below the first threshold voltage Vth1, the logic circuit 406 sets the output signal S8 to a low level.

[0263] The logic circuit 407 receives the ASC signal S1x and determines whether the ASC signal S1x exceeds the second threshold voltage Vth2. The logic circuit 407 generates an output signal S9 according to the determination result. Specifically, if the ASC signal S1x exceeds the second threshold voltage Vth2, the logic circuit 407 sets the output signal S9 to a high level. Conversely, if the ASC signal S1x is below the second threshold voltage Vth2, the logic circuit 407 sets the output signal S9 to a low level.

[0264] The logic circuit 408 receives the ASC signal S1x and determines whether the ASC signal S1x exceeds the third threshold voltage Vth3. The logic circuit 408 generates an output signal S10 according to the determination result. Specifically, if the ASC signal S1x exceeds the third threshold voltage Vth3, the logic circuit 408 sets the output signal S10 to a high level. Conversely, if the ASC signal S1x is below the third threshold voltage Vth3, the logic circuit 408 sets the output signal S10 to a low level.

[0265] 12, OR gate 409 receives output signals S8 to S10 as inputs and generates decision result signal S7a. NOR gate 410 receives an inverted input of output signal S8 and inputs of output signals S9 and S10 and generates decision result signal S7b. NOR gate 411 receives an inverted input of output signals S8 and S9 and input of S10 and generates decision result signal S7c. Decision result signal S7d receives an inverted input of output signals S8 to S10 and generates decision result signal S7d. It should be understood that decision result signals S7a to S7d are included in the above-mentioned decision result signal S7.

[0266] 13 is a table showing the correlation between the logic levels of the output signals S8 to S10, the determination result signals S7a to S7d, the high-side signal GH, the low-side signal GL, the terminal voltage VH, and the terminal voltage VL and the state of the drive target switch SW10. In FIG. 13, a high level is defined as "H," a low level as "L," and a high-impedance state as "Hi-Z."

[0267] 13, the OR gate 409 sets the determination result signal S7a to a high level when at least one of the output signals S8 to S10 is at a high level. Conversely, the OR gate 409 sets the determination result signal S7a to a low level when all of the output signals S8 to S10 are at a low level.

[0268] Each of the NOR gates 410 to 412 sets its output signal (one of the determination result signals S7a to S7d) to a high level only when all three input voltages input to it are at a low level, and sets its output signal to a low level otherwise.

[0269] The NOR gate 410 sets the determination result signal S7b to a high level only when the inverted input value of the output signal S8 is at a low level (= the output signal S8 is at a high level) and the output signals S9 and S10 are at a low level. Otherwise, the NOR gate 410 sets the determination result signal S7b to a low level.

[0270] The NOR gate 411 sets the determination result signal S7c to a high level only when the inverted input values ​​of the output signals S8 and S9 are low level (=output signals S8 and S9 are high level) and S10 is low level. Otherwise, the NOR gate 411 sets the determination result signal S7c to a low level.

[0271] The NOR gate 412 sets the determination result signal S7d to a high level only when all of the inverted input values ​​of the output signals S8 to S10 are at a low level (=all of the output signals S8 to S10 are at a high level).In all other cases, the NOR gate 412 sets the determination result signal S7d to a low level.

[0272] The drive control circuit 405 receives the determination result signals S7a to S7d and the PWM signal S2, and generates the high-side signal GH and the low-side signal GL. More specifically, this is as follows.

[0273] The determination result signal S7a can be considered as a flag for interrupt processing. That is, when the determination result signal S7a rises to high level, the control of the execution of the active short circuit function interrupts the drive control of the drive target switch SW10 by the PWM signal S2.

[0274] When the determination result signal S7a is at a low level, the drive control circuit 405 generates the high-side signal GH and the low-side signal GL based on the PWM signal S2 as usual. At this time, the drive target switch SW10 is driven in response to the PWM signal S2.

[0275] On the other hand, when the determination result signal S7a is at a high level, the drive control circuit 405 ignores the PWM signal S2 and generates the high-side signal GH and the low-side signal GL according to the determination result signals S7b to S7d. At this time, the drive target switch SW10 is driven and controlled according to the voltage value of the ASC signal S1x.

[0276] The drive control of the drive target switch SW10 using the ASC signal S1x will now be described in detail. As shown in Figure 13, when the determination result signals S7a and S7b are at a high level and the determination result signals S7c and S7d are at a low level, the high-side signal GH goes to a low level and the low-side signal GL goes to a high level. This turns the high-side switch SWH off and the low-side switch SWL on. This causes the terminal voltage VH to enter a high-impedance state and the terminal voltage VL to go to a low level. At this time, the drive voltage Vge goes to a low level, and the drive target switch SW10 goes off.

[0277] When the determination result signals S7a and S7c are at a high level and the determination result signals S7b and S7d are at a low level, the high-side signal GH and the low-side signal GL go to a low level. This turns off the high-side switch SWH and the low-side switch SWL. This causes the terminal voltages VH and VL to go to a high-impedance state. At this time, the gate of the drive target switch SW10 goes to an open state ("OPEN" in FIG. 13).

[0278] When the determination result signals S7a and S7d are high and the determination result signals S7b and S7c are low, the high-side signal GH goes high and the low-side signal GL goes low. This turns on the high-side switch SWH and turns off the low-side switch SWL. This causes the terminal voltage VH to go high and the terminal voltage VL to enter a high-impedance state. At this time, the drive voltage Vge goes high and the drive target switch SW10 turns on.

[0279] As described above, according to the signal transmission device 200X of the present disclosure, even if the nonvolatile memory (corresponding to the nonvolatile memory 403) is omitted from the driver chip 400x, the active short circuit function can be executed by processing on the driver chip 400x side. Therefore, when the signal transmission device 200X is started, it is not necessary for the ECU 600 to transmit information required for the active short circuit function to the register 402. As a result, even if some kind of communication failure occurs along the signal path from the ECU 600 to the register 402, the active short circuit function can be executed effectively.

[0280] Furthermore, nonvolatile memories (corresponding to the nonvolatile memories 353 and 403) can be omitted from the controller chip 350x and the driver chip 400x, thereby reducing the circuit area of ​​the signal transmitter 200X.

[0281] Furthermore, by forcibly placing the gate of the switch SW10 to be driven in an open state using the active short circuit function and then turning on the switch SW5, the switch SW10 to be driven can be softly turned on. As a result, even if some kind of communication failure occurs as described above, charge can be extracted from the smoothing capacitor (not shown) connected to the node n1.

[0282] Furthermore, even if a false detection occurs by the DESAT protection circuit 430 as described above, the driver chip 400x (more specifically, the drive control circuit 405) can ignore the PWM signal S2 and forcibly place the drive target switch SW10 in the gate open state on the driver chip 400x side.

[0283] Furthermore, as described above, when the signal transmission device 200X is started up, it is not necessary for the ECU 600 to transmit information required for the active short circuit function to the register 402. Therefore, the signal processing and various controls when the signal transmission device 200X is started up can be made relatively simple.

[0284] Furthermore, as described above, the logic circuits 406 to 408 can be Schmitt buffers. This allows the logic circuits 406 to 408 to output the output signals S8 to S10 with hysteresis relative to the input. Even if noise occurs in the ASC signal S1x or if the ASC signal S1x momentarily rises due to some kind of malfunction, the logic circuits 406 to 408 can be prevented from erroneously determining the ASC signal S1x. This allows the active short circuit function to be performed with greater accuracy.

[0285] Fig. 14 is a diagram showing the configuration of a vehicle A equipped with an electronic device 400. As shown in Fig. 14, the electronic device 400 of the present disclosure can be suitably used as a power supply device or a motor drive device for on-board equipment installed in the vehicle A. The vehicle A includes not only engine vehicles but also electric vehicles (FCEV / FCV).

[0286] <Modification> The present disclosure is not limited to the above-described embodiments and various modifications are possible without departing from the spirit and scope of the present disclosure. For example, although the switch SW10 to be driven is described as an IGBT, this is not limited to this. For example, the switch SW10 to be driven can be an N-channel or P-channel MOSFET. In this case, the meanings described in this specification, FIGS. 1 to 14, and the claims can be interpreted with the emitter and collector of the switch SW10 to be driven as the source and drain, respectively. In this case, the SAT voltage is the gate-source voltage during the on-period of the switch SW10 to be driven.

[0287] Alternatively, for example, the soft turn-on circuit 420 may be configured to gradually reduce the soft turn-on voltage Vs to a soft turn-off voltage Vs at a predetermined slew rate. In this case, the soft turn-off voltage Vs can be supplied to the gate of the switch SW10 to be driven, thereby softly turning off the switch SW10 to be driven.

[0288] Also, for example, an output terminal of a predetermined signal can be connected to the gate of the switch SW10 to be driven, which allows the switch SW10 to be forcibly put into an open state by the active short circuit function, and then the switch SW10 to be driven can be controlled by the predetermined signal.

[0289] <Additional Notes> The signal transmission device (200X) disclosed in the specification includes a transmission circuit (350x) configured to output a pulse-driven control signal (S2) in response to input signals (IN1, IN2), a reception circuit (400x) configured to drive a switch (SW10) to be driven in response to the control signal (S2), and an isolation circuit (500) configured to transmit the control signal (S2) while isolating the transmission circuit (350x) from the reception circuit (400x). 00x) receives an input of an external signal (S1x) separate from the input signals (IN1, IN2), and the receiving circuit (400x) drives the switch to be driven (SW10) based on the control signal (S2) when the external signal (S1x) is at a first logic level that is equal to or lower than a first threshold voltage (Vth1), and drives and controls the switch to be driven (SW10) based on the external signal (S1x) regardless of the control signal (S2) when the external signal (S1x) is at a second logic level that is higher than the first threshold (first configuration).

[0290] In the signal transmission device (200X) of the first configuration, the receiving circuit (400x) sets the state of the drive target switch (SW10) to either on, off, or gate open state when the external signal (S1x) is at a second logic level (second configuration).

[0291] In the signal transmission device (200X) according to the first or second configuration, the receiving circuit (400x) includes an output stage (415) configured to drive the switch to be driven (SW10), and a logic circuit (401x) configured to control the output stage (415) so that, when the external signal (S1x) is at a first logic level, the output stage (415) drives the switch to be driven (SW10) based on the input signals (IN1, IN2), and to control the output stage (415) so that, when the external signal (S1x) is at a second logic level, the output stage (415) drives the switch to be driven (SW10) based on the external signal (S1x) regardless of the input signals (IN1, IN2) (third configuration).

[0292] In a signal transmission device (200X) according to a third configuration, the output stage (415) includes a high-side switch (SWH) that, in an on state, supplies a first voltage exceeding an on-threshold voltage of the switch (SW10) to a control end of the switch (SW10) to be driven, and a low-side switch (SWL) that, in an on state, supplies a second voltage less than the on-threshold voltage to the control end, and the logic circuit (401x) includes an external signal determination circuit (404) configured to be able to determine the logic level of an external signal (S1x), and a drive control circuit (405) configured to control driving of the high-side switch (SWH) and the low-side switch (SWL) based on the determination result of the external signal determination circuit (404) and the input signals (IN1, IN2), and the drive control circuit (405) controls the drive of the high-side switch (SWH) and the low-side switch (SWL) based on the determination result of the external signal determination circuit (404) and the input signals (IN1, IN2). When the external signal (S1x) is at a first logic level, the drive is controlled to turn on the high-side switch (SWH) and turn off the low-side switch (SWL), or to turn off the high-side switch (SWH) and turn on the low-side switch (SWL), based on the input signals (IN1, IN2); when the external signal (S1x) is at a second logic level, the drive is controlled to turn on the high-side switch (SWH) and turn off the low-side switch (SWL), or to turn off the high-side switch (SWH) and turn on the low-side switch (SWL), or to turn off the high-side switch (SWH) and turn off the low-side switch (SWL) based on the external signal (S1x) regardless of the input signals (IN1, IN2) (fourth configuration).

[0293] In the signal transmission device (200X) of the fourth configuration, the external signal determination circuit (404) is capable of determining whether or not the voltage value of the external signal (S1x) exceeds each of a plurality of threshold voltages (Vth1 to Vth3) including a first threshold voltage (Vth1) (fifth configuration).

[0294] In a signal transmission device (200X) according to a fifth configuration, the threshold voltages (Vth1 to Vth3) include a first threshold voltage (Vth1), a second threshold voltage (Vth2) higher than the first threshold voltage (Vth1), and a third threshold voltage (Vth3) higher than the second threshold voltage (Vth2), and the drive control circuit (405) drives the high-side The switch (SWH) and the low-side switch (SWL) are driven and controlled, and when the external signal determination circuit (404) determines that the voltage value of the external signal (S1x) is higher than the first threshold voltage (Vth1) and lower than the second threshold voltage (Vth2), the high-side switch (SWH) and the low-side switch (SWL) are driven and controlled so that the switch (SW10) to be driven is in a first state, which is either an on state, an off state, or a gate open state, regardless of the input signals (IN1, IN2). ), and when the external signal determination circuit (404) determines that the voltage value of the external signal (S1x) is higher than the second threshold voltage (Vth2) and lower than the third threshold voltage (Vth3), the high-side switch (SWH) and the low-side switch (SWL) are driven and controlled so that the switch to be driven (SW10) is in a second state other than the first state, among the on state, the off state, and the gate open state, regardless of the input signals (IN1, IN2); and when the external signal determination circuit (404) determines that the voltage value of the external signal (S1x) is higher than the second threshold voltage (Vth2) and lower than the third threshold voltage (Vth3), the high-side switch (SWH) and the low-side switch (SWL) are driven and controlled so that the switch to be driven (SW10) is in a third state other than the first state and the second state, among the on state, the off state, and the gate open state, regardless of the input signals (IN1, IN2) (sixth configuration).

[0295] The electronic device (400) disclosed in the specification includes a signal transmission device (200X) according to any one of the first to sixth configurations, a control circuit (600) configured to generate input signals (IN1, IN2), an external signal generating circuit (700x) configured to generate an external signal (S1x), and a drive target switch (SW10) (seventh configuration).

[0296] An electronic device (400) according to a seventh configuration includes a protection circuit (430) configured to monitor the SAT voltage of the switch (SW10) to be driven, and an external signal generating circuit (700x) sets the external signal (S1x) to a first logic level or a second logic level according to the monitoring result of the protection circuit (430) (eighth configuration).

[0297] The vehicle (A) disclosed in the specification includes the electronic device (400) according to the seventh or eighth configuration (ninth configuration). [Explanation of symbols]

[0298] 5. Semiconductor Devices 11, 11A~11F Low potential terminal 12, 12A~12F high potential terminal 21, 21A~21D Transformer 22 Low potential coil (primary coil) 23 High potential coil (secondary coil) 24 1st medial end 25 First outer end 26 1st spiral part 27 Second medial end 28 Second outer end 29 Second spiral part 31 1st low potential wiring 32 2nd low potential wiring 33 1st high potential wiring 34 2nd high potential wiring 41 Semiconductor chips 42 First main surface 43 Second main surface 44A~44D Chip sidewall 45 First Functional Device 51 Insulating layer 52 Main insulating surface 53A~53D Insulated sidewall 55 Bottom insulating layer 56 Top insulating layer 57 Interlayer insulation layer 58 First insulating layer 59 Second insulating layer 60 Second Function Device 61 Sealed conductor 62 Device Area 63 Outer area 64 Seal plug conductor 65 Seal via conductor 66 1st medial area 67 Second medial area 71 Through-wiring 72 Low-potential connection wiring 73 Lead Wiring 74 First connecting plug electrode 75 Second connecting plug electrode 76 Pad plug electrode 77 PCB plug electrode 78 1st electrode layer 79 Second electrode layer 80 Wiring plug electrode 81 High-potential connection wiring 82 Pad plug electrode 85 Dummy Pattern 86 High-potential dummy pattern 87 First high potential dummy pattern 88 Second high potential dummy pattern 89 First area 90 Second area 91 Third area 92 First connection part 93 First Pattern 94 Second Pattern 95 Third Pattern 96 First Outer Line 97 Second Outer Line 98 First Intermediate Line 99 First connecting line 100 slits 130 Separation structure 140 Inorganic insulating layer 141 First inorganic insulating layer 142 Second inorganic insulating layer 143 Low potential pad opening 144 High potential pad opening 145 Organic insulating layer 146 Part 1 147 Part 2 148 Low potential terminal opening 149 High potential terminal opening 200 Signal Transmission Device 200p primary circuit system 200s Secondary circuit system 210 Controller Chip (1st Chip) 211 Pulse transmitting circuit (pulse generator) 212, 213 buffer 220 Driver Chip (Second Chip) 221, 222 buffer 223 Pulse receiving circuit (RS flip-flop) 224 Driver 230 Transformer Chip (3rd Chip) 230a 1st wiring layer (lower layer) 230b 2nd wiring layer (upper layer) 231, 232 transformer 231p, 232p Primary coil 231s, 232s Secondary coil 300 Trans Chip 301 1st transformer 302 2nd transformer 303 Third Transformer 304 4th Transformer 305 1st Guard Ring 306 Second Guard Ring a1 to a8 pads (corresponding to the first current supply pads) b1~b8 pads (corresponding to the first voltage measurement pads) c1 to c4 pads (corresponding to the second current supply pads) d1~d4 pads (corresponding to the second voltage measurement pads) e1, e2 pads L1p, L2p Primary coil L1s, L2s, L3s, L4s Secondary coil T21, T22, T23, T24, T25, T26 external terminals X 1st direction X21, X22, X23 internal terminals Y Second direction Y21, Y22, Y23 wiring Z normal direction Z21, Z22, Z23 vias 200X Signal Transmitter 200Y signal transmission device 350x controller chip (transmitting circuit) 350y controller chip 351 SPI controller 352 registers 353 Non-volatile Memory 354 Controller side logic circuit 400 Electronic equipment 400x driver chip (receiving circuit) 400y driver tip 401x Driver side logic circuit (logic circuit) 401y Driver side logic circuit 402 Register 403 Non-volatile memory 404 ASC signal judgment circuit (external signal judgment circuit) 406~408 Logic Circuits 409 OR Gate 410~412 NOR gate 415 output stage 420 Soft Turn-On Circuit 430 DESAT protection circuit (protection circuit) 500 Transformer chip (isolated circuit) 600 ECU (control circuit 700x Drive-side ASC Controller (External Signal Generation Circuit) 700y drive side ASC controller Vehicle A Cd capacitor GH High-side signal GL low side signal IN1, IN2 input signals R1~R3 ​​resistance S1x ASC signal (external signal) S1y ASC signal S2 PWM signal (control signal) S3~S6 control signals S7 Judgment result signal S7a~S7d Judgment result signal S8~S10 output signal SW10 Drive target switch SW5 switch SWH High-side switch SWL Low-side switch Sd data signal Sdst monitoring signal T1~T9 external terminals Tv1 Primary side power supply terminal Tv2 Secondary power supply terminal VCC1 power supply voltage VCC2 power supply voltage VEE1 reference voltage VEE2 reference voltage VH terminal voltage VL terminal voltage Vcc1 Primary power supply voltage Vcc2 Secondary power supply voltage Vge driving voltage Vs Soft turn-on voltage Vth1 First threshold voltage Vth2 Second threshold voltage Vth3 Third threshold voltage n1 node n2 node

Claims

1. a transmission circuit configured to output a pulse-driven control signal in response to an input signal; a receiving circuit configured to drive the switch to be driven in response to the control signal; an isolation circuit configured to transmit the control signal while isolating the transmitting circuit from the receiving circuit; Equipped with the receiving circuit receives an input of an external signal separate from the input signal; The receiving circuit driving the switch to be driven based on the control signal when the external signal is at a first logic level equal to or lower than a first threshold voltage; The signal transmission device drives and controls the switch to be driven based on the external signal, regardless of the control signal, when the external signal is at a second logic level higher than the first threshold.

2. 2. The signal transmission device according to claim 1, wherein the receiving circuit sets the state of the switch to be driven to one of an on state, an off state, and a gate open state when the external signal is at the second logic level.

3. The receiving circuit an output stage configured to drive the switch to be driven; a logic circuit configured to control the output stage so that the output stage drives the switch to be driven based on the input signal when the external signal is at the first logic level, and to control the output stage so that the output stage drives the switch to be driven based on the external signal regardless of the input signal when the external signal is at the second logic level; The signal transmission device according to claim 1 , comprising:

4. The output stage comprises: a high-side switch that supplies a first voltage exceeding an on-threshold voltage of the switch to be driven to a control end of the drive switch in an on state; a low-side switch that supplies a second voltage lower than the on-threshold voltage to the control end in an on-state; Including, The logic circuit an external signal determination circuit configured to be able to determine the logic level of the external signal; a drive control circuit configured to control driving of the high-side switch and the low-side switch based on the determination result of the external signal determination circuit and the input signal; Including, The drive control circuit includes: based on the input signal when the external signal is at the first logic level, controlling the driving so as to turn on the high-side switch and turn off the low-side switch; Alternatively, the driving is controlled so that the high-side switch is turned off and the low-side switch is turned on, When the external signal is at the second logic level, the control circuit 100 controls the external signal to be at the second logic level. controlling the driving so as to turn on the high-side switch and turn off the low-side switch; Alternatively, the driving is controlled so that the high-side switch is turned off and the low-side switch is turned on, Alternatively, the drive is controlled so as to turn off the high-side switch and the low-side switch. The signal transmission device according to claim 3 .

5. 5. The signal transmission device according to claim 4, wherein the external signal determination circuit is capable of determining whether or not a voltage value of the external signal exceeds each of a plurality of threshold voltages including the first threshold voltage.

6. The threshold voltage is the first threshold voltage; a second threshold voltage higher than the first threshold voltage; a third threshold voltage higher than the second threshold voltage; Including, The drive control circuit includes: When the external signal determination circuit determines that the voltage value of the external signal is lower than the first threshold voltage, driving and controlling the high-side switch and the low-side switch based on the input signal; when the external signal determination circuit determines that the voltage value of the external signal is higher than the first threshold voltage and lower than the second threshold voltage, drive-controlling the high-side switch and the low-side switch so that the switch to be driven is in a first state which is one of an on state, an off state, or a gate open state, regardless of the input signal; when the external signal determination circuit determines that the voltage value of the external signal is higher than the second threshold voltage and lower than the third threshold voltage, drive-controlling the high-side switch and the low-side switch so that the switch to be driven is in a second state other than the first state, out of an on state, an off state, or a gate open state, regardless of the input signal; 6. The signal transmission device according to claim 5, wherein, when the external signal determination circuit determines that the voltage value of the external signal is higher than the second threshold voltage and lower than the third threshold voltage, the high-side switch and the low-side switch are driven and controlled so that the switch to be driven is in a third state, which is one of an on state, an off state, and a gate open state, and is a state other than the first state and the second state, regardless of the input signal.

7. A signal transmission device according to any one of claims 1 to 6, a control circuit configured to generate the input signal; an external signal generating circuit configured to generate the external signal; the switch to be driven; An electronic device comprising:

8. a protection circuit configured to monitor a SAT voltage of the switch to be driven; The electronic device according to claim 7 , wherein the external signal generating circuit sets the external signal to the first logic level or the second logic level in accordance with a monitoring result of the protection circuit.

9. A vehicle comprising the electronic device according to claim 7.

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