Detection device and method for manufacturing detection device

Abstract

To provide a detection device capable of improving detection accuracy, and a method of manufacturing the detection device.SOLUTION: The detection device includes a substrate, a plurality of photodiodes arranged in a matrix in a detection region of the substrate, and an element insulating film provided between the plurality of photodiodes, in which the plurality of photodiodes are stacked in order of a lower electrode, an active layer, a first upper electrode, and a second upper electrode, the lower electrode, the active layer, and the first upper electrode are disposed separately for each of the plurality of photodiodes, and the second upper electrode is provided continuously over the plurality of photodiodes to cover the first upper electrode and the element insulating film.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a detection device and a method for manufacturing a detection device. [Background technology]

[0002] Optical sensors capable of detecting fingerprint patterns and vein patterns are known (for example, Patent Document 1). Such optical sensors have a plurality of photodiodes (OPDs: Organic Photodiodes) that use an organic semiconductor material as the active layer. As described in Patent Document 2, the photodiodes are stacked, for example, in the following order: a lower electrode, an electron transport layer, an active layer, a hole transport layer, and an upper electrode. The electron transport layer or the hole transport layer is also called a buffer layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-32005 [Patent Document 2] International Publication No. 2020 / 188959 Summary of the Invention [Problem to be solved by the invention]

[0004] There is a demand for improved detection accuracy in optical sensors having such OPDs.

[0005] An object of the present invention is to provide a detection device and a method for manufacturing the detection device that can improve detection accuracy. [Means for solving the problem]

[0006] A detection device according to one embodiment of the present disclosure includes a substrate, a plurality of photodiodes arranged in a matrix in a detection region of the substrate, and an element insulating film provided between the plurality of photodiodes, wherein the plurality of photodiodes are stacked in the order of a lower electrode, an active layer, a first upper electrode, and a second upper electrode, the lower electrode, the active layer, and the first upper electrode are arranged spaced apart for each of the plurality of photodiodes, and the second upper electrode is provided continuously across the plurality of photodiodes, covering the first upper electrode and the element insulating film.

[0007] A manufacturing method for a detection device according to one embodiment of the present disclosure includes the steps of stacking an active layer and a first upper electrode so as to cover a plurality of lower electrodes provided in a detection region of a substrate; patterning the first upper electrode so as to separate each of the plurality of lower electrodes, and then using the patterned plurality of first upper electrodes as a mask, patterning the active layer so as to separate each of the plurality of lower electrodes; forming an element insulating film so as to cover at least the side surfaces of the active layer and the first upper electrode; and forming a second upper electrode so as to cover the plurality of first upper electrodes and the element insulating film. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view schematically showing a detection device according to an embodiment. [Figure 2] FIG. 2 is a block diagram illustrating an example of the configuration of the detection device according to the embodiment. [Figure 3] FIG. 3 is a circuit diagram showing a detection device according to an embodiment. [Figure 4] FIG. 4 is a plan view schematically showing the arrangement relationship between the plurality of photodiodes in the detection region and the contact portions and mounting portions in the peripheral region. [Figure 5] FIG. 5 is a cross-sectional view taken along line VV' in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI' in FIG. [Figure 7] FIG. 7 is an explanatory diagram for explaining a method for manufacturing a detection device according to an embodiment. [Figure 8] FIG. 8 is an explanatory diagram for explaining a method for manufacturing a detection device according to an embodiment. [Figure 9] FIG. 9 is an explanatory diagram for explaining a method of manufacturing a detection device according to a modified example. [Figure 10] FIG. 10 is an explanatory diagram for explaining a method for manufacturing a detection device according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0009] Modes (embodiments) for carrying out the present disclosure will be described in detail with reference to the drawings. The present disclosure is not limited to the contents described in the following embodiments. Furthermore, the components described below include those that can be easily imagined by a person skilled in the art and those that are substantially identical. Furthermore, the components described below can be combined as appropriate. Note that the disclosure is merely an example, and any appropriate modifications that a person skilled in the art can easily conceive while maintaining the gist of the present disclosure are naturally included within the scope of the present disclosure. Furthermore, for clarity of explanation, the drawings may schematically depict the width, thickness, shape, etc. of each part compared to the actual embodiment. However, these are merely examples and are not intended to limit the interpretation of the present disclosure. Furthermore, in this disclosure and each figure, elements similar to those described above with reference to the previous figures may be designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0010] In the present disclosure, when expressing an aspect of placing another structure on top of a certain structure, the term "on top" is used, unless otherwise specified, to include both a case in which another structure is placed directly on top of a certain structure so as to be in contact with the certain structure, and a case in which another structure is placed above a certain structure via yet another structure.

[0011] (Embodiment) Fig. 1 is a plan view schematically showing a detection device according to an embodiment. As shown in Fig. 1, the detection device 1 includes a substrate 21, a sensor unit 10, a gate line driving circuit 15, a signal line selection circuit 16, a detection circuit 48, a control circuit 122, a power supply circuit 123, a first light source substrate 51, a second light source substrate 52, and light sources 53 and 54. The first light source substrate 51 is provided with a plurality of light sources 53. The second light source substrate 52 is provided with a plurality of light sources 54.

[0012] A control board 121 is electrically connected to the substrate 21 via a wiring board 71. The wiring board 71 is, for example, a flexible printed circuit board or a rigid board. The detection circuit 48 is provided on the wiring board 71. The control board 121 is provided with a control circuit 122 and a power supply circuit 123. The control circuit 122 is, for example, an FPGA (Field Programmable Gate Array). The control circuit 122 supplies control signals to the sensor unit 10, the gate line driving circuit 15, and the signal line selection circuit 16 to control the detection operation of the sensor unit 10. The control circuit 122 also supplies control signals to the light sources 53 and 54 to control the lighting or non-lighting of the light sources 53 and 54. The power supply circuit 123 supplies voltage signals such as a sensor power supply signal VDDSNS (see FIG. 3) to the sensor unit 10, the gate line driving circuit 15, and the signal line selection circuit 16. The power supply circuit 123 also supplies a power supply voltage to the light sources 53 and 54.

[0013] The substrate 21 has a detection area AA and a peripheral area GA. The detection area AA is an area where a plurality of photodiodes PD (see FIG. 4) of the sensor unit 10 are provided. The peripheral area GA is an area between the outer periphery of the detection area AA and the outer edge of the substrate 21, where a plurality of photodiodes PD are not provided.

[0014] The gate line driving circuit 15 and the signal line selection circuit 16 are provided in the peripheral area GA. Specifically, the gate line driving circuit 15 is provided in a region of the peripheral area GA extending along the second direction Dy. The signal line selection circuit 16 is provided in a region of the peripheral area GA extending along the first direction Dx, and is provided between the sensor unit 10 and the detection circuit 48.

[0015] In the following description, the first direction Dx is a direction in a plane parallel to the substrate 21. The second direction Dy is a direction in a plane parallel to the substrate 21, and is a direction perpendicular to the first direction Dx. The second direction Dy may intersect with the first direction Dx without being perpendicular thereto. The third direction Dz is a direction perpendicular to the first direction Dx and the second direction Dy, and is a normal direction to the main surface of the substrate 21. Furthermore, "plan view" refers to the positional relationship when viewed from a direction perpendicular to the substrate 21 (the third direction Dz).

[0016] The plurality of light sources 53 are provided on the first light source substrate 51 and arranged along the second direction Dy. The plurality of light sources 54 are provided on the second light source substrate 52 and arranged along the second direction Dy. The first light source substrate 51 and the second light source substrate 52 are electrically connected to the control circuit 122 and the power supply circuit 123 via terminal portions 124 and 125 provided on the control board 121, respectively.

[0017] For example, inorganic light emitting diodes (LEDs) or organic light emitting diodes (OLEDs) are used as the light sources 53 and 54. The light sources 53 and 54 emit light of different wavelengths.

[0018] The first light emitted from light source 53 is mainly reflected by the surface of the object to be detected, such as a finger, and enters sensor unit 10. As a result, sensor unit 10 can detect a fingerprint by detecting the uneven shape of the surface of the finger or the like. The second light emitted from light source 54 is mainly reflected by the inside of the finger or the like or passes through the finger or the like and enters sensor unit 10. As a result, sensor unit 10 can detect information about the living body inside the finger or the like. The information about the living body includes, for example, the pulse wave, pulse rate, blood vessel image, etc. of the finger or palm. In other words, detection device 1 may be configured as a fingerprint detection device that detects fingerprints, or a vein detection device that detects blood vessel patterns such as veins.

[0019] The arrangement of the light sources 53, 54 shown in FIG. 1 is merely an example and can be changed as appropriate. The detection device 1 is provided with multiple types of light sources 53, 54 as light sources. However, this is not limited to this, and the light source may be of one type. For example, multiple light sources 53 and multiple light sources 54 may be arranged in each of the first light source substrate 51 and the second light source substrate 52. Furthermore, the number of light source substrates on which the light sources 53 and the light sources 54 are arranged may be one or three or more. Alternatively, it is sufficient that at least one or more light sources are arranged.

[0020] 2 is a block diagram showing an example of the configuration of a detection device according to an embodiment. As shown in FIG. 2, the detection device 1 further includes a detection control circuit 11 and a detection unit 40. Some or all of the functions of the detection control circuit 11 are included in a control circuit 122. In addition, some or all of the functions of the detection unit 40 other than the detection circuit 48 are included in the control circuit 122.

[0021] The sensor unit 10 has a plurality of photodiodes PD. The photodiodes PD of the sensor unit 10 output electrical signals corresponding to the incident light as detection signals Vdet to the signal line selection circuit 16. The sensor unit 10 also performs detection in accordance with the gate drive signal VGL supplied from the gate line drive circuit 15.

[0022] The detection control circuit 11 is a circuit that supplies control signals to the gate line drive circuit 15, the signal line selection circuit 16, and the detection unit 40, respectively, and controls their operations. The detection control circuit 11 supplies various control signals, such as a start signal STV and a clock signal CK, to the gate line drive circuit 15. The detection control circuit 11 also supplies various control signals, such as a selection signal ASW, to the signal line selection circuit 16. The detection control circuit 11 also supplies various control signals to the light sources 53 and 54, controlling their lighting and non-lighting.

[0023] The gate line driving circuit 15 is a circuit that drives multiple gate lines GL (see FIG. 3) based on various control signals. The gate line driving circuit 15 selects the multiple gate lines GL sequentially or simultaneously and supplies a gate driving signal VGL to the selected gate lines GL. In this way, the gate line driving circuit 15 selects multiple photodiodes PD connected to the gate lines GL.

[0024] The signal line selection circuit 16 is a switch circuit that sequentially or simultaneously selects a plurality of signal lines SL (see FIG. 3). The signal line selection circuit 16 is, for example, a multiplexer. The signal line selection circuit 16 connects the selected signal line SL to the detection circuit 48 based on a selection signal ASW supplied from the detection control circuit 11. As a result, the signal line selection circuit 16 outputs a detection signal Vdet of the photodiode PD to the detection unit 40.

[0025] The detection unit 40 includes a detection circuit 48, a signal processing circuit 44, a coordinate extraction circuit 45, a memory circuit 46, and a detection timing control circuit 47. Based on a control signal supplied from the detection control circuit 11, the detection timing control circuit 47 controls the detection circuit 48, the signal processing circuit 44, and the coordinate extraction circuit 45 so that they operate in synchronization.

[0026] The detection circuit 48 is, for example, an analog front end (AFE) circuit. The detection circuit 48 is a signal processing circuit having at least the functions of a detection signal amplifier circuit 42 and an A / D conversion circuit 43. The detection signal amplifier circuit 42 amplifies the detection signal Vdet. The A / D conversion circuit 43 converts the analog signal output from the detection signal amplifier circuit 42 into a digital signal.

[0027] The signal processing circuit 44 is a logic circuit that detects a predetermined physical quantity input to the sensor unit 10 based on the output signal of the detection circuit 48. When a finger comes into contact with or close to the detection surface, the signal processing circuit 44 can detect unevenness on the surface of the finger or palm based on the signal from the detection circuit 48. The signal processing circuit 44 can also detect information about the living body based on the signal from the detection circuit 48. The information about the living body includes, for example, an image of the blood vessels of the finger or palm, a pulse wave, a pulse rate, and a blood oxygen concentration.

[0028] The memory circuit 46 temporarily stores the signals calculated by the signal processing circuit 44. The memory circuit 46 may be, for example, a RAM (Random Access Memory), a register circuit, or the like.

[0029] The coordinate extraction circuit 45 is a logic circuit that calculates the detected coordinates of the unevenness of the surface of a finger or the like when the signal processing circuit 44 detects contact or proximity of a finger. The coordinate extraction circuit 45 is also a logic circuit that calculates the detected coordinates of the blood vessels of the finger or palm. The coordinate extraction circuit 45 combines the detection signals Vdet output from each photodiode PD of the sensor unit 10 to generate two-dimensional information indicating the shape of the unevenness of the surface of the finger or the like and two-dimensional information indicating the shape of the blood vessels of the finger or palm. The coordinate extraction circuit 45 may output the detection signal Vdet as the sensor output voltage Vo without calculating the detection coordinates.

[0030] Fig. 3 is a circuit diagram showing a detection device according to an embodiment. Fig. 3 also shows the circuit configuration of a detection circuit 48. As shown in Fig. 3, a sensor pixel PX includes a photodiode PD, a capacitance element Ca, and a drive transistor Tr. The capacitance element Ca is a capacitance (sensor capacitance) formed in the photodiode PD, and is equivalently connected in parallel with the photodiode PD.

[0031] 3 shows two gate lines GL(m) and GL(m+1) aligned in the second direction Dy among the multiple gate lines GL. Also, two signal lines SL(n) and SL(n+1) aligned in the first direction Dx among the multiple signal lines SL. A sensor pixel PX is an area surrounded by the gate lines GL and the signal lines SL.

[0032] The drive transistors Tr are provided corresponding to the respective photodiodes PD. The drive transistors Tr are configured by thin film transistors, and in this example, are configured by n-channel MOS (Metal Oxide Semiconductor) TFTs (Thin Film Transistors).

[0033] Each of the gate lines GL is connected to the gates of a plurality of drive transistors Tr arranged in a first direction Dx. Each of the signal lines SL is connected to one of the source and drain of a plurality of drive transistors Tr arranged in a second direction Dy. The other of the source and drain of each of the drive transistors Tr is connected to the cathode of the photodiode PD and the capacitance element Ca.

[0034] A sensor power supply signal VDDSNS is supplied to the anode of the photodiode PD from the power supply circuit 123 (see FIG. 1). In addition, a sensor reference voltage COM, which serves as the initial potential of the signal line SL and the capacitance element Ca, is supplied to the signal line SL and the capacitance element Ca from the power supply circuit 123 via the reset transistor TrR.

[0035] When light is irradiated onto the sensor pixel PX during the exposure period, a current corresponding to the amount of light flows through the photodiode PD, causing charge to accumulate in the capacitance element Ca. When the drive transistor Tr is turned on during the readout period, a current corresponding to the charge accumulated in the capacitance element Ca flows through the signal line SL. The signal line SL is connected to the detection circuit 48 via the output transistor TrS of the signal line selection circuit 16. This allows the detection device 1 to detect a signal corresponding to the amount of light irradiated onto the photodiode PD for each sensor pixel PX.

[0036] During the readout period, the switch SSW of the detection circuit 48 is turned on and connected to the signal line SL. The detection signal amplifier circuit 42 of the detection circuit 48 converts the current or charge supplied from the signal line SL into a voltage corresponding to the current or charge. A reference potential (Vref) having a fixed potential is input to the non-inverting input terminal (+) of the detection signal amplifier circuit 42, and the signal line SL is connected to the inverting input terminal (-). In this embodiment, a signal equal to the sensor reference voltage COM is input as the reference potential (Vref) voltage. The control circuit 122 (see FIG. 1) calculates the difference between the detection signal Vdet when light is irradiated and the detection signal Vdet when light is not irradiated as the sensor output voltage Vo. The detection signal amplifier circuit 42 also has a capacitance element Cb and a reset switch RSW. During the reset period, the reset switch RSW is turned on and the charge of the capacitance element Cb is reset.

[0037] The driving transistor Tr is not limited to an n-type TFT, but may be a p-type TFT. The pixel circuit of the sensor pixel PX shown in Fig. 3 is merely an example, and the sensor pixel PX may be provided with multiple transistors corresponding to one photodiode PD.

[0038] Next, the detailed configuration of the photodiode PD will be described with reference to Fig. 4 to Fig. 6. Fig. 4 is a plan view schematically showing the arrangement relationship between a plurality of photodiodes in the detection region and contact parts and mounting parts in the peripheral region.

[0039] 4, a plurality of photodiodes PD are arranged in a matrix in the detection area AA. The photodiodes PD of this embodiment are organic photodiodes (OPDs) that use an organic semiconductor as the active layer 33 (see FIG. 5).

[0040] The lower electrodes 31 of the photodiodes PD are provided separately for each of the photodiodes PD and are arranged in a matrix in the detection area AA. The second upper electrodes 36 of the photodiodes PD are provided continuously across the photodiodes PD and are provided throughout the detection area AA. A portion of the second upper electrode 36 extends into the peripheral area GA, is connected to the contact portion CN, and is electrically connected to an external circuit (e.g., a control circuit 122 or a power supply circuit 123 (see FIG. 1)) through wiring on the substrate 21.

[0041] The detection device 1 has a sealing film 90 that covers the multiple photodiodes PD. The sealing film 90 is provided across the detection area AA and the peripheral area GA, and is provided up to the outer edge side of the substrate 21. The sealing film 90 extends further to the outer edge side of the substrate 21 than multiple insulating films (e.g., the organic insulating film 26, the barrier film 27, etc.) provided on the substrate 21. The sealing film 90 can prevent moisture from entering from the outer edge side of the substrate 21 to the detection area AA side. Note that the detailed configurations of the photodiodes PD, each insulating film, and sealing film 90 will be described later with reference to FIGS. 5 and 6.

[0042] The mounting portion 95 is provided on the substrate 21 outside the outer periphery of the sealing film 90. The mounting portion 95 includes, for example, a connection terminal for connecting to the wiring board 71 (see FIG. 1). Alternatively, the mounting portion 95 may include a mounting terminal for mounting an IC (Integrated Circuit) that constitutes the detection circuit 48 or the like.

[0043] Next, a description will be given of the laminated structure of the multiple photodiodes PD and the sealing film 90 of the detection device 1. Fig. 5 is a cross-sectional view taken along line VV' in Fig. 4. Fig. 5 shows two photodiodes PD (sensor pixels PX) adjacent to each other in the first direction Dx.

[0044] In the following description, the direction perpendicular to the surface of the substrate 21, from the substrate 21 toward the sealing film 90, will be referred to as the "upper side" or simply "upper." The direction from the sealing film 90 toward the substrate 21 will be referred to as the "lower side" or simply "lower."

[0045] 5, the detection device 1 includes a substrate 21, a drive transistor Tr, a plurality of inorganic insulating films (an undercoat film 22, a gate insulating film 23, an interlayer insulating film 24, and a superimposed insulating film 25), an organic insulating film 26, a barrier film 27, a photodiode PD, an element insulating film 39, and a sealing film 90. In the detection area AA, the plurality of inorganic insulating films (the undercoat film 22, the gate insulating film 23, the interlayer insulating film 24, and the superimposed insulating film 25), the organic insulating film 26, the barrier film 27, the photodiode PD, the element insulating film 39, and the sealing film 90 are stacked in this order on the substrate 21.

[0046] The substrate 21 is an insulating substrate made of a film-like resin. The driving transistor Tr is provided in a region overlapping with the lower electrode 31 of the photodiode PD. Specifically, the driving transistor Tr has a semiconductor layer 61, a source electrode 62, a drain electrode 63, and a gate electrode 64.

[0047] The light-shielding film 65 is provided on the substrate 21. The light-shielding film 65 is provided between the semiconductor layer 61 and the substrate 21. The light-shielding film 65 prevents light from entering the channel region of the semiconductor layer 61 from the substrate 21 side.

[0048] The undercoat film 22 is provided on the substrate 21, covering the light-shielding film 65. The undercoat film 22 is formed of an inorganic insulating film such as a silicon nitride film or a silicon oxide film. The configuration of the undercoat film 22 is not limited to a single layer, and may be a laminated film having two or more layers stacked together, for example.

[0049] The drive transistor Tr is provided on a substrate 21. The semiconductor layer 61 is provided on an undercoat film 22. The gate insulating film 23 is provided on the undercoat film 22, covering the semiconductor layer 61. The gate insulating film 23 is an inorganic insulating film such as a silicon oxide film. The gate electrode 64 is provided on the gate insulating film 23.

[0050] 5, the driving transistor Tr has a top gate structure. However, without being limited to this, the driving transistor Tr may have a bottom gate structure or a dual gate structure in which gate electrodes 64 are provided on both the upper and lower sides of the semiconductor layer 61.

[0051] The interlayer insulating film 24 is provided on the gate insulating film 23, covering the gate electrode 64. The interlayer insulating film 24 has, for example, a stacked structure of a silicon nitride film and a silicon oxide film. The source electrode 62 and the drain electrode 63 are provided on the interlayer insulating film 24. The source electrode 62 is connected to the source region of the semiconductor layer 61 through a contact hole CH2 provided through the gate insulating film 23 and the interlayer insulating film 24. The drain electrode 63 is connected to the drain region of the semiconductor layer 61 through a contact hole CH3 provided through the gate insulating film 23 and the interlayer insulating film 24. The superposed insulating film 25 is provided on the interlayer insulating film 24, covering the source electrode 62 and the drain electrode 63.

[0052] A connection wiring 64a is provided in the same layer as the gate electrode 64. The connection wiring 64a is electrically connected to the gate electrode 64. A connection wiring 65a is provided in the same layer as the light-shielding film 65. The connection wiring 65a is electrically connected to the light-shielding film 65. The connection wiring 64a and the connection wiring 65a are connected via a contact hole CH4 that penetrates the undercoat film 22 and the gate insulating film 23. As a result, the light-shielding film 65 is electrically connected to the gate electrode 64 via the connection wirings 64a, 65a, and is supplied with the same potential as the gate electrode 64.

[0053] The organic insulating film 26 is provided on the superposed insulating film 25, covering the source electrode 62 and the drain electrode 63 of the drive transistor Tr. The organic insulating film 26 is a planarizing film made of an organic insulating material. In this embodiment, a contact hole CH1 in the organic insulating film 26 is provided in a region overlapping with the source electrode 62. The lower electrode 31 of the photodiode PD is electrically connected to the source electrode 62 at the bottom of the contact hole CH1.

[0054] The detection device 1 may be configured such that the superimposed insulating film 25 of the inorganic insulating films (the undercoat film 22, the gate insulating film 23, the interlayer insulating film 24, and the superimposed insulating film 25) is not provided. In this case, the organic insulating film 26 is provided on the interlayer insulating film 24, covering the source electrode 62 and the drain electrode 63.

[0055] The barrier film 27 is provided on the organic insulating film 26. The barrier film 27 is made of an inorganic insulating material such as a silicon nitride (SiN) film.

[0056] The photodiode PD is provided on the barrier film 27. The photodiode PD has a lower electrode 31, a lower buffer layer 32, an active layer 33, an upper buffer layer 34, a first upper electrode 35, and a second upper electrode 36. In the photodiode PD, the lower electrode 31, the lower buffer layer 32, the active layer 33, the upper buffer layer 34, the first upper electrode 35, and the second upper electrode 36 are stacked in this order in a direction perpendicular to the substrate 21.

[0057] The lower electrode 31 is formed of a light-transmitting conductive material such as ITO (Indium Tin Oxide). As described above, a lower electrode 31 is provided for each photodiode PD. The lower electrodes 31 of adjacent photodiodes PD are arranged to be spaced apart from each other.

[0058] The insulating film 38 is provided to cover the periphery of the lower electrode 31. The insulating film 38 provides insulation between the lower electrodes 31 of adjacent photodiodes PD. The insulating film 38 is also provided to cover the contact hole CH1, covering the lower electrode 31 in the region overlapping with the contact hole CH1. Even if a step occurs in the lower buffer layer 32 in the region overlapping with the contact hole CH1, the insulating film 38 prevents a short circuit between the active layer 33 and the lower electrode 31. In this embodiment, the insulating film 38 is formed of an inorganic insulating material such as silicon nitride (SiN) or silicon oxide (SiO2).

[0059] The lower electrode 31, the lower buffer layer 32, the active layer 33, the upper buffer layer 34, and the first upper electrode 35 are provided separately for each of the photodiodes PD. Specifically, the lower buffer layer 32, the active layer 33, the upper buffer layer 34, and the first upper electrode 35 are provided in this order to overlap the lower electrode 31.

[0060] The characteristics (for example, voltage-current characteristics and resistance value) of the active layer 33 change depending on the light irradiated thereto. An organic material is used as the material of the active layer 33. Specifically, the active layer 33 has a bulk heterostructure in which a p-type organic semiconductor and an n-type organic semiconductor, an n-type fullerene derivative (PCBM), are mixed. For example, a low-molecular organic material, C 60 (fullerene), PCBM (phenyl C 61 Butyric acid methyl ester: Phenyl C 61 -butyric acid methyl ester), CuPc (Copper Phthalocyanine), F 16 CuPc (fluorinated copper phthalocyanine), rubrene (5,6,11,12-tetraphenyltetracene), PDI (perylene derivative), etc. can be used.

[0061] The active layer 33 can be formed by a vapor deposition (dry process) using these low molecular weight organic materials. In this case, the active layer 33 is formed by, for example, CuPc and F 16 CuPc laminated film or rubrene and C 60The active layer 33 may be a laminated film of the above-mentioned low molecular weight organic material and high molecular weight organic material. The active layer 33 may also be formed by a coating process (wet process). In this case, the active layer 33 is made of a material that is a combination of the above-mentioned low molecular weight organic material and high molecular weight organic material. Examples of high molecular weight organic materials that can be used include P3HT (poly(3-hexylthiophene)) and F8BT (F8-alt-benzothiadiazole). The active layer 33 may be a film in which P3HT and PCBM are mixed, or a film in which F8BT and PDI are mixed. The active layer 33 is not limited to a bulk heterostructure, and may also be a PIN type.

[0062] The lower buffer layer 32 and the upper buffer layer 34 are provided to allow holes and electrons generated in the active layer 33 to easily reach the lower electrode 31 or the first upper electrode 35. The lower buffer layer 32 is provided between the lower electrode 31 and the active layer 33, and is in direct contact with the lower electrode 31 and the active layer 33. The upper buffer layer 34 is provided between the active layer 33 and the first upper electrode 35, and is in direct contact with the active layer 33 and the first upper electrode 35.

[0063] In this embodiment, the lower electrode 31 is the cathode electrode of the photodiode PD, and the upper electrode (first upper electrode 35 and second upper electrode 36) is the anode electrode of the photodiode PD. In this case, the lower buffer layer 32 is an electron transport layer, and the upper buffer layer 34 is a hole transport layer. Ethoxylated polyethyleneimine (PEIE) is used as a material for the electron transport layer. A metal oxide layer is used as a material for the hole transport layer. Tungsten oxide (WO3), molybdenum oxide, or the like is used as the metal oxide layer.

[0064] Alternatively, the lower electrode 31 may be the anode electrode of the photodiode PD, and the upper electrode (the first upper electrode 35 and the second upper electrode 36) may be the cathode electrode of the photodiode PD. In this case, the lower buffer layer 32 may be a hole transport layer, and the upper buffer layer 34 may be an electron transport layer.

[0065] The first upper electrode 35 is provided on the upper buffer layer 34. The first upper electrode 35 is formed of a light-transmitting conductive material such as ITO or IZO (Indium Zinc Oxide). However, without being limited thereto, the first upper electrode 35 may be formed of a light-non-transmitting conductive material such as silver (Ag).

[0066] The element insulating film 39 is provided between adjacent photodiodes PD. Specifically, the element insulating film 39 is provided on the insulating film 38 between adjacent photodiodes PD, covering at least the side surfaces of the lower buffer layer 32, the active layer 33, the upper buffer layer 34, and the first upper electrode 35. This provides insulation between the lower buffer layer 32, the active layer 33, the upper buffer layer 34, and the first upper electrode 35 of adjacent photodiodes PD. Furthermore, the element insulating film 39 covers the periphery of the first upper electrode 35, and has an opening in a region overlapping with the first upper electrode 35. The element insulating film 39 is formed of an organic insulating material, such as acrylic resin. Alternatively, the element insulating film 39 may be made of an inorganic insulating material, such as silicon nitride (SiN).

[0067] The second upper electrode 36 is provided continuously across the multiple photodiodes PD, covering the first upper electrode 35 and the element insulating film 39. Furthermore, the second upper electrode 36 contacts the first upper electrode 35 of each of the multiple photodiodes PD through an opening in the element insulating film 39. A sensor power supply signal VDDSNS (see FIG. 3) having a predetermined potential is supplied to each of the multiple photodiodes PD through the second upper electrode 36.

[0068] The sealing film 90 is provided on the second upper electrode 36. The sealing film 90 is made of an inorganic insulating material such as silicon nitride (SiN). The sealing film 90 seals the photodiode PD well and can prevent moisture from entering from the upper surface side. The sealing film 90 is not limited to a single layer film and may be a multilayer film. The sealing film 90 may also be a multilayer film made of inorganic sealing films made of inorganic insulating materials and organic sealing films made of organic insulating materials.

[0069] Next, the connection configuration between the second upper electrode 36 and the contact portion CN in the peripheral region GA will be described. Fig. 6 is a cross-sectional view taken along line VI-VI' in Fig. 4. Note that in Fig. 6, the lower buffer layer 32 and the upper buffer layer 34 are omitted for ease of viewing.

[0070] 6, the contact portion CN has a connection terminal 81 and power supply voltage supply wirings 82 and 83. The power supply voltage supply wirings 82 and 83 are connected to, for example, a power supply circuit 123 (see FIG. 1), and supply a sensor power supply signal VDDSNS to the multiple photodiodes PD. The power supply voltage supply wiring 82 is provided on the interlayer insulating film 24, and the power supply voltage supply wiring 83 is provided on the gate insulating film 23.

[0071] The connection terminal 81 is provided on the superimposed insulating film 25 in the peripheral area GA. The connection terminal 81 is connected to the power supply voltage supply wiring 82 through an opening provided in the superimposed insulating film 25 in a region where the connection terminal 81 overlaps with the power supply voltage supply wiring 82.

[0072] The second upper electrode 36 is provided continuously from the detection area AA to the peripheral area GA, and is connected to the connection terminal 81 in the peripheral area GA. With this configuration, the second upper electrode 36 is connected to the contact portion CN, and a power supply signal VDDSNS is supplied from, for example, the power supply circuit 123 (see FIG. 1).

[0073] In addition, in the region between the contact portion CN (connection terminal 81) and the sensor pixel PX in the detection area AA, the organic insulating film 26, the barrier film 27, and the lower electrode 31, active layer 33, and first upper electrode 35 that constitute the photodiode PD are removed, and an insulating film 38 and an element insulating film 39 are laminated on the superimposed insulating film 25. In the peripheral area GA, the second upper electrode 36 is provided on the element insulating film 39. In addition, in the contact portion CN (region where the connection terminal 81 is provided), the insulating film 38 and the element insulating film 39 are not provided, and the second upper electrode 36 and the sealing film 90 are laminated in this order on the connection terminal 81.

[0074] With the above-described configuration, in the detection device 1 of this embodiment, the active layer 33 (including the lower buffer layer 32 and the upper buffer layer 34) is patterned to be spaced apart for each photodiode PD, and therefore, compared to a configuration in which the active layer 33 is provided continuously across multiple photodiodes PD, it is possible to suppress delays in the arrival time of carriers (holes and electrons) generated in the active layer 33.

[0075] More specifically, if the active layer 33 is provided over the entire detection area AA, the active layer 33 is also present in the area between adjacent lower electrodes 31. Carriers generated in the active layer 33 in the area that does not overlap with the lower electrode 31 may experience a delay in response until they reach the lower electrode 31 compared to carriers generated in the active layer 33 in the area that overlaps with the lower electrode 31. The delay of carriers generated in the active layer 33 may result in detection errors and a decrease in resolution between sensor pixels PX.

[0076] In this embodiment, the active layer 33 is patterned separately for each photodiode PD (each lower electrode 31), and an insulating film 38 and an element insulating film 39 are provided in the region between adjacent lower electrodes 31. Therefore, compared to when the active layer 33 is provided over the entire surface of the detection area AA, generation of carriers in the region between adjacent lower electrodes 31 is suppressed. Therefore, it is possible to suppress delay in the arrival time of carriers (holes and electrons) generated in the active layer 33 in each photodiode PD.

[0077] In this embodiment, an insulating film 38 is provided between adjacent lower electrodes 31, and an element insulating film 39 is provided between adjacent active layers 33. This makes it possible to suppress leakage current between adjacent photodiodes PD.

[0078] (Method of manufacturing the detection device) Fig. 7 is an explanatory diagram for explaining a method for manufacturing a detection device according to an embodiment. Fig. 8 is an explanatory diagram for explaining a method for manufacturing a detection device according to an embodiment. Fig. 7 shows up to the step of patterning the active layer 33 and the first upper electrode 35, and Fig. 8 shows from the step of forming the element insulating film 39 to the step of forming the sealing film 90. Note that Figs. 7 and 8 omit illustration of the drive transistor Tr, various wirings, and insulating film formed between the substrate 21 and the photodiode PD.

[0079] 7, an organic layer that will become the active layer 33 is formed by coating to cover the plurality of lower electrodes 31, insulating film 38, and connection terminals 81 formed on substrate 21 (step ST1). The active layer 33 is formed by coating, for example, using spin coating or a slit coater. Note that before step ST1, there is a step of forming the plurality of lower electrodes 31 in the detection area AA of substrate 21, and forming connection terminals 81 for supplying a predetermined potential to the plurality of photodiodes PD in a peripheral area GA different from the detection area AA.

[0080] Next, the first upper electrode 35 is formed on the active layer 33 (step ST2). For example, IZO is used as the material of the first upper electrode 35. The first upper electrode 35 is formed on the entire surface of the active layer 33 by, for example, sputtering.

[0081] A resist 92 is formed on the first upper electrode 35 by photolithography and etching (step ST3). The resist 92 is provided in an area overlapping with the lower electrode 31 (an area where the photodiode PD is to be formed), and is removed in an area not overlapping with the lower electrode 31. The resist 92 is also removed in an area overlapping with the connection terminal 81 in the peripheral area GA.

[0082] The first upper electrode 35 is patterned so as to be spaced apart for each of the plurality of lower electrodes 31 (step ST4). In step ST4, the first upper electrode 35 is removed by dry etching from the region where the resist 92 is not provided. Furthermore, the first upper electrode 35 remains in the region where the resist 92 is provided (the region where the photodiode PD is to be formed).

[0083] Next, using the plurality of first upper electrodes 35 patterned in step ST4 as a mask, the active layer 33 is patterned so as to be spaced apart for each of the plurality of lower electrodes 31 (step ST5). In step ST5, the active layer 33 in the region where the first upper electrode 35 is not provided is removed by dry etching. The active layer 33 in the region where the first upper electrode 35 is provided (the region where the photodiode PD is to be formed) remains. In step ST5, the resist 92 on the first upper electrode 35 is also removed. Furthermore, in steps ST4 and ST5, the active layer 33 and the first upper electrode 35 are also removed in the region overlapping with the connection terminal 81 in the peripheral region GA.

[0084] 8, an element insulating film 39 is formed to cover the plurality of first upper electrodes 35 and between the adjacent plurality of active layers 33 and the plurality of first upper electrodes 35 (step ST6). The element insulating film 39 covers the side surfaces of the active layers 33 and the first upper electrodes 35 and is provided on the insulating film 38 between the adjacent active layers 33 and first upper electrodes 35.

[0085] A resist 93 is formed on the element insulating film 39 by photolithography and etching (step ST7). The resist 93 is provided in a region that does not overlap with the first upper electrode 35, and is removed in a region that overlaps with the first upper electrode 35 (a region where the photodiode PD is to be formed).

[0086] An opening is formed in the element insulating film 39 by dry etching in a region overlapping with the first upper electrode 35 (step ST8). In step ST8, the portion of the element insulating film 39 overlapping with the connection terminal 81 in the peripheral region GA is also removed, exposing the connection terminal 81.

[0087] A second upper electrode 36 is formed to cover the plurality of first upper electrodes 35 and the element insulating film 39 (step ST9). In step ST9, the second upper electrode 36 contacts the first upper electrode 35 through the opening in the element insulating film 39. The second upper electrode 36 is also provided extending to a region overlapping with the connection terminal 81 in the peripheral region GA, and is connected to the connection terminal 81.

[0088] A resist 94 is patterned on the second upper electrode 36 by photolithography and etching (step ST10). The resist 94 is formed on the second upper electrode 36 in an area that overlaps the entire detection area AA and the connection terminals 81. In addition, the resist 94 is removed from the area that does not overlap the connection terminals 81 in the peripheral area GA.

[0089] By dry etching, the portions of the second upper electrode 36 where the resist 94 is not provided, that is, the portions that do not overlap with the connection terminals 81 in the peripheral area GA, are removed (step ST11).

[0090] Next, the passivation film 90 is formed on the second upper electrode 36 (step ST12). Note that the passivation film 90 is not limited to a single layer film, and may be a laminated film in which a plurality of insulating films are laminated.

[0091] The detection device 1 can be manufactured through the steps described above. According to the manufacturing method for the detection device 1 of this embodiment, the active layer 33 is patterned using the first upper electrode 35 as a mask, which makes it possible to suppress shape variations in the active layer 33 compared to a method in which the first upper electrode 35 and the active layer 33 are patterned individually using masks. Therefore, the detection device 1 suppresses detection errors caused by shape variations in the multiple photodiodes PD. Therefore, the detection device 1 can improve detection accuracy.

[0092] The manufacturing method of the detection device 1 shown in FIGS. 7 and 8 is merely an example and can be modified as appropriate.

[0093] (Variation) Fig. 9 is an explanatory diagram for explaining a manufacturing method of a detection device according to a modified example. Fig. 10 is an explanatory diagram for explaining a manufacturing method of a detection device according to a modified example. In the following explanation, the same components as those explained in the above embodiment are assigned the same reference numerals, and duplicate explanations will be omitted.

[0094] As shown in FIG. 9, an organic layer that will become the active layer 33 is formed by coating to cover the plurality of lower electrodes 31, the insulating film 38, and the connection terminals 81 that are formed on the substrate 21 (step ST21).

[0095] Next, the first upper electrode 35 and the inorganic insulating film 91 are formed on the active layer 33 (step ST22). The first upper electrode 35 and the inorganic insulating film 91 are formed on the entire surface of the active layer 33. The inorganic insulating film 91 is made of an inorganic insulating material such as silicon nitride (SiN).

[0096] Resist 92 is formed on inorganic insulating film 91 by photolithography and etching (step ST23). Resist 92 is provided in a region overlapping with lower electrode 31 (a region where photodiode PD is to be formed), and is removed in a region not overlapping with lower electrode 31.

[0097] The inorganic insulating film 91 and the first upper electrode 35 are patterned so as to be spaced apart for each of the plurality of lower electrodes 31 (step ST24). In step ST24, the inorganic insulating film 91 and the first upper electrode 35 are removed by dry etching from the region where the resist 92 is not provided. The inorganic insulating film 91 and the first upper electrode 35 remain in the region where the resist 92 is provided (the region where the photodiode PD is to be formed).

[0098] Next, using the inorganic insulating films 91 and the first upper electrodes 35 patterned in step ST24 as a mask, the active layer 33 is patterned so as to separate each of the lower electrodes 31 (step ST25). In step ST25, the active layer 33 in the regions where the inorganic insulating films 91 and first upper electrodes 35 are not provided is removed by dry etching. The active layer 33 in the regions where the inorganic insulating films 91 and first upper electrodes 35 are provided (regions where the photodiodes PD are to be formed) remains. In step ST25, the resist 92 on the inorganic insulating film 91 is also removed.

[0099] In this modification, since the inorganic insulating film 91 is provided on the first upper electrode 35, it is possible to prevent the first upper electrode 35 from being damaged by dry etching in the process of patterning the active layer 33 in step ST25.

[0100] 10, the element insulating film 39 is formed to cover the inorganic insulating films 91 and the first upper electrodes 35, and between the adjacent active layers 33, the first upper electrodes 35, and the inorganic insulating films 91 (step ST26). The element insulating film 39 covers the side surfaces of the active layers 33, the first upper electrodes 35, and the inorganic insulating films 91, and is provided on the insulating film 38 between the adjacent active layers 33, the first upper electrodes 35, and the inorganic insulating films 91.

[0101] Resist 93 is formed on the element insulating film 39 by photolithography and etching (step ST27). The resist 93 is provided in a region that does not overlap with the first upper electrode 35, and is removed in a region that overlaps with the first upper electrode 35 (a region where the photodiode PD is to be formed).

[0102] An opening is formed in the element insulating film 39 by dry etching in a region overlapping with the first upper electrode 35 (step ST28). In step ST28, the inorganic insulating film 91 is also removed, and the first upper electrode 35 is exposed in the opening of the element insulating film 39.

[0103] In step ST28 shown in FIG. 10, all of the inorganic insulating film 91 is removed, but this is not limited to this, and part of the inorganic insulating film 91 may remain around the periphery of the opening of the element insulating film 39.

[0104] In the following steps, the second upper electrode 36 is formed and patterned in the same manner as in steps ST9 to ST12 (see FIG. 8) of the above-described embodiment, and then the sealing film 90 is formed. In this way, the detection device 1 can be manufactured.

[0105] Although preferred embodiments of the present disclosure have been described above, the present disclosure is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible within the scope of the present disclosure. Appropriate modifications made within the scope of the present disclosure naturally fall within the technical scope of the present disclosure. At least one of various omissions, substitutions, and modifications of components can be made within the scope of the gist of each of the above-described embodiments and modifications. [Explanation of symbols]

[0106] 1. Detection device 10 Sensor section 21 PCB 26 Organic insulating film 27 Barrier membranes, 31 Lower electrode 32 Lower buffer layer 33 Active layer 34 Upper buffer layer 35 1st upper electrode 36 2nd upper electrode 38 insulating film 39 Element insulating film 81 Connection terminal 90 Sealing film 95 Mounting section PD photodiode PX sensor pixel Tr drive transistor

Claims

1. A substrate; a plurality of photodiodes arranged in a matrix in a detection region of the substrate; an element insulating film provided between the plurality of photodiodes, The plurality of photodiodes are stacked in the order of a lower electrode, an active layer, a first upper electrode, and a second upper electrode, the lower electrode, the active layer, and the first upper electrode are spaced apart for each of the plurality of photodiodes; The second upper electrode covers the first upper electrode and the element insulating film and is provided continuously across the plurality of photodiodes. Detection device.

2. the element insulating film covers at least the side surfaces of the active layer and the first upper electrode, and has an opening provided in a region overlapping with the first upper electrode; The second upper electrode is in contact with the first upper electrodes through the openings in the device insulating film. The detection device according to claim 1 .

3. a connection terminal provided in a peripheral region of the substrate different from the detection region and supplying a predetermined potential to the plurality of photodiodes; The second upper electrode is provided across the detection region and the peripheral region and is connected to the connection terminal. The detection device according to claim 1 .

4. depositing an active layer and a first upper electrode over the plurality of lower electrodes provided in the detection region of the substrate; patterning the first upper electrode so as to separate the plurality of lower electrodes, and then patterning the active layer so as to separate the plurality of lower electrodes using the patterned plurality of first upper electrodes as a mask; forming an element insulating film covering at least the side surfaces of the active layer and the first upper electrode; forming a second upper electrode to cover the first upper electrodes and the device insulating film; A method for manufacturing a detection device.

5. The step of forming an element insulating film includes: forming the element insulating film covering the plurality of first upper electrodes and between the plurality of adjacent active layers and the plurality of first upper electrodes; forming openings in the element insulating film in regions overlapping the plurality of first upper electrodes; In the step of forming the second upper electrode, the second upper electrode is in contact with the plurality of first upper electrodes through the openings in the element insulating film. A method for manufacturing the detection device according to claim 4.

6. forming connection terminals for supplying a predetermined potential to a plurality of photodiodes in a peripheral region of the substrate different from the detection region; In the step of forming the second upper electrode, the second upper electrode is provided across the detection region and the peripheral region and is connected to the connection terminal. A method for manufacturing the detection device according to claim 4.

7. forming an inorganic insulating film on the first upper electrode after the step of stacking the active layer and the first upper electrode; In the step of patterning the active layer, the first upper electrode and the inorganic insulating film are patterned separately for each of the plurality of lower electrodes, and then the patterned plurality of first upper electrodes and the plurality of inorganic insulating films are used as a mask. A method for manufacturing the detection device according to claim 4.

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