Substrate processing method and substrate processing apparatus

Abstract

To reduce contact resistance between a conductive film formed on a semiconductor layer containing silicon in a recess of a substrate and the semiconductor layer.SOLUTION: A substrate processing method of the present disclosure includes forming a zirconium silicide layer forming a bottom wall of a recess by supplying a first processing gas containing zirconium to a substrate having the recess in which a semiconductor layer containing silicon is exposed at a bottom surface of the recess and a side wall of the recess is formed by an insulator film, removing zirconium remaining on the side wall of the recess by supplying a second processing gas to the substrate, and forming a conductive film in the recess by supplying a film forming gas to the substrate after the removing of the zirconium remaining on the side wall of the recess.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a substrate processing method and a substrate processing apparatus. [Background technology]

[0002] In the manufacturing process of a semiconductor device, recesses constituting via holes, trenches, etc. are formed in an insulator layer formed on a semiconductor wafer (hereinafter referred to as "wafer"), which serves as a substrate. A process is then performed to fill the recesses with a conductive film, which is a wiring material, so as to electrically connect the semiconductor layer containing silicon exposed at the bottom of the recesses. Before this filling process, the silicon at the bottom of the recesses may be converted into a metal silicide to reduce the resistance (contact resistance) at the contact between the conductive film and the semiconductor layer.

[0003] Patent Document 1 discloses a manufacturing process for a semiconductor device in which a zirconium film is formed on a well formed on a Si substrate, and then BF2 and As are implanted into the well through the zirconium film to form a source / drain junction. After that, a titanium film is stacked on the zirconium film and heat treatment is performed, thereby forming titanium silicide and zirconium silicide at the junction, and it is said that defects caused by ion implantation remain in the zirconium silicide of these metal silicides. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 9-171969 Summary of the Invention [Problem to be solved by the invention]

[0005] The present disclosure provides a technique capable of reducing the contact resistance between a conductive film formed on a semiconductor layer containing silicon in a recess in a substrate and the semiconductor layer. [Means for solving the problem]

[0006] The substrate processing method of the present disclosure includes the steps of: supplying a first process gas containing zirconium to a substrate having a recess in which a semiconductor layer containing silicon is exposed at a bottom surface and in which a sidewall is formed by an insulating film, to form a zirconium silicide layer that forms the bottom wall of the recess; supplying a second process gas to the substrate to remove zirconium remaining on the sidewall of the recess; a film formation step of supplying a film formation gas to the substrate on which the removing step has been performed to form a conductive film in the recess; A substrate processing method comprising: [Effects of the Invention]

[0007] The present disclosure can reduce the contact resistance between a conductive film formed on a semiconductor layer containing silicon in a recess in a substrate and the semiconductor layer. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 2 is a cross-sectional side view of a wafer before metal silicide is formed. [Figure 2] FIG. 2 is a longitudinal sectional side view of a wafer on which a ZrSi layer is formed. [Figure 3] FIG. 2 is a longitudinal sectional side view of a wafer on which a Ti film is formed. [Figure 4] FIG. 1 is a longitudinal sectional side view of a wafer from which the Ti film has been removed. [Figure 5] FIG. 1 is a vertical cross-sectional side view of a wafer in which a Ru film has been embedded. [Figure 6] FIG. 1 is a longitudinal sectional side view of a wafer that has undergone CMP. [Figure 7] FIG. 2 is a plan view of the substrate processing apparatus. [Figure 8] FIG. 2 is a vertical sectional side view of a wafer before processing by the substrate processing apparatus. [Figure 9] 2 is a vertical sectional side view of a processing module provided in the substrate processing apparatus; FIG. [Figure 10]FIG. 10 is a plan view showing a first modified example of the substrate processing apparatus. [Figure 11] FIG. 10 is a plan view showing a second modified example of the substrate processing apparatus. [Figure 12] FIG. 10 is a plan view showing a third modified example of the substrate processing apparatus. [Figure 13] FIG. 10 is a graph showing the results of an evaluation test. [Figure 14] FIG. 10 is a graph showing the results of an evaluation test. [Figure 15] FIG. 10 is a graph showing the results of an evaluation test. DETAILED DESCRIPTION OF THE INVENTION

[0009] <Description of the substrate processing process> An example of a substrate processing method according to an embodiment of the present disclosure will be described with reference to the longitudinal side views of wafer A in Figures 1 to 6. Figures 1 to 6 also show processing steps that are sequentially performed on wafer A when forming an NMOS field effect transistor.

[0010] Wafer A in Fig. 1 will be described. An SiO2 layer 12 is laminated on a silicon (Si) layer 11 constituting wafer A. A hole is formed in this SiO2 layer 12 in the thickness direction, and the bottom end of the hole formed in this SiO2 layer 12 reaches the Si layer 11. A SiN film (silicon nitride) 13 is formed so as to cover the side surface of the SiO2 layer 12 that forms the hole. Note that the Si layer 11 contains an appropriate amount of dopant, such as phosphorus, to form an NMOS.

[0011] By providing each layer as described above, recesses 14 forming trenches or holes are formed in wafer A, and the sidewalls of these recesses 14 are formed of an insulating layer consisting of an SiO2 layer 12 and an SiN film 13. The bottom wall of these recesses 14 is formed of an Si layer 11, i.e., a semiconductor layer containing silicon. The Si layer 11 is exposed at the bottom of the recesses 14.

[0012] To give an overview of the processing of wafer A in this embodiment, a Ru (ruthenium) film 15 is embedded in the recess 14 as a conductive film that forms a wiring metal with a relatively low resistance. Prior to this embedding, a gas treatment is performed to reduce the contact resistance between the Ru film 15 and the Si layer 11, thereby forming ZrSi (zirconium silicide) on the surface of the bottom wall of the recess 14. This ZrSi is formed by a treatment using plasmatized gas.

[0013] When forming a metal silicide as a contact portion between a semiconductor layer and a conductive film, it is also known to use a silicide of a metal other than Zr, such as TiSi (titanium silicide). In this embodiment, ZrSi is formed as the metal silicide forming the above-mentioned connection portion because, compared to forming a silicide of another metal such as TiSi, forming ZrSi reduces the Schottky barrier, which is an energy barrier formed between the metal silicide and the Si layer 11. It is known that the smaller this Schottky barrier, the smaller the contact resistance, and in an NMOS, electrons flow more easily from the Si layer 11 to the metal silicide.

[0014] However, when forming ZrSi in this manner, Zr (zirconium) contained in the gas for forming ZrSi remains on the sidewalls of the recesses 14 (i.e., the SiN film 13). When filling the recesses 14 with a conductive film (Ru film 15 in this embodiment), the larger the volume of the filled conductive film, the more the contact resistance can be reduced. Therefore, in this embodiment, the Zr remaining on the sidewalls of the recesses 14 is removed so as to increase the volume of the conductive film. If the ZrSi is etched more than necessary when removing this Zr, there is a risk that the contact resistance will not be sufficiently reduced. In this embodiment, the wafer A is processed so as to suppress etching of ZrSi and prevent a decrease in the volume of the Ru film 15 filled in the recesses 14.

[0015] 1 to 6, the processes shown in FIGS. 1 to 5 are performed by supplying various gases to wafer A, which is placed on stage 66 in processing vessel 61, which is under a vacuum atmosphere, and heated to a predetermined processing temperature. As will be described in detail later in the description of the substrate processing apparatus, wafer A is processed by being transferred between multiple processing vessels 61 in sequence.

[0016] First, plasma CVD is performed by supplying ZrCl4 (zirconium chloride) gas, Ar gas, and H2 gas to wafer A described in FIG. 1 and applying high-frequency power. As a result, as described above, the surface layer of Si layer 11 exposed at the bottom of recess 14 reacts with the plasma, and the bottom wall of recess 14 becomes ZrSi layer 21. As this ZrSi layer 21 is formed, Zr (zirconium) is deposited on the outside and side walls of recess 14 (FIG. 2, step S1). In the figure, this deposited Zr is shown as a Zr film 22. Note that in reality, the deposited Zr may be scattered throughout the surface of wafer A and not form a film, but for convenience, it will be described as a film.

[0017] After the application of high-frequency power is stopped and the supply of ZrCl4 gas, Ar gas, and H2 gas to wafer A is stopped, TiCl4 (titanium tetrachloride) gas is supplied to wafer A. The reaction shown in Equation 1 below proceeds, and the Zr film 22 becomes gaseous ZrCl2, which is removed from wafer A by exhausting the processing chamber. The TiCl2 produced along with ZrCl2 is also gaseous and is removed from wafer A along with ZrCl2. While the Zr film 22 is being removed in this manner, solid Ti is produced from the TiCl4 gas, and this Ti adheres to the outside of the recess 14 and to the sidewalls of the recess 14 (FIG. 3, step S2). In the figure, this adhered Ti is shown as a Ti film 23. However, like Zr, this Ti may actually be scattered and not form a film, but for convenience of illustration, it is shown as a film. As shown in the evaluation test described later, the supply of this TiCl4 gas etches the Zr film 22 as described above, but etching of the ZrSi layer 21 is suppressed. Formula 1...Zr+TiCl4→TiCl2+ZrCl2

[0018] After the supply of TiCl4 gas to wafer A is stopped, BCl3 (boron trichloride) gas and HF (hydrogen fluoride) gas are alternately and repeatedly supplied to wafer A. The BCl3 gas selectively reacts with the Ti film 23 out of the ZrSi layer 21 and the Ti film 23, and Ti constituting the Ti film 23 becomes TiCl4, vaporizes, and is removed from wafer A. Meanwhile, B constituting the BCl3 gas reacts with oxygen contained in the surface of wafer A to become BO (boron oxide), which adheres to various parts of the surface of wafer A, including the sidewalls of recesses 14, in place of Ti. This BO reacts with HF gas to become fluoride, vaporizes, and is removed from the surface of wafer A (FIG. 4, step S3).

[0019] The supply of BCl3 gas and HF gas to wafer A is stopped. By performing the processes of steps S2 and S3, Zr, Ti, and B contained in the gases used in steps S1 to S3 are removed from the sidewalls of recesses 14, and Ti and B are also removed from the bottom wall of recesses 14. Ru3(CO) 12 Gas (dodecacarbonyltriruthenium gas) is supplied to perform CVD, and the Ru film 15 is embedded in the recess 14 and laminated on the ZrSi layer 21 (FIG. 5, step S4).

[0020] As described above, the recess 14 is filled with the elements removed from the sidewalls and bottom wall of the recess 14, so the volume of the Ru film 15 occupying the recess 14 becomes relatively large. 12 After the supply of gas to wafer A is stopped, the portion of Ru film 15 formed on the insulator layer (SiO2 layer 12 and SiN film 13) and the upper end of the insulator layer are removed as unnecessary portions by CMP (Chemical Mechanical Polishing) (Figure 6, Step S5).

[0021] According to the above process, when the Ru film 15 is embedded in the recess 14 whose bottom wall is formed by the Si layer 11, the ZrSi layer 21 that forms the contact portion between the Si layer 11 and the Ru film 15 is formed, thereby making it possible to relatively lower the Schottky barrier and relatively increase the volume of the Ru film 15 in the recess 14. This reduces the contact resistance between the Si layer 11 and the Ru film 15. Furthermore, when the Zr film 22 is removed to increase the volume of the Ru film 15 in the recess 14, etching of the ZrSi layer 21 is suppressed, thereby ensuring a sufficient thickness of the ZrSi layer 21 with high reliability. This makes it possible to more reliably reduce the contact resistance.

[0022] <Configuration of Substrate Processing Apparatus> Next, a substrate processing apparatus 3, which is one embodiment of a substrate processing apparatus capable of performing steps S1 to S4 among the above-described steps S1 to S5, will be described with reference to the plan view of Fig. 7. Also, Fig. 8 shows a wafer A before processing by this substrate processing apparatus 3. In this wafer A, the Si layer 11 on the bottom surface of the recess 14 is naturally oxidized to form an SiO2 film 19. In the substrate processing apparatus 3, the SiO2 film 19 is also removed as a pre-processing step for step S1.

[0023] The substrate processing apparatus 3 includes a loader module 31, a load lock module 35, a first vacuum transfer module 41, a second vacuum transfer module 42, a connection module 43, a first processing module 51, a second processing module 52, a third processing module 53, a fourth processing module 54, and a fifth processing module 55. In the following description, the first vacuum transfer module 41 and the second vacuum transfer module 42 may be collectively referred to as vacuum transfer modules 41, 42. The first to fifth processing modules 51 to 55 may be simply referred to as processing modules 51 to 55.

[0024] The loader module 31, the load lock module 35, the first vacuum transfer module 41, the connection module 43, and the second vacuum transfer module 42 are arranged in a straight line in the horizontal direction in this order. In the following description of the substrate processing apparatus 3, the side where the loader module 31 is located will be referred to as the front side, and the side where the second vacuum transfer module 42 is located will be referred to as the rear side.

[0025] The loader module 31 includes a housing whose interior is at atmospheric pressure, a transfer mechanism 32 for wafer A provided within the housing, and a load port 33. In this example, four load ports 33 are provided side by side on the left and right side of the front side of the housing. A transfer container 34 called a FOUP (Front Opening Unified Pod) for storing wafer A is placed on each load port 33. The transfer mechanism 32 is configured, for example, with an articulated arm that can move left and right, and is capable of transferring wafer A between the transfer container 34 on each load port 33 and each load lock module 35.

[0026] In this example, three load lock modules 35 are provided side by side. Each load lock module 35 has a housing, and the housing is connected to the loader module 31 and the first vacuum transfer module 41 via gate valves G provided at the front and rear sides thereof, respectively. With the gate valves G at the front and rear sides of the housing closed, the pressure inside the housing can be freely changed between atmospheric pressure and vacuum pressure. A stage (not shown) on which the wafer A is placed is provided inside the housing, and the stage is configured to be able to transfer the wafer A to and from the transfer mechanism 32 and a transfer mechanism 44 (described later) that access the load lock module 35.

[0027] The first vacuum transfer module 41 and the second vacuum transfer module 42 are configured similarly to each other and include housings 41A and 42A, respectively. An exhaust port 45 is opened in each of the housings 41A and 42A, and one end of an exhaust pipe is connected to the exhaust port 45. The other end of the exhaust pipe is connected to an exhaust mechanism 46 composed of a turbomolecular pump, a valve, etc. The inside of the housing 41A and the inside of the housing 42A are each maintained in a vacuum atmosphere by exhausting air from the exhaust port 45 by the exhaust mechanism 46.

[0028] In this example, two connection modules 43 are provided side by side. The connection module 43 includes a housing 43A, which is connected to the housings 41A and 42A of the vacuum transfer modules 41 and 42. The exhaust mechanism 46 exhausts air, creating a vacuum atmosphere inside the housing 43A of the connection module 43 at the same pressure as the housings 41A and 42A. A wafer A is placed inside the housing 43A, and a stage (not shown) configured to be able to transfer the wafer A between the housing 43A and a transfer mechanism 44 (described later) is also provided. Hereinafter, the interiors of the housings 41A, 42A, and 43A, which are created into a vacuum atmosphere by the exhaust mechanism 46, will be collectively referred to as the vacuum transfer path 40 for the wafer A.

[0029] An inert gas supply mechanism 47 is connected to the housings 41A and 42A to supply inert gas, such as N2 (nitrogen) gas or Ar gas. The inert gas supply mechanism 47 includes an inert gas storage section and a valve for switching on and off the supply of inert gas from the storage section to the housings 41A and 42A. The pressure in the vacuum transfer path 40 is adjusted to a desired vacuum pressure by the supply of N2 gas or Ar gas from the inert gas supply mechanism 47 and exhaust by the exhaust mechanism 46. When no inert gas is supplied by the inert gas supply mechanism 47, the exhaust mechanism 46 adjusts the vacuum transfer path 40 to a desired vacuum pressure, for example. -7 Torr (1.333 × 10 -5 The air can be evacuated to a first pressure lower than 1 Pa.

[0030] A first processing module 51 and a third processing module 53 are connected to one of the left and right sides of the housing 41A of the first vacuum transfer module 41 via gate valves G1, and these processing modules 51, 53 are arranged side by side in the front and rear. A second processing module 52 and a fourth processing module 54 are connected to the other left and right side of the housing 41A via gate valves G1, and these processing modules 52, 54 are arranged side by side in the front and rear.

[0031] Two fifth process modules 55 are connected to each of the left and right sides of the housing 42A of the second vacuum transfer module 42 via gate valves G1. Two fifth process modules 55 are arranged in a line up front and back on each of the left and right sides of the housing 42A. The process modules 51 to 55 can process wafers A in parallel with each other. Because the process by the fifth process module 55 takes longer than the processes by the other process modules 51 to 54, the fifth process module 55 is provided in the largest number of the process modules 51 to 55, thereby improving the throughput of the substrate processing apparatus 3.

[0032] A transfer mechanism 44 is provided within each of the housings 41A and 42A, and each transfer mechanism 44 is configured, for example, by an articulated arm that can move back and forth. The transfer mechanism 44 within the housing 41A transfers wafers A between the load lock module 35, the connection module 43, and each processing module connected to the housing 41A via gate valve G1. The transfer mechanism 44 within the housing 42A transfers wafers A between the connection module 43 and each processing module connected to the housing 42A via gate valve G1. The gate valves G and G1 are closed except when necessary to transfer wafers A between the modules, separating the atmospheres between the modules. Each stage of the load lock module 35 and the connection module 43 is provided with, for example, pins that can be protruded and retracted from the stage to enable transfer of wafers A between the transfer mechanisms.

[0033] The first processing module 51 and the second processing module 52 are processing modules for pre-processing that removes the SiO2 film 19. The third processing module 53 performs steps S1 and S2 described with reference to FIGS. 1 to 3, the fourth processing module 54 performs step S3 described with reference to FIG. 4, and the fifth processing module 55 performs step S4 described with reference to FIG.

[0034] The substrate processing apparatus 3 includes a control unit 30, which is a computer, and the control unit 30 includes a program. The program contains instructions (steps) for processing and transporting wafers A in each of the processing modules 51-55. The program is stored on a storage medium, such as a compact disc, hard disk, or DVD, and is installed in the control unit 30. The control unit 30 outputs control signals to each component of the substrate processing apparatus 3 using the program to control the operation of each component. Specifically, the control unit 30 controls the operation of the processing modules 51-55, the opening and closing of gate valves G and G1, the operation of transport mechanisms 32 and 44, the operation of exhaust mechanism 46, the operation of inert gas supply mechanism 47, and switching of the pressure within the load lock module 35. The control of the operation of the processing modules 51-55 includes controlling the temperature of wafer A on stage 66 by supplying power to heater 67, which will be described later, switching between supplying and stopping the supply of each gas into processing chamber 61 by opening and closing valve V, and switching on and off high-frequency power supplies 69 and 75.

[0035] <Configuration of the third processing module 53> The third process module 53, which performs the formation of the ZrSi layer 21 and the removal of the Zr film 22 (the formation of the Ti film 23) in steps S1 and S2, will be described with reference to FIG. 9, which is a longitudinal side view. The third process module 53 is a capacitively coupled plasma processing apparatus and includes a metal process vessel 61, which is grounded. A transfer port 62 for the wafer A is provided in the side wall of the process vessel 61, and the transfer port 62 is opened and closed by the gate valve G1. A heater 63 for adjusting the temperature inside the process vessel 61 is embedded in a shower head 71 (described below) that forms the side wall and ceiling wall of the process vessel 61. One end of an exhaust path 64 opens at the bottom of the process vessel 61, and the other end of the exhaust path 64 is connected to an exhaust mechanism 65 including a valve and a vacuum pump. The exhaust mechanism 65 evacuates the inside of the process vessel 61 to a vacuum atmosphere of a desired pressure.

[0036] A stage 66 is provided within the processing vessel 61, and the wafer A is placed on the stage 66 so that it is horizontal. Above the stage 66 is a processing space 70 to which gas is supplied from a shower head 71, which will be described later. A heater 67 is embedded in the stage 66 as a heating mechanism, and the heater 67 heats the placed wafer A to a preset processing temperature. The stage 66 also functions as a lower electrode, and is connected to a high-frequency power supply 69, which supplies high-frequency power for applying a bias (for attracting ions into the plasma), via a matching box 68. Although not shown, three pins are provided on the top surface of the stage 66 that can be raised and lowered by a lifting mechanism, and the wafer A can be transferred between the top surface of the stage 66 and the transfer mechanism 44 via these pins.

[0037] A shower head 71 is provided on the ceiling wall of the processing vessel 61 and is attached to the processing vessel 61 via an insulating member 79. The shower head 71 includes a gas diffusion space 72 and a number of outlets 73 that open downward and discharge gas supplied from the diffusion space 72 toward the processing space 70. The shower head 71 is configured as an upper electrode, and is connected to a high-frequency power supply 75 via a matching box 74, which supplies high-frequency power for plasma generation.

[0038] High frequency power of a predetermined frequency is supplied from the high frequency power supply 75 to the shower head 71, and the gas supplied from the shower head 71 to the processing space 70 is converted into plasma. While this high frequency power is being supplied from the high frequency power supply 75, high frequency power is supplied from the high frequency power supply 69 to the stage 66, and ions that make up the plasma are drawn toward the stage 66. The frequency of the high frequency power supplied from the high frequency power supply 75 to the shower head 71 is higher than the frequency of the high frequency power supplied from the high frequency power supply 75 to the stage 66.

[0039] The downstream end of a gas flow path 76 is connected to the diffusion space 72 of the shower head 71. The upstream side of the gas flow path 76 branches to form gas flow paths 81-84. The upstream end of the gas flow path 81 is connected to a ZrCl4 gas supply source 81A, the upstream end of the gas flow path 82 is connected to a TiCl4 gas supply source 82A, the upstream end of the gas flow path 83 is connected to an Ar (argon) gas supply source 83A, and the upstream end of the gas flow path 84 is connected to an H2 (hydrogen) gas supply source 84A. A flow rate adjuster M, which is configured by a valve V and a mass flow controller, is disposed in order toward the upstream side of each of the gas flow paths 81-84. Opening and closing the valve V switches between supplying and stopping each gas from each gas supply source 81A-84A to the processing space 70 via the shower head 71. The flow rate adjuster M adjusts the flow rate of each gas supplied to the processing space 70 to a preset amount.

[0040] Ar gas is a carrier gas and dilution gas for ZrCl4 gas in the processing space 70, and a dilution gas for TiCl4 gas. H2 gas is also a gas for reacting with ZrCl4 gas. As described above, in step S1, for example, Ar gas and H2 gas are supplied to the processing space 70 in addition to ZrCl4 gas, plasma CVD is performed, and wafer A is processed as described in FIG. 2. Also, in the above-described step S2, for example, Ar gas is supplied to the processing space 70 in addition to TiCl4 gas, and wafer A is processed as described in FIG. 3.

[0041] <Configuration of other processing modules> Each of the processing modules other than the third processing module 53 has a configuration generally similar to that of the third processing module 53, and can process the wafer A by heating the wafer A placed on the stage 66 with a heater 67 while supplying gas from a shower head 71. However, with regard to the gas supply source, instead of the supply sources that supply the gases described for the third processing module 53, supply sources that supply gases corresponding to the processing performed in each processing module are provided. Also, some processing modules do not perform plasma processing on the wafer A, and therefore differ from the third processing module 53 in that they do not have high-frequency power supplies 75, 69.

[0042] The first processing module 51 performs a process called COR (Chemical Oxide Removal) and is equipped with a hydrogen fluoride (HF) gas supply source and an ammonia (NH) gas supply source. These gases are supplied to the wafer A to transform the SiO2 film 19 into a compound with a relatively low sublimation temperature. The second processing module 52 is a module called PHT (Post Heat Treatment) for removing the transformed compound. This second processing module 52 is equipped with a supply source of an inert gas, such as N2 (nitrogen) gas, and supplies the inert gas to the processing space 70 to create an inert gas atmosphere. The wafer A is heated in this state, and the transformed SiO2 film 19 is sublimated and removed from the wafer A. Because no plasma is used to process the wafer A, the first processing module 51 and the second processing module 52 do not have high-frequency power sources 69, 75.

[0043] The fourth process module 54 is equipped with a BCl3 gas supply source, an HF gas supply source, and an H2 gas supply source. Therefore, the fourth process module can perform processing using H2 gas, but since processing using H2 gas is not performed in this embodiment, it will be described in detail in a later embodiment. Like the third process module 53, the fourth process module 54 is equipped with high-frequency power supplies 69 and 75, and when processing using H2 gas, the H2 gas can be converted into plasma to process the wafer A. The fifth process module 55 is equipped with Ru3(CO) 12 Gas source and Ru3(CO) 12 A supply source of CO (carbon monoxide) gas, which serves as a carrier gas for the gas, is provided, but high frequency power sources 69 and 75 are not provided.

[0044] ZrCl4 gas is the first processing gas, TiCl4 gas containing Ti as a metal other than zirconium (second metal) is the second processing gas, BCl3 gas and HF gas are the third processing gas, and Ru3(CO) 12The gas is a deposition gas for a conductive film. A ZrCl4 gas supply source 81A provided in the third process module 53, a gas flow path 81 for ZrCl4 gas, and a valve V and a flow rate adjuster M provided in the gas flow path 81 constitute a first process gas supply unit. A TiCl4 gas supply source 82A provided in the third process module 53, a gas flow path 82 for TiCl4 gas, and a valve V and a flow rate adjuster M provided in the gas flow path 82 constitute a second process gas supply unit.

[0045] As described above, the fourth process module 54 and the fifth process module 55 have substantially the same configuration as the third process module 53, except for the type of gas supplied to the wafer A. Therefore, the fourth process module 54 includes a BCl3 gas supply source, a gas flow path for BCl3 gas, a valve V and a flow rate adjuster M provided in the gas flow path for the BCl3 gas, an HF gas supply source, a gas flow path for HF gas, and a valve V and a flow rate adjuster M provided in the gas flow path for the HF gas, as a third process gas supply unit. The fifth process module 55 supplies Ru3(CO) 12 Gas source and Ru3(CO) 12 A gas flow path for the gas and the Ru3(CO) 12 The deposition gas supply unit includes a valve V and a flow rate regulator M provided in a gas flow path.

[0046] As described above, the substrate processing apparatus 3 is configured such that a processing module provided with a first processing gas supply unit and a second processing gas supply unit, a processing module provided with a third processing gas supply unit, and a processing module provided with a film forming gas supply unit are individually provided and arranged at different positions. Wafer A is transported sequentially between the processing modules thus arranged at different positions, and is heated to a processing temperature set in each processing module and subjected to gas processing, thereby performing the above steps S1 to S4.

[0047] As described above, the substrate processing apparatus 3 is configured such that separate processing modules are provided according to the processing temperatures of wafer A in steps S1 to S4. Specifically, since the processing temperatures of wafer A are the same in the consecutive steps S1 and S2, these steps S1 and S2 are performed in the same processing module. Since the processing temperatures of wafer A are different in the consecutive steps S2 and S3, the processing modules that perform these steps are separate and provided in different locations. Since the processing temperatures of wafer A are also different in the consecutive steps S3 and S4, the processing modules that perform these steps are also separate and provided in different locations.

[0048] <Operation of the Substrate Processing Apparatus> The processing procedure for wafer A by the substrate processing apparatus 3 will be described. -7 The first pressure is set to a predetermined first pressure lower than Torr. The reason for this high vacuum is to sufficiently remove oxygen molecules and water molecules from the vacuum transfer path 40 to prevent an increase in contact resistance due to oxidation of the ZrSi layer 21 by the oxygen molecules and water molecules during transfer of the wafer A from the formation of the ZrSi layer 21 until the Ru film 15 is embedded in the recesses 14. After the pressure in the vacuum transfer path 40 reaches the first pressure, an inert gas such as N2 gas or Ar gas is supplied to the vacuum transfer path 40 by the inert gas supply mechanism 47, thereby increasing the pressure in the vacuum transfer path 40. The supply of this inert gas and the evacuation by the evacuation mechanism 46 are performed in parallel, so that the pressure in the vacuum transfer path 40 is maintained at a predetermined second pressure, for example, 800 mTorr (106.6 Pa).

[0049] While the pressure of the vacuum transfer path 40 is adjusted in this manner, the insides of the processing vessels 61 of the processing modules 51 to 55 are also evacuated by the exhaust mechanism 65, and are maintained at a preset pressure that is lower than the second pressure of the vacuum transfer path 40. By creating a pressure difference between the vacuum transfer path 40 and each processing vessel 61 in this manner, gas is prevented from flowing from each processing vessel 61 into the vacuum transfer path 40 when the gate valves G1 for transporting the wafer A between the vacuum transfer path 40 and each processing module 51 to 55 are opened.

[0050] 8, the wafer A having the SiO2 film 19 formed thereon is transferred from the transfer vessel 34 and transferred in the order of the loader module 31, the load lock module 35, and the first vacuum transfer module 41. That is, the wafer A is transferred to the vacuum transfer path 40 in which a differential pressure is created within each processing vessel 61 as described above. The wafer A is then transferred into the first processing module 51 and placed on the stage 66 of the first processing module 51, where it is heated to a predetermined processing temperature. In this heated state, HF gas and NH3 gas are supplied into the processing space 70 of the processing module 51, thereby altering the SiO2 film 19.

[0051] Next, wafer A is transferred to second processing module 52 via first vacuum transfer module 41 and placed on stage 66 where it is heated to a predetermined processing temperature, while an inert gas is supplied to processing space 70 of processing module 52. By being heated in this inert gas atmosphere, altered material of SiO film 19 is sublimated and removed, and the Si layer 11 is exposed on the bottom surface of recess 14 as described in FIG.

[0052] Thereafter, wafer A is transferred to third processing module 53 via first vacuum transfer module 41, and placed on stage 66 of processing module 53, where it is heated to a predetermined processing temperature, for example, 450°C. In this heated state, ZrCl4 gas, H2 gas, and Ar gas are supplied to processing space 70 of processing module 53, and plasma CVD is performed. That is, step S1 described above is performed, and the ZrSi layer 21 and Zr film 22 are formed as described in FIG.

[0053] After the plasma generation is stopped, TiCl4 gas and Ar gas are supplied to the processing space 70 of the processing module 53. That is, step S2 is performed, and the Zr film 22 is removed and the Ti film 23 is formed as described in Fig. 3. Note that even during the execution of step S2, the processing temperature of the wafer A is heated to, for example, 450°C, the same as during the execution of step S1.

[0054] Next, wafer A is transferred to fourth processing module 54 via first vacuum transfer module 41 and placed on stage 66 within processing module 54, where it is heated to a predetermined processing temperature, for example, 250°C. In this heated state, BCl3 gas is supplied to processing space 70 of processing module 54 for a predetermined time, followed by HF gas for a predetermined time. This supply of BCl3 gas and HF gas constitutes one cycle, and this cycle is repeated. That is, BCl3 gas and HF gas are alternately and repeatedly supplied to wafer A. That is, step S3 described above is performed, and Ti film 23 is removed as shown in FIG. 4.

[0055] Thereafter, wafer A is transferred in the order of first vacuum transfer module 41 → connection module 43 → second vacuum transfer module 42 → fifth processing module 55, and is placed on stage 66 in fifth processing module 55, where it is heated to a predetermined processing temperature, for example, 150° C. In this heated state, Ru3(CO) 125, the Ru film 15 is embedded in the recess 14. Thereafter, the wafer A is transferred in the order of the second vacuum transfer module 42, the connection module 43, the first vacuum transfer module 41, the load lock module 35, and the loader module 31, and then returned to the transfer container 34.

[0056] In the substrate processing apparatus 3 described above, the processing modules 51 to 54 are connected to the vacuum transfer path 40, and the wafer A is transferred through each of the processing modules 51 to 54 by a transfer mechanism 44 provided on the vacuum transfer path 40. Therefore, a vacuum atmosphere is maintained around the wafer A from the formation of the ZrSi layer 21 to the formation of the Ru film 15 on the ZrSi layer 21. Therefore, oxidation of the ZrSi layer 21 is suppressed, and an increase in contact resistance due to this oxidation can be prevented.

[0057] In addition, the vacuum transfer path 40 is temporarily set to 1×10 -7 After the vacuum transfer path 40 is depressurized to a first pressure lower than Torr, the wafer A is transferred through the vacuum transfer path 40. In the process of depressurizing the vacuum transfer path 40 to the first pressure, most of the water and oxygen in the vacuum transfer path 40 are removed, so the concentrations of water and oxygen in the vacuum transfer path 40 during transfer of the wafer A are extremely low. Therefore, oxidation of the ZrSi layer 21 by the water and oxygen is suppressed, and an increase in contact resistance is more reliably prevented.

[0058] <Modification of the Substrate Processing Apparatus> Incidentally, steps S1 and S2 may be performed at different processing temperatures. In this case, it is preferable to perform steps S1 and S2 in different processing modules to prevent a decrease in processing efficiency of wafer A due to the need to change the temperature of each section in the processing module every time wafer A is loaded. Figure 10 shows a substrate processing apparatus 3A, which is a first modification of the substrate processing apparatus 3. In this substrate processing apparatus 3A, a processing module 53A that performs step S1 and a processing module 53B that performs step S2 are provided instead of the third processing module 53, in order to accommodate the fact that steps S1 and S2 are performed at different processing temperatures.

[0059] 9 except that processing module 53A is provided with a gas supply source that performs only step S1 of steps S1 and S2, and performs processing by heating wafer A to 400° C. Processing module 53B is provided with a gas supply source that performs only step S2 of steps S1 and S2, and does not perform plasma processing, so does not have high-frequency power supplies 69 and 75. Processing module 53A is provided with a gas supply source that performs only step S2 of steps S1 and S2, and performs processing by heating wafer A to 450° C.

[0060] The substrate processing apparatus 3A will be further described, focusing on the differences from the substrate processing apparatus 3. As shown in the figure, processing modules 53A and 53B are connected to a first vacuum transfer module 41 instead of a third processing module 53 and a fourth processing module 54. In the substrate processing apparatus 3A, a fourth processing module 54 is connected to a second vacuum transfer module 42 instead of one of the four fifth processing modules 55 provided in the substrate processing apparatus 3. After the SiO2 film 19 is removed in the second processing module 52, the wafer A is transferred via the vacuum transfer path 40 in the order of processing module 53A, processing module 53B, fourth processing module 54, and fifth processing module 55, and is subjected to the processing of steps S1 to S4.

[0061] As described above, the substrate processing apparatus 3A is provided with a processing module including a first processing gas supply unit and a second processing gas supply unit, a processing module including a third processing gas supply unit, and a processing module including a film forming gas supply unit, similar to the substrate processing apparatus 3. However, the processing module including the first processing gas supply unit and the processing module including the second processing gas supply unit are also provided separately.

[0062] To perform wafer A at a more appropriate processing temperature during steps S1 and S2, it is preferable to configure the substrate processing apparatus 3A so that steps S1 and S2 are performed in separate processing modules. Furthermore, when a Zr film 22 is formed on wafer A in step S1, a Zr film 22 is also formed on the inner wall of the processing vessel 61. In the substrate processing apparatus 3A in which steps S1 and S2 are performed in separate processing modules 53A and 53B, respectively, when TiCl4 gas is supplied in step S2, the Zr film 22 on the inner wall is not peeled off by the TiCl4 gas and adheres to wafer A as foreign matter. This is preferable because it suppresses a decrease in the yield of products manufactured from wafer A. However, from the perspective of increasing throughput by increasing the number of fifth processing modules 55, which require a relatively long processing time as described above, it is preferable to configure the substrate processing apparatus 3 so that steps S1 and S2 are performed in the same processing module.

[0063] 11 is a plan view of a substrate processing apparatus 3B that is a second modification of the substrate processing apparatus 3, and the following description will focus on the differences between the substrate processing apparatus 3B and the substrate processing apparatus 3. The first processing module 51 of the substrate processing apparatus 3B heats the wafer A to a relatively high temperature during processing, thereby sublimating the SiO2 film 19 that has been altered by the HF gas and NH3 gas. Therefore, while the substrate processing apparatus 3 uses two processing modules (processing modules 51 and 52) to remove the SiO2 film 19, the substrate processing apparatus 3B uses a single processing module (processing module 51) to remove the SiO2 film 19.

[0064] Therefore, the first vacuum transfer module 41 of the substrate processing apparatus 3B is not connected to the second processing module 52. Instead, two fourth processing modules 54 are connected to the first vacuum transfer module 41. After being processed in the first processing module 51, the wafer A is transferred to the third processing module 53 for further processing, and then, as in the substrate processing apparatus 3, is transferred to the fourth processing module 54 and the fifth processing module 55 in that order for further processing.

[0065] FIG. 12 shows a substrate processing apparatus 3C, which is a third modification of the substrate processing apparatus 3. The differences between the substrate processing apparatus 3C and the substrate processing apparatus 3 will be described in detail below. Similar to the first vacuum transfer module 41 of the substrate processing apparatus 3A shown in FIG. 10, the first vacuum transfer module 41 of the substrate processing apparatus 3C is connected to process modules 53A and 53B instead of process module 53. Similarly to the first process module 51 of the substrate processing apparatus 3B shown in FIG. 11, the first process module 51 of the substrate processing apparatus 3C is configured to be able to remove the SiO2 film 19 by sublimation, and the substrate processing apparatus 3C does not include a second process module 52. Unlike the substrate processing apparatus 3B, the substrate processing apparatus 3C includes only one third process module 54. The wafer A transferred from the first process module 51 is transferred to process module 53A and then transferred between the process modules in the same order as the substrate processing apparatus 3A for processing.

[0066] As illustrated above, the configuration of the substrate processing apparatus 3 can be appropriately changed. As with the substrate processing apparatus 3, the substrate processing apparatuses 3A to 3C also have a configuration in which the wafer A is transferred via the vacuum transfer path 40 after the ZrSi layer 21 is formed, and the vacuum transfer path 40 is temporarily set to a value of 1×10 -7 The pressure is set to be lower than Torr, which prevents oxidation of the ZrSi layer 21 during transfer of the wafer A, thereby preventing an increase in contact resistance.

[0067] As described above, in the substrate processing apparatuses 3 and 3A to 3C, processes using chlorine compound gases such as ZrCl4, TiCl4, and BCl3 are performed in the first to fourth process modules 51 to 54. Therefore, when the Ru film 15 is formed in the fifth process module, chlorine is attached to various parts of the surface of the wafer A, including the sidewalls of the recesses 14. When chlorine is attached to the sidewalls of the recesses 14, Ru3(CO) 12 Since the adsorption of Ru generated from the gas onto the sidewall is suppressed, the growth of the Ru film 15 from the sidewall of the recess 14 in the lateral direction (the direction perpendicular to the opening direction of the recess) is suppressed. Therefore, the recess 14 is prevented from being closed before the Ru film 15 is sufficiently filled in the recess 14. Therefore, an increase in contact resistance due to a reduction in the volume of the Ru film 15 formed in the recess 14 is more reliably suppressed.

[0068] However, to improve adhesion of the Ru film 15 to the wall surface of the recess 14, a process for removing chlorine from the recess 14 may be performed before the Ru film 15 is filled. Specifically, after the process of step S4 for removing the Ti film 23 is performed in the fourth process module 54, H gas is supplied into the process container 61 of the process module 54 and the H gas is converted into plasma. When the wafer A is exposed to the plasma, chlorine adhering to the wall surface of the recess 14 becomes HCl, which is vaporized and removed. Thereafter, the wafer A is transferred to the fifth process module 55, as described above, and the Ru film 15 is filled.

[0069] The processing steps illustrated in FIGS. 1 to 6 have been described as steps for manufacturing an NMOS. However, for example, a PMOS may be manufactured in parallel with the NMOS. In that case, the processing steps illustrated in FIGS. 1 to 6 are performed on the portion of wafer A that will form the PMOS. Therefore, this technology is not limited to the manufacturing of an NMOS. Also, although FIGS. 1 to 6 show the semiconductor layer forming the bottom wall of recess 14 as being an Si layer 11, it may be a semiconductor layer containing Si other than Si layer 11, such as an SiGe (silicon germanium) layer, and ZrSi layer 21 may be formed on the semiconductor layer other than Si layer 11. Incidentally, "containing Si" here means that Si is included as a constituent component, not that Si is included as an impurity.

[0070] Instead of supplying TiCl4 gas in step S2, for example, a gas such as MoCl5 (molybdenum chloride) or WCl5 (tungsten chloride) may be supplied to remove the Zr film 22, and instead of Ti, Mo or W remaining on the sidewall of the recess 14 may be removed in step S3. In this way, the second process gas supplied to the wafer A in step S2 may be a metal chloride gas other than TiCl4 gas. The second metal, which is a metal other than Zr, contained in the second process gas is not limited to Ti.

[0071] Alternatively, after step S1, HCl (hydrogen chloride) gas may be supplied to wafer A as a second process gas to remove the Zr film 22, and then the recesses 14 may be filled with a Ru film 15 in step S4. Therefore, after the Zr film 22 is formed and before the Ru film 15 is filled, the second process gas (e.g., TiCl4 gas) and the third process gas (e.g., BCl3 gas and HF gas) may not be supplied. While supplying HCl gas in this manner can remove the Zr film 22, the ZrSi layer 21 is also etched relatively significantly, as shown in the evaluation test described below. Therefore, to suppress etching of the ZrSi layer 21 and ensure a lower contact resistance, it is preferable to supply the respective gases to form and remove the Ti film 22 as described with reference to FIGS. 2 and 3.

[0072] In step S3, BCl3 gas and HF gas are alternately supplied to wafer A, but they may also be supplied simultaneously to wafer A. Furthermore, the conductive film embedded in recess 14 in step S4 is preferably a Ru film 15 to reduce wiring resistance, but may also be another metal film, specifically, a W film or a Mo film, for example. Furthermore, by adjusting the processing conditions for steps S1 to S4, the process described as a plasma process may be performed as a non-plasma process, and the process described as a non-plasma process may be performed as a plasma process.

[0073] It should be noted that the embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects, and the above-described embodiments may be omitted, substituted, modified, and / or combined in various forms without departing from the scope and spirit of the appended claims.

[0074] <Evaluation Test> The evaluation tests related to this technology are described below.

[0075] Evaluation Test 1 For evaluation test 1, multiple substrates were prepared, and a Zr film was formed on the Si layer constituting each substrate. A different etching gas was supplied to each substrate, and the thickness of the Zr film remaining on the substrate was measured. Since the Zr film reacts with the Si layer to form a ZrSi film by heating the substrate during Zr film formation, measuring the thickness of this Zr film corresponds to measuring the thickness of a ZrSi film. Within evaluation test 1, the test in which etching was performed by supplying TiCl4 gas and the test in which etching was performed by supplying HCl gas are designated evaluation tests 1-1 and 1-2, respectively. In each of evaluation tests 1-1 and 1-2, the supply time (etching time) of the etching gas was set to a different time for each substrate.

[0076] Evaluation Test 2 For Evaluation Test 2, multiple substrates were prepared, and a Zr film was formed on the SiO2 layer formed on each substrate. A different etching gas was then supplied to each substrate, and the thickness of the Zr film remaining on the substrate was measured. Of Evaluation Test 2, the test in which etching was performed by supplying TiCl4 gas, the test in which etching was performed by supplying HCl gas, and the test in which etching was performed by supplying ZrCl4 gas are designated Evaluation Tests 2-1, 2-2, and 2-3, respectively. For Evaluation Tests 2-1, 2-2, and 2-3, different etching times were set for each substrate.

[0077] The graphs in Figures 13 and 14 show the results of Evaluation Tests 1 and 2, respectively. As shown in Figure 13, in Evaluation Test 1-2, which used HCl gas as the etching gas, the thickness of the Zr film decreased as the etching time increased. However, in Evaluation Test 1-1, which used TiCl4 gas as the etching gas, the change in the Zr film thickness was suppressed even when the etching time was relatively long, and the Zr film thickness was larger than in Evaluation Test 1-1, except when the etching time was 0 seconds.

[0078] 14, in Evaluation Test 2-3, which used ZrCl4 gas as the etching gas, the change in the thickness of the Zr film due to the supply of etching gas is small. Therefore, it can be seen that when step S1 described in the embodiment is performed, the thickness of the Zr film 22 formed on the side wall of the recess 14 is prevented from becoming excessively thick. In Evaluation Tests 2-1 and 2-2, which used TiCl4 gas and HCl gas as the etching gas, the thickness of the Zr film relative to the etching time is significantly reduced compared to Evaluation Test 2-3.

[0079] Therefore, evaluation test 2 showed that a non-silicided Zr film can be etched at a relatively high etching rate with TiCl4 gas or HCl gas. As described in the embodiment, in step S1 for forming the ZrSi layer 21, a Zr film 22 is also formed on the SiN film 16 forming the sidewall of the recess 14. That is, a non-silicided Zr film 22 is formed, but the results of evaluation test 2 show that such a Zr film 22 can be removed by supplying TiCl4 gas.

[0080] The results of the above evaluation tests 1 and 2 show that supplying TiCl gas in step S2 described in the embodiment makes it possible to etch the Zr film 22 while suppressing etching of the ZrSi layer 21 formed in step S1. In addition, in tests conducted separately from evaluation tests 1 and 2, images of the vertical cross section of the recess 14 were obtained after performing step S1 and before performing step S2, and after performing step S2 and before performing step S3. These images confirm that performing step S2 removed the Zr film 22 that was present on the SiN film 13 after performing step S1.

[0081] Evaluation Test 3 For evaluation test 3, multiple substrates were prepared and a Ti film was formed on each substrate. A cycle consisting of supplying BCl3 gas and HF gas to each substrate was repeated to etch the Ti film, and the amount of etching was measured. The combination of the substrate processing temperature during this cycle and the number of cycle repetitions was changed for each substrate. The substrate temperature was set to 250°C, 300°C, or 350°C.

[0082] FIG. 15 is a graph showing the results of Evaluation Test 3. The graph shows the measurement results of the etching amount, as well as an approximation line calculated from the measurement results at the same processing temperature. Note that the approximation line for the processing temperature of 250°C is calculated from the measurement results shown in the graph and the measurement results that are hidden because they are located outside the graph. As shown in the graph, the Ti film was etched at all processing temperatures of 250°C, 300°C, and 350°C, and the etching amount of the Ti film increased with the number of cycles. Furthermore, the etching amount increased with the substrate temperature. The results of Evaluation Test 3 demonstrated that the Ti film 23 formed by step S2 described in the embodiment can be removed by performing step S3. [Explanation of symbols]

[0083] A wafer 11 Silicon (Si) layer 12 Silicon oxide (SiO2) layer 13 Silicon nitride (SiN) film 14 Recess 15 Ruthenium (Ru) film 15

Claims

1. supplying a first process gas containing zirconium to a substrate having a recess in which a semiconductor layer containing silicon is exposed at the bottom surface and whose sidewall is formed by an insulating film, to form a zirconium silicide layer that forms the bottom wall of the recess; supplying a second process gas to the substrate to remove zirconium remaining on the sidewall of the recess; a film formation step of supplying a film formation gas to the substrate on which the removing step has been performed to form a conductive film in the recess; A substrate processing method comprising:

2. the second process gas is a gas containing a second metal other than zirconium, 2. The substrate processing method according to claim 1, further comprising the step of supplying a third process gas to the substrate to remove the second metal remaining on the sidewall of the recess, the step being performed after the step of removing the zirconium and before the step of forming the film.

3. the second metal is titanium, tungsten, or molybdenum; 3. The substrate processing method according to claim 2, wherein the second processing gas is a gas of a chloride of the second metal.

4. 3. The substrate processing method according to claim 2, wherein the third processing gas is a mixture of boron trichloride gas and hydrogen fluoride gas.

5. the first process gas, the second process gas, and the third process gas are chloride gases; 3. The substrate processing method according to claim 2, further comprising the step of exposing the substrate to hydrogen gas plasma in order to remove chlorine from within the recess before the film forming step.

6. a processing module including a processing vessel in which a stage for placing a substrate thereon is provided to perform gas processing on the substrate having a recessed portion with a sidewall formed by an insulating film; a first process gas supply unit that supplies a first process gas containing zirconium into the process vessel in which the substrate, the semiconductor layer containing silicon being exposed at the bottom surface of the recess, is stored, to form a zirconium silicide layer that forms the bottom wall of the recess; a second process gas supply unit that supplies a second process gas into the process vessel to remove zirconium remaining on a sidewall of the recess of the substrate; a film formation gas supply unit that supplies a film formation gas into the processing chamber to form a conductive film in the recessed portion of the substrate after the second processing gas is supplied; A substrate processing apparatus comprising:

7. A plurality of the processing modules are provided, a substrate transport path is provided, the substrate transport path including a transport mechanism that connects the processing modules and transports the substrate between the processing modules; 7. The substrate processing apparatus according to claim 6, wherein the first process gas supply unit, the second process gas supply unit, and the film forming gas supply unit are provided in any one of the plurality of process modules.

8. the second process gas is a gas containing a second metal other than zirconium, 8. A substrate processing apparatus according to claim 7, wherein a third processing gas supply unit is provided in any of the processing modules to supply a third processing gas into the processing vessel in which the substrate is stored after the second processing gas has been supplied and before the film forming gas is supplied, thereby removing the second metal remaining on the side wall of the recess.

9. The transport path is evacuated to reduce the pressure in the transport path to 1×10 －７ an exhaust mechanism for setting a first pressure lower than Torr; an inert gas supply mechanism for supplying an inert gas to the transfer path, which is set at the first pressure, to increase the pressure to a second pressure; a control unit that outputs a control signal so that the substrate is transported between the processing modules by the transport mechanism while the transport path is maintained at the second pressure and the interior of each processing vessel is maintained at a pressure lower than the second pressure; The substrate processing apparatus according to claim 7 , further comprising:

10. the stage includes a heating mechanism for heating the substrate; Among the plurality of processing modules, a processing module provided with the first processing gas supply unit and the second processing gas supply unit, a processing module provided with the third processing gas supply unit, and a processing module provided with the film forming gas supply unit are individually provided processing modules, 8. The substrate processing apparatus according to claim 7, wherein the substrate is heated by each of the heating mechanisms to temperatures different from each other.

Images