Semiconductor device and method of manufacturing the same

Abstract

To improve the performance of a semiconductor device which performs electrical non-contact signal transmission.SOLUTION: A first pattern overlapping with the n-type semiconductor region NR1 in plan view and formed above the substrate SB, and a second pattern overlapping with the first pattern in plan view and magnetically or capacitively coupled to the first pattern, the first pattern and the second pattern being formed on the substrate SB, the substrate SB including a p-type semiconductor region and an n-type semiconductor region NR1 disposed on the p-type semiconductor region; SELECTED DRAWING: Figure 28

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device that enables signal transmission between different potentials by utilizing a pair of inductors that are inductively coupled to each other, and a technology that is effective when applied to a manufacturing method thereof. [Background technology]

[0002] International Publication No. 2014 / 097425 (Patent Document 1) describes a technique for suppressing dielectric breakdown in a digital isolator. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2014 / 097425 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, there is a transformer that enables electrical contactless signal transmission using a pair of inductors that are inductively coupled to each other. This transformer enables electrical contactless signal transmission, which prevents electrical noise from one circuit from adversely affecting the other circuit. Furthermore, there is a demand for a transformer configured in this way to further reduce crosstalk noise.

[0005] The number of transformers mounted on a semiconductor chip varies depending on the product's application. However, cutting semiconductor chips with a given number of transformers from a single semiconductor wafer results in excess chips, which reduces production efficiency.

[0006] The above-described problem can also occur when signal transmission is performed in a non-contact electrical state and when capacitively coupled capacitors are used instead of the transformer.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] A brief summary of a representative embodiment of the present invention will be given below.

[0009] One embodiment of the semiconductor device comprises a semiconductor substrate having a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type different from the first conductivity type arranged on the first semiconductor region, a first pattern that overlaps the second semiconductor region in a planar view and is formed above the semiconductor substrate, and a second pattern that overlaps the first pattern in a planar view and is magnetically or capacitively coupled to the first pattern.

[0010] A method for manufacturing a semiconductor device according to one embodiment includes the steps of: preparing a lot including a first semiconductor wafer and a second semiconductor wafer; forming a plurality of patterns arranged in a matrix in a planar view above each of the first semiconductor wafer and the second semiconductor wafer; cutting the first semiconductor wafer to obtain a first semiconductor chip having n patterns; and cutting the second semiconductor wafer to obtain a second semiconductor chip having m patterns, wherein each of the plurality of patterns includes an upper pattern and a lower pattern that overlap each other in a planar view and are magnetically or capacitively coupled to each other, and a conductor pattern that surrounds the upper pattern and the lower pattern in a planar view.

[0011] A method for manufacturing a semiconductor device according to one embodiment includes the steps of forming a plurality of patterns arranged in a matrix in a plan view above a semiconductor wafer, and cutting the semiconductor wafer along a main surface of the semiconductor wafer to obtain a first semiconductor chip having n patterns and a second semiconductor chip having m patterns, wherein each of the plurality of patterns includes an upper pattern and a lower pattern that overlap each other in a plan view and are magnetically or capacitively coupled to each other, and a conductor pattern that surrounds the upper pattern and the lower pattern in a plan view. [Effects of the Invention]

[0012] According to one embodiment disclosed in the present application, the performance of a semiconductor device can be improved.

[0013] Furthermore, according to one embodiment disclosed in the present application, it is possible to improve the production efficiency of semiconductor devices. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 2 is a diagram illustrating an example of the configuration of a drive control unit that drives a load circuit. [Figure 2] FIG. 10 is an explanatory diagram showing an example of signal transmission. [Figure 3] 1 is a diagram showing a three-chip configuration including a semiconductor device according to a first embodiment. [Figure 4] 1 is a diagram showing a three-chip configuration including a semiconductor device according to a first embodiment. [Figure 5] 1 is a diagram showing a three-chip configuration including a semiconductor device according to a first embodiment. [Figure 6] 1 is a planar layout showing a semiconductor chip according to a first embodiment. [Figure 7] FIG. 7 is a cross-sectional view of the semiconductor chip taken along line AA in FIG. 6. [Figure 8] FIG. 2 is a plan view of the semiconductor device according to the first embodiment during the manufacturing process. [Figure 9] 1 is a cross-sectional view of the semiconductor device according to the first embodiment during the manufacturing process. [Figure 10]FIG. 10 is a cross-sectional view of the semiconductor device during the manufacturing process, continuing from FIG. [Figure 11] 11 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 10. [Figure 12] 12 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 11. [Figure 13] 13 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 12. [Figure 14] 14 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 13. [Figure 15] FIG. 15 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. [Figure 16] 15 is a plan view of the semiconductor device during the manufacturing process, continuing from FIG. 14. FIG. [Figure 17] FIG. 17 is a plan view of the semiconductor device during the manufacturing process, continuing from FIG. [Figure 18] 1 is a schematic diagram showing a semiconductor package using the semiconductor device according to the first embodiment. [Figure 19] FIG. 10 is a perspective view showing a lot including a plurality of semiconductor wafers according to a modification of the first embodiment. [Figure 20] FIG. 10 is a plan view of a semiconductor device according to a modification of the first embodiment during a manufacturing process. [Figure 21] 10 is a planar layout showing a semiconductor chip according to a second embodiment. [Figure 22] 22 is a cross-sectional view of the semiconductor chip taken along line BB in FIG. 21. [Figure 23] FIG. 10 is a plan view of a semiconductor device according to a second embodiment during a manufacturing process. [Figure 24] FIG. 10 is a cross-sectional view of a semiconductor device according to a modification of the second embodiment during a manufacturing process. [Figure 25] FIG. 25 is a cross-sectional view of the semiconductor device during the manufacturing process following FIG. 24. [Figure 26] FIG. 10 is a cross-sectional view of a semiconductor device according to a modification of the second embodiment during a manufacturing process. [Figure 27] FIG. 10 is a cross-sectional view of a semiconductor device according to a modification of the second embodiment during a manufacturing process. [Figure 28] FIG. 10 is a cross-sectional view showing a semiconductor device according to a third embodiment. [Figure 29] FIG. 11 is a cross-sectional view showing a semiconductor device according to a modification of the third embodiment. [Figure 30] 10 is a planar layout showing a semiconductor device according to a fourth embodiment. [Figure 31] 31 is a cross-sectional view of the semiconductor chip taken along line CC in FIG. 30. [Figure 32] 10A and 10B are cross-sectional views of a semiconductor device according to a fourth embodiment during a manufacturing process. [Figure 33] FIG. 10 is a plan view of a semiconductor device according to a fourth embodiment during a manufacturing process. [Figure 34] 1 is a planar layout showing a semiconductor device according to a first comparative example. [Figure 35] 10 is a planar layout showing a semiconductor device according to Comparative Example 2. [Figure 36] FIG. 10 is a cross-sectional view showing a semiconductor device according to Comparative Example 3. DETAILED DESCRIPTION OF THE INVENTION

[0015] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the mentioned number, and may be more or less than the mentioned number, unless otherwise specified or when it is clearly limited in principle to a specific number.

[0016] Furthermore, in the following embodiments, the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numerical values ​​and ranges.

[0017] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0018] (Embodiment 1) <Circuit configuration> Fig. 1 is a diagram showing an example of the configuration of a drive control unit (e.g., an inverter system) that drives a load circuit such as a motor. As shown in Fig. 1, the drive control unit has a control circuit CC, transformers TR1 and TR2, a drive circuit DR, and an inverter INV, and is electrically connected to a load circuit LOD.

[0019] The transmitter circuit TX1 and receiver circuit RX1 transmit control signals output from a control circuit (microcontroller) CC to a drive circuit (driver) DR. Meanwhile, the transmitter circuit TX2 and receiver circuit RX2 transmit signals output from the drive circuit DR to the control circuit CC. The control circuit CC controls the drive circuit DR. The drive circuit DR operates an inverter INV that controls a load circuit LOD based on the control from the control circuit CC.

[0020] The control circuit CC is supplied with a power supply potential VCC1 and is grounded to a ground potential GND1. On the other hand, the inverter INV is supplied with a power supply potential VCC2 and is grounded to a ground potential GND2. In this case, for example, the power supply potential VCC1 is smaller than the power supply potential VCC2 supplied to the inverter INV.

[0021] A transformer TR1 is interposed between the transmitter circuit TX1 and the receiver circuit RX1. The transformer TR1 consists of coils (inductors) CL1a and CL1b, which are inductively coupled (magnetically coupled) to each other. This allows signals to be transmitted from the transmitter circuit TX1 to the receiver circuit RX1 via the transformer TR1. As a result, the driver circuit DR receives a control signal output from the control circuit CC via the transformer TR1. The coils CL1a and CL1b are electrically insulated.

[0022] In this way, the transformer TR1 transmits the control signal from the control circuit CC to the drive circuit DR while suppressing the transmission of electrical noise from the control circuit CC to the drive circuit DR, thereby suppressing malfunction of the drive circuit DR due to the superposition of electrical noise on the control signal, thereby improving the operational reliability of the semiconductor device.

[0023] The coils CL1a and CL1b each function as an inductor, and the transformer TR1 functions as a magnetically coupled element made up of the coils CL1a and CL1b that are inductively coupled to each other.

[0024] Similarly, a transformer TR2 is interposed between the transmitter circuit TX2 and the receiver circuit RX2. The transformer TR2 consists of coils CL2b and CL2a, which are inductively coupled to each other. This allows signals to be transmitted from the transmitter circuit TX2 to the receiver circuit RX2 via the transformer TR2. As a result, the control circuit CC receives the signal output from the driver circuit DR via the transformer TR2.

[0025] In this way, the transformer TR2 transmits signals from the drive circuit DR to the control circuit CC while suppressing the transmission of electrical noise from the drive circuit DR to the control circuit CC, thereby suppressing malfunction of the control circuit CC due to the superposition of electrical noise on the signals, thereby improving the operational reliability of the semiconductor device.

[0026] The transformer TR1 is composed of coils CL1a and CL1b. Coils CL1a and CL1b are not connected by a conductor but are magnetically coupled. Therefore, when current flows through coil CL1a, an induced electromotive force is generated in coil CL1b in response to changes in the current, resulting in an induced current. In this case, coil CL1a is the primary coil, and coil CL1b is the secondary coil. In this way, the transformer TR1 utilizes the electromagnetic induction phenomenon that occurs between coils CL1a and CL1b. That is, when the transmitter circuit TX1 sends a signal to coil CL1a of the transformer TR1, causing a current to flow, the receiver circuit RX1 detects the induced current generated in coil CL1b of the transformer TR1. This allows the receiver circuit RX1 to receive a signal corresponding to the control signal output from the transmitter circuit TX1.

[0027] Similarly, transformer TR2 is composed of coils CL2a and CL2b, which are magnetically coupled rather than connected by a conductor. Therefore, when current flows through coil CL2b, an induced electromotive force is generated in coil CL2a in response to changes in the current, resulting in an induced current. Thus, the transmitter circuit TX2 sends a signal to coil CL2b of transformer TR2, causing a current to flow. The receiver circuit RX2 detects the induced current in coil CL2a of transformer TR2. This allows the receiver circuit RX2 to receive a signal corresponding to the control signal output from the transmitter circuit TX2.

[0028] Signals are transmitted and received between the control circuit CC and the driver circuit DR via a path from the transmitter circuit TX1 to the receiver circuit RX1 via the transformer TR1 and a path from the transmitter circuit TX2 to the receiver circuit RX2 via the transformer TR2. Specifically, signals are transmitted and received between the control circuit CC and the driver circuit DR by the receiver circuit RX1 receiving the signal transmitted by the transmitter circuit TX1 and the receiver circuit RX2 receiving the signal transmitted by the transmitter circuit TX2. As described above, signals are transmitted from the transmitter circuit TX1 to the receiver circuit RX1 via the transformer TR1, while signals are transmitted from the transmitter circuit TX2 to the receiver circuit RX2 via the transformer TR2. This allows the driver circuit DR to drive the inverter INV to operate the load circuit LOD in response to the signal transmitted from the control circuit CC. Each of these paths is called a channel. The driver control unit shown in FIG. 1 has two channels.

[0029] The voltage level of the reference potential of the control circuit CC and the voltage level of the reference potential of the drive circuit DR are different from each other. That is, the reference potential of the control circuit CC is fixed to the ground potential GND1, while the drive circuit DR is electrically connected to the inverter INV as shown in FIG. 1. The inverter INV includes, for example, a high-side IGBT (insulated gate bipolar transistor) and a low-side IGBT. The inverter INV controls the on / off of the high-side IGBT and the low-side IGBT using the drive circuit DR, thereby controlling the load circuit LOD by the inverter INV. Specifically, the on / off control of the high-side IGBT is achieved by controlling the potential applied by the drive circuit DR to the gate electrode of the high-side IGBT. Similarly, the on / off control of the low-side IGBT is achieved by controlling the potential applied by the drive circuit DR to the gate electrode of the low-side IGBT.

[0030] Here, for example, the on-control of the low-side IGBT is realized by applying "emitter potential (0V) + threshold voltage (15V)" to the gate electrode, with the emitter potential (0V) of the low-side IGBT connected to ground potential GND2 as a reference. On the other hand, for example, the off-control of the low-side IGBT is realized by applying "emitter potential (0V)" to the gate electrode, with the emitter potential (0V) of the low-side IGBT connected to ground potential GND2 as a reference. Therefore, the on / off control of the low-side IGBT is performed by whether or not to apply the threshold voltage (15V) to the gate electrode, with 0V as the reference potential.

[0031] On the other hand, for example, the on-control of the high-side IGBT is performed by applying a "reference potential plus threshold voltage (15 V)" to the gate electrode with respect to the emitter potential of the high-side IGBT as a reference potential. However, the emitter potential of the high-side IGBT is not fixed to the ground potential GND2 like the emitter potential of the low-side IGBT. That is, in the inverter INV, the high-side IGBT and the low-side IGBT are connected in series between the power supply potential VCC2 and the ground potential GND2. When the high-side IGBT is turned on, the inverter INV turns off the low-side IGBT, and when the high-side IGBT is turned off, the low-side IGBT is turned on. Therefore, when the high-side IGBT is off, the low-side IGBT is on, and the emitter potential of the high-side IGBT is set to the ground potential GND2 by the on-state low-side IGBT. On the other hand, when the high-side IGBT is on, the low-side IGBT is off, so the emitter potential of the high-side IGBT is the power supply potential VCC2. At this time, the on / off control of the high-side IGBT is performed by applying or not applying "reference potential + threshold voltage (15V)" to the gate electrode, with the emitter potential of the high-side IGBT as the reference potential.

[0032] As described above, the emitter potential of the high-side IGBT varies depending on whether the high-side IGBT is on or off. That is, the emitter potential of the high-side IGBT varies from the ground potential GND2 (0 V) to the power supply potential VCC2 (e.g., 800 V). Therefore, to turn on the high-side IGBT, the emitter potential of the high-side IGBT is used as the reference potential, and a "reference potential (800 V) + threshold voltage (15 V)" must be applied to the gate electrode. Therefore, the driver circuit DR, which controls the on / off of the high-side IGBT, must grasp the emitter potential of the high-side IGBT. Therefore, the driver circuit DR is configured to input the emitter potential of the high-side IGBT. As a result, a reference potential of 800 V is input to the driver circuit DR, and the driver circuit DR controls the high-side IGBT to be on by applying a threshold voltage (15 V) to the gate electrode of the high-side IGBT relative to this 800 V reference potential. Therefore, a high potential of about 800 V is applied to the drive circuit DR.

[0033] In this way, the drive control unit has a control circuit CC that handles low potentials (tens of volts) and a drive circuit DR that handles high potentials (hundreds of volts). In other words, the control circuit CC is driven at a predetermined voltage, while the drive circuit DR is driven at a different voltage. For this reason, signal transmission between the control circuit CC and the drive circuit DR must be performed between circuits driven at different potentials.

[0034] In this regard, since signals are transmitted between the control circuit CC and the drive circuit DR via the transformers TR1 and TR2, signals can be transmitted between circuits driven at different potentials.

[0035] As described above, a large potential difference may occur between the primary and secondary coils of the transformers TR1 and TR2. Conversely, because a large potential difference may occur, the primary and secondary coils are magnetically coupled, not connected by a conductor, and are used for signal transmission. Therefore, when forming the transformer TR1, it is important to maximize the dielectric strength between the coils CL1a and CL1b in order to improve the operational reliability of the semiconductor device. Similarly, when forming the transformer TR2, it is important to maximize the dielectric strength between the coils CL2b and CL2a in order to improve the operational reliability of the semiconductor device.

[0036] <Signal transmission example> FIG. 2 is an explanatory diagram showing an example of signal transmission. In FIG. 2, a transmitter circuit TX1 extracts the edge portion of a square-wave signal SG1 input to the transmitter circuit TX1 to generate a signal SG2 with a constant pulse width and sends the signal SG2 to the coil CL1a (primary coil) of a transformer TR1. When a current due to this signal SG2 flows through the coil CL1a (primary coil) of the transformer TR1, a corresponding signal SG3 flows through the coil CL1b (secondary coil) of the transformer TR1 due to induced electromotive force. This signal SG3 is amplified by a receiver circuit RX1 and further modulated into a square wave, thereby outputting a square-wave signal SG4 from the receiver circuit RX1. This allows the receiver circuit RX1 to output a signal SG4 corresponding to the signal SG1 input to the transmitter circuit TX1. In this manner, a signal can be transmitted from the transmitter circuit TX1 to the receiver circuit RX1. Signals can also be transmitted from the transmitter circuit TX2 to the receiver circuit RX2 in a similar manner.

[0037] <3-chip configuration> The following describes how the transmission / reception circuit section of the drive control section is configured using three semiconductor chips.

[0038] Fig. 3 is a diagram showing a three-chip configuration. In Fig. 3, a transmitter circuit TX1 and a receiver circuit RX2 are formed in a primary-side semiconductor chip CHP1b. A driver circuit DR, a receiver circuit RX1, and a transmitter circuit TX2 are formed in a secondary-side semiconductor chip CHP2b. Meanwhile, a transformer TR1 and a transformer TR2 are formed in a semiconductor chip CHP3b.

[0039] As a result, in a three-chip configuration, even if the design of the semiconductor chip CHP1b or the semiconductor chip CHP2b is changed, the semiconductor chip CHP3b can be used without changing its design. Therefore, a three-chip configuration increases the variety of usable semiconductor chips CHP1b and CHP2b. In other words, the versatility of the semiconductor chip CHP3b having the transformers TR1 and TR2 is enhanced. Furthermore, because the semiconductor chip CHP3b having the transformers TR1 and TR2 does not include transistors, it can be formed using only a wiring process, thereby simplifying the manufacturing process. Therefore, a three-chip configuration enables reduction in manufacturing costs, thereby enabling the manufacture of highly competitive products.

[0040] The semiconductor chips CHP1b, CHP2b, and CHP3b are sealed together with molding resin and manufactured as a single semiconductor package (chip). The semiconductor chip CHP3b, which includes the transformers TR1 and TR2, is called a transformer chip. The drive control unit has, for example, six transformers between the control circuit CC and the drive circuit DR. In other words, two more sets of the semiconductor chips CHP1b, CHP2b, and CHP3b shown in FIG. 3 are connected between the control circuit CC and the drive circuit DR.

[0041] 3 has two signal transmission / reception paths: one from the transmitter circuit TX1 to the receiver circuit RX1 via the transformer TR1, and the other from the transmitter circuit TX2 to the receiver circuit RX2 via the transformer TR2. This drive control unit has two channels between the control circuit CC (primary side) and the drive circuit DR (secondary side).

[0042] <Other 3-chip configuration examples> 3 shows a configuration using a transformer chip with two transformers. However, the configuration is not limited to this, and the transformer chip may have one or three transformers. Note that the driver circuit DR is omitted from the semiconductor chips CHP2a and CHP2c shown in the following FIGS. 4 and 5, respectively.

[0043] Figure 4 shows a three-chip configuration in which the number of transformers formed on the transformer chip is one. Here, a transmitter circuit TX1 is formed on the semiconductor chip CHP1a, a transformer TR1 is formed on the semiconductor chip CHP3a, and a receiver circuit RX1 is formed on the semiconductor chip CHP2a. In a chip consisting of the semiconductor chips CHP1a, CHP2a, and CHP3a, signals are transmitted and received along a path from the transmitter circuit TX1 to the receiver circuit RX1 via the transformer TR1. In other words, the drive control unit shown in Figure 4 has one channel that transmits signals from the primary side to the secondary side.

[0044] FIG. 5 shows a three-chip configuration in which the number of transformers formed on the transformer chip is three. Here, the semiconductor chip CHP1c is formed with a transmitter circuit TX1, a transmitter circuit TX3, a receiver circuit RX4, and a receiver circuit RX2. The semiconductor chip CHP3c is formed with a transformer TR1, a transformer TR3, and a transformer TR2. Like the transformer TR1, the transformer TR3 has a primary coil and a secondary coil. The semiconductor chip CHP2c is formed with a receiver circuit RX1, a receiver circuit RX3, a transmitter circuit TX4, and a transmitter circuit TX2. In a chip consisting of the semiconductor chips CHP1c, CHP2c, and CHP3c, signals are transmitted and received via four paths. Two of the four paths are from the transmitter circuit TX1 to the receiver circuit RX1 via the transformer TR1, and from the transmitter circuit TX2 to the receiver circuit RX2 via the transformer TR2. The other two paths are a path from the transmitter circuit TX3 to the receiver circuit RX3 via the transformer TR3, and a path from the transmitter circuit TX4 to the receiver circuit RX4 via the transformer TR3. In other words, two of the four paths perform bidirectional transmission and reception using one channel via one transformer TR3. In other words, the drive control unit shown in Figure 5 has a total of three channels: a channel for transmitting signals from the primary side to the secondary side, a channel for transmitting signals from the secondary side to the primary side, and a channel for transmitting signals bidirectionally between the primary side and the secondary side.

[0045] Here, in a drive control unit that transmits and receives signals via four paths, the manufacturing cost of the semiconductor device is reduced by forming three transformers on the transformer chip. This configuration is not limited to this, and four transformers may be formed on the transformer chip to match the number of four signal paths. As described above, the number of transformers formed on the transformer chip varies depending on the application of the drive control unit. The number of transformers formed on the transformer chip is not limited to the above-mentioned one to four, but may be five or more.

[0046] <Structure of semiconductor device> The following describes a three-chip configuration, and describes the configuration of the semiconductor chip (transformer chip) CHP3b, which is the semiconductor device of embodiment 1. Here, the configuration of the transformer chip having two transformers will be described, similarly to FIG.

[0047] Fig. 6 is a plan view showing the semiconductor chip CHP3b according to the first embodiment. In Fig. 6, the conductor patterns on the multilayer wiring layer formed in the semiconductor chip CHP3b are shown with hatching, and the insulating film included in the multilayer wiring layer is shown in the area other than the conductor patterns. In Fig. 6, the multilayer wiring layer and the protective film formed above the conductor patterns are omitted from the illustration.

[0048] As shown in FIG. 6, the semiconductor chip CHP3b has a rectangular planar shape. In plan view, the semiconductor chip CHP3b has two element regions 1A aligned in the Y direction. Since the two element regions 1A have the same structure, the structure of one element region 1A will be described in detail below. The X direction is along the main surface of the semiconductor substrate SB (see FIG. 7) that constitutes the semiconductor chip CHP3b. The Y direction is along the main surface of the semiconductor substrate SB (see FIG. 7) that constitutes the semiconductor chip CHP3b. In plan view, the Y direction is orthogonal to the X direction. In the semiconductor chip CHP3b, the element regions 1A are aligned in the Y direction, and in plan view, the element regions 1A are not aligned in the X direction.

[0049] A conductor pattern (guard ring) W2 is formed on the periphery of the element region 1A. The conductor pattern W2 is made of wiring formed so as to surround the element region 1A in a plan view. The conductor patterns W2 formed in adjacent element regions 1A are spaced apart from each other. Then, in a plan view, the conductor pattern W1 is formed so as to be surrounded by the conductor pattern W2. The conductor pattern W1 is made of wiring formed so as to surround the element region 1A in a plan view. Then, in a plan view, the upper layer inductor (upper layer coil) 100 is formed so as to be surrounded by the conductor pattern W1. In other words, the upper layer inductor 100 is also surrounded by the conductor pattern W2 in a plan view. The conductor patterns W1 formed in adjacent element regions 1A in the semiconductor chip CHP3b are spaced apart from each other.

[0050] The upper layer inductor 100 includes a tap pad 1a, a spiral wiring 1b and a spiral wiring 1d connected to the tap pad 1a, a transformer pad 1c connected to the spiral wiring 1b, and a transformer pad 1e connected to the spiral wiring 1d. The tap pad 1a, the spiral wiring 1b, the spiral wiring 1d, the transformer pad 1c, and the transformer pad 1e are integrated into a single conductor pattern. The upper layer inductor 100 and a lower layer inductor 300 (described later) constitute a transformer TR formed in the element region 1A. The two transformers TR shown in FIG. 6 correspond to the transformers TR1 and TR2 shown in FIG. 3. The upper layer inductor 100 corresponds to the coil CL2a shown in FIG. 3, and the lower layer inductor 300 corresponds to the coil CL2b shown in FIG. 3.

[0051] In a plan view, the spiral wiring 1b extends around the transformer pad 1c, and the spiral wiring 1d extends around the transformer pad 1e. The tap pad 1a is located between the transformer pads 1c and 1e in the Y direction. The tap pad 1a may be located at a position offset in the X direction from the midpoint between the transformer pads 1c and 1e in the Y direction.

[0052] In plan view, the tap pad 3a, the transformer pad 3c, and the transformer pad 3d are formed so as to be surrounded by the conductor pattern W2. The tap pad 3a, the transformer pad 3c, and the transformer pad 3d are arranged in a region surrounded by the conductor pattern W2 in plan view, and in a position different from the region including the conductor pattern W1 and the upper layer inductor 100. However, the conductor pattern W1, the upper layer inductor 100, the tap pad 3a, the transformer pad 3c, and the transformer pad 3d may be included in one region surrounded by the conductor pattern W2.

[0053] The tap pad 3a, the transformer pad 3c, and the transformer pad 3d are connected to the lower layer inductor (see FIG. 7). The lower layer inductor is formed below the upper layer inductor 100. The upper layer inductor 100 and the lower layer inductor directly below the upper layer inductor 100 form a pair. The tap pad 3a, the transformer pad 3c, and the transformer pad 3d are formed in the same layer as the upper layer inductor 100. The conductor pattern W1, the conductor pattern W2, the upper layer inductor 100, the tap pad 3a, the transformer pad 3c, and the transformer pad 3d are formed in the same layer and at the same height from the main surface of the semiconductor substrate SB shown in FIG. 7 in a direction perpendicular to the main surface.

[0054] Here, for example, a reference potential of approximately 800 V is applied to the upper layer inductor 100 electrically connected to the control circuit CC. In contrast, a reference potential of approximately 0 V is applied to the lower layer inductors electrically connected to the drive circuit DR, as well as the tap pad 3a, the transformer pad 3c, and the transformer pad 3d. In other words, a reference potential different from the reference potential applied to the upper layer inductor 100 is applied to the lower layer inductor paired with the upper layer inductor 100. A reference potential of approximately 800 V, for example, is applied to the conductor pattern W1. A reference potential of approximately 0 V, for example, is applied to the conductor pattern W2.

[0055] For this reason, when the drive control unit is operating, a large potential difference occurs between the upper layer inductor 100 and the conductor pattern W2. Therefore, in order to prevent dielectric breakdown between the upper layer inductor 100 and the conductor pattern W2, the upper layer inductor 100 and the conductor pattern W2 are arranged at a distance from each other. In other words, a region 1B where no wiring (conductor pattern) is formed exists between the upper layer inductor 100 and the conductor pattern W2. Region 1B surrounds the periphery of the upper layer inductor 100 in a plan view.

[0056] Next, Fig. 7 is a cross-sectional view of the semiconductor chip taken along line AA in Fig. 6. In Fig. 7, hatching applied to insulating films is omitted for ease of understanding.

[0057] As shown in FIG. 7, the semiconductor chip CHP3b includes a p-type semiconductor substrate SB. In the semiconductor chip CHP3b, a p-type semiconductor region PR is formed at a predetermined depth from the main surface of the semiconductor substrate SB and having a higher impurity concentration than the semiconductor substrate SB. A multilayer wiring layer ML is formed on the p-type semiconductor region PR. The p-type semiconductor region PR is connected to a fixed potential (e.g., ground potential). A conductor pattern W2 is formed as the wiring in the uppermost layer of the multilayer wiring layer ML. That is, the conductor pattern W2 is formed in the multilayer wiring layer ML and includes alternately stacked wirings and conductive connecting portions (contact plugs, vias), and includes a pattern formed on the multilayer wiring layer ML (see FIG. 6). A conductive connecting portion CP constituting the conductor pattern W2 in the multilayer wiring layer ML is connected to the p-type semiconductor region PR.

[0058] Furthermore, a lower layer inductor (lower layer coil) 300 having a spiral wiring 3b is formed in the multilayer wiring layer ML. The spiral wiring 3b is made of a conductor pattern that overlaps with the spiral wiring 1b in a planar view. Furthermore, in an area not shown in FIG. 7, a spiral wiring made of a conductor pattern that overlaps with the spiral wiring 1d (see FIG. 6) in a planar view is formed. The spiral wiring 3b directly below the spiral wiring 1b and the spiral wiring directly below the spiral wiring 1d are connected to each other, thereby forming the lower layer inductor 300. The lower layer inductor 300 and the transformer pad 3c are connected to each other via wiring formed in the multilayer wiring layer ML. In other words, the spiral wiring 3b is electrically connected to the transformer pad 3c formed in the top layer of the multilayer wiring layer ML. The lower layer inductor 300 is electrically connected to the tap pad 3a, the transformer pad 3c, and the transformer pad 3d (see FIG. 6) via wiring formed in the multilayer wiring layer ML.

[0059] Furthermore, an upper layer inductor 100 is formed on the multilayer wiring layer ML. That is, the upper layer inductor 100 is formed above the lower layer inductor 300, and this upper layer inductor 100 has a tap pad 3a, a spiral wiring 1b, a spiral wiring 1d, a transformer pad 1c, and a transformer pad 1e. The upper layer inductor 100 and the lower layer inductor 300 overlap each other in a plan view, are magnetically coupled, and form one transformer TR.

[0060] A surface protective film PAS and a polyimide resin film PI are formed in this order on the multilayer wiring layer ML so as to cover the upper layer inductor 100, the conductor pattern W1, and the conductor pattern W2. The laminated film consisting of the surface protective film PAS and the polyimide resin film PI has a plurality of openings extending from the upper surface of the polyimide resin film PI to the lower surface of the surface protective film PAS, and portions of the surfaces of the transformer pad 3c and the transformer pad 1c are exposed at the bottoms of the openings. The surface protective film PAS is composed of a silicon oxide film and a silicon nitride film.

[0061] 6 and 7 have been described with reference to a case where two element regions 1A are formed on a semiconductor chip (transformer chip), that is, a case where two transformers are formed on a semiconductor chip. In contrast, as shown in Fig. 4, when only one transformer is formed on a semiconductor chip, only one element region 1A shown in Fig. 6 is formed on the semiconductor chip. Furthermore, as shown in Fig. 5, when three transformers are formed on a semiconductor chip, three element regions 1A shown in Fig. 6 are formed side by side in the Y direction on one semiconductor chip.

[0062] <Method of manufacturing a semiconductor device> A method for manufacturing the semiconductor device of the first embodiment will be described below with reference to Fig. 8 to Fig. 17. Fig. 8, Fig. 16, and Fig. 17 are plan views of the semiconductor device of the first embodiment during the manufacturing process. Fig. 9 to Fig. 15 are cross-sectional views of the semiconductor device of the first embodiment during the manufacturing process.

[0063] First, as shown in Figures 8 and 9, a p-type semiconductor substrate SB (semiconductor wafer WF) is prepared, which has a main surface (upper surface) and a back surface (lower surface) opposite the main surface. The semiconductor wafer WF has a substantially circular planar shape and a notch NT at one edge. On the main surface of the semiconductor wafer WF, multiple element regions 1A are arranged in rows and columns in the X and Y directions.

[0064] 10, p-type impurities are introduced into the semiconductor substrate SB by, for example, ion implantation, thereby forming a p-type semiconductor region PR having a predetermined depth from the main surface of the semiconductor substrate SB in the semiconductor substrate SB.

[0065] Next, as shown in FIG. 11, an insulating film IF1 is formed on the main surface of the semiconductor substrate SB. The insulating film IF1 is made mainly of, for example, silicon oxide and is formed by, for example, a CVD (Chemical Vapor Deposition) method. Next, an opening penetrating the insulating film IF1 is formed using photolithography and etching. Next, a conductive connection portion (contact plug) CP is formed to fill the opening of the insulating film IF1. The conductive connection portion CP is formed by, for example, forming a conductive film to fill the opening using a sputtering method, and then removing the conductive film on the insulating film IF1, with the conductive film remaining in the opening.

[0066] 12, a plurality of wirings M1 are formed on the insulating film IF1 and the conductive connecting portion CP. The plurality of wirings M1 can be formed, for example, by forming a conductive film using a sputtering method, and then patterning the conductive film using a photolithography technique and an etching method. The plurality of wirings M1 are made of, for example, aluminum (Al).

[0067] Next, as shown in Fig. 13, the conductive connection portion forming process described with reference to Fig. 11 and the wiring formation process described with reference to Fig. 12 are repeated. As a result, a multilayer wiring layer ML including a plurality of insulating films, a plurality of conductive connection portions, and a plurality of wirings is formed on the semiconductor substrate SB. Note that Fig. 13 shows the stacked insulating films as an integrated unit. A lower layer inductor 300 including the spiral wiring 3b described with reference to Fig. 7 is formed in the multilayer wiring layer ML.

[0068] Next, as shown in Figure 14, conductor patterns W1, W2, upper layer inductor 100, tap pad 3a, transformer pad 3c, and transformer pad 3d (see Figure 6) are formed on the multilayer wiring layer ML. These conductor patterns can be formed, for example, by forming a conductive film on the multilayer wiring layer using a sputtering method, and then patterning the conductive film using photolithography and etching. This forms a transformer TR consisting of the upper layer inductor 100 and the lower layer inductor 300.

[0069] Next, as shown in FIG. 15, a surface protective film PAS and a polyimide resin film PI are sequentially formed on the multilayer wiring layer ML so as to cover the conductor pattern W1, the conductor pattern W2, the upper layer inductor 100, the tap pad 3a, the transformer pad 3c, and the transformer pad 3d (see FIG. 6). The surface protective film PAS can be formed, for example, by a CVD method. The polyimide resin film PI can be formed, for example, by applying a polyimide resin onto the surface protective film PAS. Next, using photolithography and etching, openings are formed through the surface protective film PAS and the polyimide resin film PI to expose the tap pad 1a, the transformer pad 1c, the transformer pad 1e, the tap pad 3a, the transformer pad 3c, and the transformer pad 3d (see FIG. 6).

[0070] 16, a transformer TR made up of an upper layer inductor 100 and a lower layer inductor 300 is formed in each of the element regions 1A arranged in a matrix on the semiconductor wafer WF in a plan view. In other words, a plurality of patterns (transformers TR) arranged in a matrix in a plan view are formed.

[0071] 17, the semiconductor wafer WF is cut by dicing to separate the plurality of element regions 1A, thereby obtaining a plurality of semiconductor chips CHP3a and a plurality of semiconductor chips CHP3b. Here, after a tape is attached so as to cover the back surface of the semiconductor substrate SB, dicing is performed to cut the multilayer wiring layer ML and the semiconductor substrate SB.

[0072] Here, for example, dicing is performed along the X direction from X-axis cutting positions X1, X2, and X3 shown in FIG. 17, and dicing is performed along the Y direction from Y-axis cutting positions Y1 to Y4. Each X-axis cutting position is a position for cutting between adjacent element regions 1A in the Y direction, and each Y-axis cutting position is a position for cutting between adjacent element regions 1A in the X direction. Y-axis cutting positions Y1 to Y4 are positioned at equal intervals in the X direction, and only one element region 1A is arranged in the X direction between adjacent Y-axis cutting positions. In contrast, X-axis cutting positions X1 to X3 do not need to be arranged at equal intervals. For example, in the Y direction, two element regions 1A are arranged between adjacent X-axis cutting positions X1 and X2, while only one element region 1A is arranged between adjacent X-axis cutting positions X2 and X3.

[0073] By performing dicing as described above, a plurality of semiconductor chips CHP3b each having two element regions 1A can be obtained from the region between adjacent X-axis cutting positions X1 and X2. Furthermore, a plurality of semiconductor chips CHP3a each having one element region 1A can be obtained from the region between adjacent X-axis cutting positions X2 and X3. A semiconductor chip CHP3b each having two transformers TR can be used for a drive control unit having two channels as described with reference to FIG. 3. A semiconductor chip CHP3a each having one transformer TR can be used for a drive control unit having one channel as described with reference to FIG. 4. Furthermore, by separating adjacent X-axis cutting positions in the Y direction so that three element regions 1A are sandwiched between them, a semiconductor chip having three transformers TR arranged in the Y direction can be obtained. In other words, a transformer chip that can be used for a drive control unit having three channels as described with reference to FIG. 5 can be obtained.

[0074] In this way, in the first embodiment, when dicing one semiconductor wafer WF, the intervals between adjacent X-axis cutting positions are not standardized, but dicing is performed at a variety of intervals, thereby obtaining a variety of semiconductor chips, each having a different number of transformers TR formed thereon, from one semiconductor wafer WF.

[0075] In this way, the semiconductor device of the first embodiment can be formed. Of the semiconductor chips formed in this way, for example, a semiconductor chip CHP3b having two transformers TR is disposed between the semiconductor chips CHP1b and CHP2b as shown in FIG. 3. FIG. 18 is a schematic diagram of a semiconductor package using the semiconductor device of the first embodiment. As shown in FIG. 18, the semiconductor chip CHP1b is bonded onto the die DI1, the semiconductor chip CHP2b is bonded onto the die DI2, and the semiconductor chip CHP3b is bonded onto the die DI3.

[0076] Next, the tap pad 1a, transformer pad 1c, and transformer pad 1e (see FIG. 6) of the semiconductor chip CHP3b are connected to the pads of the primary-side semiconductor chip CHP1b via bonding wires BW. The tap pad 3a, transformer pad 3c, and transformer pad 3d (see FIG. 6) of the semiconductor chip CHP3b are connected to the pads of the secondary-side semiconductor chip CHP2b via bonding wires BW. The semiconductor chips CHP1b and CHP2b are connected to the multiple lead frames LF via bonding wires, respectively. The tap pad 1a and tap pad 3a do not necessarily need to be connected to other semiconductor chips. The die DI1, die DI2, die DI3, the multiple lead frames LF, the semiconductor chips CHP1b, CHP2b, and CHP3b are then sealed together with a resin mold MD to manufacture a semiconductor package.

[0077] <Advantages of First Embodiment> 3 to 5, when configuring the drive control unit with three chips, it is possible to design the primary-side semiconductor chip, transformer chip, and secondary-side semiconductor chip according to the application of the drive control unit. However, designing the semiconductor chips according to the application of the drive control unit increases the cost of design man-hours and manufacturing management (controlling production volume).

[0078] For example, when transformer chips are cut from an 8-inch semiconductor wafer, approximately 22,000 one-channel transformer chips can be obtained from one semiconductor wafer. Similarly, approximately 14,000 two-channel transformer chips can be obtained from one semiconductor wafer, and approximately 10,000 three-channel transformer chips can be obtained from one semiconductor wafer. Since more transformer chips than necessary are obtained for each product with a different number of channels, problems arise in not only the increase in transformer chip manufacturing costs but also poor production efficiency. In particular, as element miniaturization progresses, the number of semiconductor chips obtained from one semiconductor wafer increases, further reducing production efficiency.

[0079] Therefore, in the first embodiment, one transformer TR having the same layout is formed in each of the element regions 1A arranged in a matrix on the semiconductor wafer WF, as shown in Fig. 17. Therefore, there is no need to change the design of the semiconductor chip for each transformer chip with a different number of channels, which reduces the design cost of the transformer chip.

[0080] Furthermore, by appropriately changing the cutting size of the semiconductor chips in the dicing process, transformer chips with multiple channel counts can be obtained from a single semiconductor wafer WF. That is, while multiple Y-axis cutting positions are set at regular intervals, the intervals between adjacent X-axis cutting positions are not constant but are changed appropriately. This allows the number of channels (the number of transformers mounted) of the semiconductor chips cut out from the semiconductor wafer WF to be changed. Therefore, since the required number of semiconductor chips with different channel counts can be obtained from a single semiconductor wafer WF, the generation of surplus chips can be reduced. As a result, the manufacturing cost of semiconductor devices can be reduced.

[0081] 3 and 18, the semiconductor chip CHP3b is disposed between the primary-side semiconductor chip CHP1b and the secondary-side semiconductor chip CHP2b. The semiconductor chip CHP3b is connected to each of the semiconductor chips CHP1b and CHP2b by bonding wires BW. Therefore, it is desirable that the multiple transformers constituting the transformer chip be aligned in a direction perpendicular to the alignment direction of the semiconductor chips CHP1b, CHP3b, and CHP2b in a plan view. This also applies when the number of transformers formed in the transformer chip is three or more.

[0082] For example, as shown in Comparative Example 1 in Figure 34, a transformer chip may have four transformers TR, two arranged in each of the X and Y directions in plan view. In this case, even if an attempt is made to connect the transformer chip to another semiconductor chip with bonding wires, the bonding wires cannot be formed because the multiple bonding wires overlap each other. Similarly, as shown in Comparative Example 2 in Figure 35, when the transformers TR are arranged in a staggered pattern in the transformer chip, bonding wires cannot be formed.

[0083] In the first embodiment, as shown in FIG. 17, Y-axis cutting positions Y1 to Y4 are all arranged at the boundaries of element regions 1A aligned in the X direction. As a result, both ends of each element region 1A in the X direction are always cut in the dicing process. Therefore, the number of transformers aligned in the X direction in the cut-out semiconductor chip (the number of upper layer inductors and the number of lower layer inductors) is one. Therefore, because the transformers are aligned only in the Y direction in the transformer chip, bonding between the transformer chip and the primary-side semiconductor chip and the secondary-side semiconductor chip is easy.

[0084] <Modification> In the first embodiment described with reference to Figures 1 to 18, it has been described how multiple types of transformer chips are obtained from one semiconductor wafer. In a modification of the first embodiment, it will be described with reference to Figures 19 and 20 how different types of transformer chips are obtained from each semiconductor wafer.

[0085] 19 is a perspective view showing a lot including a plurality of semiconductor wafers according to a modification of the first embodiment. A lot is a name used as a unit in the production of semiconductor devices. One lot includes, for example, about 25 semiconductor wafers. FIG. 20 is a plan view showing a manufacturing process of the semiconductor device according to the modification of the first embodiment.

[0086] In the manufacturing process of a semiconductor device, first, one lot LT is prepared. One lot LT has a plurality of semiconductor wafers WF housed in a box BX.

[0087] Next, one semiconductor wafer WF is taken out from the lot LT, and a semiconductor substrate SB is prepared using this as described with reference to Fig. 8. Thereafter, a plurality of transformers TR are formed on the semiconductor wafer WF by performing the steps described with reference to Figs.

[0088] Next, as shown on the left side of Fig. 20, the semiconductor wafer WF is cut by dicing to separate the plurality of element regions 1A into a plurality of semiconductor chips CHP3a. Unlike the process described in Fig. 17, only a plurality of semiconductor chips CHP3a each having one transformer TR are cut out from the semiconductor wafer WF, and semiconductor chips each having two or more transformers TR are not cut out.

[0089] Next, one semiconductor wafer WF is taken out from the lot LT, and a semiconductor substrate SB is prepared using this as described with reference to Fig. 8. Thereafter, a plurality of transformers TR are formed on the semiconductor wafer WF by performing the steps described with reference to Figs.

[0090] Next, as shown on the right side of Fig. 20, the semiconductor wafer WF is cut by dicing to separate the element regions 1A into individual semiconductor chips CHP3b. Unlike the process described in Fig. 17, only the semiconductor chips CHP3b having two transformers TR are cut out from the semiconductor wafer WF, and semiconductor chips having one transformer TR or three or more transformers TR are not cut out.

[0091] In this way, a semiconductor device according to a modification of the first embodiment can be formed. Here, a plurality of element regions 1A are formed in each of a plurality of semiconductor wafers WF included in a lot LT in the same process. Then, by changing the X-axis cutting position for each semiconductor wafer WF, dicing is performed at different locations. This allows different types of semiconductor chips to be obtained from each semiconductor wafer WF. That is, for example, a plurality of semiconductor chips CHP3a each having one transformer TR can be obtained from one semiconductor wafer WF, and a plurality of semiconductor chips CHP3b each having two transformers TR can be obtained from another semiconductor wafer WF.

[0092] Therefore, different types of semiconductor chips can be obtained from multiple semiconductor wafers containing elements formed by the same process. Here, since transformer chips with different numbers of channels can be obtained from multiple semiconductor wafers, there is no need to change the design for each of the multiple semiconductor wafers, which reduces the design cost of the transformer chip.

[0093] (Embodiment 2) Hereinafter, a description will be given of half-cutting a semiconductor substrate as a structure for preventing the propagation of crosstalk noise between adjacent transformers in a transformer chip.

[0094] <Structure of semiconductor device> Fig. 21 shows a planar layout of a semiconductor chip which is a semiconductor device according to the second embodiment, and Fig. 22 shows a cross-sectional view of the semiconductor chip taken along line BB in Fig. 21.

[0095] 21 and 22 differs from the first embodiment in that the main surface (upper surface) of the semiconductor substrate SB is cut to a depth partway through the semiconductor substrate SB at the boundary between adjacent element regions 1A, and a structure including the multilayer wiring layer ML, the surface protective film PAS, and the polyimide resin film PI on the semiconductor substrate SB is separated. The other structure of the semiconductor chip CHP3b of the second embodiment is substantially the same as the structure of the semiconductor chip of the first embodiment shown in FIG.

[0096] A trench D1 having a predetermined depth from the main surface of the semiconductor substrate SB is formed near the boundary between adjacent element regions 1A. In plan view, the trench D1 is disposed between adjacent transformers TR. The trench D1 extends in the X direction from one end to the other end of the semiconductor substrate SB. The depth L1 of the trench D1 is, for example, 1.75 μm or more. The thickness of the semiconductor substrate SB is, for example, 250 μm. The area directly above the trench D1 is open, and no multilayer wiring layer ML, surface protective film PAS, polyimide resin film PI, or other conductor patterns are formed therein. The area within the trench D1 and the area directly above it are filled with a resin mold MD as shown in FIG. 18.

[0097] <Method of manufacturing a semiconductor device> FIG. 23 is a plan view showing a manufacturing process of a semiconductor device according to the second embodiment. FIG. 23 is a plan view showing a portion of the semiconductor wafer WF in a dicing process corresponding to FIG. 17 after the processes described with reference to FIGS. 8 to 16 have been performed. In the dicing process according to the second embodiment, structures (such as the multilayer wiring layer ML) on the semiconductor substrate SB are cut, and half-cutting is performed to form grooves D1 (see FIG. 22) that reach partway from the main surface of the semiconductor substrate SB. The half-cutting is performed at the X-axis partial removal position XA shown in FIG. 23. In the half-cutting, it is not necessary to cut halfway through the thickness of the semiconductor substrate SB into the semiconductor substrate SB; the depth of the grooves D1 may be, for example, 1.75 μm or more. The half-cutting is performed using, for example, a dicing blade. However, instead of using a dicing blade, laser grooving may be performed to remove the structures (such as the multilayer wiring layer ML) on the semiconductor substrate SB and form the grooves D1 in the main surface of the semiconductor substrate SB.

[0098] Thereafter, the semiconductor wafer WF is cut using a dicing blade at X-axis cutting position X1, X-axis cutting position X2, Y-axis cutting position Y1, Y-axis cutting position Y2, and Y-axis cutting position Y3, as in embodiment 1. This allows a plurality of types of semiconductor chips, each having a different number of transformers TR, to be obtained from the semiconductor wafer WF.

[0099] The half-cutting in the second embodiment is not performed on semiconductor chips having one transformer. The X-axis partial removal position is set at a position that does not overlap with the X-axis cutting position. Here, in a semiconductor chip having two or more transformers, the half-cutting is performed between adjacent transformers. That is, the half-cutting is performed along the X direction at all boundaries of element regions 1A that exist between adjacent X-axis cutting positions in the Y direction. In FIG. 23, in the area where semiconductor chips containing two transformers are cut out, the X-axis cutting position and the X-axis partial removal position are set alternately in the Y direction. Furthermore, in some areas where semiconductor chips containing three or more transformers are cut out, the X-axis partial removal positions are set so as to be adjacent to each other across one element region 1A.

[0100] <Advantages of the Second Embodiment> In a transformer chip having multiple transformers, crosstalk noise may propagate between adjacent transformers via a semiconductor substrate. Crosstalk noise propagation is capacitive noise propagation caused by the capacitance between the semiconductor substrate and the lowest-layer wiring (lower-layer wiring) in a multi-layer wiring layer. That is, in each channel (each transformer), capacitance occurs between the lower-layer wiring and the semiconductor substrate. Crosstalk noise propagates from one transformer to another, passing through the capacitance of one transformer, the semiconductor substrate, and the capacitance of another transformer in that order.

[0101] 13, it is conceivable to reduce the capacitance between the lower layer wiring and the semiconductor substrate SB, thereby suppressing the occurrence of crosstalk noise. In other words, if the first layer wiring M1 is not formed, the distance between the semiconductor substrate SB and the lower layer wiring becomes larger than when the wiring M1 is present, and therefore the capacitance decreases.

[0102] Another approach to reducing crosstalk noise is to insulate the wiring M1 from the lower-layer inductor 300 and form the wiring M1 so that it covers the entire main surface of the semiconductor substrate SB. However, this approach requires cutting the wiring M1 during the dicing process. In this case, aluminum constituting the wiring M1 adheres to the dicing blade, necessitating frequent cleaning or replacement of the dicing blade. This reduces the productivity of the semiconductor device. Another approach is to further form an oxide film between the semiconductor substrate SB and the lower-layer wiring to reduce the capacitance, but this makes the semiconductor chip more prone to bending.

[0103] In the second embodiment, the propagation of crosstalk noise can be prevented by forming groove D1 in the main surface of the semiconductor substrate SB, without removing the wiring M1, forming the wiring M1 over the entire surface, or forming an oxide film as described above. That is, crosstalk noise propagates from the main surface of the semiconductor substrate through a relatively shallow region, but by forming groove D1, the propagation of crosstalk noise can be blocked. Therefore, the performance of the semiconductor device can be improved.

[0104] Here, when crosstalk noise is suppressed by not forming the first-layer wiring M1, it is desirable to reduce capacitance by digging the semiconductor substrate SB so that the capacitance corresponds to the capacitance reduction due to the thickness of the insulating film between the bottom surface of the wiring M1 and the second-layer wiring on the wiring M1. The inventors converted the capacitance reduction due to the thickness of the insulating film into the capacitance reduction due to the digging of the semiconductor substrate SB, taking into account the difference in dielectric constant between the silicon oxide constituting the insulating film and the silicon (Si) constituting the semiconductor substrate SB. As a result, the inventors found that the propagation of crosstalk noise can be effectively prevented by digging the semiconductor substrate SB by 1.75 μm or more. For this reason, in the second embodiment, the depth of the groove D1 is set to 1.75 μm or more.

[0105] <Modification> 23 illustrates a case in which the X-axis cutting positions and the X-axis partial removal positions are alternately set and do not overlap each other. In contrast, the X-axis partial removal positions and the X-axis cutting positions may overlap. In other words, the area where the semiconductor wafer WF is cut may overlap with a portion of the groove D1 formed by half-cutting in a plan view. That is, a half-cut may be performed at the X-axis partial removal positions, and then the half-cut area may be cut using a dicing blade, a process known as step dicing.

[0106] In this case, for example, it is conceivable to half-cut all of the boundaries between adjacent element regions 1A in the Y direction as X-axis cutting positions. On the other hand, the X-axis cutting positions are set according to the type of transformer chip required, as in the first embodiment.

[0107] In step dicing, first, as shown in Fig. 24, for example, a laser LD is irradiated onto the main surface of the semiconductor substrate SB. This performs laser grooving, thereby removing structures (such as the multilayer wiring layer ML) on the semiconductor substrate SB and forming grooves D1 in the main surface of the semiconductor substrate SB. Here, before performing half-cutting (laser grooving), a tape TP is attached to the entire back surface of the semiconductor substrate SB.

[0108] Next, as shown in FIG. 25, the semiconductor substrate SB is cut using a dicing blade DB so as to cut the bottom surface of the semiconductor substrate SB from the bottom surface of the groove D1. The width of the dicing blade DB is smaller than the width of the groove D1. By performing step dicing in this manner, the generation of residue due to dicing can be suppressed. Furthermore, the generation of cracks or chipping of the semiconductor chips due to dicing can be prevented.

[0109] While the half-cutting has been described here as being performed by laser grooving, the half-cutting may also be performed using a dicing blade DBA as shown in FIG. 26 . Alternatively, the half-cutting may also be performed using a dicing blade DBB as shown in FIG. 27 . The cross-sectional shape of the tip of the dicing blade DBB is V-shaped. The width of the dicing blade DB used in the subsequent cutting process is smaller than the width of either the dicing blade DBA or the dicing blade DBB. Here, a dicing blade DBA or a dicing blade DBB suitable for cutting the multilayer wiring layer ML and a dicing blade DB suitable for cutting the semiconductor substrate SB are used, thereby achieving high-quality processing results. When a V-shaped dicing blade DBB as shown in FIG. 27 is used, chamfering is performed during cutting, enabling high-quality cutting with high bending strength.

[0110] (Embodiment 3) As a method for reducing crosstalk noise, in the third embodiment, an n-type semiconductor region is formed instead of the p-type semiconductor region PR shown in FIG. 7, which will be described below.

[0111] FIG. 28 is a cross-sectional view of a semiconductor device according to a third embodiment. FIG. 28 shows two transformers TR arranged side by side in one transformer chip. In FIG. 28, conductors other than the conductor pattern constituting the transformer TR, as well as a surface protective film PAS and a polyimide resin film PI on the multilayer wiring layer ML, are omitted. The structure of the semiconductor device according to the third embodiment is the same as that of the semiconductor device shown in FIG. 7, except that an n-type semiconductor region NR1 is formed instead of the p-type semiconductor region PR. The n-type semiconductor region NR1 has a predetermined depth from the main surface of the p-type semiconductor substrate SB. That is, the semiconductor substrate SB includes a p-type semiconductor region and an n-type semiconductor region NR1 formed on the p-type semiconductor region.

[0112] The n-type semiconductor region NR1 is connected to a fixed potential (for example, ground potential). The upper layer inductor 100 and the lower layer inductor 300 overlap with the n-type semiconductor region NR1 in plan view. The n-type semiconductor region NR1 can be formed by implanting n-type impurities into the main surface of the semiconductor substrate SB using an ion implantation method, for example, in the process described with reference to FIG. 10. The impurity concentration of the n-type semiconductor region NR1 is, for example, 1×10 19 cm -3 The depth of the n-type semiconductor region NR1 from the main surface of the semiconductor substrate SB is, for example, not less than 0.5 μm and not more than 2 μm.

[0113] 36 is a cross-sectional view of a semiconductor device of Comparative Example 3. The structure shown in FIG. 36 differs from the semiconductor device of Embodiment 3 in that a p-type semiconductor region PR is formed instead of the n-type semiconductor region NR1. In the semiconductor device of Comparative Example 3, a capacitance C1 occurs between the p-type semiconductor region PR formed in the semiconductor substrate SB and arranged on the main surface of the semiconductor substrate SB, and a wiring M1 that is a lower-layer wiring immediately above the p-type semiconductor region PR. The occurrence of crosstalk noise (capacitive noise) between the lower-layer wiring and the semiconductor substrate SB becomes more noticeable as the capacitance between the lower-layer wiring and the semiconductor substrate SB increases.

[0114] Therefore, in the third embodiment, an n-type semiconductor region NR1 is formed on the main surface of the semiconductor substrate SB. In each transformer TR, a capacitance C2 occurs between the n-type semiconductor region NR1 and the wiring M1, and a capacitance C3 occurs between the n-type semiconductor region NR1 and the p-type semiconductor substrate SB. The capacitances C2 and C3 are connected in series between the wiring M1 and the semiconductor substrate SB. Here, the reciprocal of the combined capacitance between the wiring M1 and the semiconductor substrate SB is the sum of the reciprocals of the capacitances C2 and C3. That is, the combined capacitance between the wiring M1 and the semiconductor substrate SB is smaller than any of the capacitances C1, C2, and C3. Therefore, in the third embodiment, by generating the capacitance C3 between the n-type semiconductor region NR1 and the semiconductor substrate SB, the propagation of crosstalk noise can be suppressed compared to the third comparative example shown in FIG.

[0115] <Modification> As shown in Fig. 29, an n-type semiconductor region NR2 having an impurity concentration lower than that of the n-type semiconductor region NR1 may be formed immediately below the transformer TR in the location where the n-type semiconductor region NR1 shown in Fig. 28 is formed. Fig. 29 is a cross-sectional view showing a semiconductor device according to a modification of the third embodiment.

[0116] FIG. 29 shows an embodiment in which two transformers TR are arranged side by side in one transformer chip. An n-type semiconductor region NR1 and an n-type semiconductor region NR2 are formed in a p-type semiconductor substrate SB. Each of the n-type semiconductor region NR1 and the n-type semiconductor region NR2 is formed at a predetermined depth from the main surface of the p-type semiconductor substrate SB. The impurity concentration of the n-type semiconductor region NR1 is higher than that of the n-type semiconductor region NR2. That is, when comparing the impurity concentrations of the n-type semiconductor region NR1 and the n-type semiconductor region NR2, the n-type semiconductor region NR1 is a high-concentration region, and the n-type semiconductor region NR2 is a low-concentration region. The n-type semiconductor region NR2 is formed at a position overlapping the lower layer inductor 300 and the upper layer inductor 100 in a planar view. The n-type semiconductor region NR1 is formed at a position spaced apart from the lower layer inductor 300 and the upper layer inductor 100 in a planar view. The n-type semiconductor region NR1 and the n-type semiconductor region NR2 are in contact with each other in the X direction or the Y direction. That is, the n-type semiconductor region NR1 and the n-type semiconductor region NR2 are electrically connected to each other. The n-type semiconductor region NR1 is connected to a fixed potential (for example, ground potential).

[0117] The n-type semiconductor regions NR1 and NR2 can be formed by implanting n-type impurities into the main surface of the semiconductor substrate SB using an ion implantation method, for example, in the process described with reference to Fig. 10. For example, after the n-type semiconductor region NR1 is formed in the main surface of the semiconductor substrate SB, the n-type semiconductor region NR2 is formed by implanting ions using a resist pattern as a mask. The impurity concentration of the n-type semiconductor region NR1 is, for example, 1 x 10 19 cm -3 The impurity concentration of the n-type semiconductor region NR2 is, for example, 1×10 17 cm -3 The depth of each of the n-type semiconductor regions NR1 and NR2 from the main surface of the semiconductor substrate SB is, for example, 0.5 μm or more and 2 μm or less. In each transformer TR, a capacitance C4 occurs between the n-type semiconductor region NR2 and the wiring M1, and a capacitance C5 occurs between the n-type semiconductor region NR2 and the p-type semiconductor substrate SB.

[0118] In this modification, the impurity concentration of the n-type semiconductor region NR2 directly below the transformer TR is lower than the impurity concentration of the n-type semiconductor region NR1 of the semiconductor device described with reference to Fig. 28. Therefore, the capacitance component (capacitance C5) of the junction between the n-type semiconductor region NR2 and the semiconductor substrate SB is smaller than the capacitance component (capacitance C3) of the junction between the n-type semiconductor region NR1 and the semiconductor substrate SB shown in Fig. 28. This is because a depletion layer expands from the junction surface between the n-type semiconductor region NR2 and the semiconductor substrate SB toward the upper surface of the n-type semiconductor region NR2, thereby reducing the capacitance C5.

[0119] Therefore, in this modification, the value of the capacitance C5 between the n-type semiconductor region NR2 and the semiconductor substrate SB is reduced, thereby making it possible to suppress propagation of crosstalk noise compared to the semiconductor device shown in FIG.

[0120] (Fourth embodiment) The following describes the formation of an isolation region in a semiconductor substrate as a method for preventing the propagation of crosstalk noise between adjacent transformers in a transformer chip.

[0121] <Structure of semiconductor device> Fig. 30 shows a planar layout of a semiconductor chip which is a semiconductor device according to the fourth embodiment, and Fig. 31 shows a cross-sectional view of the semiconductor chip taken along line CC in Fig. 30.

[0122] 30 and 31 differs from the first embodiment in that grooves D2 are formed in the main surface (upper surface) of the semiconductor substrate SB at the boundaries between adjacent element regions 1A, and element isolation regions DTI are formed in the grooves D2. The other structures of the semiconductor chip CHP3b of the fourth embodiment are substantially the same as the structures of the semiconductor chip of the first embodiment shown in FIG.

[0123] Near the boundary between adjacent element regions 1A, a trench D2 is formed in the main surface of the semiconductor substrate SB, reaching partway down into the semiconductor substrate SB. That is, the trench D2 has a predetermined depth from the main surface of the semiconductor substrate SB. In plan view, the trench D2 is disposed between adjacent transformers TR. The depth L2 of the trench D2 is, for example, 1.75 μm or more. An element isolation region DTI made mainly of silicon oxide is formed within the trench D2. The element isolation region DTI is made of an insulating film that constitutes the multilayer wiring layer ML. The upper part of the element isolation region DTI is covered with the insulating film, surface protective film PAS, and polyimide resin film PI that constitute the multilayer wiring layer ML.

[0124] <Method of manufacturing a semiconductor device> Fig. 32 is a cross-sectional view showing a state during a manufacturing process of the semiconductor device of the embodiment 4. Fig. 32 is a cross-sectional view showing a state after a p-type semiconductor region PR is formed in the semiconductor substrate SB as described with reference to Figs. 8 to 10 and before the process described with reference to Fig. 11 is performed.

[0125] First, as shown in FIG. 32, a trench D2 is formed in the main surface of the semiconductor substrate SB. For example, a hard mask made of an insulating film is formed on the main surface of the semiconductor substrate SB, and then the hard mask is patterned using photolithography and etching. In this patterning, an opening is formed through the hard mask so as to expose a part of the main surface of the semiconductor substrate SB located at the boundary between adjacent element regions 1A in the Y direction. Next, dry etching is performed using the hard mask as an etching prevention mask, thereby forming a trench D2 in the main surface of the semiconductor substrate SB below the opening. Thereafter, the hard mask is removed using, for example, wet etching.

[0126] 11, the insulating film IF1 is formed on the main surface of the semiconductor substrate SB. As a result, the trenches D2 are filled with the insulating film IF1. The insulating film IF1 left in the trenches D2 configures the element isolation region DTI.

[0127] Thereafter, the process of forming the conductive connection part CP described with reference to Fig. 11 and the processes described with reference to Figs. 12 to 16 are performed to obtain the structure shown in Figs. 33 and 31. The element isolation region DTI located at the boundary between adjacent element regions 1A in the Y direction is covered with an insulating film constituting the multilayer wiring layer ML. However, no conductor pattern is formed directly above the element isolation region DTI.

[0128] As shown in FIG. 33, the element isolation region DTI is located between the transformers TR adjacent to each other in the Y direction in a plan view. The element isolation region DTI extends in the X direction. Here, the element isolation region DTI is not formed near the boundary between the element regions 1A adjacent to each other in the X direction. In other words, the element isolation regions DTI adjacent to each other in the Y direction are separated from each other. Therefore, the element isolation region DTI is separated from the Y-axis cutting position in a plan view.

[0129] 17, dicing is performed, for example, at the same locations as in the first embodiment to separate the semiconductor wafer WF. At this time, at the X-axis cutting position, the element isolation region DTI is also cut along with the semiconductor substrate SB and the multilayer wiring layer ML. The width of the element isolation region DTI in the Y direction may be smaller or larger than the width in the Y direction of the dicing blade that performs cutting at the X-axis cutting position.

[0130] Furthermore, at the boundaries between adjacent element regions 1A in the Y direction, where dicing is not performed along the X direction, the element isolation regions DTI remain as part of the semiconductor chip. That is, in a transformer chip including multiple transformers TR aligned in the Y direction, the element isolation regions DTI remain in the semiconductor substrate SB between the adjacent transformers TR.

[0131] In this way, the semiconductor device of Embodiment 4 can be formed. Note that the trench D2 and the element isolation region DTI may be formed after the step described with reference to FIG. 10 and before the step described with reference to FIG.

[0132] <Advantages of the Fourth Embodiment> In the fourth embodiment, in a transformer chip including multiple transformers TR, an isolation region DTI is formed on the main surface of the semiconductor substrate SB between adjacent transformers TR. This prevents the propagation of crosstalk noise between the adjacent transformers TR. This effect is effectively achieved by setting the depth of the groove D2 to 1.75 μm or more, as in the second embodiment.

[0133] The invention made by the present inventors has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention.

[0134] For example, the transformer chip described in each of the above embodiments may have a capacitor instead of a transformer as an element for transmitting and receiving signals while maintaining insulation between the primary and secondary sides. In this case, instead of the upper layer inductor and the lower layer inductor, a plate made of a conductor pattern extending in the X and Y directions in a planar view is formed. The capacitor is composed of an upper layer plate and a lower layer plate that overlap each other in a planar view and are capacitively coupled to each other, and does not have a spiral wiring. In the planar layout shown in Figure 6, in the element region 1A, a capacitor used to transmit a signal of one channel is formed surrounded by the conductor pattern W1 and the conductor pattern W2 in a planar view.

[0135] 28 and 29 may be combined with the semiconductor device of the third embodiment described with reference to FIGS. 28 and 29 and the second or fourth embodiment. That is, the semiconductor substrate SB at the location where the n-type semiconductor region NR1 or the n-type semiconductor region NR2 is formed may be partially removed by half-cutting or by forming an element isolation region DTI. In this case, the depth of the groove D1 or the groove D2 may be greater or smaller than the depth of the n-type semiconductor region NR1 or the n-type semiconductor region NR2. [Explanation of symbols]

[0136] 1a, 3a tap pad 1A Element Area 1b, 1d, 3b spiral wiring 1B area 1c, 1e, 3c, 3d transformer pads 100 Upper layer inductor 300 Lower layer inductor C1, C2, C3, C4, C5 capacity CC control circuit CHP1a, CHP1b, CHP1c, CHP2a, CHP2b, CHP2c, CHP3a, CHP3b, CHP3c semiconductor chips CL1a, CL1b, CL2a, CL2b coils D1, D2 groove DR drive circuit DTI element isolation area INV Inverter LOD load circuit M1 wiring MD resin mold ML multilayer wiring layer NR1, NR2 n-type semiconductor region PAS surface protection film PI Polyimide resin film PR p-type semiconductor region RX1, RX2, RX3, RX4 receiving circuits SB semiconductor substrate TR, TR1, TR2, TR3 transformers TX1, TX2, TX3, TX4 transmitter circuits W1, W2 conductor patterns WF Semiconductor wafer X1, X2, X3 X-axis cutting position XA X-axis portion removal position Y1, Y2, Y3, Y4 Y-axis cutting position

Claims

1. a semiconductor substrate having a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type different from the first conductivity type disposed on the first semiconductor region; a first pattern that overlaps the second semiconductor region in a plan view and is formed above the semiconductor substrate; a second pattern that overlaps the first pattern in a plan view and is magnetically or capacitively coupled to the first pattern; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, a third pattern that overlaps the second semiconductor region in a plan view and is formed above the semiconductor substrate; a fourth pattern that overlaps the third pattern in a plan view and is magnetically or capacitively coupled to the third pattern; A semiconductor device comprising:

3. 3. The semiconductor device according to claim 2, the first pattern is a first inductor, the second pattern is a second inductor, the third pattern is a third inductor, the fourth pattern is a fourth inductor, the first inductor and the second inductor are magnetically coupled to each other, The third inductor and the fourth inductor are magnetically coupled to each other.

4. 3. The semiconductor device according to claim 2, the first pattern is a first plate; the second pattern is a second plate; the third pattern is a third plate; the fourth pattern is a fourth plate, the first plate and the second plate are capacitively coupled to each other; The third plate and the fourth plate are capacitively coupled to each other.

5. 3. The semiconductor device according to claim 2, a first conductor pattern surrounding the first pattern and the second pattern in a plan view; a second conductor pattern surrounding the third pattern and the fourth pattern in a plan view; Equipped with The first conductive pattern and the second conductive pattern are spaced apart from each other.

6. 3. The semiconductor device according to claim 2, The second semiconductor region is a low concentration region; a high-concentration region having a higher impurity concentration than the low-concentration region; and the first pattern and the third pattern overlap with the low-concentration region in a plan view, The high concentration region is connected to a fixed potential.

7. 3. The semiconductor device according to claim 2, a trench formed in the semiconductor substrate, the trench having a predetermined depth from a main surface of the semiconductor substrate, and the trench being disposed between the first pattern and the third pattern in a plan view;

8. 8. The semiconductor device according to claim 7, the first pattern and the third pattern are aligned along a first direction, The semiconductor device, wherein the trench extends from one end to the other end of the semiconductor substrate in a second direction perpendicular to the first direction in a plan view.

9. 3. The semiconductor device according to claim 2, a first circuit driven by a first voltage; a second circuit driven by a second voltage different from the first voltage; Equipped with the first pattern is electrically connected to the first circuit; The third pattern is electrically connected to the second circuit.

10. (a) providing a lot including a plurality of semiconductor wafers; (b) forming a plurality of patterns arranged in a matrix in a plan view above each of the plurality of semiconductor wafers; (c) cutting a first semiconductor wafer among the plurality of semiconductor wafers along a first direction along a main surface of the first semiconductor wafer to obtain a first semiconductor chip having n first patterns (n ​​is a positive natural number) among the plurality of patterns arranged in a second direction perpendicular to the first direction; (d) cutting the second semiconductor wafer, which is different from the first semiconductor wafer, among the plurality of semiconductor wafers along a third direction along a main surface of the second semiconductor wafer, to obtain a second semiconductor chip having m (m is a positive natural number different from n) second patterns among the plurality of patterns arranged in a fourth direction perpendicular to the third direction; and Each of the plurality of patterns is The downward pattern and an upper pattern that overlaps the lower pattern in a plan view and is magnetically or capacitively coupled to the lower pattern; a conductor pattern surrounding the lower pattern and the upper pattern in a plan view; A method for manufacturing a semiconductor device, comprising:

11. (a) providing a semiconductor wafer; (b) forming a plurality of patterns arranged in a matrix in a plan view above the semiconductor wafer; (c) cutting the semiconductor wafer along a first direction along a main surface of the semiconductor wafer to obtain a first semiconductor chip having n first patterns (n ​​is a positive natural number) of the plurality of patterns aligned in a second direction perpendicular to the first direction, and a second semiconductor chip having m second patterns (m is a positive natural number different from n) of the plurality of patterns aligned in the second direction; and Each of the plurality of patterns is The downward pattern and an upper pattern that overlaps the lower pattern in a plan view and is magnetically or capacitively coupled to the lower pattern; a conductor pattern surrounding the lower pattern and the upper pattern in a plan view; A method for manufacturing a semiconductor device, comprising:

12. 12. The method for manufacturing a semiconductor device according to claim 11, the lower pattern is a first inductor, the upper pattern is a second inductor, The method for manufacturing a semiconductor device, wherein the first inductor and the second inductor are magnetically coupled to each other.

13. 12. The method for manufacturing a semiconductor device according to claim 11, the lower pattern is a first plate; the upper pattern is a second plate; The method for manufacturing a semiconductor device, wherein the first plate and the second plate are capacitively coupled to each other.

14. 12. The method for manufacturing a semiconductor device according to claim 11, the number of the first patterns arranged in the first direction in the first semiconductor chip is one; a number of the second patterns aligned in the first direction in the second semiconductor chip is one;

15. 12. The method for manufacturing a semiconductor device according to claim 11, (b1) after the step (b) and before the step (c), forming a groove having a predetermined depth from the main surface on the main surface of the semiconductor wafer between two patterns among the plurality of patterns that are adjacent to each other in the second direction in a plan view; and The method for manufacturing a semiconductor device, wherein the first semiconductor chip or the second semiconductor chip has the groove.

16. 16. The method for manufacturing a semiconductor device according to claim 15, a region of the semiconductor wafer cut in the step (c) overlapping a portion of the groove in a plan view;

17. 16. The method for manufacturing a semiconductor device according to claim 15, The method for manufacturing a semiconductor device, wherein the region of the semiconductor wafer that is cut in the step (c) is separated from the groove in a plan view.

18. 12. The method for manufacturing a semiconductor device according to claim 11, (a1) before the step (b), a step of introducing impurities into the semiconductor wafer having a first semiconductor region of a first conductivity type, thereby forming a second semiconductor region of a second conductivity type different from the first conductivity type in the semiconductor wafer on the first semiconductor region; and the second semiconductor region is formed on the main surface of the semiconductor wafer, In the step (b), the plurality of patterns are formed above the semiconductor wafer so as to overlap the second semiconductor region.

19. 20. The method of manufacturing a semiconductor device according to claim 18, The second semiconductor region is a low concentration region; a high-concentration region having a higher impurity concentration than the low-concentration region; and the plurality of patterns overlap with the low-concentration region in a plan view, The method for manufacturing a semiconductor device, wherein the high concentration region is connected to a fixed potential.

20. 12. The method for manufacturing a semiconductor device according to claim 11, (a1) after the step (a) and before the step (b), forming a groove in the main surface of the semiconductor wafer, the groove reaching from the main surface to a depth of the semiconductor wafer; (a2) forming an isolation structure in the semiconductor wafer by filling the trenches with an insulating material; (d) cutting the semiconductor wafer along the second direction; and the element isolation structure is located between two of the patterns adjacent to each other in the second direction in a plan view, In the step (d), the semiconductor wafer is cut so as not to cut the element isolation structure.

21. 13. The method for manufacturing a semiconductor device according to claim 12, the lower pattern included in each of the plurality of patterns is electrically connected to a first circuit driven by a first voltage; The upper pattern included in each of the plurality of patterns is electrically connected to a second circuit that is driven by a second voltage different from the first voltage.

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