Oscillator

Abstract

It is possible to realize an oscillator having a small area, power saving, and a wide frequency variable range.SOLUTION: A first circuit including an inverter unit including an inverter first terminal coupled to a first coupling point and an inverter second terminal coupled to a signal output unit via a second coupling point, an input terminal coupled to the second coupling point, and an output terminal coupled to the first coupling point; The first circuit includes a variable resistance unit having a voltage input terminal for determining a resistance value, and a fixed resistance unit not having a voltage input terminal for determining a resistance value, and the variable resistance unit and the fixed resistance unit are connected in series between the input terminal and the output terminal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an oscillator. [Background technology]

[0002] As the integration of circuit elements progresses, power saving is becoming a requirement in recent electronic circuits. It is common for computer operation speeds to be varied as needed to reduce power consumption in standby mode. This operation speed is determined by the frequency of a clock signal. Generally, voltage-controlled oscillators that vary the oscillation frequency according to the input voltage value are used to vary the operation speed. For example, Patent Document 1 shows a voltage-controlled oscillator equipped with a ring oscillator in which three or more inverters are connected in an odd number of stages. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2024-47400 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when using a ring oscillator in a power-controlled oscillator, it is difficult to reduce the number of elements, i.e., to reduce the area, because the current at the input terminal of each inverter is limited or forced to flow in. Also, because the input terminal of each inverter is discharged from the power supply voltage to the threshold voltage or charged and discharged from the ground to the threshold voltage, the amount of moving charge is large, making it difficult to reduce power consumption.

[0005] SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned points, and has as its object to provide an oscillator that is small in area, power-saving, and has a wide frequency variable range. [Means for solving the problem]

[0006] One aspect of the present invention is an oscillator comprising: an inverter section having an inverter first terminal connected to a first connection point and an inverter second terminal connected to a signal output section via a second connection point; a first circuit having an input terminal connected to the second connection point and an output terminal connected to the first connection point; and a time constant determination section having a capacitance having one end connected to the first connection point and the other end connected to a reference voltage, wherein the first circuit comprises a variable resistance section having a voltage input terminal that determines a resistance value, and a fixed resistance section that does not have a voltage input terminal that determines a resistance value, and the variable resistance section and the fixed resistance section are connected in series between the input terminal and the output terminal.

[0007] In one aspect of the present invention, the fixed resistance section includes a first transistor and a first resistor, the gate of the first transistor is connected to one end of the first resistor, one of the source or drain of the first transistor is connected to the other end of the first resistor and is connected to the input terminal side, and the other of the source or drain of the first transistor is connected to the output terminal side.

[0008] In one aspect of the present invention, the first resistance is an on-resistance of a transistor.

[0009] In one aspect of the present invention, the variable resistance section includes a second transistor, the gate of the second transistor is connected to the voltage input terminal, one of the source or drain of the second transistor is connected to the input terminal side, and the other of the source or drain of the second transistor is connected to the output terminal side. [Effects of the Invention]

[0010] According to the present invention, it is possible to realize an oscillator that is small in area, low in power consumption, and has a wide variable frequency range. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 2 is a diagram illustrating an example of a specific configuration of an oscillator according to an embodiment. [Figure 2] FIG. 3 is a diagram illustrating an example of parameters of each circuit element included in the oscillator according to the embodiment. [Figure 3] FIG. 2 is a schematic diagram for explaining an example of the function of each circuit element of the oscillator according to the embodiment. [Figure 4] FIG. 10 is a diagram for explaining an example of the role of a fourth N-type transistor. [Figure 5] FIG. 10 is a diagram illustrating transistor characteristics. [Figure 6] FIG. 10 is a diagram for explaining an example of the role of a fifth N-type transistor. [Figure 7] FIG. 10 is a diagram for explaining an example of the role of a sixth N-type transistor. [Figure 8] FIG. 10 is a diagram showing an example of a simulation of the oscillation frequency and power consumption of an oscillator relative to the input voltage when the power supply voltage is 1.8 V. [Figure 9] FIG. 10 is a diagram showing an example of a circuit layout of an oscillator when a 1.8 V power supply is used. [Figure 10] 10A and 10B are diagrams illustrating the results of a comparison between the oscillator according to the embodiment and a conventional oscillator using a ring oscillator. [Figure 11] FIG. 1 is a diagram illustrating a conventional oscillator using a Schmitt trigger inverter. DETAILED DESCRIPTION OF THE INVENTION

[0012] [Embodiment] The oscillator according to the present embodiment will be described in detail below with reference to the accompanying drawings, showing preferred embodiments. In the drawings, identical or similar parts are designated by identical or similar reference numerals. Note that the present embodiment is not limited to these embodiments and includes various modifications or improvements. In other words, the components described below include those that can be easily imagined by a person skilled in the art and those that are substantially identical, and the components described below can be combined as appropriate. Furthermore, the present embodiment may include various omissions, substitutions, or modifications of components within the scope of the present invention.

[0013] 1 is a diagram showing an example of a specific configuration of an oscillator 1 according to an embodiment. The oscillator 1 includes an inverter section 10 and a time constant determination section 20.

[0014] The inverter unit 10 is, for example, a Schmitt trigger inverter including six transistors: a first P-type transistor Mps1, a second P-type transistor Mps2, a third P-type transistor Mps3, a first N-type transistor Mns1, a second N-type transistor Mns2, and a third N-type transistor Mns3. The inverter unit 10 also includes an inverter first terminal IP1 and an inverter second terminal IP2.

[0015] The inverter first terminal IP1 corresponds to the input terminal of the inverter unit 10. The inverter first terminal IP1 is connected to the first connection point P1. The inverter first terminal IP1 is also connected to the gate of the first P-type transistor Mps1, the gate of the second P-type transistor Mps2, the gate of the first N-type transistor Mns1, and the gate of the second N-type transistor Mns2.

[0016] The first connection point P1 is connected to the inverter first terminal IP1 of the inverter unit 10, one end of the capacitance C, and the output terminal TP2 of the first circuit 30.

[0017] The inverter second terminal IP2 corresponds to the output terminal of the inverter unit 10. The inverter second terminal IP2 is connected to the second connection point P2. The inverter second terminal IP2 is also connected to the drain of the second P-type transistor Mps2, the drain of the first N-type transistor Mns1, the gate of the third P-type transistor Mps3, and the gate of the third N-type transistor Mns3.

[0018] The second connection point P2 is connected to the inverter second terminal IP2 of the inverter unit 10, the input terminal TP1 of the first circuit 30, and the signal output unit Vso. The signal output unit Vso is an output terminal from which the oscillator 1 outputs a signal of a given frequency.

[0019] The first P-type transistor Mps1 is a P-type semiconductor having a source connected to a power supply voltage Vdd, a drain connected to the sources of the second P-type transistor Mps2 and the third P-type transistor Mps3, and a gate connected to the inverter first terminal IP1. The power supply voltage Vdd is a voltage supplied to the oscillator 1 and may be, for example, a voltage of any value set by the designer of the oscillator 1. The power supply voltage Vdd may be, for example, 1.8 V or 3.3 V.

[0020] The second P-type transistor Mps2 is a P-type semiconductor having a source connected to the drain of the first P-type transistor Mps1 and the source of the third P-type transistor Mps3, a drain connected to the inverter second terminal IP2, and a gate connected to the inverter first terminal IP1.

[0021] The third P-type transistor Mps3 is a P-type semiconductor having a source connected to the drain of the first P-type transistor Mps1 and the source of the second P-type transistor Mps2, a drain connected to a reference voltage, and a gate connected to the inverter second terminal IP2. The reference voltage may be, for example, 0 V, a small voltage close to 0 V, or an arbitrary voltage set by the designer of the oscillator 1.

[0022] The first N-type transistor Mns1 is an N-type semiconductor having a source connected to the drain of the second N-type transistor Mns2 and the source of the third N-type transistor Mns3, a drain connected to the inverter second terminal IP2, and a gate connected to the inverter first terminal IP1.

[0023] The second N-type transistor Mns2 is an N-type semiconductor having a source connected to a reference voltage, a drain connected to the source of the first N-type transistor Mns1 and the source of the third N-type transistor Mns3, and a gate connected to the inverter first terminal IP1.

[0024] The third N-type transistor Mns3 is an N-type semiconductor having a source connected to the source of the first N-type transistor Mns1 and the drain of the second N-type transistor Mns2, a drain connected to a reference voltage, and a gate connected to the inverter second terminal IP2.

[0025] The time constant determining section 20 includes a first circuit 30 and a capacitance C. The capacitance C may also be referred to as a second circuit. One end of the capacitance C is connected to a first connection point P1, and the other end is connected to a reference voltage. The time constant of the oscillator 1, and therefore the oscillation frequency, are determined based on the magnitude of the resistance and capacitance of the elements in the time constant determining section 20.

[0026] The first circuit 30 includes a variable resistance section 40 and a fixed resistance section 50. The first circuit 30 also includes an input terminal TP1 and an output terminal TP2. The input terminal TP1 is connected to, for example, a second connection point P2 and the variable resistance section 40. The output terminal TP2 is connected to, for example, the first connection point P1 and the fixed resistance section 50.

[0027] The variable resistance unit 40 has, for example, a fourth N-type transistor Mns4 as a component. The fixed resistance unit 50 has, for example, a voltage input terminal Vsi that determines the resistance value of the time constant determination unit 20 (variable resistance unit 40). A voltage that controls the resistance value is input to the voltage input terminal Vsi. The voltage value input to the voltage input terminal Vsi may be an arbitrary voltage value set by the designer of the oscillator 1, or may be a voltage value determined by a control device (not shown).

[0028] In the fourth N-type transistor Mns4, as well as the fifth N-type transistor Mns5 and sixth N-type transistor Mns6 described below, the body is not connected to the source or drain. In the following description, one of the source or drain of a transistor whose body is not connected to the source or drain may be referred to as the first end, and the other as the second end. In this specification, the first end refers to the source or drain terminal that is on the upper side in the drawing, and the second end refers to the source or drain terminal that is on the lower side in the drawing.

[0029] The fourth N-type transistor Mns4 is an N-type semiconductor having a first terminal connected to the second terminal of the fifth N-type transistor Mns5, the second terminal of the sixth N-type transistor Mns6, and the gate of the sixth N-type transistor Mns6, a second terminal connected to the input terminal TP1, a body connected to the reference voltage, and a gate connected to the voltage input terminal Vsi. The resistance value of the fourth N-type transistor Mns4 varies depending on the voltage value input to the voltage input terminal Vsi.

[0030] The fixed resistance section 50 includes, for example, a fifth N-type transistor Mns5 and a sixth N-type transistor Mns6 as components. The fixed resistance section 50 does not include a voltage input terminal Vsi that determines the resistance value of the time constant determination section 20.

[0031] The fifth N-type transistor Mns5 is, for example, an N-type semiconductor having a first terminal connected to the output terminal TP2, a first terminal of the fourth N-type transistor Mns4, a second terminal of the sixth N-type transistor Mns6, a second terminal connected to the gate of the sixth N-type transistor Mns6, a body connected to a reference voltage, and the first terminal of the sixth N-type transistor Mns6.

[0032] The sixth N-type transistor Mns6 is an N-type semiconductor having, for example, a first terminal connected to the gate of the fifth N-type transistor Mns5, a second terminal connected to the first terminal of the fourth N-type transistor Mns4 and the second terminal of the fifth N-type transistor Mns5, a gate connected to the first terminal of the fourth N-type transistor Mns4 and the second terminal of the fifth N-type transistor Mns5 in the same manner as the second terminal, and a body connected to a reference voltage.

[0033] FIG. 2 is a diagram showing an example of parameters of each circuit element included in the oscillator 1 according to the embodiment. The first N-type transistor Mns2, the second N-type transistor Mns3, the first P-type transistor Mps1, the second P-type transistor Mps2, and the third P-type transistor Mps3Mns1 included in the inverter unit 10 have a size (W / L) of 220 nm / 180 nm. The fourth N-type transistor Mns4 included in the variable resistance unit 40 has a size of 220 nm / 5 μm. The fifth N-type transistor Mns5 included in the fixed resistance unit 50 has a size of 4 μm / 180 nm, and the sixth N-type transistor Mns6 has a size of 5 μm / 180 nm. The fourth N-type transistor Mns4, the fifth N-type transistor Mns5, and the sixth N-type transistor Mns6 are used as resistors that determine the time constant, and are therefore larger than the transistors included in the inverter unit 10. The capacitance value of the capacitor C is 16 fF. Therefore, the area occupied by the capacitance C in the integrated circuit is small.

[0034] Next, the function of each circuit element included in the oscillator 1 will be specifically described.

[0035] FIG. 11 is a diagram showing a general oscillator 9 using a Schmitt trigger inverter 91. FIG. 3 is a schematic diagram for explaining an example of the function of each circuit element of the oscillator 1 according to the embodiment. The oscillator 9 includes a variable resistance unit 94 and a capacitance C9 as a time constant determination unit 92. In contrast, the oscillator 1 according to the embodiment includes a variable resistance unit 40, a fixed resistance unit 50, and a capacitance C as a time constant determination unit 20. In other words, the oscillator 1 according to the embodiment differs from the general oscillator 9 in that it further includes the fixed resistance unit 50.

[0036] One end of the variable resistance section 40 is connected to the input terminal TP1, and the other end is connected to the output terminal TP2. The fixed resistance section 50 is a diode with the cathode on the first connection point P1 (capacitance C) side and the anode on the second connection point P2 side. In other words, the fixed resistance section 50 can be said to be reverse diode-connected with the capacitance C as the reference.

[0037] In the above description, an example is shown in which one end of the fixed resistance section 50 is connected to the output terminal TP2 and one end of the variable resistance section 40 is connected to the input terminal TP1. However, this embodiment is not limited to this example. The fixed resistance section 50 and the variable resistance section 40 may be connected in series between the input terminal TP1 and the output terminal TP2. Specifically, one end of the fixed resistance section 50 may be connected to the input terminal TP1 and one end of the variable resistance section 40 may be connected to the output terminal TP2.

[0038] That is, the oscillator 1 according to this embodiment includes an inverter unit 10 including an inverter first terminal IP1 connected to a first connection point P1 and an inverter second terminal IP2 connected to a signal output unit Vso via a second connection point P2, a first circuit 30 including an input terminal TP1 connected to the second connection point P2 and an output terminal TP2 connected to the first connection point P1, and a time constant determination unit 20 including a capacitor C connected to the first connection point P1 and a reference voltage at its other end. The first circuit 30 includes a variable resistor unit 40 having a voltage input terminal Vsi for determining a resistance value, and a fixed resistor unit 50 not having a voltage input terminal Vsi for determining a resistance value. The variable resistor unit 40 and the fixed resistor unit 50 are connected in series between the input terminal TP1 and the output terminal. The fixed resistor unit 50, which is connected in a reverse diode configuration, makes it difficult for electric charge returning from the capacitor C to pass through, thereby enabling the oscillator 1 to operate even at low frequencies. Furthermore, the fixed resistor section 50, which is a diode, has a resistance with a very large value, and the capacitance value of the capacitor C and therefore the area can be kept small.

[0039] Fig. 4 is a diagram illustrating an example of the role of the fourth N-type transistor Mns4. In Fig. 4, the variable resistance unit 40 includes a fourth N-type transistor Mns4. That is, the oscillator 1 uses the fourth N-type transistor Mns4 as a variable resistance.

[0040] The fourth N-type transistor Mns4 has a first terminal connected to the variable resistor unit 40, a second terminal connected to the input terminal TP1, a body connected to a reference voltage, and a gate connected to the voltage input terminal Vsi. Figure 5 shows transistor characteristics. The fourth N-type transistor Mns4 exponentially changes the current flowing between its source and drain in response to the voltage input to its gate. Its resistance also changes rapidly with the change in current. When the resistance of the fourth N-type transistor Mns4 changes, the current flowing from the inverter unit 10 to the capacitor C via the fourth N-type transistor Mns4 also changes, changing the time required for charge to accumulate in the capacitor C. The on / off timing of the inverter unit 10 changes depending on the time required for charge to accumulate in the capacitor C, enabling the oscillator 1 to vary its frequency using the fourth N-type transistor Mns4.

[0041] That is, in the oscillator 1 according to this embodiment, the variable resistance unit 40 includes a fourth N-type transistor Mns4 (which may also be referred to as a second transistor). The fourth N-type transistor Mns4 is connected to the voltage input terminal Vsi, one of the source or drain (second terminal) of the fourth N-type transistor Mns4 is connected to the input terminal TP1, and the other of the source or drain (first terminal) of the fourth N-type transistor Mns4 is connected to the output terminal TP2. By using the fourth N-type transistor Mns4 as the variable resistance unit 40, the oscillator 1 can reduce the overall circuit area. Furthermore, due to the characteristic of the fourth N-type transistor Mns4, in which the resistance value changes sharply, the oscillator 1 can achieve an extremely wide frequency variable range.

[0042] 6 is a diagram illustrating an example of the role of the fifth N-type transistor Mns5. In FIG. 6, the fixed resistance unit 50 includes a fifth N-type transistor Mns5 and a first resistor 51. The fifth N-type transistor Mns5 in FIG. 6 includes a first terminal connected to the output terminal TP2, a second terminal connected to the variable resistance unit 40 and one terminal of the first resistor 51, a body connected to a reference voltage, and a gate connected to the other terminal of the first resistor 51. One terminal of the first resistor 51 is connected to the second terminal of the fifth N-type transistor Mns5, and the other terminal is connected to the gate of the fifth N-type transistor Mns5.

[0043] That is, in the oscillator 1 according to this embodiment, the fixed resistor unit 50 includes a fifth N-type transistor Mns5 (which may also be referred to as a first transistor) and a first resistor 51. The gate of the fifth N-type transistor Mns5 is connected to one end of the first resistor 51. One of the source or drain (second end) of the fifth N-type transistor Mns5 is connected to the other end of the first resistor 51 and connected to the output terminal TP2. The other of the source or drain (first end) of the fifth N-type transistor Mns5 is connected to the output terminal TP2. By using the fifth N-type transistor Mns5 instead of a diode, the oscillator 1 can reduce the overall circuit area while maintaining high resistance. Furthermore, by using the first resistor 51, the oscillator 1 can delay the accumulation of charge at the gate of the fifth N-type transistor Mns5. Therefore, the oscillator 1 can tune its frequency up to a low frequency band.

[0044] 7 is a diagram illustrating an example of the role of the sixth N-type transistor Mns6. In FIG. 7, the fixed resistance unit 50 includes a fifth N-type transistor Mns5 and a sixth N-type transistor Mns6. That is, the fixed resistance unit 50 includes the sixth N-type transistor Mns6 instead of the first resistor 51.

[0045] 7 differs from the fifth N-type transistor Mns5 in Fig. 4 in that a second terminal of the fifth N-type transistor Mns5 is connected to the second terminal of the sixth N-type transistor Mns6 and the gate of the sixth N-type transistor Mns6. The sixth N-type transistor Mns6 in Fig. 6 is an N-type semiconductor having a first terminal connected to the gate of the fifth N-type transistor Mns5, a second terminal and a gate connected to the variable resistance unit 40, and a body connected to a reference voltage.

[0046] That is, in the oscillator 1 according to this embodiment, the first resistor 51 is the on-resistance of the sixth N-type transistor Mns6. By using the on-resistance of the sixth N-type transistor Mns6 instead of the first resistor 51, the oscillator 1 can reduce the overall circuit area while maintaining a high resistance.

[0047] Figure 8 shows an example of a simulation of the oscillation frequency and power consumption of oscillator 1 versus input voltage when the power supply voltage Vdd is 1.8V. From Figure 8, it can be seen that the oscillation frequency of oscillator 1 is in the range of approximately 400Hz to 200MHz, and the power consumption of oscillator 1 is a maximum of 120µW within the input voltage range in which oscillation occurs. It can also be seen that as the temperature increases, the maximum oscillation frequency of oscillator 1 decreases from 200MHz to approximately 150MHz, and the maximum power consumption of oscillator 1 decreases from just over 120µW to less than 100µW.

[0048] FIG. 9 is a diagram showing an example of the circuit layout of the oscillator 1 when a 1.8V power supply is used. In FIG. 9, the transistors included in the oscillator 1 are set to the minimum size that does not take into account printing errors. From FIG. 9, the oscillator 1 is set to a size of approximately 130 μm 2 It can be seen that it can be created with an area of ​​.

[0049] FIG. 10 is a diagram showing a comparison result between the oscillator 1 according to the embodiment and a conventional oscillator using a ring oscillator. The oscillator 1 according to the embodiment consumes about 50% of the power compared to oscillator [1], making it energy-saving. Furthermore, the oscillator 1 according to the embodiment has a circuit area that is 20% of the circuit area compared to oscillator [2], making it a small area. Furthermore, the oscillator 1 according to the embodiment consumes less power and has a smaller circuit area than oscillator [3] and oscillator [3]. Despite its small area, the oscillator 1 according to the embodiment consumes only about 47 μW of power and can be driven over a frequency band 30,000 times wider.

[0050] The oscillator 1 described above can be used in various technologies, such as technologies using power semiconductors such as DC-DC converters and down converters, data recovery for high-speed serial communications, frequency synthesizers, changing the operating speed of CPUs, phase-locked loops, and robot walking control using neuromorphic devices.

[0051] In the above description, an example is shown in which the inverter unit 10 and the first circuit 30 have input terminals and output terminals. However, the present embodiment is not limited to this example, and the inverter unit 10 and the first circuit 30 do not need to actually have terminals. For example, the terminals of the inverter unit 10 and the first circuit 30 may be exemplified as points on the respective connection lines connecting the circuit elements of the oscillator 1.

[0052] In the above description, an example is shown in which the fifth N-type transistor Mns5 and the sixth N-type transistor Mns6 included in the fixed resistance unit 50 are N-type semiconductors. However, the present embodiment is not limited to this example, and the transistors included in the fixed resistance unit 50 may be P-type semiconductors. [Explanation of symbols]

[0053] 1...oscillator, P1...first connection point, P2...second connection point, Vsi...voltage input terminal, Vso...signal output section, IP1...inverter first terminal, IP2...inverter second terminal, inverter section 10, 20...time constant determination section, 30...first circuit, TP1...input terminal, TP2...output terminal, C...capacitance, 40...variable resistor section, 50...fixed resistor section, 51...first resistor

Claims

1. an inverter unit including an inverter first terminal connected to the first connection point and an inverter second terminal connected to the signal output unit via the second connection point; a time constant determination unit including a first circuit having an input terminal connected to the second connection point and an output terminal connected to the first connection point, and a capacitor having one end connected to the first connection point and the other end connected to a reference voltage; Equipped with the first circuit includes a variable resistance section having a voltage input terminal for determining a resistance value, and a fixed resistance section having no voltage input terminal for determining a resistance value, the variable resistance unit and the fixed resistance unit are connected in series between the input terminal and the output terminal, Oscillator.

2. the fixed resistor unit includes a first transistor and a first resistor; a gate of the first transistor is connected to one end of the first resistor; one of a source and a drain of the first transistor is connected to the other end of the first resistor and to the input terminal; the other of the source and the drain of the first transistor is connected to the output terminal side; 2. The oscillator of claim 1.

3. The first resistance is an on-resistance of a transistor.

3. The oscillator according to claim 2.

4. the variable resistance unit includes a second transistor, the gate of the second transistor is connected to the voltage input terminal; one of the source and the drain of the second transistor is connected to the input terminal side; the other of the source and the drain of the second transistor is connected to the output terminal side; The oscillator according to any one of claims 1 to 3.

Images