Wiring board and method for manufacturing wiring board

Abstract

To provide a wiring board having fine wiring.SOLUTION: The circuit board 1 of the embodiment includes the insulating layer 31, and the conductive layer 21 that is laminated on the 31a of the insulating layer 31 and includes the multiple parallel circuit patterns 2. The plurality of wiring patterns 2 include wiring patterns 20 adjacent to each other at an interval S of 3 μm or less, and at least one wiring pattern 20 of the plurality of wiring patterns 2 has, at an end portion on the insulating layer 31 side in a lamination direction of the insulating layer 31 and the conductor layer 21, a width smaller than a width at a central portion in the lamination direction of the insulating layer 31 and the conductor layer 21.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a wiring board and a method for manufacturing a wiring board. [Background technology]

[0002] Patent Document 1 discloses a printed wiring board having a circuit pattern in which the relationship (L / S) between the wiring width (L) and the wiring spacing (S) of the circuit pattern is 3 to 15 μm / 3 to 15 μm. In Patent Document 1, when a resist pattern used to form fine wiring is formed by exposure and development, an increase in the width of the resist pattern is suppressed by suppressing the proportion of diffused light during exposure. In addition, to suppress the proportion of diffused light, approximately conical convex portions are formed on the surface of a metal layer (seed layer) underlying the resist pattern. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-136646 Summary of the Invention [Problem to be solved by the invention]

[0004] In the printed wiring board and its manufacturing method disclosed in Patent Document 1, the resist pattern cannot be maintained in an appropriate state during wiring formation, and wiring according to fine wiring rules, for example, less than 3 μm, cannot be provided. Also, it is thought that a longer plating time than usual is required to form approximately conical convex portions on the surface of the metal layer (seed layer). [Means for solving the problem]

[0005] The wiring board of the present invention includes an insulating layer and a conductor layer laminated on the surface of the insulating layer and including a plurality of parallel wiring patterns, wherein the plurality of wiring patterns include adjacent wiring patterns spaced at intervals of 3 μm or less, and at least one of the plurality of wiring patterns has a width at an end portion on the insulating layer side in a lamination direction between the insulating layer and the conductor layer that is smaller than the width at a center portion in the lamination direction.

[0006] A method for manufacturing a wiring board according to the present invention includes forming an insulating layer and forming a plurality of parallel wiring patterns on a surface of the insulating layer, wherein forming the plurality of wiring patterns includes forming a plurality of parallel resist walls on the surface of the insulating layer and forming a plating film between each of the parallel resist walls, and forming at least one resist wall having a width at an end of each of the plurality of resist walls on the insulating layer side in a height direction that is greater than the width at a center portion of the height direction.

[0007] According to the embodiment of the present invention, it is believed that the resist pattern is stable in the formation of wiring, and therefore the wiring substrate can have fine wiring. Also, it may be easier to form a fine wiring pattern. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view partially illustrating an example of a wiring board according to an embodiment. [Figure 2A] FIG. 2 is a cross-sectional perspective view of the wiring pattern of FIG. 1. [Figure 2B] FIG. 2 is an enlarged cross-sectional view of a portion IIB in FIG. [Figure 3] FIG. 2 is a cross-sectional view showing an example of the wiring substrate according to the first embodiment. [Figure 4] FIG. 10 is a cross-sectional view showing an example of a wiring board according to a second embodiment. [Figure 5A] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a wiring board according to an embodiment. [Figure 5B]5A to 5C are cross-sectional views showing an example of a method for manufacturing a wiring board according to an embodiment. [Figure 5C] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a wiring board according to an embodiment. [Figure 5D] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a wiring board according to an embodiment. [Figure 5E] 1A to 1C are cross-sectional perspective views showing an example of a method for manufacturing a wiring board according to an embodiment. [Figure 5F] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a wiring board according to an embodiment. [Figure 5G] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a wiring board according to an embodiment. [Figure 5H] 1A to 1C are cross-sectional perspective views showing an example of a method for manufacturing a wiring board according to an embodiment. [Figure 5I] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a wiring board according to an embodiment. [Figure 5J] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a wiring board according to an embodiment. [Figure 5K] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a wiring board according to an embodiment. [Figure 5L] 5A to 5C are cross-sectional views showing an example of a method for manufacturing a wiring board according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Wiring boards according to embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional view of a portion of a wiring board 1, which is an example of a wiring board according to an embodiment. FIG. 2A shows a cross-sectional perspective view of the wiring pattern of the wiring board 1 of FIG. 1, and FIG. 2B shows an enlarged view of portion IIB of FIG. 1. Note that the wiring boards shown in the drawings referred to in the following description are merely examples of wiring boards according to an embodiment. The layered structure of the wiring board according to the embodiment is not limited to the layered structure of the wiring board shown in the drawings, and the number of conductor layers and insulating layers included in the wiring board according to the embodiment is not limited to the number of conductor layers and insulating layers included in the wiring board according to the embodiment. The wiring board according to the embodiment may include any number of insulating layers and conductor layers in addition to the insulating layers and conductor layers included in the wiring board shown in the drawings, and may not include all of the insulating layers and conductor layers included in the wiring board shown in the drawings. Note that in the drawings referred to in the following description, certain portions may be enlarged to facilitate understanding of the disclosed embodiments. Therefore, the components may not be drawn to exact proportions relative to each other in terms of size or length.

[0010] <Configuration of wiring pattern in wiring board of embodiment> As shown in FIGS. 1 to 2B, the wiring board 1 includes an insulating layer 31 (first insulating layer) and a conductor layer 21 laminated on a surface 31a of the insulating layer 31. The wiring board 1 of FIG. 1 further includes an insulating layer 32 (second insulating layer). The insulating layer 32 is laminated on the insulating layer 31, and covers the surface 31a of the insulating layer 31 and the conductor layer 21. Note that the insulating layer 32 is not shown in FIG. 2A to make it easier to see the configuration of the multiple wiring patterns 2.

[0011] The conductor layer 21 includes a plurality of wiring patterns 2. As shown in FIG. 2A, the wiring patterns 20 of the plurality of wiring patterns 2 are arranged in parallel in a direction (X direction) that is approximately perpendicular to the direction in which the wiring patterns 20 extend (Y direction). That is, each wiring pattern 20 of the plurality of wiring patterns 2 extends in the Y direction along the adjacent wiring patterns 20, and is arranged with a gap S between each adjacent wiring pattern 20 in the X direction. The spaces between the plurality of wiring patterns 2, i.e., the spaces between the wiring patterns 20, are filled with an insulating layer 32 as shown in FIGS. 1 and 2B.

[0012] In the description of the wiring board 1 shown in FIGS. 1 to 2B, the insulating layer 32 side in the lamination direction of the insulating layers 31 and 32 is also referred to as the "upper side" or simply "top", and the insulating layer 31 side is also referred to as the "upper side" or simply "top". It is also referred to as the "lower side" or simply "bottom." That is, insulating layer 32 is an upper insulating layer with respect to insulating layer 31, and insulating layer 31 is a lower insulating layer with respect to insulating layer 32. The stacking direction of insulating layer 31 and insulating layer 32, i.e., the thickness direction of wiring board 1, is the thickness direction of the multiple wiring patterns 2 (or the height direction of each wiring pattern 20), and is also referred to as the "Z direction."

[0013] In one example, the wiring board 1 of the embodiment has a rectangular shape with each side having a length of 80 μm or more and 240 μm or less in plan view. The wiring board of the embodiment may have a planar shape of such size, but by using direct imaging exposure, which will be described later, each conductor pattern of the conductor layer 21 can be formed relatively easily. Note that "planar view" means viewing an object from a line of sight along the Z direction.

[0014] Each wiring pattern 20 of the plurality of wiring patterns 2 may be a conductor pattern designed and used to apply a voltage, pass a current, supply power, or transmit an electrical signal from an arbitrary position on the wiring board 1 in a plan view to another arbitrary position different from the arbitrary position. However, the functions of each wiring pattern 20 are not limited to these.

[0015] 1 to 2B, the conductor layer 21 is composed of a metal film 2a in contact with the surface 31a of the insulating layer 31 and a plating film 2b in contact with the metal film 2a. Accordingly, each wiring pattern 20 of the plurality of wiring patterns 2 is also composed of a metal film 2a and a plating film 2b. Note that in the wiring board of the embodiment, the conductor layer 21 and each wiring pattern 20 do not have to be composed of two stacked conductor films as shown in FIG. 1, etc., and may be composed of a single conductor film.

[0016] 3 and 4, which will be referred to later, the conductor layer 21 in the wiring board of the embodiment may include a plurality of wiring patterns 2, each consisting of more than four individual wiring patterns 20. A conductor layer such as the conductor layer 21 provided in the wiring board of the embodiment may include a plurality of wiring patterns, each consisting of any number of individual wiring patterns, equal to or greater than two. In this case, each of the two or more wiring patterns extends along the adjacent wiring patterns and is arranged in parallel with the adjacent wiring patterns at intervals in a direction substantially perpendicular to the direction in which each wiring pattern extends.

[0017] The insulating layer 31 and the insulating layer 32 are mainly formed of any insulating resin. Examples of insulating resins used to form the insulating layer 31 and the insulating layer 32 include thermosetting resins such as epoxy resin, bismaleimide triazine resin (BT resin), and phenolic resin, as well as thermoplastic resins such as fluororesin, liquid crystal polymer (LCP), fluoroethylene (PTFE) resin, polyester (PE) resin, and modified polyimide (MPI) resin. The insulating layer 31 and the insulating layer 32 may further contain a filler made of, for example, silicon oxide, alumina, or mullite. Note that the resins listed above are merely examples of materials that can form the insulating layer 31 or the insulating layer 32. The insulating layer 31 and the insulating layer 32 can be formed of any material that provides insulation to the conductor layer 21 and can support or cover the conductor layer 21.

[0018] The conductor layer 21 is formed of any metal having suitable conductivity. Examples of materials for the conductor layer 21 include copper and nickel. However, the material for the conductor layer 21 is not limited to these metals. In the example shown in FIG. 1 , the conductor layer 21 has a two-layer structure including a metal film 2a and a plating film 2b, as described above. The metal film 2a is, for example, a plating film formed by electroless plating or a sputtering film formed by sputtering. On the other hand, the plating film 2b is, for example, a metal film formed by electrolytic plating using the metal film 2a as a power supply layer. The plating film 2b is preferably formed by pattern plating using a plating resist having a suitable opening pattern. Unlike the example shown in FIG. 1 , the conductor layer 21 may be formed of only one metal film formed by pattern plating using electroless plating.

[0019] In the wiring board 1 of the embodiment, the minimum value of the spacing S between the wiring patterns 20 included in the plurality of wiring patterns 2 is 3 μm or less. Furthermore, the minimum value of the width L of each wiring pattern 20 included in the plurality of wiring patterns 2 may be 3 μm or less. That is, the plurality of wiring patterns 2 may be multiple wiring patterns designed according to a fine wiring rule of 3 μm / 3 μm or less, where the wiring rule is expressed as L / S (line and space) using the minimum wiring width L and the minimum wiring spacing S. In other words, the plurality of wiring patterns 2 include at least two adjacent wiring patterns 20 spaced 3 μm or less apart, and may further include a wiring pattern 20 having a width of 3 μm or less. Therefore, the wiring board 1 of the embodiment may include multiple wirings arranged at an extremely fine pitch in light of the wiring pitch levels that wiring provided on wiring boards designed or manufactured at the time of this disclosure may have.

[0020] Furthermore, the minimum value of the width L of each wiring pattern 20 of the multiple wiring patterns 2 may be 1 μm or more, and the minimum value of the spacing S between the wiring patterns 20 may be 1 μm or more. That is, the multiple wiring patterns 2 may include at least two wiring patterns 20 adjacent to each other with a spacing of 1 μm or more and 3 μm or less, and may include a wiring pattern 20 having a width of 1 μm or more and 3 μm or less.

[0021] In the description of the wiring board of the embodiment, the "width" of each wiring pattern 20 included in the plurality of wiring patterns 2 is the largest width among the widths at any position between the top and bottom ends of each wiring pattern 20 in the thickness direction (Z direction) of the plurality of wiring patterns 2. For example, the width of each wiring pattern 20 may be the width of each wiring pattern 20 at the center in the Z direction. In addition, when each wiring pattern 20 is composed of a metal film 2a and a plating film 2b as in the example of FIG. 1, the width of each wiring pattern 20 may be the width of each wiring pattern 20 at the center of the plating film 2b in the Z direction.

[0022] Meanwhile, in the description of the wiring board of the embodiment, the "spacing" between the individual wiring patterns 20 of the multiple wiring patterns 2 is the smallest spacing between the individual wiring patterns 20 at any position between the top and bottom of each wiring pattern 20 in the Z direction. For example, the spacing S between the individual wiring patterns 20 may be the spacing between the individual wiring patterns 20 at the center in the Z direction. Note that when each wiring pattern 20 is composed of a metal film 2a and a plating film 2b as in the example of FIG. 1, the spacing between the individual wiring patterns 20 may be the spacing between the individual wiring patterns 20 at the center of the plating film 2b in the Z direction.

[0023] In the wiring board 1 of the embodiment, the multiple wiring patterns 2 may further include wiring patterns 20 having an aspect ratio of 2 or greater. That is, the maximum aspect ratio of each wiring pattern 20 is 2 or greater. The maximum aspect ratio of each wiring pattern 20 may be 2 or greater and 5 or less. That is, the multiple wiring patterns 2 may include wiring patterns 20 having an aspect ratio of 2 or greater and 5 or less. In this way, the multiple wiring patterns 2 may include one or more wiring patterns 20 that are fine yet have a large cross-section and therefore relatively low conductor resistance. Therefore, the wiring board 1 of the embodiment may include wiring that is fine and has relatively high conductivity for its fine wiring width.

[0024] In the description of the wiring board of the embodiment, the aspect ratio of each wiring pattern 20 of the multiple wiring patterns 2 is the ratio of the height of each wiring pattern 20 (the length of each wiring pattern 20 in the Z direction) to the “width” of each wiring pattern 20.

[0025] 2B, in the wiring board 1 of the embodiment, the wiring patterns 20 constituting the plurality of wiring patterns 2 have a width L1 at the end 20a on the insulating layer 31 side in the stacking direction (Z direction) of the insulating layer 31 and the conductor layer 21, which is smaller than the width L at the center in the Z direction. Therefore, when the conductor layer 21 is formed by pattern plating so that a fine wiring pattern 20 can be formed during the manufacture of the wiring board 1 of the embodiment, a resist wall having a large contact area with the underlying metal film 2a or insulating layer 31 can be provided.

[0026] That is, a resist wall that contacts the metal film 2 or the insulating layer 31 over a large area can be provided as a plating resist between adjacent wiring pattern 20 formation regions. Even if the width of the central portion of the wiring pattern 20 in the Z direction is small, a resist wall having a contact area corresponding to the width larger than the width can be formed. Therefore, it is believed that the plating resist can maintain an appropriate state without collapsing or peeling during the formation of the conductor layer 21. That is, it is believed that multiple wiring patterns 2 arranged at extremely fine wiring intervals in the central portion can be formed with good yield. Therefore, it is believed that the wiring board of the embodiment can be provided with fine wiring while maintaining good productivity.

[0027] In particular, in the wiring board of the embodiment, as described above, the multiple wiring patterns 2 include at least two wiring patterns 20 adjacent to each other with an interval of 3 μm or less, and may include a wiring pattern 20 having a width of 3 μm or less. The multiple wiring patterns 2 may further include a wiring pattern 20 having an aspect ratio of 2 or more. In this way, the wiring board of the embodiment can be provided with fine wiring that has relatively high conductivity for its fine wiring width, while also achieving good productivity in which the occurrence of defects during manufacturing is suppressed.

[0028] In addition, as in the example of Figures 1 to 2B, when the wiring pattern 20 is composed of a metal film 2a and a plating film 2b formed by electrolytic plating using the metal film 2a as a power supply layer, the "center" of the wiring pattern 20 in the Z direction means the center of the plating film 2b in the Z direction.

[0029] In the wiring board of the embodiment, all of the wiring patterns 20 of the multiple wiring patterns 2 may have a width at the end 20a in the Z direction that is smaller than the width at the center. Alternatively, only some of the wiring patterns 20 of the multiple wiring patterns 2 may have a width at the end 20a in the Z direction that is smaller than the width at the center. That is, in the wiring board of the embodiment, at least one wiring pattern 20 of the multiple wiring patterns 2 has a width at the end 20a in the Z direction that is smaller than the width at the center. A resist wall that is less likely to collapse or peel off can be provided as a resist wall for forming the at least one wiring pattern 20. Therefore, the wiring board of the embodiment may be provided with at least one fine wiring that has relatively high conductivity for its fine wiring width, while also achieving good productivity by suppressing the occurrence of defects during manufacturing.

[0030] 2B, the ratio of the width L1 at the end 20a to the width L at the center is 80% or more and 95% or less. This can provide the effect of suppressing the collapse and peeling of the resist wall described above, and may also provide the desired conductivity in the wiring pattern 20.

[0031] The thickness of the conductor layer 21 may be 2 μm or more and 5 μm or less. It is believed that the desired conductivity can be obtained in the wiring pattern 20, and collapse of the wiring pattern and collapse of the resist wall during the formation of the wiring pattern 20 are unlikely to occur.

[0032] As shown in FIG. 2B, in the wiring board 1, a wiring pattern 20 having a smaller width at an end 20a in the Z direction than at its center has a smaller width at an end 20b opposite the end 20a in the Z direction than at its center. That is, in the wiring board 1 illustrated in FIG. 1 and the like, a wiring pattern 20 having a smaller width at an end 20a than at its center has a smaller width at both ends in the Z direction than at its center in the Z direction. Therefore, the side surfaces 20s of the wiring pattern 20 having a smaller width at the end 20a than at its center are curved so as to bulge outward from the wiring pattern 20 at the center in the Z direction of the wiring pattern 20. In other words, the portions between the plurality of wiring patterns 2 in the insulating layer 32 (the upper insulating layer relative to the insulating layer 31) are constricted at the center in the Z direction.

[0033] 1 to 2B, the plating film 2b constituting each wiring pattern 20 may have a relatively smooth side surface. For example, the side surface of the portion of each of the plurality of wiring patterns 2 that is constituted by the plating film 2b (i.e., part of the side surface 20s of the wiring pattern 20) may have a surface roughness of 0.01 μm or more and 0.2 μm or less in arithmetic mean roughness (Ra). For example, in the transmission of high-frequency signals, the degradation of transmission characteristics due to the skin effect may be small.

[0034] As mentioned above, the plating film 2b is preferably formed by pattern plating. Therefore, the side surfaces of the plating film 2b can have a surface roughness within the above range, which is smoother than the side surfaces of conductive patterns formed by subtractive methods. In other words, the side surfaces of the portions of the multiple wiring patterns 2 that are formed by the plating film 2b are not dissolved surfaces exposed by etching, but may be contact surfaces with the plating resist and deposited surfaces of the plating metal that are exposed when the plating resist is removed.

[0035] On the other hand, as described above, the metal film 2a may be an electroless plating film or a sputtering film. In particular, if the metal film 2a is a sputtering film, the metal film 2a is likely to have a thin and uniform thickness. Therefore, in forming the conductor layer 21 by a semi-additive method including pattern plating, when the portions of the metal film 2a that are not covered by the plating film 2b are removed after the pattern plating, the exposed portions of the metal film 2a are likely to be removed in a short time by, for example, quick etching. Therefore, the plating film 2b already formed by electroplating is likely to be less susceptible to the effects of this quick etching.

[0036] First Embodiment FIG. 3 shows a cross-sectional view of a wiring board 1a, which is an example of a wiring board according to the first embodiment. Similar to the wiring board 1 of FIG. 1, the wiring board 1a includes an insulating layer 31 and a conductor layer 21 laminated on a surface 31a of the insulating layer 31. Similar to the conductor layer 21 of the wiring board 1 of FIG. 1, the conductor layer 21 includes multiple wiring patterns 2, each of which includes parallel wiring patterns 20. As shown in FIG. 3, the wiring board 1a of this embodiment includes multiple insulating layers 31 and multiple conductor layers 21, and each insulating layer of the multiple insulating layers 31 and each conductor layer of the multiple conductor layers 21 are alternately laminated. The wiring board 1a of FIG. 3 includes four insulating layers 31 and four conductor layers 21. Note that each insulating layer 31 is depicted above the conductor layer 21 formed on the surface 31a of each insulating layer 31. That is, in FIG. 3, a pair of insulating layer 31 and conductor layer 21 is depicted as if the insulating layer 31 and conductor layer 21 in FIG. 1 were rotated 180°.

[0037] The wiring board 1a has two surfaces (a first surface 1F and a second surface 1B opposite to the first surface 1F) that are perpendicular to the thickness direction. In addition to a plurality of insulating layers 31 and a plurality of conductor layers 21, the wiring board 1a also includes a conductor layer 22 exposed on the first surface 1F, a conductor layer 23 exposed on the second surface 1B, and an insulating layer 32 exposed on the second surface 1B. In the description of the wiring board 1a, the second surface 1B side of the wiring board 1a is also referred to as the "upper side" or simply "top".

[0038] That is, in wiring board 1a, conductor layer 22 is provided on first surface 1F, and on conductor layer 22, the insulating layers of four insulating layers 31 and the conductor layers of four conductor layers 21 are alternately stacked toward second surface 1B. Then, insulating layer 32 is formed to cover insulating layer 31 and conductor layer 21 closest to second surface 1B, and conductor layer 23 is formed on the surface of insulating layer 32. In this way, wiring board 1a includes laminate 10 of multiple conductor layers and multiple insulating layers.

[0039] In the wiring board 1a of FIG. 3, the multiple wiring patterns 2 included in each of the multiple conductor layers 21 include adjacent wiring patterns 20 spaced at intervals of 3 μm or less. The multiple wiring patterns 2 include wiring patterns 20 having widths of 3 μm or less, and may also include wiring patterns 20 having an aspect ratio of 2 or greater. Although not explicitly shown in FIG. 3, each wiring pattern 20 has a width smaller at its end in the thickness direction (Z direction) of the wiring board 1a than at its central portion in the Z direction, similar to the wiring pattern 20 shown in FIG. 1. Each wiring pattern 20 has a width smaller at its end in the Z direction, at least on the first surface 1F side, than at its central portion. Therefore, the wiring board 1a of this embodiment is considered to be capable of providing fine wiring that has relatively high conductivity for its fine wiring width, while maintaining good productivity.

[0040] Conductor layers facing each other across an insulating layer in wiring board 1a are connected by via conductors 11c. Conductor layer 22 and conductor layer 23 each include an arbitrary conductor pattern. Conductor layer 22 includes a conductor pad 22p, and conductor layer 23 includes a conductor pad 23p. An external component (not shown) may be mounted on and connected to conductor pad 22p when wiring board 1a is in use. In other words, conductor pad 22p may be a component mounting pad, and therefore wiring board 1a shown in FIG. 3 may have a component mounting surface formed by first surface 1F.

[0041] On the other hand, the second surface 1B of the wiring board 1a is a surface that can be connected, when the wiring board 1a is in use, to a motherboard of an electronic device in which the wiring board 1a is used or to a rewiring board of a semiconductor package in which the wiring board 1a is used. The wiring board 1a may further include, on the first surface 1F and / or the second surface 1B, a solder resist (not shown) having openings that expose the conductor pads 22p or the conductor pads 23p.

[0042] The insulating layers 31 and 32 of the wiring board 1a are made of a resin similar to the insulating resin described above as the constituent material of the insulating layers 31 and 32 of the wiring board 1 in Fig. 1, for example, a thermosetting resin such as an epoxy resin, a BT resin, or a phenolic resin, or a thermoplastic resin such as a fluororesin or an LCP. The insulating layers 31 and 32 of the wiring board 1a may further contain a filler made of, for example, silicon oxide.

[0043] The conductor layers 21-23 and the via conductor 11c are formed of any metal having suitable conductivity, such as copper or nickel, similar to the conductor layer 21 of the wiring board 1 in Fig. 1. In Fig. 3, the conductor layers 21-23 are each depicted as a single layer for ease of viewing, and the via conductor 11c is also depicted as a single layer. However, the conductor layers 21-23 and the via conductor 11c may have a multilayer structure including two or more metal films formed by any method, such as sputtering or electrolytic or electroless plating.

[0044] Second Embodiment Fig. 4 shows a cross-sectional view of wiring board 1b, which is an example of a wiring board according to the second embodiment. As shown in Fig. 4, wiring board 1b includes a laminate 11 (first buildup layer) of multiple conductor layers and multiple insulating layers, and buildup layer 12 (second buildup layer) formed by a laminate of insulating layer 12a and conductor layer 12b. Wiring board 1b in Fig. 4 further includes buildup layer 13 (third buildup layer) formed by a laminate of insulating layer 13a and conductor layer 13b.

[0045] Similar to the laminate 10 constituting the wiring board 1a in Fig. 3, the laminate 11 includes one or more conductor layers 21 and one or more insulating layers 31. In the example of Fig. 4, the laminate 11 includes four conductor layers 21 and four insulating layers 31. Each insulating layer 31 has an individual conductor layer 21 formed on its surface 31a. Similar to the conductor layer 21 of the wiring board 1 in Fig. 1, each conductor layer 21 includes a plurality of wiring patterns 2, and the plurality of wiring patterns 2 include parallel wiring patterns 20.

[0046] The wiring board 1b in FIG. 4 has a first surface 11F corresponding to the first surface 1F of the wiring board 1a in FIG. 3, and also has a second surface 13S that is the opposite surface to the first surface 11F. In the description of the wiring board 1b, the second surface 13S side of the wiring board 1b is also referred to as the "upper side" or simply "top." The buildup layer 12 is laminated on the laminate 11. The buildup layer 13 is laminated on the buildup layer 12.

[0047] In the wiring board 1b of FIG. 4, the multiple wiring patterns 2 included in each of the multiple conductor layers 21 include adjacent wiring patterns 20 spaced at intervals of 3 μm or less. The multiple wiring patterns 2 include wiring patterns 20 having widths of 3 μm or less, and may also include wiring patterns 20 having an aspect ratio of 2 or greater. Although not explicitly shown in FIG. 4, each wiring pattern 20 has a width smaller at its end in the thickness direction (Z direction) of the wiring board 1b than at its central portion in the Z direction, similar to the wiring pattern 20 shown in FIG. 1. Each wiring pattern 20 has a width smaller at its end in the Z direction, at least on the first surface 11F side, than at its central portion. Therefore, the wiring board 1b of this embodiment is considered to be capable of providing fine wiring that has relatively high conductivity for its fine wiring width, while maintaining good productivity.

[0048] In the build-up layer 12, insulating layers 12a and conductor layers 12b are alternately stacked. Via conductors 12c are formed in the insulating layers 12a, penetrating each insulating layer 12a and connecting opposing conductor layers via each insulating layer 12a. Each conductor layer 12b includes a desired conductor pattern.

[0049] The buildup layer 13 includes an insulating layer 13a formed on the insulating layer 12a and the conductor layer 12b of the buildup layer 12, and a conductor layer 13b formed on the surface of the insulating layer 13a facing the second surface 13S of the wiring board 1b. Via conductors 13c are formed in the insulating layer 13a, penetrating the insulating layer 13a and connecting the conductor layer 13b to the conductor layer 12b of the buildup layer 12. The conductor layer 13b may include a desired conductor pattern. In the example of FIG. 4, the conductor layer 13b includes conductor pads 13p.

[0050] The wiring board 1b in the example of FIG. 4 further includes a solder resist layer 14 formed on the second surface 13S. The solder resist layer 14 is formed using, for example, a photosensitive polyimide resin or an epoxy resin. Openings 14a are formed in the solder resist layer 14. Conductor pads 13p of the conductor layer 13b are exposed through the openings 14a.

[0051] The second surface 13S of the wiring board 1b is the surface that is connected to an external member (not shown) such as a motherboard of an electronic device in which the wiring board 1b is used when the wiring board 1b is in use. The conductor pads 13p may be connected to any substrate, electrical component, or mechanical component.

[0052] The insulating layer 12a constituting the buildup layer 12 and the insulating layer 13a of the buildup layer 13 may be formed using the same insulating resin as the insulating layer 31. Although not shown, the insulating layer 12a may include a core material (reinforcing material) made of glass fiber or aramid fiber. In the example of FIG. 4, the insulating layer 13a of the buildup layer 13 includes a core material 13aa made of glass fiber. The insulating layer 12a and the insulating layer 13a may further include an inorganic filler (not shown) made of fine particles such as silica (SiO2), alumina, or mullite. In the wiring board 1b, the thickness of the insulating layer 12a may be thicker than the thickness of the insulating layer 31, and the thickness of the insulating layer 13a may be thicker than the thickness of the insulating layer 12a.

[0053] Like conductor layer 21 and via conductor 11c, conductor layer 12b of buildup layer 12, conductor layer 13b of buildup layer 13, and via conductors 12c and 13c may be formed using any metal such as copper or nickel. Conductor layer 12b, conductor layer 13b, and via conductors 12c and 13c may each have a single layer made of, for example, a plated film, as in the example of FIG. 4, or may have a multilayer structure including two or more metal films formed by any method, such as sputtering or various plating processes. In wiring board 1b, conductor layer 12b may be thicker than conductor layer 21, and conductor layer 13b may be thicker than conductor layer 12b.

[0054] In wiring board 1b, when conductor layer 12b includes two or more wiring patterns, the width of the wiring patterns may be larger than the width of wiring pattern 20 of conductor layer 21, and the spacing between the wiring patterns included in conductor layer 12b may be larger than the spacing between wiring patterns 20 of conductor layer 21. Furthermore, when conductor layer 12b and conductor layer 13b each include two or more wiring patterns, the width of the wiring patterns included in conductor layer 13b may be larger than the width of the wiring patterns included in conductor layer 12b, and the spacing between the wiring patterns included in conductor layer 13b may be larger than the spacing between wiring patterns included in conductor layer 12b. This allows a large current to flow through the wiring patterns of conductor layer 12b and conductor layer 13b, and may enable conductor layers 12b and 13b to be formed easily and inexpensively.

[0055] <Method for manufacturing wiring board according to embodiment> 5A to 5L, an example of a method for manufacturing a wiring board according to an embodiment will be described using the case where the wiring board 1b shown in Fig. 4 is manufactured as an example. Note that the materials described for the components of the wiring boards 1, 1a, and 1b according to the embodiment can be used as the materials for the corresponding components in the method for manufacturing a wiring board according to the embodiment, even if they are not explicitly stated again in the following description.

[0056] As shown in Figure 5A, a support substrate SP is prepared, which includes a core layer GS and metal film layers ML1 and ML2 laminated on both sides of the core layer GS. The core layer GS is made of, for example, glass or glass epoxy material. The metal film layers ML1 and ML2 are metal layers formed by electroless plating or sputtering using, for example, copper or titanium. The metal film layers ML1 and ML2 are bonded together by an adhesive layer AL made of, for example, an adhesive whose adhesiveness changes when irradiated with light.

[0057] In the following description, the side of the support substrate SP closer to the core layer GS is also referred to as the "bottom" or "lower side," and the side farther from the core layer GS is also referred to as the "top" or "upper side." Therefore, the surface of each component of the manufactured wiring board that faces the support substrate SP is also referred to as the "bottom surface," and the surface that faces the opposite side to the support substrate SP is also referred to as the "upper surface."

[0058] As shown in FIG. 5B, a conductor layer 22 including a plurality of conductor pads 22p is formed on a support substrate SP. To form the conductor layer 22, for example, a resist film (not shown) is formed on the metal film layer ML2. A plating resist is formed by forming openings in the resist film corresponding to the formation areas of the conductor pads 22p using photolithography. A plating film is formed in the openings of the plating resist by electrolytic plating using the metal film layer ML2 as a power supply layer. The plating resist is then removed. The conductor layer 22 shown in FIG. 5B is obtained.

[0059] 5B, as well as 5C, 5F, and 5I to 5L, which will be referred to below, show only one surface side of the support substrate SP after each process, and the state of the other surface side is not shown. However, on the surface of the support substrate SP on the side not shown, each insulating layer and each conductor layer may be formed, as on the side shown in the drawings, or such conductor layers and insulating layers may not be formed.

[0060] An insulating layer 31 is formed to cover the conductor layer 22. The insulating layer 31 is formed of, for example, a thermosetting resin such as epoxy resin, BT resin, or phenolic resin, or a thermoplastic resin such as fluororesin or LCP. The insulating layer 31 is formed by thermocompression bonding these resins formed into a film shape. In the insulating layer 31, through holes 11d are formed at the positions where the via conductors 11c (see FIG. 5I) are to be formed by, for example, irradiation with a carbon dioxide laser beam or an excimer laser beam. Although not shown, the formation of the through holes 11d may be performed while protecting the upper surface of the insulating layer 31 with a protective film such as a polyethylene terephthalate (PET) film. Preferably, after the formation of the through holes 11d, resin residues (smears) that tend to form in the through holes 11d are removed by dry desmearing using plasma gas or wet desmearing using a permanganate solution.

[0061] After the through holes 11d are formed, a plurality of parallel wiring patterns 2 (see FIG. 5I) are formed on the surface 31a of the insulating layer 31 through the steps shown in FIGS. 5B to 5I. First, as shown in FIG. 5B, a metal film 2a is formed by sputtering on the inner walls of the through holes 11d and on the surface 31a of the insulating layer 31. Sputtering can easily form a thin metal film 2a with a uniform thickness. The metal film 2a may also be formed by a method other than sputtering, such as electroless plating.

[0062] Then, in forming the multiple wiring patterns 2, as shown in FIGS. 5C to 5F, multiple parallel resist walls 4 (see FIG. 5F) are formed on the surface 31a of the insulating layer 31 with the metal film 2a interposed therebetween. In forming the multiple resist walls 4, first, as shown in FIG. 5C, a photosensitive resist layer 40 is formed on the surface 31a of the insulating layer 31 with the metal film 2a interposed therebetween. The resist layer 40 is a plating resist that functions against the deposition of plating metal. The resist layer 40 is formed, for example, by laminating a dry film containing a photosensitive epoxy resin on the metal film 2a.

[0063] Then, the resist layer 40 is exposed and developed, thereby forming openings 4a (see FIG. 5E) in the resist layer 40. The exposure of the resist layer 40 is preferably performed by direct imaging, as shown in FIG. 5C. That is, the resist layer 40 is directly irradiated with laser light LZ along a pattern corresponding to the multiple wiring patterns 2 (see FIG. 5I) without using an exposure mask. In direct imaging, the focal depth of the laser light LZ is relatively deep, so the influence of undulations on the surface 31a of the insulating layer 31 on the exposure of the resist layer 40 is small. In addition, in direct imaging, the position in the Z direction where the laser light LZ is focused can be adjusted depending on the irradiation position of the laser light LZ. Therefore, it may be possible to accurately form minute openings in the resist layer 40. Furthermore, direct imaging may be able to expose a wider area in a single exposure process compared to when an exposure mask is used. For example, in the manufacture of a wiring board having a rectangular planar shape with sides of 80 mm to 240 mm, it may be possible to efficiently form openings in the resist layer 40.

[0064] In direct imaging exposure of the resist layer 40, as shown in FIG. 5D, laser light LZ is sequentially irradiated onto regions (opening formation regions 4b) of the resist layer 40 where openings 4a (see FIG. 5E) are to be formed. That is, FIG. 5D shows an example in which exposure is performed on a positive resist layer 40 whose solubility in a developer increases upon exposure. In FIG. 5D, low-density dot hatching on the resist layer 40 indicates portions whose solubility has increased upon exposure. Note that FIGS. 5D, 5E, 5G, and 5H show enlarged views of only the regions where four wiring patterns 20 (see FIG. 5H) are to be formed.

[0065] When exposing the positive resist layer 40, by focusing the laser light LZ at a desired position in the thickness direction of the resist layer 40, i.e., the thickness direction (Z direction) of the wiring board to be manufactured, the area that responds to the exposure can be increased around that position. That is, the area where solubility is increased around a specific position in the Z direction can be made larger than the areas around other positions where the laser light LZ is not focused. Therefore, by focusing the laser light LZ at the center of the thickness direction of the resist layer 40, the area where solubility is increased in the resist layer 40 can be made larger at the center in the Z direction than at both ends in the Z direction, as in the leftmost opening formation region 4b in FIG. 5D. In this way, the exposure of the resist layer 40 may include converging the light used for exposure, such as the laser light LZ, at the center of the thickness direction of the resist layer 40.

[0066] After the resist layer 40 is exposed, i.e., the opening formation region 4b is irradiated with laser light LZ, the portions of the resist layer 40 whose solubility has increased due to the exposure are removed by development using, for example, an alkaline solution. As a result, as shown in FIGS. 5E and 5F , a plurality of parallel resist walls 4 are formed with the openings 4a interposed therebetween. By performing exposure as described with reference to FIG. 5D , the resist walls 4 are formed such that the end 41 of each resist wall 4 on the insulating layer 31 side in the height direction (Z direction) has a width W1 that is larger than the width W at the center in the Z direction. Because the resist wall 4 has a width W1 that is larger at the end 41 on the insulating layer 31 side than the width W at the center, even if the width W at the center is small, the contact area between the resist wall 4 and the metal film 2a is relatively large, and therefore, it is considered that the resist wall 4 is less likely to collapse or peel off.

[0067] Thus, forming the multiple resist walls 4 in the wiring board manufacturing method of the embodiment includes forming the multiple resist walls 4 at the end 41 on the insulating layer 31 side in the Z direction, each of the multiple resist walls 4, with a width W1 that is larger than the width W at the center. Forming the multiple resist walls 4 may further include forming a positive photosensitive resist layer 40 on the surface 31a of the insulating layer 31 and patterning at least a portion of the resist layer 40 into the multiple resist walls 4. Forming the photosensitive resist layer 40 can easily form multiple openings and multiple adjacent resist walls 4 via the individual openings. Furthermore, forming the positive resist layer 40 can sometimes easily form the resist walls 4 at the end 41 on the insulating layer 31 side, with a width W1 that is larger than the width W at the center in the Z direction.

[0068] 5E, the resist wall 4 has a width W1 at the end 41 on the insulating layer 31 side in the Z direction that is larger than the width W at the center, and the resist wall 4 has a width larger at both ends in the height direction than at the center. Therefore, in the example of FIG. 5E, the resist wall 4 has a constriction at the center in the height direction of the resist wall 4.

[0069] Unlike the example of FIG. 5E , in the method for manufacturing a wiring board according to the embodiment, the end 41 on the insulating layer 31 side in the Z direction has a larger width than the central portion, but the end opposite the end 41 may have substantially the same width as the central portion. For example, in the direct imaging exposure described with reference to FIGS. 5C and 5D , the exposure laser light LZ may be focused over the entire range from the central portion to the top surface of the resist layer 40 in the thickness direction. This may allow the formation of a resist wall 4 at the end opposite the end 41 that has substantially the same width as the central portion. Even in this case, the contact area between the end 41 and the metal film 2a is relatively large, so it is believed that the resist wall 4 is less likely to collapse or peel off.

[0070] 5E, all of the resist walls 4 have a width W1 at the end 41 on the insulating layer 31 side that is larger than the width W at the center. However, when forming a plurality of resist walls 4, only one resist wall 4 may be formed that has a width W1 at the end 41 on the insulating layer 31 side that is larger than the width W at the center.

[0071] In the method for manufacturing a wiring board according to the embodiment, the metal film 2a is not necessarily provided, and the resist layer 40 may be formed directly on the surface 31a of the insulating layer 31. Therefore, the resist wall 4 may be formed directly on the surface 31a of the insulating layer 31.

[0072] The multiple resist walls 4 are preferably two or more resist walls arranged at a fine pitch and having a high ratio of height to width. Forming such resist walls 4 may enable the formation of a fine wiring pattern 20 with low conductor resistance. For example, the multiple resist walls 4 may be two or more resist walls each having a width W of 3 μm or less. Alternatively, the multiple resist walls 4 may be formed such that the ratio of height H to width W is 3 or more, and adjacent resist walls may be formed at an interval G of 3 μm or less.

[0073] In addition, when the position in the Z direction is not specified, the "width" of each of the multiple resist walls 4 is the smallest width among the widths at any position between one end of the resist wall 4 and the other end in the Z direction. For example, the width of the resist wall 4 may be the width of the resist wall 4 at the center in the Z direction. On the other hand, the "spacing" between the individual resist walls 4 of the multiple resist walls 4 is the largest spacing among the spacings between the resist walls 4 at any position between one end of each resist wall 4 and the other end in the Z direction. For example, the spacing G between the individual resist walls 4 may be the spacing between the individual resist walls 4 at the center in the Z direction.

[0074] As shown in FIG. 5F, in addition to the plurality of resist walls 4 and the openings 4a interposed between the resist walls 4, openings 4c and resist walls 4d for forming each conductor pattern of the conductor layer 21 (see FIG. 5I) are also formed.

[0075] After the resist walls 4 are formed, as shown in FIG. 5G, plating films 2b are formed in the openings 4a between the parallel resist walls 4. The plating films 2b are formed by pattern plating using the resist layer 40 as a mask. When the metal film 2a is formed as shown in FIG. 5G, the plating films 2b are preferably formed by electrolytic plating using the metal film 2a as a power supply layer. Although not shown in FIG. 5G, plating films 2b are also formed in openings 4c (see FIG. 5F) other than the openings 4a in the resist layer 40, forming various conductor patterns such as via conductors 11c (see FIG. 5I).

[0076] After the plating film 2b is formed, the resist layer 40 including the resist walls 4 is removed using, for example, an alkaline stripping solution. Furthermore, the portion of the metal film 2a exposed by removing the resist layer 40 is removed by, for example, quick etching.

[0077] As a result, a conductor layer 21 including a plurality of wiring patterns 2 is formed as shown in FIGS. 5H and 5I. Via conductors 11c that penetrate the insulating layer 3 are also formed. The plurality of wiring patterns 2 are made up of wiring patterns 20 that are separated from one another and arranged in parallel. The wiring patterns 20 are composed of a metal film 2a and a plating film 2b. The wiring pattern 20 has a width L1 at the end 20a on the insulating layer 31 side that is smaller than the width L at the center in the Z direction.

[0078] As shown in Fig. 5J, a desired number of insulating layers 31 and conductor layers 21 (three layers each in Fig. 5J) are further formed using a method similar to the previously described method for forming insulating layer 31, conductor layer 21, and via conductor 11c, as well as via conductor 11c penetrating each insulating layer. Then, an insulating layer 32 is formed on the formed insulating layer 31 and conductor layer 21 using, for example, a method similar to the method for forming insulating layer 31. Furthermore, a conductor layer 23 is formed on the surface of insulating layer 32 using, for example, a general semi-additive method. Also, via conductors 11c penetrating insulating layer 32 are formed together with conductor layer 23.

[0079] As shown in FIG. 5K, the build-up layer 12 is formed. That is, a desired number of insulating layers 12a and conductor layers 12b are alternately stacked on the conductor layer 23 and the insulating layer 32. In FIG. 5K, three pairs of insulating layers 12a and conductor layers 12b are stacked. In each insulating layer 12a, via conductors 12c are formed to connect the upper and lower conductor layers. The insulating layer 12a is formed, for example, by a method similar to the method for forming the insulating layer 31 described above. In forming the insulating layer 12a, a resin containing a core material molded into a sheet shape, such as a prepreg, may be used instead of a film-shaped resin. The conductor layer 12b and the via conductors 12c are formed using any method, for example, a semi-additive method.

[0080] The buildup layer 13 is formed on the uppermost insulating layer 12a and conductor layer 12b of the buildup layer 12. First, the insulating layer 13a is formed using a method similar to that for the insulating layer 12a. In the example of FIG. 5K, the insulating layer 13a is formed using a prepreg including a core material 13aa made of, for example, glass fiber. A prepreg with copper foil may also be used. Through holes are formed in the insulating layer 13a by irradiation with laser light or drilling at positions where the via conductors 13c will be formed. Then, the conductor layer 13b is formed on the surface of the insulating layer 13a, and the via conductors 13c are formed in the through holes of the insulating layer 13a. The conductor layer 13b and the via conductors 13c are formed by any method, such as a semi-additive method or a subtractive method.

[0081] After the build-up layer 13 is formed, a solder resist layer 14 is formed on the surfaces of the insulating layer 13a and the conductor layer 13b using a photosensitive epoxy resin or polyimide resin, and openings 14a that define the conductor pads 13p are then formed by photolithography.

[0082] As shown in FIG. 5L, the core layer GS of the support substrate SP is removed. The lower surface of the metal film layer ML2 below the conductor pads 22p is exposed. When removing the support substrate SP, for example, the adhesive layer AL is softened by irradiation with laser light, and then the metal film layer ML2 is peeled off from the adhesive layer AL. The metal film layer ML2 is then removed by etching, exposing the lower surfaces of the conductor pads 22p and the insulating layer 31. The wiring board 1b shown in FIG. 4 is completed.

[0083] The wiring board of the embodiment is not limited to those having the structure illustrated in each drawing and the structure, shape, and material illustrated in this specification. As described above, the wiring board of the embodiment may have any laminated structure. The wiring board of the embodiment may have any number of conductor layers and insulating layers. Each conductor layer may include any conductor pattern other than the multiple wiring patterns. The multiple wiring patterns do not need to be provided on all conductor layers, and the surface of the wiring board of the embodiment does not need to be a component mounting surface. The insulating layer 12a and the insulating layer 13a may be thinner than the insulating layer 31, and the conductor layer 12b and the conductor layer 13b may be thinner than the conductor layer 21.

[0084] The method for manufacturing a wiring board according to the embodiment is not limited to the method described with reference to the drawings. For example, the method for forming each insulating layer and each conductor layer is not limited to the method described with reference to FIGS. 5A to 5L. The resist layer may be exposed to light using an exposure mask having openings corresponding to multiple wiring patterns. Each conductor layer may be formed by a method other than a semi-additive method, such as a full-additive method. Each insulating layer is not limited to a film-like resin, and may be formed using any type of resin. The method for manufacturing a wiring board according to the embodiment may include any additional step in addition to the steps described above, or some of the steps described above may be omitted. [Explanation of symbols]

[0085] 1, 1a, 1b Wiring board 2. Multiple wiring patterns 20 Wiring Pattern 2a Metal film 2b Plating film 20a End of the wiring pattern on the insulating layer side 20b The end of the wiring pattern on the insulating layer side and the end opposite to the insulating layer side 20s Wiring pattern side 21~23 Conductor layers 31 Insulating layer 31a: Surface of insulating layer 31 32 Insulation layer (upper insulation layer) 4. Resist Wall 40 resist layer 41 End of resist wall on insulating layer side G Distance between resist walls H Height of resist wall L Wiring pattern width L1 Width of the wiring pattern at the end of the insulating layer S Spacing between wiring patterns W Width of resist wall W1 Width of the resist wall at the end of the insulating layer

Claims

1. an insulating layer; a conductor layer laminated on the surface of the insulating layer and including a plurality of parallel wiring patterns; A wiring board comprising: the plurality of wiring patterns include wiring patterns adjacent to each other at intervals of 3 μm or less, At least one of the plurality of wiring patterns has a width at an end portion on the insulating layer side in the stacking direction of the insulating layer and the conductor layer that is smaller than the width at a central portion in the stacking direction.

2. 2. The wiring board according to claim 1, wherein the plurality of wiring patterns include wiring patterns having an aspect ratio of 2 or more.

3. 2. The wiring board according to claim 1, wherein the at least one wiring pattern has a width at an end opposite to the end in the stacking direction that is smaller than a width at the central portion.

4. 4. The wiring board according to claim 3, wherein the side surface of the at least one wiring pattern is curved so as to bulge outward at the central portion.

5. 2. The wiring board according to claim 1, the conductor layer is composed of a metal film in contact with the surface of the insulating layer and a plating film in contact with the metal film, The side surfaces of the portions of the plurality of wiring patterns that are made of the plating film have an arithmetic mean roughness (Ra) of 0.01 μm or more and 0.2 μm or less.

6. 6. The wiring board according to claim 5, wherein the metal film is a sputtered film.

7. 2. The wiring board according to claim 1, further comprising an upper insulating layer covering the surface of the insulating layer and the conductor layer, the spaces between the plurality of wiring patterns are filled with the upper insulating layer, The portions between the plurality of wiring patterns in the upper insulating layer are constricted at the center in the stacking direction.

8. forming an insulating layer; forming a plurality of parallel wiring patterns on the surface of the insulating layer; A method for manufacturing a wiring substrate, comprising: The forming of the plurality of wiring patterns includes: forming a plurality of parallel resist walls on the surface of the insulating layer; forming a plating film between each of the plurality of parallel resist walls; Including, Forming the plurality of resist walls includes forming at least one resist wall having a width at an end portion of each of the plurality of resist walls on the insulating layer side in the height direction that is greater than the width at a central portion of the height direction.

9. 9. The method for manufacturing a wiring board according to claim 8, wherein the at least one resist wall has a width greater at both ends in the height direction than at the central portion.

10. 10. The method for manufacturing a wiring board according to claim 9, wherein the at least one resist wall has a constriction in the central portion in the height direction.

11. 9. The method for manufacturing a wiring board according to claim 8, wherein forming the plurality of resist walls includes forming resist walls having a width of 3 [mu]m or less.

12. 12. The method for manufacturing a wiring board according to claim 11, wherein forming the plurality of resist walls includes forming resist walls having a height to width ratio of 3 or more.

13. 9. The method for manufacturing a wiring board according to claim 8, further comprising forming a metal film on the surface of the insulating layer, The plurality of resist walls are formed on the surface of the insulating layer via the metal film.

14. 9. The method for manufacturing a wiring board according to claim 8, forming the plurality of resist walls forming a photosensitive resist layer on the surface of the insulating layer; patterning at least a portion of the resist layer into the plurality of resist walls; Including, The patterning includes exposing the resist layer by direct imaging.

15. 15. The method for manufacturing a wiring board according to claim 14, wherein the resist layer is a resist layer having positive photosensitivity.

16. 16. A method for manufacturing a wiring board according to claim 15, wherein exposing the resist layer includes converging light used for the exposure at a central portion of the resist layer in a thickness direction.

17. 15. The method for manufacturing a wiring board according to claim 14, further comprising forming a metal film on the surface of the insulating layer, The resist layer is formed on the surface of the insulating layer with the metal film interposed therebetween.

Images