Semiconductor device

Abstract

To increase a capacitance value.SOLUTION: The plurality of trenches 30 are recessed from the first substrate surface 20S toward the second substrate surface 20R. The dielectric layer 40 includes a plurality of inner surface dielectric layers 41 respectively provided on the inner surfaces 32 of the plurality of trenches 30. The conductive layer 50 includes a plurality of internal electrodes 51 provided to fill at least a portion of a first internal region 81 surrounded by the plurality of inner surface dielectric layers 41. The plurality of partition wall portions 21, which partition the plurality of trenches 30 and are electrically connected to each other, and the plurality of internal electrodes 51 face each other with the plurality of inner surface dielectric layers 41 interposed therebetween, thereby constituting a capacitor C1. When viewed from the Z-axis direction, the plurality of trenches 30 have a circular shape. The plurality of trenches 30 are arranged at intervals L1 of 5 μm or less. The opening diameters D1 of the plurality of trenches 30 are 9 μm or less, and the depths T2 of the plurality of trenches 30 are 5 times or more and 20 times or less the opening diameters D1.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a chip capacitor comprising a substrate, a first conductive film formed on the substrate, a dielectric film disposed on the first conductive film and on the substrate, and a second conductive film disposed on the dielectric film. The first conductive film includes a first connection region and a first capacitor-forming region. The second conductive film includes a second capacitor-forming region facing the first capacitor-forming region across the dielectric film. A first external electrode is connected to the first connection region of the first conductive film, and a second external electrode is connected to the second connection region of the second conductive film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2017-195321

[0004] [overview] 2. Description of the Related Art In semiconductor devices including capacitors, there is a demand for increased capacitance.

[0005] A semiconductor device according to one aspect of the present disclosure includes a semiconductor substrate including a first substrate surface and a second substrate surface opposite to the first substrate surface, a plurality of trenches recessed from the first substrate surface toward the second substrate surface, a dielectric layer covering inner surfaces of the plurality of trenches and the first substrate surface, and a conductive layer provided on the dielectric layer, the dielectric layer including a plurality of inner surface dielectric layers respectively provided on the inner surfaces of the plurality of trenches and a surface dielectric layer covering the first substrate surface, and the conductive layer including a plurality of internal electrodes provided so as to fill at least a portion of a first internal region surrounded by the plurality of inner surface dielectric layers. and a surface electrode provided on the surface dielectric layer and electrically connecting the plurality of internal electrodes, wherein a capacitor is formed by a plurality of partition wall portions that partition the plurality of trenches and are electrically connected to each other, and the plurality of internal electrodes facing each other with the plurality of inner surface dielectric layers in between, and the plurality of trenches have a circular shape when viewed in the thickness direction of the semiconductor substrate, the plurality of trenches are arranged at intervals of 5 μm or less, the opening diameter of the plurality of trenches is 9 μm or less, and the depth of the plurality of trenches is 5 to 20 times the opening diameter. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic perspective view of an exemplary semiconductor device according to one embodiment. [Figure 2] FIG. 2 is a schematic plan view of the semiconductor device of FIG. [Figure 3] FIG. 3 is a schematic plan view showing a semiconductor substrate and trenches of the semiconductor device of FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view of the semiconductor device taken along line F4-F4 in FIG. [Figure 5] FIG. 5 is a schematic perspective view of the semiconductor device of FIG. [Figure 6] FIG. 6 is a characteristic diagram showing the relationship between the opening diameter of the trench and the capacitance density in the semiconductor device of FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a semiconductor device according to a modified example. [Figure 8]FIG. 8 is a schematic cross-sectional view showing a semiconductor device according to a modified example. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a semiconductor device according to a modified example.

[0007] [Detailed explanation] Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure. Terms such as "first," "second," and "third" in the present disclosure are used merely to distinguish between objects and do not rank the objects.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] <Embodiment> A semiconductor device 10 according to an embodiment will be described with reference to FIGS. FIG. 1 is a schematic perspective view of an exemplary semiconductor device according to one embodiment. FIG. 2 is a schematic plan view of the semiconductor device of FIG. 1. FIG. 3 is a schematic plan view showing a semiconductor substrate and trenches of the semiconductor device of FIG. 1. In FIG. 3, the surface electrode 53 of the conductive layer 50 is indicated by a two-dot chain line. FIG. 4 is a schematic cross-sectional view of the semiconductor device taken along line F4-F4 of FIG. 2. FIG. 5 is a schematic perspective view of the semiconductor device of FIG. 4. In FIG. 5, components on the first substrate surface 20S of the semiconductor substrate 20 (the surface dielectric layer 43 of the dielectric layer 40, the surface conductive layer 53 of the conductive layer 50, and the first electrode 71) are indicated by two-dot chain lines. FIG. 6 is a characteristic diagram showing the relationship between the opening diameter of the trench and the capacitance density of the semiconductor device of FIG. 1.

[0010] As shown in FIGS. 1 and 2, the semiconductor device 10 has a generally rectangular parallelepiped shape. The semiconductor device 10 includes a semiconductor substrate 20. The semiconductor substrate 20 has a rectangular parallelepiped shape. In one example, the semiconductor substrate 20 may have a square shape in a plan view.

[0011] The semiconductor substrate 20 includes multiple side surfaces 201, 202, 203, and 204 that intersect with the first substrate surface 20S and the second substrate surface 20R. For ease of explanation, the two mutually orthogonal directions within the first substrate surface 20S of the semiconductor substrate 20 are referred to as the X-axis direction and the Y-axis direction, and the direction orthogonal to the X-axis direction and the Y-axis direction is referred to as the Z-axis direction. The Z-axis direction may be perpendicular to the first substrate surface 20S. Viewing a target component from the Z-axis direction is referred to as a planar view. The Z-axis direction corresponds to the thickness direction of the semiconductor substrate 20. The X-axis direction corresponds to the "second direction," and the Y-axis direction corresponds to the "first direction." In one example, the first side surface 201 and the second side surface 202 extend along the Y-axis direction and face opposite each other. In another example, the third side surface 203 and the fourth side surface 204 extend along the X-axis direction and face opposite each other. The semiconductor substrate 20 may have a rounded shape with chamfered corners in a planar view. The side surfaces 201 to 204 of the semiconductor substrate 20 may be curved so as to be convex toward the outside of the semiconductor substrate 20. The side surfaces of the semiconductor substrate 20 do not have to be clearly divided into the first to fourth side surfaces 201 to 204.

[0012] The semiconductor substrate 20 may be made of a material containing Si (silicon). For example, the semiconductor substrate 20 may be a silicon substrate. The semiconductor substrate 20 may contain impurities. The impurities may be impurities of a first conductivity type. For example, the semiconductor substrate 20 may be a silicon substrate containing impurities of the first conductivity type. The first conductivity type may be, for example, p-type. The resistivity of the semiconductor substrate 20 may be 1 mΩ·cm or more and 100 mΩ·cm or less by introducing p-type impurities. The resistivity of the semiconductor substrate 20 may be 1 mΩ·cm or less. The thickness T1 of the semiconductor substrate 20 may be 100 μm or more and 500 μm or less.

[0013] The semiconductor device 10 may include a dielectric layer 40. The dielectric layer 40 may cover the entire first substrate surface 20S of the semiconductor substrate 20. The dielectric layer 40 includes a first surface 40S and a second surface 40R opposite to the first surface 40S. The second surface 40R of the dielectric layer 40 is in contact with the first substrate surface 20S of the semiconductor substrate 20. The dielectric layer 40 includes a plurality of side surfaces 401, 402, 403, and 404 connecting the first surface 40S and the second surface 40R. The side surfaces 401 to 404 of the dielectric layer 40 may be flush with the side surfaces 201 to 204 of the semiconductor substrate 20.

[0014] The dielectric layer 40 is made of an insulating material. The dielectric layer 40 may be made of a material containing at least one of SiO2 (silicon oxide), SiN (silicon nitride), SiON (silicon oxynitride), and Al2O3 (aluminum oxide). The dielectric layer 40 may also be an ON film or an ONO film. The dielectric layer 40 may also be made of a high-dielectric material (high-k material). In one example, the dielectric layer 40 is made of a material containing SiO2. The dielectric layer 40 may have a structure in which a plurality of insulating films are stacked.

[0015] The semiconductor device 10 may include a conductive layer 50. The conductive layer 50 is disposed on the semiconductor substrate 20. The conductive layer 50 may partially cover the first surface 40S of the dielectric layer 40. The conductive layer 50 includes the first surface 50S and a second surface 50R opposite the first surface 50S. The second surface 50R of the conductive layer 50 is in contact with the first surface 40S of the dielectric layer 40.

[0016] The conductive layer 50 is disposed in a central region of the semiconductor substrate 20 in a plan view. The conductive layer 50 is formed in a region spaced inward from the side surfaces 201 to 204 of the semiconductor substrate 20. In a plan view, the conductive layer 50 can be said to be surrounded by the dielectric layer 40 on the first substrate surface 20S of the semiconductor substrate 20. The conductive layer 50 can be said to be spaced apart from the periphery of the first substrate surface 20S of the semiconductor substrate 20.

[0017] The conductive layer 50 includes a plurality of side surfaces 501, 502, 503, and 504 connecting the first surface 50S and the second surface 50R. The side surfaces 501 to 504 of the conductive layer 50 are arranged inwardly from the side surfaces 201 to 204 of the semiconductor substrate 20 at intervals. It can be said that the conductive layer 50 includes the side surfaces 501 to 504 arranged inwardly from the side surfaces 201 to 204 of the semiconductor substrate 20 at intervals. The side surfaces 501 to 504 of the conductive layer 50 may also be called edges or end surfaces of the conductive layer 50. The regions between the side surfaces 501 to 504 of the conductive layer 50 and the side surfaces 201 to 204 of the semiconductor substrate 20 may be insulating regions in which the dielectric layer 40 on the first substrate surface 20S of the semiconductor substrate 20 is exposed.

[0018] The conductive layer 50 is made of a conductive material and may be made of a material containing at least one of polysilicon, W (tungsten), Cu (copper), and Al (aluminum).

[0019] The semiconductor device 10 may include a first electrode 71. The first electrode 71 is disposed on the semiconductor substrate 20. The first electrode 71 is disposed on the conductive layer 50. The first electrode 71 may cover at least a portion of the conductive layer 50. In one example, the first electrode 71 covers the entire conductive layer 50.

[0020] The first electrode 71 includes a first surface 71S and a second surface 71R opposite to the first surface 71S. The second surface 71R of the first electrode 71 is in contact with the first surface 50S of the conductive layer 50. The first electrode 71 is disposed in a central region of the semiconductor substrate 20 in a plan view. The first electrode 71 is formed in a region spaced inward from the side surfaces 201 to 204 of the semiconductor substrate 20. In a plan view, the first electrode 71 can be said to be surrounded by the dielectric layer 40 on the first substrate surface 20S of the semiconductor substrate 20. The first electrode 71 can be said to be spaced apart from the periphery of the first substrate surface 20S of the semiconductor substrate 20.

[0021] The first electrode 71 includes a plurality of side surfaces 711, 712, 713, and 714 connecting the first surface 71S and the second surface 71R. The side surfaces 711 to 714 of the first electrode 71 are spaced apart inward from the side surfaces 201 to 204 of the semiconductor substrate 20. The side surfaces 711 to 714 of the first electrode 71 may be flush with the side surfaces 501 to 504 of the conductive layer 50. The first electrode 71 can be said to include the side surfaces 711 to 714 spaced apart inward from the side surfaces 201 to 204 of the semiconductor substrate 20. The side surfaces 711 to 714 of the first electrode 71 may also be referred to as the edges or end surfaces of the first electrode 71. The regions between the side surfaces 711 to 714 of the first electrode 71 and the side surfaces 201 to 204 of the semiconductor substrate 20 may be insulating regions in which the dielectric layer 40 on the first substrate surface 20S of the semiconductor substrate 20 is exposed.

[0022] The first electrode 71 may be made of one or more metal materials such as Cu, Al, Ni (nickel), Pd (palladium), Au (gold), etc. In one example, the first electrode 71 may be made of a material containing Al.

[0023] The semiconductor device 10 may include a second electrode 72. The second electrode 72 is disposed on the second substrate surface 20R of the semiconductor substrate 20. The second electrode 72 may cover the second substrate surface 20R of the semiconductor substrate 20. The second electrode 72 includes a first surface 72S and a second surface 72R opposite to the first surface 72S. The first surface 72S of the second electrode 72 is in contact with the semiconductor substrate 20. The second electrode 72 includes multiple side surfaces connecting the first surface 72S and the second surface 72R. The side surfaces of the second electrode 72 may be flush with the side surfaces 201 to 204 of the semiconductor substrate 20. The second electrode 72 is made of a conductive material. For example, the second electrode 72 may be made of a material containing Ti (titanium). The second electrode 72 may be made of multiple stacked metal layers. The semiconductor device 10 does not necessarily include the second electrode 72.

[0024] (Internal structure of semiconductor device) 3 to 5, the semiconductor device 10 includes a plurality of trenches 30 provided in a semiconductor substrate 20. The plurality of trenches 30 are recessed from a first substrate surface 20S of the semiconductor substrate 20 toward a second substrate surface 20R.

[0025] The plurality of trenches 30 are arranged at intervals from one another in a plan view. In one example, the plurality of trenches 30 are arranged so that one trench 30 is located at each of the three vertices of an equilateral triangle DS in a plan view. In this case, the plurality of trenches 30 can be said to be arranged in a close-packed arrangement in a plan view, in which the greatest number of trenches 30 are arranged in a given area. Furthermore, the plurality of trenches 30 can be said to be arranged in a staggered arrangement at intervals from one another in a plan view.

[0026] The plurality of trenches 30 open to the first substrate surface 20S of the semiconductor substrate 20. The plurality of trenches 30 may be considered to be bottomed recesses having openings 31 in the first substrate surface 20S of the semiconductor substrate 20. The openings of the plurality of trenches 30 may have a circular shape in a plan view. In other words, the plurality of trenches 30 may have a cylindrical shape. The plurality of trenches 30 may be formed by removing a portion of the semiconductor substrate 20 from the first substrate surface 20S by, for example, dry etching.

[0027] 4 and 5 , the inner surfaces 32 of the multiple trenches 30 include a bottom surface 33 and an inner side surface 34 between the bottom surface 33 and the opening 31. In one example, the inner side surface 34 extends in the Z-axis direction, that is, in the thickness direction of the semiconductor substrate 20. The inner side surface 34 may be inclined or curved so that the size (inner diameter) of the trench 30 at the portion closer to the bottom surface 33 is smaller than the size (inner diameter) of the trench 30 at the opening 31 in a plan view.

[0028] The inner surfaces 32 of the plurality of trenches 30 are formed by a plurality of partition walls 21 that partition each of the plurality of trenches 30. It can be said that the semiconductor substrate 20 includes a plurality of partition walls 21 that partition the plurality of trenches 30. The plurality of partition walls 21 are formed by the semiconductor substrate 20. Therefore, it can be said that the plurality of partition walls 21 are electrically connected to each other. The inner side surface 34 and the bottom surface 33 may be curved so as to be convex toward the inside of the semiconductor substrate 20. The inner surface 32 of the trench 30 does not need to be clearly divided into the inner side surface 34 and the bottom surface 33.

[0029] The size of the multiple trenches 30 may be indicated by the size of their openings on the first substrate surface 20S. In one example, the multiple trenches 30 have circular openings 31 in a plan view. Therefore, the size of the multiple trenches 30 may be indicated by the diameter D1 of the openings 31. The diameter D1 of the openings 31 may be referred to as the opening diameter. The opening diameter D1 of the multiple trenches 30 may be 5 μm or more and 9 μm or less. In one example, the opening diameter of the multiple trenches 30 may be 6 μm.

[0030] The depth T2 of the multiple trenches 30 may be indicated by the distance in the Z-axis direction from the first substrate surface 20S of the semiconductor substrate 20 to the bottom surfaces 33 of the multiple trenches 30. For example, the depth T2 of the multiple trenches 30 may be 5 to 20 times the opening diameter D1 of the multiple trenches 30. The aspect ratio of the multiple trenches 30 may be the ratio of the depth T2 to the opening diameter D1, and the aspect ratio may be 5 to 20. For example, when the opening diameter D1 of the multiple trenches 30 is 6 μm, the depth T2 of the multiple trenches 30 may be 30 μm to 120 μm.

[0031] 3, adjacent trenches 30 are arranged with a distance L1 between them in a plan view. The distance L1 between adjacent trenches 30 may be 2 μm or more and 5 μm or less. For example, the distance L1 between adjacent trenches 30 may be 2 μm. The arrangement pitch L2 of the trenches 30 arranged along the first substrate surface 20S of the semiconductor substrate 20 may be 7 μm or more and 14 μm or less. For example, the arrangement pitch L2 may be 8 μm.

[0032] The dielectric layer 40 covers the inner surfaces 32 of the trenches 30 and the first substrate surface 20S of the semiconductor substrate 20. The dielectric layer 40 includes a plurality of inner surface dielectric layers 41 provided on the inner surfaces of the trenches 30, respectively, and a surface dielectric layer 43 covering the first substrate surface 20S. The dielectric layer 40 may be formed by, for example, a CVD method to cover the first substrate surface 20S of the semiconductor substrate 20 and the inner surfaces 32 of the trenches 30.

[0033] The plurality of inner surface dielectric layers 41 include a first covering portion 42A covering the inner side surfaces 34 of the plurality of trenches 30 and a second covering portion 42B covering the bottom surfaces 33 of the plurality of trenches 30. The thickness of the first covering portion 42A and the thickness of the second covering portion 42B may be equal. The thickness of the surface dielectric layer 43 may be equal to the thickness of the inner surface dielectric layer 41. The thickness T11 of the plurality of inner surface dielectric layers 41 is smaller than the opening diameter D1 of the plurality of trenches 30. The thickness T11 of the inner surface dielectric layer 41 may be the distance between the inner peripheral surface and the outer peripheral surface of the inner surface dielectric layer 41 on a line passing through the center of the trench 30. The thickness T11 of the plurality of inner surface dielectric layers 41 may be the thickness T11 of the dielectric layer 40 within the trench 30. The thickness T11 of the plurality of inner surface dielectric layers 41 may be 0.1 μm or more and 1.5 μm or less. In one example, the thickness T11 of the inner surface dielectric layer 41 may be 1.0 μm.

[0034] The inner surface dielectric layer 41 covering the inner surfaces 32 of the plurality of trenches 30 forms a first internal region 81 recessed from the first surface 40S of the dielectric layer 40 toward the bottom surfaces 33 of the plurality of trenches 30. It can be said that the first internal region 81 is recessed from the first surface 40S of the dielectric layer 40 toward the second substrate surface 20R of the semiconductor substrate 20. It can be said that the semiconductor device 10 includes, inside the plurality of trenches 30, a first internal region 81 surrounded by the plurality of inner surface dielectric layers 41.

[0035] The conductive layer 50 is provided on the dielectric layer 40. The conductive layer 50 includes a plurality of internal electrodes 51 provided to fill at least a portion of the first internal region 81 surrounded by the plurality of inner surface dielectric layers 41, and a surface electrode 53 provided on the surface dielectric layer 43 and electrically connecting the plurality of internal electrodes 51. The plurality of internal electrodes 51 face a plurality of partition walls 21 across the plurality of inner surface dielectric layers 41. The plurality of partition walls 21 and the plurality of internal electrodes 51 face each other across the plurality of inner surface dielectric layers 41 to form a capacitor C1A. The plurality of partition walls 21 face the surface electrode 53 across the surface dielectric layer 43. The plurality of partition walls 21 face each other across the surface dielectric layer 43 to form a capacitor C1B. Therefore, the semiconductor device 10 includes a capacitor C1 (=C1A+C1B) formed by the plurality of partition walls 21 and the conductive layer 50 facing each other across the dielectric layer 40.

[0036] The multiple inner dielectric layers 41 include a surface 41S opposite to the semiconductor substrate 20. The surface electrode 53 includes a surface 43S opposite to the semiconductor substrate 20. The first surface 40S of the dielectric layer 40 includes the surface 41S of the inner dielectric layer 41 and the surface 43S of the surface dielectric layer 43. The multiple internal electrodes 51 may each cover at least a portion of the surface 41S of the multiple inner dielectric layers 41. The multiple internal electrodes 51 may each cover the entire surface 41S of the multiple inner dielectric layers 41. The surface electrode 53 may cover at least a portion of the surface 43S of the surface dielectric layer 43. The surface electrode 53 may cover a region of the surface 43S of the surface dielectric layer 43 in which the multiple trenches 30 are arranged.

[0037] The conductive layer 50 may be provided so as to fill at least the opening portion 81A of each of the multiple first internal regions 81. The conductive layer 50 may be provided so as to block the opening portion 81A of the multiple first internal regions 81. It can also be said that the conductive layer 50 covers at least a portion of the surfaces 41S of the multiple inner surface dielectric layers 41 that constitute the multiple first internal regions 81, and is provided so as to cover the multiple first internal regions 81. The semiconductor device 10 may include at least one void inside at least one of the multiple internal electrodes 51 provided in the multiple first internal regions 81.

[0038] In one example, the conductive layer 50 may include a first conductive layer 61 and a second conductive layer 62. The first conductive layer 61 covers the first surface 40S of the dielectric layer 40. The first conductive layer 61 covers the surface 41S of the inner surface dielectric layer 41 and the surface 43S of the surface dielectric layer 43. The first conductive layer 61 may be made of polysilicon containing impurities. The impurities may be p-type impurities or n-type impurities. The first conductive layer 61 may be made of a material containing Cu or Al. The first conductive layer 61 may be formed by forming a conductive film on the dielectric layer 40 by, for example, a CVD method and selectively etching the conductive film.

[0039] The thickness T21 of the first conductive layer 61 is smaller than the opening diameter D1 of the plurality of trenches 30. The thickness T21 of the first conductive layer 61 may be the distance between the inner peripheral surface and the outer peripheral surface of the first conductive layer 61 on a line passing through the center of the trench 30. The thickness T21 of the first conductive layer 61 may be larger than the thickness T11 of the plurality of inner dielectric layers 41. In one example, the thickness T21 of the first conductive layer 61 may be 1.8 μm. The thickness T21 of the first conductive layer 61 may be equal to or smaller than the thickness T11 of the plurality of inner dielectric layers 41.

[0040] The first conductive layer 61 covers the surfaces 41S of the multiple inner surface dielectric layers 41. The first conductive layer 61 may define a second internal region 82 recessed from the surface 61S of the first conductive layer 61 toward the bottom surfaces 33 of the multiple trenches 30. It can be said that the second internal region 82 is recessed from the surface 61S of the first conductive layer 61 toward the second substrate surface 20R of the semiconductor substrate 20. It can be said that the semiconductor device 10 includes, inside the multiple trenches 30, the second internal region 82 surrounded by the first conductive layer 61.

[0041] The second conductive layer 62 is provided on the first conductive layer 61. The second conductive layer 62 covers the first conductive layer 61. The second conductive layer 62 may be provided so as to fill at least the opening portion 82A of each of the multiple second internal regions 82. The second conductive layer 62 may be provided so as to block the opening portion 82A of the multiple second internal regions 82. It can also be said that the second conductive layer 62 covers at least a portion of the first conductive layer 61 that constitutes the multiple second internal regions 82, and is provided so as to cover the multiple second internal regions 82.

[0042] The second conductive layer 62 may include a buried portion 62A buried in a second internal region 82 formed by the first conductive layer 61 and a protruding portion 62B protruding upward from a surface 61S of the first conductive layer 61. In one example, the buried portion 62A fills the second internal region 82 of the first conductive layer 61. The buried portion 62A may have a cylindrical shape that is elongated in the Z-axis direction. The buried portion 62A may have a shape in which an end portion near the bottom surface 33 of the trench 30 is chamfered. It is preferable that no voids are present inside the multiple trenches 30. In one example, the second conductive layer 62 is made of W. The second conductive layer 62 may also be made of a material containing Cu or Al. The second conductive layer 62 may be formed by forming a conductive film on the first conductive layer 61 by, for example, a CVD method and selectively etching the conductive film.

[0043] The thickness T22 of the second conductive layer 62 is smaller than the thickness T21 of the first conductive layer 61. The thickness T22 of the second conductive layer 62 may be, for example, the thickness of the protruding portion 62B in the Z-axis direction. The size of the buried portion 62A may be represented by a diameter D22 of the buried portion 62A on a line passing through the center of the trench 30. The diameter D22 of the buried portion 62A may be smaller than the thickness T22 of the protruding portion 62B.

[0044] (Operation of the embodiment) Next, the operation of the semiconductor device 10 of the embodiment will be described. The semiconductor substrate 20 includes a first substrate surface 20S and a second substrate surface 20R opposite the first substrate surface 20S. The plurality of trenches 30 are recessed from the first substrate surface 20S toward the second substrate surface 20R. A dielectric layer 40 covers the inner surfaces 32 of the plurality of trenches 30 and the first substrate surface 20S. A conductive layer 50 is provided on the dielectric layer 40. The dielectric layer 40 includes a plurality of inner surface dielectric layers 41 provided on the inner surfaces 32 of the plurality of trenches 30, respectively, and a surface dielectric layer 43 covering the first substrate surface 20S. The conductive layer 50 includes a plurality of internal electrodes 51 provided to fill at least a portion of a first internal region 81 surrounded by the plurality of inner surface dielectric layers 41, and a surface electrode 53 provided on the surface dielectric layer 43 and electrically connecting the plurality of internal electrodes 51. A capacitor C1 is formed by a plurality of partition walls 21, which define the plurality of trenches 30 and are electrically connected to one another, and a plurality of internal electrodes 51, which face each other with a plurality of inner surface dielectric layers 41 interposed therebetween. When viewed from the Z-axis direction of the semiconductor substrate 20, the plurality of trenches 30 have a circular shape. The plurality of trenches 30 are arranged at intervals L1 of 5 μm or less. The opening diameter D1 of the plurality of trenches 30 is 9 μm or less, and the depth T2 of the plurality of trenches 30 is 5 to 20 times the opening diameter D1.

[0045] FIG. 6 shows the capacitance density per unit area versus the opening diameter D1 of the trench 30. In FIG. 6, the horizontal axis represents the opening diameter D1, and the vertical axis represents the capacitance density. FIG. 6 shows four characteristic curves LT1 to LT4. Each characteristic curve LT1 to LT4 represents a characteristic when the distance L1 between the trenches 30 is different. The characteristic curves LT1 to LT4 have increasing distance L1 in this order. In one example, the distance L1 for the characteristic curves LT1, LT2, LT3, and LT4 is 2 μm, 3 μm, 4 μm, and 5 μm. As shown in FIG. 6, the capacitance density increases as the opening diameter D1 increases for each of the characteristic curves LT1 to LT4. For the same opening diameter D1, the capacitance density decreases in the order of the characteristic curves LT1, LT2, LT3, and LT4, i.e., as the distance L1 between the trenches 30 increases.

[0046] In the manufacturing process of the semiconductor device 10, it is difficult to form multiple trenches 30 with a spacing L1 of less than 2 μm, for example. For example, forming multiple trenches 30 with a spacing L1 of 5 μm or more can result in an increase in the size of the semiconductor device 10. For this reason, the spacing L1 between the multiple trenches 30 is preferably 2 μm or more and 5 μm or less.

[0047] Here, a semiconductor device that is a comparative example to the semiconductor device 10 of the above embodiment will be described. Note that in the semiconductor device of the comparative example, components similar to those of the semiconductor device 10 of the above embodiment will be described using the same component names and symbols. The semiconductor device of the comparative example has a dielectric layer 40 and a conductive layer 50 stacked on the first substrate surface 20S of the semiconductor substrate 20. A capacitor is formed by the conductive layer 50 facing the first substrate surface 20S of the semiconductor substrate 20 with the dielectric layer 40 sandwiched between them.

[0048] In the semiconductor device 10 of the embodiment, the trenches 30 are circular and arranged at intervals L1 of 5 μm or less. The opening diameter D1 of the trenches 30 is 9 μm or less, and the depth T2 of the trenches 30 is 5 to 20 times the opening diameter D1. As a result, the capacitance value of the semiconductor device 10 can be increased.

[0049] The opening diameter D1 of the multiple trenches 30 affects the formation and manufacturing process of the capacitor. If the opening diameter D1 of the trench 30 is, for example, less than 3 μm, it becomes difficult to form the dielectric layer 40 and the conductive layer 50 in the trench 30. If the dielectric layer 40 is not formed on a portion of the inner surface 32 of the trench 30, such as the bottom surface 33, the capacitor C1 cannot be formed. If the opening diameter D1 of the trench 30 exceeds, for example, 9 μm, it becomes difficult to cover the opening 31 of the trench 30 with the dielectric layer 40 and the conductive layer 50, and an opening connecting to the void in the trench 30 may be formed in the conductive layer 50. Such an opening may affect the formation of an etching mask during the manufacturing process. For this reason, the opening diameter D1 of the multiple trenches 30 is preferably 5 μm or more and 9 μm or less.

[0050] By setting the opening diameter D1 and the spacing L1 of the plurality of trenches 30 within the above ranges, the semiconductor device 10 can obtain a desired capacitance value. In other words, a semiconductor device 10 having a desired capacitance value can be obtained. Furthermore, by setting the opening diameter D1 and the spacing L1 of the plurality of trenches 30 within the above ranges, the semiconductor device 10 can be provided with a desired breakdown voltage. As a result, a semiconductor device 10 having a desired breakdown voltage and capacitance value can be obtained.

[0051] In the case of a trench having corners on the inner surface 32 in plan view, the corners can be a factor in reducing the breakdown voltage. In the semiconductor device 10 of the embodiment, the multiple trenches 30 have a circular shape in plan view. Therefore, the semiconductor device 10 of the embodiment can suppress the influence on the breakdown voltage.

[0052] The depth T2 of the trenches 30 affects the opposing area between the partition wall portions 21 constituting the trenches 30 and the conductive layer 50. If the trenches 30 are shallow, the capacitance value of the capacitor formed by each trench 30 is small, which may result in the semiconductor device 10 becoming larger in size in order to obtain the required capacitance value. If the trenches 30 are deep, it becomes difficult to form the trenches 30 and to fill the interiors of the trenches 30. For this reason, the depth T2 of the trenches 30 is preferably 5 to 20 times the opening diameter D1 of the trenches 30. This allows for the semiconductor device 10 to have the desired breakdown voltage and capacitance value.

[0053] The thickness T11 of the dielectric layer 40 in the trench 30 affects the capacitance value and the breakdown voltage of the capacitor C1. Increasing the thickness of the dielectric layer 40 decreases the capacitance value of the capacitor C1 and increases the breakdown voltage of the capacitor C1. Therefore, the thickness of the dielectric layer 40 is preferably 0.1 μm or more and 1.5 μm or less. This allows a semiconductor device 10 with the desired breakdown voltage and capacitance value to be obtained.

[0054] The multiple trenches 30 are arranged such that, in a plan view, one trench 30 is located at each of the three vertices of an equilateral triangle DS. By arranging the multiple trenches 30 in this manner, more trenches 30 can be formed in the semiconductor substrate 20 than when the trenches 30 are arranged, for example, along the X-axis direction and the Y-axis direction. This makes it possible to obtain a semiconductor device 10 having a desired breakdown voltage and capacitance value. Furthermore, compared to when the trenches 30 are arranged, for example, along the X-axis direction and the Y-axis direction, the area of ​​the region where the multiple trenches 30 are formed, i.e., the semiconductor device 10, can be made smaller.

[0055] A surface electrode material such as a wire or ribbon is bonded to the first electrode 71 of the semiconductor device 10. The second electrode 72 of the semiconductor substrate 20 is mounted on a mounting substrate, for example. The surface electrode material may be a bonding wire, a ribbon, or the like. The surface electrode material is made of a material such as Cu, Al, or Au. The second electrode 72 is connected to the mounting substrate by solder or conductive paste. The first electrode 71 may be made of a material containing Al. In this case, by using a surface electrode material made of a soft metal such as Au, the influence of bonding to the semiconductor device 10 can be reduced and the surface electrode material can be reliably connected to the first electrode 71.

[0056] (Effects of the embodiment) As described above, the semiconductor device 10 of the embodiment provides the following advantages. (1) The semiconductor substrate 20 includes a first substrate surface 20S and a second substrate surface 20R opposite the first substrate surface 20S. The plurality of trenches 30 are recessed from the first substrate surface 20S toward the second substrate surface 20R. The dielectric layer 40 covers the inner surfaces 32 of the plurality of trenches 30 and the first substrate surface 20S. The conductive layer 50 is provided on the dielectric layer 40. The dielectric layer 40 includes a plurality of inner surface dielectric layers 41 provided on the inner surfaces 32 of the plurality of trenches 30, respectively, and a surface dielectric layer 43 covering the first substrate surface 20S. The conductive layer 50 includes a plurality of internal electrodes 51 provided to fill a first internal region 81 surrounded by the plurality of inner surface dielectric layers 41, and a surface electrode 53 provided on the surface dielectric layer 43 and electrically connecting the plurality of internal electrodes 51. A capacitor C1 (C1A) is formed by a plurality of partition walls 21, which define a plurality of trenches 30 and are electrically connected to one another, and a plurality of internal electrodes 51, which face each other with a plurality of inner surface dielectric layers 41 interposed therebetween. When viewed from the Z-axis direction of the semiconductor substrate 20, the plurality of trenches 30 have a circular shape. The plurality of trenches 30 are arranged at intervals L1 of 5 μm or less. The opening diameter D1 of the plurality of trenches 30 is 9 μm or less, and the depth T2 of the plurality of trenches 30 is 5 to 20 times the opening diameter D1. As a result, the capacitance value of the semiconductor device 10 can be increased.

[0057] (2) By setting the opening diameter D1 and the spacing L1 of the plurality of trenches 30 within the above ranges, it is possible to obtain a desired capacitance value for the semiconductor device 10. Furthermore, by setting the opening diameter D1 and the spacing L1 of the plurality of trenches 30 within the above ranges, it is possible to obtain a desired breakdown voltage for the semiconductor device 10. As a result, it is possible to obtain a semiconductor device 10 having a desired breakdown voltage and capacitance value.

[0058] (3) In the case of a trench having corners on the inner surface 32 in plan view, the corners can be a factor in reducing the breakdown voltage. In the semiconductor device 10 of the embodiment, the multiple trenches 30 have a circular shape in plan view. Therefore, the semiconductor device 10 of the embodiment can suppress the influence on the breakdown voltage.

[0059] (4) The depth T2 of the trenches 30 affects the opposing area between the partition wall portions 21 constituting the trenches 30 and the conductive layer 50. If the trenches 30 are shallow, the capacitance value of the capacitor formed by each trench 30 is small, which may result in the semiconductor device 10 becoming larger in size in order to obtain the required capacitance value. If the trenches 30 are deep, it becomes difficult to form the trenches 30 and to fill the interiors of the trenches 30. For this reason, the depth T2 of the trenches 30 is preferably 5 to 20 times the opening diameter D1 of the trenches 30. This allows for the semiconductor device 10 to have the desired breakdown voltage and capacitance value.

[0060] (5) The thickness T11 of the dielectric layer 40 in the trench 30 affects the capacitance and breakdown voltage of the capacitor C1. Increasing the thickness of the dielectric layer 40 decreases the capacitance and increases the breakdown voltage of the capacitor C1. Therefore, the thickness of the dielectric layer 40 is preferably 0.1 μm or more and 1.5 μm or less. This allows a semiconductor device 10 with the desired breakdown voltage and capacitance to be obtained.

[0061] (6) For example, the conductive layer 50 may include a first conductive layer 61 and a second conductive layer 62. The first conductive layer 61 covers the first surface 40S of the dielectric layer 40. The first conductive layer 61 covers the surface 41S of the inner surface dielectric layer 41 and the surface 43S of the surface dielectric layer 43 of the dielectric layer 40. The first conductive layer 61 may be made of polysilicon containing impurities. The second conductive layer 62 is provided on the first conductive layer 61. For example, the second conductive layer 62 is made of W. The second conductive layer 62 made of W fills the second internal region 82 of the first conductive layer 61. This allows the interior of the trench 30 to be reliably filled with the dielectric layer 40 and the conductive layer 50.

[0062] (7) The multiple trenches 30 are arranged such that, in a plan view, one trench 30 is located at each of the three vertices of an equilateral triangle DS. By arranging the multiple trenches 30 in this manner, more trenches 30 can be formed in the semiconductor substrate 20 than when the trenches 30 are arranged, for example, along the X-axis direction and the Y-axis direction. This makes it possible to obtain a semiconductor device 10 having the desired breakdown voltage and capacitance value. Furthermore, compared to when the trenches 30 are arranged, for example, along the X-axis direction and the Y-axis direction, the area of ​​the region where the multiple trenches 30 are formed, i.e., the semiconductor device 10, can be made smaller.

[0063] (8) A surface electrode material such as a wire or ribbon is bonded to the first electrode 71 of the semiconductor device 10. The second electrode 72 of the semiconductor substrate 20 is mounted on a mounting substrate, for example. The surface electrode material may be a bonding wire, a ribbon, or the like. The surface electrode material is made of a material such as Cu, Al, or Au. The second electrode 72 is connected to the mounting substrate by solder or conductive paste. The first electrode 71 may be made of a material containing Al. In this case, by using a surface electrode material made of a soft metal such as Au, the influence of bonding to the semiconductor device 10 can be reduced and the surface electrode material can be reliably connected to the first electrode 71.

[0064] <Example of change> The above embodiment can be modified, for example, as follows: The above embodiment and each of the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, parts common to the above embodiment will be assigned the same reference numerals as in the above embodiment, and their description will be omitted.

[0065] FIG. 7 is a schematic cross-sectional view of a semiconductor device 10A according to a modified example. The dielectric layer 40A may include a first dielectric layer 40A1 and a second dielectric layer 40A2. The first dielectric layer 40A1 and the second dielectric layer 40A2 may be made of different materials. In one example, the first dielectric layer 40A1 is made of a material containing SiO2, and the second dielectric layer 40A2 is made of a material containing SiN. In one example, the second dielectric layer 40A2 is disposed on the semiconductor substrate 20, and the first dielectric layer 40A1 is disposed on the second dielectric layer 40A2. Alternatively, the first dielectric layer 40A1 may be disposed on the semiconductor substrate 20, and the second dielectric layer 40A2 may be disposed on the first dielectric layer 40A1. In this dielectric layer 40A, the sum of the thicknesses of the first dielectric layer 40A1 and the second dielectric layer 40A2 may be the thickness T11.

[0066] 8 is a schematic cross-sectional view of a modified semiconductor device 10B. In this modified semiconductor device 10B, the conductive layer 50B is composed of a single conductive layer. The conductive layer 50B is composed of polysilicon. The conductive layer 50B may be composed of tungsten (W).

[0067] FIG. 9 is a schematic cross-sectional view of a semiconductor device 10C according to a modified example. The semiconductor device 10C of the modified example may include an insulating layer 90. The insulating layer 90 covers the side surfaces of the conductive layer 50. The insulating layer 90 may cover the side surfaces of the first electrode 71. The insulating layer 90 may also cover the first surface 40S of the dielectric layer 40 exposed from the conductive layer 50. The insulating layer 90 may also cover a portion of the first surface 71S of the first electrode 71, such as the peripheral portion. The insulating layer 90 may be made of a material containing at least one of SiO2, SiN, SiON, and Al2O3. The insulating layer 90 may also be made of a resin material such as polyimide resin or epoxy resin.

[0068] The term "on" as used in this disclosure includes both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0069] <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0070] [Appendix 1] a semiconductor substrate (20) including a first substrate surface (20S) and a second substrate surface (20R) opposite to the first substrate surface (20S); a plurality of trenches (30) recessed from the first substrate surface (20S) toward the second substrate surface (20R); a dielectric layer (40, 40A) covering the inner surfaces of the trenches (30) and the first substrate surface (20S); a conductive layer (50, 50B) provided on the dielectric layer (40, 40A); Including, The dielectric layers (40, 40A) are a plurality of inner surface dielectric layers (41) provided on the inner surfaces (32) of the plurality of trenches (30), respectively; a surface dielectric layer (43) covering the first substrate surface (20S); Including, The conductive layers (50, 50B) are a plurality of internal electrodes (51) provided so as to fill at least a portion of a first internal region surrounded by the plurality of inner surface dielectric layers (41); a surface electrode (53) provided on the surface dielectric layer (43) and electrically connecting the plurality of internal electrodes (51); Including, a plurality of partition walls (21) that partition the plurality of trenches (30) and are electrically connected to one another and that face the plurality of internal electrodes (51) with the plurality of inner surface dielectric layers (41) interposed therebetween, thereby constituting capacitors (C1A, C1); When viewed from the thickness direction (Z) of the semiconductor substrate (20), the plurality of trenches (30) have a circular shape, The plurality of trenches (30) are arranged at intervals (L1) of 5 μm or less, The opening diameter (D1) of the plurality of trenches (30) is 9 μm or less, and the depth of the plurality of trenches (30) is 5 times or more and 20 times or less than the opening diameter (D1). Semiconductor device.

[0071] [Appendix 2] the conductive layer is provided so as to cover openings of the plurality of first internal regions. 2. The semiconductor device according to claim 1.

[0072] [Appendix 3] The depth of the plurality of trenches (30) is 10 times or more the opening diameter (D1). 3. The semiconductor device according to claim 1 or 2.

[0073] [Appendix 4] The thickness (T11) of the inner surface dielectric layer (41) is 0.1 μm or more and 1.5 μm or less. 4. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0074] [Appendix 5] The semiconductor substrate (20) is made of a material containing Si. 5. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating film.

[0075] [Appendix 6] The resistivity of the semiconductor substrate (20) is 100 mΩ·cm or less. 6. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0076] [Appendix 7] The thickness of the semiconductor substrate (20) is 100 μm or more and 500 μm or less. 7. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0077] [Appendix 8] The dielectric layers (40, 40A) are made of a material containing SiO2 or SiN. 8. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0078] [Appendix 9] The dielectric layer (40A) includes both a first dielectric layer (40A1) made of a material including SiO2 and a second dielectric layer (40A2) made of a material including SiN. 8. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0079] [Appendix 10] The conductive layers (50, 50B) are made of polysilicon or tungsten. 10. The semiconductor device according to claim 1.

[0080] [Appendix 11] The conductive layer (50) is a first conductive layer (61) provided on the dielectric layer (40, 40A); a second conductive layer (62) provided on the first conductive layer (61); 10. The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 9, comprising:

[0081] [Appendix 12] The first conductive layer (61) is made of polysilicon, The second conductive layer (62) is made of tungsten. 12. The semiconductor device according to claim 11.

[0082] [Appendix 13] The thickness (T21) of the first conductive layer (61) is greater than the thickness (T22) of the second conductive layer (62). 13. The semiconductor device according to claim 11 or 12.

[0083] [Appendix 14] The thickness (T11) of the inner dielectric layer (41) is smaller than the thickness (T21) of the first conductive layer (61). 13. The semiconductor device according to claim 11 or 12.

[0084] [Appendix 15] The thickness (T11) of the inner dielectric layer (41) is greater than the thickness (T21) of the first conductive layer (61). 13. The semiconductor device according to claim 11 or 12.

[0085] [Appendix 16] The second conductive layer (62) is provided so as to fill at least a part of a second internal region surrounded by the first conductive layer (61). 16. The semiconductor device according to any one of claims 11 to 15.

[0086] [Appendix 17] The second conductive layer (62) is provided so as to close the opening portion of the second internal region. 17. The semiconductor device according to claim 16.

[0087] [Appendix 18] The plurality of trenches (30) are arranged such that one trench (30) is located at each of the three vertices of an equilateral triangle (DS) when viewed from the thickness direction (Z). 18. The semiconductor device according to any one of claims 1 to 17.

[0088] [Appendix 19] The length of one side of the equilateral triangle (DS) is 5 μm or more and 14 μm or less. 19. The semiconductor device according to claim 18.

[0089] [Appendix 20] The plurality of trenches (30) are arranged in a staggered pattern at intervals (L1) in a plan view. 19. The semiconductor device according to claim 1.

[0090] [Appendix 21] a first electrode (71) provided so as to cover at least a part of the conductive layer (50, 50B); a second electrode (72) provided on the second substrate surface (20R); 21. The semiconductor device according to claim 1, further comprising:

[0091] [Appendix 22] At least one of the first electrode (71) and the second electrode (72) is made of a plurality of metal films. 22. The semiconductor device according to claim 21.

[0092] [Appendix 23] the first electrode (71) is made of a material containing Al, The second electrode (72) is made of a material containing Ti. 23. The semiconductor device according to claim 21 or 22.

[0093] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0094] 10 Semiconductor devices 10A, 10B, 10C Semiconductor device 20 Semiconductor substrate 20S 1st board surface 20R Second board surface 21 Compartment wall 30 Trench 31 Opening 32 Inner 33 bottom 34 Inner surface 40 Dielectric Layer 40S 1st page 40R 2nd side 40A dielectric layer 40A1 First dielectric layer 40A2 Second dielectric layer 41 Inner dielectric layer 41S surface 42A First coated part 42B Second coated part 43 Surface dielectric layer 43S surface 50,50B conductive layer 50S 1st page 50R 2nd side 51 Internal electrode 53 Surface electrode 61 First conductive layer 61S surface 62 Second conductive layer 62A Embedded part 62B protruding part 71 1st electrode 71S Page 1 71R 2nd side 72 2nd electrode 72S 1st page 72R 2nd side 81 1st internal area 82 Second internal area 90 Insulating layer 201~204 1st~4th aspects 401~404 Side 501~504 Side 711~714 Side C1, C1A, C1B capacitors D1 Opening diameter (diameter) DS equilateral triangle L1 interval (distance) L2 placement pitch LT1~LT4 characteristic curve T1 Thickness T11, T21, T22 thickness T2 depth

Claims

1. a semiconductor substrate including a first substrate surface and a second substrate surface opposite the first substrate surface; a plurality of trenches recessed from the first substrate surface toward the second substrate surface; a dielectric layer covering the inner surfaces of the plurality of trenches and the first substrate surface; a conductive layer disposed on the dielectric layer; Including, The dielectric layer is a plurality of inner surface dielectric layers respectively provided on the inner surfaces of the plurality of trenches; a surface dielectric layer covering the first substrate surface; Including, The conductive layer is a plurality of internal electrodes provided so as to fill at least a portion of a first internal region surrounded by the plurality of inner surface dielectric layers; a surface electrode provided on the surface dielectric layer and electrically connecting the plurality of internal electrodes; Including, a capacitor is formed by a plurality of partition wall portions that partition the plurality of trenches and are electrically connected to each other, and a plurality of the internal electrodes that face each other with the plurality of inner surface dielectric layers interposed therebetween; When viewed in a thickness direction of the semiconductor substrate, the plurality of trenches have a circular shape, The plurality of trenches are arranged at intervals of 5 μm or less, The opening diameter of the plurality of trenches is 9 μm or less, and the depth of the plurality of trenches is 5 times or more and 20 times or less than the opening diameter. Semiconductor device.

2. the conductive layer is provided so as to cover openings of the plurality of first internal regions. The semiconductor device according to claim 1 .

3. The depth of the plurality of trenches is 10 times or more the diameter of the opening. The semiconductor device according to claim 1 .

4. The thickness of the inner surface dielectric layer is 0.1 μm or more and 1.5 μm or less. The semiconductor device according to claim 1 .

5. The semiconductor substrate is made of a material containing Si. The semiconductor device according to claim 1 .

6. The resistivity of the semiconductor substrate is 100 mΩ cm or less. The semiconductor device according to claim 1 .

7. The thickness of the semiconductor substrate is 100 μm or more and 500 μm or less. The semiconductor device according to claim 1 .

8. The dielectric layer is made of SiO ２ Or made of a material containing SiN, The semiconductor device according to claim 1 .

9. The dielectric layer is made of SiO ２ and a second dielectric layer made of a material including SiN, The semiconductor device according to claim 1 .

10. The conductive layer is made of polysilicon or tungsten. The semiconductor device according to claim 1 .

11. The conductive layer is a first conductive layer disposed on the dielectric layer; a second conductive layer provided on the first conductive layer; The semiconductor device according to claim 1 , comprising:

12. the first conductive layer is made of polysilicon, the second conductive layer is made of tungsten. The semiconductor device according to claim 11.

13. The thickness of the first conductive layer is greater than the thickness of the second conductive layer.

13. The semiconductor device according to claim 11 or 12.

14. the thickness of the inner surface dielectric layer is less than the thickness of the first conductive layer; 13. The semiconductor device according to claim 11 or 12.

15. the thickness of the inner surface dielectric layer is greater than the thickness of the first conductive layer; 13. The semiconductor device according to claim 11 or 12.

16. the second conductive layer is provided so as to fill at least a part of a second internal region surrounded by the first conductive layer; The semiconductor device according to claim 11.

17. the plurality of trenches are arranged such that one trench is located at each of three vertices of an equilateral triangle when viewed from the thickness direction; The semiconductor device according to claim 1 .

18. The length of one side of the equilateral triangle is 5 μm or more and 14 μm or less.

18. The semiconductor device according to claim 17.

19. a first electrode provided so as to cover at least a portion of the conductive layer; a second electrode provided on the second substrate surface; The semiconductor device according to claim 1 , comprising:

20. At least one of the first electrode and the second electrode is made of a plurality of metal films.

20. The semiconductor device according to claim 19.

Images